ARMAsmParser.cpp revision 6eef361b73b457896b310d411251aedd5e72476a 
1//===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "ARMFeatures.h"
11#include "llvm/MC/MCTargetAsmParser.h"
12#include "MCTargetDesc/ARMAddressingModes.h"
13#include "MCTargetDesc/ARMBaseInfo.h"
14#include "MCTargetDesc/ARMMCExpr.h"
15#include "llvm/ADT/BitVector.h"
16#include "llvm/ADT/OwningPtr.h"
17#include "llvm/ADT/STLExtras.h"
18#include "llvm/ADT/SmallVector.h"
19#include "llvm/ADT/StringSwitch.h"
20#include "llvm/ADT/Twine.h"
21#include "llvm/MC/MCAsmInfo.h"
22#include "llvm/MC/MCAssembler.h"
23#include "llvm/MC/MCContext.h"
24#include "llvm/MC/MCELFStreamer.h"
25#include "llvm/MC/MCExpr.h"
26#include "llvm/MC/MCInst.h"
27#include "llvm/MC/MCInstrDesc.h"
28#include "llvm/MC/MCInstrInfo.h"
29#include "llvm/MC/MCParser/MCAsmLexer.h"
30#include "llvm/MC/MCParser/MCAsmParser.h"
31#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
32#include "llvm/MC/MCRegisterInfo.h"
33#include "llvm/MC/MCStreamer.h"
34#include "llvm/MC/MCSubtargetInfo.h"
35#include "llvm/Support/ELF.h"
36#include "llvm/Support/MathExtras.h"
37#include "llvm/Support/SourceMgr.h"
38#include "llvm/Support/TargetRegistry.h"
39#include "llvm/Support/raw_ostream.h"
40
41using namespace llvm;
42
43namespace {
44
45class ARMOperand;
46
47enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
48
49class ARMAsmParser : public MCTargetAsmParser {
50  MCSubtargetInfo &STI;
51  MCAsmParser &Parser;
52  const MCInstrInfo &MII;
53  const MCRegisterInfo *MRI;
54
55  // Unwind directives state
56  SMLoc FnStartLoc;
57  SMLoc CantUnwindLoc;
58  SMLoc PersonalityLoc;
59  SMLoc HandlerDataLoc;
60  int FPReg;
61  void resetUnwindDirectiveParserState() {
62    FnStartLoc = SMLoc();
63    CantUnwindLoc = SMLoc();
64    PersonalityLoc = SMLoc();
65    HandlerDataLoc = SMLoc();
66    FPReg = -1;
67  }
68
69  // Map of register aliases registers via the .req directive.
70  StringMap<unsigned> RegisterReqs;
71
72  struct {
73    ARMCC::CondCodes Cond;    // Condition for IT block.
74    unsigned Mask:4;          // Condition mask for instructions.
75                              // Starting at first 1 (from lsb).
76                              //   '1'  condition as indicated in IT.
77                              //   '0'  inverse of condition (else).
78                              // Count of instructions in IT block is
79                              // 4 - trailingzeroes(mask)
80
81    bool FirstCond;           // Explicit flag for when we're parsing the
82                              // First instruction in the IT block. It's
83                              // implied in the mask, so needs special
84                              // handling.
85
86    unsigned CurPosition;     // Current position in parsing of IT
87                              // block. In range [0,3]. Initialized
88                              // according to count of instructions in block.
89                              // ~0U if no active IT block.
90  } ITState;
91  bool inITBlock() { return ITState.CurPosition != ~0U;}
92  void forwardITPosition() {
93    if (!inITBlock()) return;
94    // Move to the next instruction in the IT block, if there is one. If not,
95    // mark the block as done.
96    unsigned TZ = countTrailingZeros(ITState.Mask);
97    if (++ITState.CurPosition == 5 - TZ)
98      ITState.CurPosition = ~0U; // Done with the IT block after this.
99  }
100
101
102  MCAsmParser &getParser() const { return Parser; }
103  MCAsmLexer &getLexer() const { return Parser.getLexer(); }
104
105  bool Warning(SMLoc L, const Twine &Msg,
106               ArrayRef<SMRange> Ranges = None) {
107    return Parser.Warning(L, Msg, Ranges);
108  }
109  bool Error(SMLoc L, const Twine &Msg,
110             ArrayRef<SMRange> Ranges = None) {
111    return Parser.Error(L, Msg, Ranges);
112  }
113
114  int tryParseRegister();
115  bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
116  int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
117  bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
118  bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
119  bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
120  bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
121  bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
122                              unsigned &ShiftAmount);
123  bool parseDirectiveWord(unsigned Size, SMLoc L);
124  bool parseDirectiveThumb(SMLoc L);
125  bool parseDirectiveARM(SMLoc L);
126  bool parseDirectiveThumbFunc(SMLoc L);
127  bool parseDirectiveCode(SMLoc L);
128  bool parseDirectiveSyntax(SMLoc L);
129  bool parseDirectiveReq(StringRef Name, SMLoc L);
130  bool parseDirectiveUnreq(SMLoc L);
131  bool parseDirectiveArch(SMLoc L);
132  bool parseDirectiveEabiAttr(SMLoc L);
133  bool parseDirectiveFnStart(SMLoc L);
134  bool parseDirectiveFnEnd(SMLoc L);
135  bool parseDirectiveCantUnwind(SMLoc L);
136  bool parseDirectivePersonality(SMLoc L);
137  bool parseDirectiveHandlerData(SMLoc L);
138  bool parseDirectiveSetFP(SMLoc L);
139  bool parseDirectivePad(SMLoc L);
140  bool parseDirectiveRegSave(SMLoc L, bool IsVector);
141
142  StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
143                          bool &CarrySetting, unsigned &ProcessorIMod,
144                          StringRef &ITMask);
145  void getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
146                             bool &CanAcceptCarrySet,
147                             bool &CanAcceptPredicationCode);
148
149  bool isThumb() const {
150    // FIXME: Can tablegen auto-generate this?
151    return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
152  }
153  bool isThumbOne() const {
154    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
155  }
156  bool isThumbTwo() const {
157    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
158  }
159  bool hasThumb() const {
160    return STI.getFeatureBits() & ARM::HasV4TOps;
161  }
162  bool hasV6Ops() const {
163    return STI.getFeatureBits() & ARM::HasV6Ops;
164  }
165  bool hasV7Ops() const {
166    return STI.getFeatureBits() & ARM::HasV7Ops;
167  }
168  bool hasV8Ops() const {
169    return STI.getFeatureBits() & ARM::HasV8Ops;
170  }
171  bool hasARM() const {
172    return !(STI.getFeatureBits() & ARM::FeatureNoARM);
173  }
174
175  void SwitchMode() {
176    unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
177    setAvailableFeatures(FB);
178  }
179  bool isMClass() const {
180    return STI.getFeatureBits() & ARM::FeatureMClass;
181  }
182
183  /// @name Auto-generated Match Functions
184  /// {
185
186#define GET_ASSEMBLER_HEADER
187#include "ARMGenAsmMatcher.inc"
188
189  /// }
190
191  OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
192  OperandMatchResultTy parseCoprocNumOperand(
193    SmallVectorImpl<MCParsedAsmOperand*>&);
194  OperandMatchResultTy parseCoprocRegOperand(
195    SmallVectorImpl<MCParsedAsmOperand*>&);
196  OperandMatchResultTy parseCoprocOptionOperand(
197    SmallVectorImpl<MCParsedAsmOperand*>&);
198  OperandMatchResultTy parseMemBarrierOptOperand(
199    SmallVectorImpl<MCParsedAsmOperand*>&);
200  OperandMatchResultTy parseInstSyncBarrierOptOperand(
201    SmallVectorImpl<MCParsedAsmOperand*>&);
202  OperandMatchResultTy parseProcIFlagsOperand(
203    SmallVectorImpl<MCParsedAsmOperand*>&);
204  OperandMatchResultTy parseMSRMaskOperand(
205    SmallVectorImpl<MCParsedAsmOperand*>&);
206  OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
207                                   StringRef Op, int Low, int High);
208  OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
209    return parsePKHImm(O, "lsl", 0, 31);
210  }
211  OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
212    return parsePKHImm(O, "asr", 1, 32);
213  }
214  OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
215  OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
216  OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
217  OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
218  OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
219  OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
220  OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&);
221  OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&);
222  OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
223                                       SMLoc &EndLoc);
224
225  // Asm Match Converter Methods
226  void cvtThumbMultiply(MCInst &Inst,
227                        const SmallVectorImpl<MCParsedAsmOperand*> &);
228  void cvtThumbBranches(MCInst &Inst,
229                        const SmallVectorImpl<MCParsedAsmOperand*> &);
230
231  bool validateInstruction(MCInst &Inst,
232                           const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
233  bool processInstruction(MCInst &Inst,
234                          const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
235  bool shouldOmitCCOutOperand(StringRef Mnemonic,
236                              SmallVectorImpl<MCParsedAsmOperand*> &Operands);
237  bool shouldOmitPredicateOperand(StringRef Mnemonic,
238                              SmallVectorImpl<MCParsedAsmOperand*> &Operands);
239public:
240  enum ARMMatchResultTy {
241    Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
242    Match_RequiresNotITBlock,
243    Match_RequiresV6,
244    Match_RequiresThumb2,
245#define GET_OPERAND_DIAGNOSTIC_TYPES
246#include "ARMGenAsmMatcher.inc"
247
248  };
249
250  ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser,
251               const MCInstrInfo &MII)
252      : MCTargetAsmParser(), STI(_STI), Parser(_Parser), MII(MII), FPReg(-1) {
253    MCAsmParserExtension::Initialize(_Parser);
254
255    // Cache the MCRegisterInfo.
256    MRI = getContext().getRegisterInfo();
257
258    // Initialize the set of available features.
259    setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
260
261    // Not in an ITBlock to start with.
262    ITState.CurPosition = ~0U;
263
264    // Set ELF header flags.
265    // FIXME: This should eventually end up somewhere else where more
266    // intelligent flag decisions can be made. For now we are just maintaining
267    // the statu/parseDirects quo for ARM and setting EF_ARM_EABI_VER5 as the default.
268    if (MCELFStreamer *MES = dyn_cast<MCELFStreamer>(&Parser.getStreamer()))
269      MES->getAssembler().setELFHeaderEFlags(ELF::EF_ARM_EABI_VER5);
270  }
271
272  // Implementation of the MCTargetAsmParser interface:
273  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
274  bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
275                        SMLoc NameLoc,
276                        SmallVectorImpl<MCParsedAsmOperand*> &Operands);
277  bool ParseDirective(AsmToken DirectiveID);
278
279  unsigned validateTargetOperandClass(MCParsedAsmOperand *Op, unsigned Kind);
280  unsigned checkTargetMatchPredicate(MCInst &Inst);
281
282  bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
283                               SmallVectorImpl<MCParsedAsmOperand*> &Operands,
284                               MCStreamer &Out, unsigned &ErrorInfo,
285                               bool MatchingInlineAsm);
286};
287} // end anonymous namespace
288
289namespace {
290
291/// ARMOperand - Instances of this class represent a parsed ARM machine
292/// operand.
293class ARMOperand : public MCParsedAsmOperand {
294  enum KindTy {
295    k_CondCode,
296    k_CCOut,
297    k_ITCondMask,
298    k_CoprocNum,
299    k_CoprocReg,
300    k_CoprocOption,
301    k_Immediate,
302    k_MemBarrierOpt,
303    k_InstSyncBarrierOpt,
304    k_Memory,
305    k_PostIndexRegister,
306    k_MSRMask,
307    k_ProcIFlags,
308    k_VectorIndex,
309    k_Register,
310    k_RegisterList,
311    k_DPRRegisterList,
312    k_SPRRegisterList,
313    k_VectorList,
314    k_VectorListAllLanes,
315    k_VectorListIndexed,
316    k_ShiftedRegister,
317    k_ShiftedImmediate,
318    k_ShifterImmediate,
319    k_RotateImmediate,
320    k_BitfieldDescriptor,
321    k_Token
322  } Kind;
323
324  SMLoc StartLoc, EndLoc;
325  SmallVector<unsigned, 8> Registers;
326
327  struct CCOp {
328    ARMCC::CondCodes Val;
329  };
330
331  struct CopOp {
332    unsigned Val;
333  };
334
335  struct CoprocOptionOp {
336    unsigned Val;
337  };
338
339  struct ITMaskOp {
340    unsigned Mask:4;
341  };
342
343  struct MBOptOp {
344    ARM_MB::MemBOpt Val;
345  };
346
347  struct ISBOptOp {
348    ARM_ISB::InstSyncBOpt Val;
349  };
350
351  struct IFlagsOp {
352    ARM_PROC::IFlags Val;
353  };
354
355  struct MMaskOp {
356    unsigned Val;
357  };
358
359  struct TokOp {
360    const char *Data;
361    unsigned Length;
362  };
363
364  struct RegOp {
365    unsigned RegNum;
366  };
367
368  // A vector register list is a sequential list of 1 to 4 registers.
369  struct VectorListOp {
370    unsigned RegNum;
371    unsigned Count;
372    unsigned LaneIndex;
373    bool isDoubleSpaced;
374  };
375
376  struct VectorIndexOp {
377    unsigned Val;
378  };
379
380  struct ImmOp {
381    const MCExpr *Val;
382  };
383
384  /// Combined record for all forms of ARM address expressions.
385  struct MemoryOp {
386    unsigned BaseRegNum;
387    // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
388    // was specified.
389    const MCConstantExpr *OffsetImm;  // Offset immediate value
390    unsigned OffsetRegNum;    // Offset register num, when OffsetImm == NULL
391    ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
392    unsigned ShiftImm;        // shift for OffsetReg.
393    unsigned Alignment;       // 0 = no alignment specified
394    // n = alignment in bytes (2, 4, 8, 16, or 32)
395    unsigned isNegative : 1;  // Negated OffsetReg? (~'U' bit)
396  };
397
398  struct PostIdxRegOp {
399    unsigned RegNum;
400    bool isAdd;
401    ARM_AM::ShiftOpc ShiftTy;
402    unsigned ShiftImm;
403  };
404
405  struct ShifterImmOp {
406    bool isASR;
407    unsigned Imm;
408  };
409
410  struct RegShiftedRegOp {
411    ARM_AM::ShiftOpc ShiftTy;
412    unsigned SrcReg;
413    unsigned ShiftReg;
414    unsigned ShiftImm;
415  };
416
417  struct RegShiftedImmOp {
418    ARM_AM::ShiftOpc ShiftTy;
419    unsigned SrcReg;
420    unsigned ShiftImm;
421  };
422
423  struct RotImmOp {
424    unsigned Imm;
425  };
426
427  struct BitfieldOp {
428    unsigned LSB;
429    unsigned Width;
430  };
431
432  union {
433    struct CCOp CC;
434    struct CopOp Cop;
435    struct CoprocOptionOp CoprocOption;
436    struct MBOptOp MBOpt;
437    struct ISBOptOp ISBOpt;
438    struct ITMaskOp ITMask;
439    struct IFlagsOp IFlags;
440    struct MMaskOp MMask;
441    struct TokOp Tok;
442    struct RegOp Reg;
443    struct VectorListOp VectorList;
444    struct VectorIndexOp VectorIndex;
445    struct ImmOp Imm;
446    struct MemoryOp Memory;
447    struct PostIdxRegOp PostIdxReg;
448    struct ShifterImmOp ShifterImm;
449    struct RegShiftedRegOp RegShiftedReg;
450    struct RegShiftedImmOp RegShiftedImm;
451    struct RotImmOp RotImm;
452    struct BitfieldOp Bitfield;
453  };
454
455  ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
456public:
457  ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
458    Kind = o.Kind;
459    StartLoc = o.StartLoc;
460    EndLoc = o.EndLoc;
461    switch (Kind) {
462    case k_CondCode:
463      CC = o.CC;
464      break;
465    case k_ITCondMask:
466      ITMask = o.ITMask;
467      break;
468    case k_Token:
469      Tok = o.Tok;
470      break;
471    case k_CCOut:
472    case k_Register:
473      Reg = o.Reg;
474      break;
475    case k_RegisterList:
476    case k_DPRRegisterList:
477    case k_SPRRegisterList:
478      Registers = o.Registers;
479      break;
480    case k_VectorList:
481    case k_VectorListAllLanes:
482    case k_VectorListIndexed:
483      VectorList = o.VectorList;
484      break;
485    case k_CoprocNum:
486    case k_CoprocReg:
487      Cop = o.Cop;
488      break;
489    case k_CoprocOption:
490      CoprocOption = o.CoprocOption;
491      break;
492    case k_Immediate:
493      Imm = o.Imm;
494      break;
495    case k_MemBarrierOpt:
496      MBOpt = o.MBOpt;
497      break;
498    case k_InstSyncBarrierOpt:
499      ISBOpt = o.ISBOpt;
500    case k_Memory:
501      Memory = o.Memory;
502      break;
503    case k_PostIndexRegister:
504      PostIdxReg = o.PostIdxReg;
505      break;
506    case k_MSRMask:
507      MMask = o.MMask;
508      break;
509    case k_ProcIFlags:
510      IFlags = o.IFlags;
511      break;
512    case k_ShifterImmediate:
513      ShifterImm = o.ShifterImm;
514      break;
515    case k_ShiftedRegister:
516      RegShiftedReg = o.RegShiftedReg;
517      break;
518    case k_ShiftedImmediate:
519      RegShiftedImm = o.RegShiftedImm;
520      break;
521    case k_RotateImmediate:
522      RotImm = o.RotImm;
523      break;
524    case k_BitfieldDescriptor:
525      Bitfield = o.Bitfield;
526      break;
527    case k_VectorIndex:
528      VectorIndex = o.VectorIndex;
529      break;
530    }
531  }
532
533  /// getStartLoc - Get the location of the first token of this operand.
534  SMLoc getStartLoc() const { return StartLoc; }
535  /// getEndLoc - Get the location of the last token of this operand.
536  SMLoc getEndLoc() const { return EndLoc; }
537  /// getLocRange - Get the range between the first and last token of this
538  /// operand.
539  SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
540
541  ARMCC::CondCodes getCondCode() const {
542    assert(Kind == k_CondCode && "Invalid access!");
543    return CC.Val;
544  }
545
546  unsigned getCoproc() const {
547    assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
548    return Cop.Val;
549  }
550
551  StringRef getToken() const {
552    assert(Kind == k_Token && "Invalid access!");
553    return StringRef(Tok.Data, Tok.Length);
554  }
555
556  unsigned getReg() const {
557    assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
558    return Reg.RegNum;
559  }
560
561  const SmallVectorImpl<unsigned> &getRegList() const {
562    assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
563            Kind == k_SPRRegisterList) && "Invalid access!");
564    return Registers;
565  }
566
567  const MCExpr *getImm() const {
568    assert(isImm() && "Invalid access!");
569    return Imm.Val;
570  }
571
572  unsigned getVectorIndex() const {
573    assert(Kind == k_VectorIndex && "Invalid access!");
574    return VectorIndex.Val;
575  }
576
577  ARM_MB::MemBOpt getMemBarrierOpt() const {
578    assert(Kind == k_MemBarrierOpt && "Invalid access!");
579    return MBOpt.Val;
580  }
581
582  ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const {
583    assert(Kind == k_InstSyncBarrierOpt && "Invalid access!");
584    return ISBOpt.Val;
585  }
586
587  ARM_PROC::IFlags getProcIFlags() const {
588    assert(Kind == k_ProcIFlags && "Invalid access!");
589    return IFlags.Val;
590  }
591
592  unsigned getMSRMask() const {
593    assert(Kind == k_MSRMask && "Invalid access!");
594    return MMask.Val;
595  }
596
597  bool isCoprocNum() const { return Kind == k_CoprocNum; }
598  bool isCoprocReg() const { return Kind == k_CoprocReg; }
599  bool isCoprocOption() const { return Kind == k_CoprocOption; }
600  bool isCondCode() const { return Kind == k_CondCode; }
601  bool isCCOut() const { return Kind == k_CCOut; }
602  bool isITMask() const { return Kind == k_ITCondMask; }
603  bool isITCondCode() const { return Kind == k_CondCode; }
604  bool isImm() const { return Kind == k_Immediate; }
605  // checks whether this operand is an unsigned offset which fits is a field
606  // of specified width and scaled by a specific number of bits
607  template<unsigned width, unsigned scale>
608  bool isUnsignedOffset() const {
609    if (!isImm()) return false;
610    if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
611    if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
612      int64_t Val = CE->getValue();
613      int64_t Align = 1LL << scale;
614      int64_t Max = Align * ((1LL << width) - 1);
615      return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max);
616    }
617    return false;
618  }
619  // checks whether this operand is an signed offset which fits is a field
620  // of specified width and scaled by a specific number of bits
621  template<unsigned width, unsigned scale>
622  bool isSignedOffset() const {
623    if (!isImm()) return false;
624    if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
625    if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
626      int64_t Val = CE->getValue();
627      int64_t Align = 1LL << scale;
628      int64_t Max = Align * ((1LL << (width-1)) - 1);
629      int64_t Min = -Align * (1LL << (width-1));
630      return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max);
631    }
632    return false;
633  }
634
635  // checks whether this operand is a memory operand computed as an offset
636  // applied to PC. the offset may have 8 bits of magnitude and is represented
637  // with two bits of shift. textually it may be either [pc, #imm], #imm or
638  // relocable expression...
639  bool isThumbMemPC() const {
640    int64_t Val = 0;
641    if (isImm()) {
642      if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
643      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val);
644      if (!CE) return false;
645      Val = CE->getValue();
646    }
647    else if (isMem()) {
648      if(!Memory.OffsetImm || Memory.OffsetRegNum) return false;
649      if(Memory.BaseRegNum != ARM::PC) return false;
650      Val = Memory.OffsetImm->getValue();
651    }
652    else return false;
653    return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020);
654  }
655  bool isFPImm() const {
656    if (!isImm()) return false;
657    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
658    if (!CE) return false;
659    int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
660    return Val != -1;
661  }
662  bool isFBits16() const {
663    if (!isImm()) return false;
664    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
665    if (!CE) return false;
666    int64_t Value = CE->getValue();
667    return Value >= 0 && Value <= 16;
668  }
669  bool isFBits32() const {
670    if (!isImm()) return false;
671    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
672    if (!CE) return false;
673    int64_t Value = CE->getValue();
674    return Value >= 1 && Value <= 32;
675  }
676  bool isImm8s4() const {
677    if (!isImm()) return false;
678    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
679    if (!CE) return false;
680    int64_t Value = CE->getValue();
681    return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
682  }
683  bool isImm0_1020s4() const {
684    if (!isImm()) return false;
685    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
686    if (!CE) return false;
687    int64_t Value = CE->getValue();
688    return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
689  }
690  bool isImm0_508s4() const {
691    if (!isImm()) return false;
692    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
693    if (!CE) return false;
694    int64_t Value = CE->getValue();
695    return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
696  }
697  bool isImm0_508s4Neg() const {
698    if (!isImm()) return false;
699    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
700    if (!CE) return false;
701    int64_t Value = -CE->getValue();
702    // explicitly exclude zero. we want that to use the normal 0_508 version.
703    return ((Value & 3) == 0) && Value > 0 && Value <= 508;
704  }
705  bool isImm0_255() const {
706    if (!isImm()) return false;
707    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
708    if (!CE) return false;
709    int64_t Value = CE->getValue();
710    return Value >= 0 && Value < 256;
711  }
712  bool isImm0_4095() const {
713    if (!isImm()) return false;
714    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
715    if (!CE) return false;
716    int64_t Value = CE->getValue();
717    return Value >= 0 && Value < 4096;
718  }
719  bool isImm0_4095Neg() const {
720    if (!isImm()) return false;
721    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
722    if (!CE) return false;
723    int64_t Value = -CE->getValue();
724    return Value > 0 && Value < 4096;
725  }
726  bool isImm0_1() const {
727    if (!isImm()) return false;
728    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
729    if (!CE) return false;
730    int64_t Value = CE->getValue();
731    return Value >= 0 && Value < 2;
732  }
733  bool isImm0_3() const {
734    if (!isImm()) return false;
735    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
736    if (!CE) return false;
737    int64_t Value = CE->getValue();
738    return Value >= 0 && Value < 4;
739  }
740  bool isImm0_7() const {
741    if (!isImm()) return false;
742    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
743    if (!CE) return false;
744    int64_t Value = CE->getValue();
745    return Value >= 0 && Value < 8;
746  }
747  bool isImm0_15() const {
748    if (!isImm()) return false;
749    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
750    if (!CE) return false;
751    int64_t Value = CE->getValue();
752    return Value >= 0 && Value < 16;
753  }
754  bool isImm0_31() const {
755    if (!isImm()) return false;
756    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
757    if (!CE) return false;
758    int64_t Value = CE->getValue();
759    return Value >= 0 && Value < 32;
760  }
761  bool isImm0_63() const {
762    if (!isImm()) return false;
763    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
764    if (!CE) return false;
765    int64_t Value = CE->getValue();
766    return Value >= 0 && Value < 64;
767  }
768  bool isImm8() const {
769    if (!isImm()) return false;
770    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
771    if (!CE) return false;
772    int64_t Value = CE->getValue();
773    return Value == 8;
774  }
775  bool isImm16() const {
776    if (!isImm()) return false;
777    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
778    if (!CE) return false;
779    int64_t Value = CE->getValue();
780    return Value == 16;
781  }
782  bool isImm32() const {
783    if (!isImm()) return false;
784    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
785    if (!CE) return false;
786    int64_t Value = CE->getValue();
787    return Value == 32;
788  }
789  bool isShrImm8() const {
790    if (!isImm()) return false;
791    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
792    if (!CE) return false;
793    int64_t Value = CE->getValue();
794    return Value > 0 && Value <= 8;
795  }
796  bool isShrImm16() const {
797    if (!isImm()) return false;
798    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
799    if (!CE) return false;
800    int64_t Value = CE->getValue();
801    return Value > 0 && Value <= 16;
802  }
803  bool isShrImm32() const {
804    if (!isImm()) return false;
805    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
806    if (!CE) return false;
807    int64_t Value = CE->getValue();
808    return Value > 0 && Value <= 32;
809  }
810  bool isShrImm64() const {
811    if (!isImm()) return false;
812    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
813    if (!CE) return false;
814    int64_t Value = CE->getValue();
815    return Value > 0 && Value <= 64;
816  }
817  bool isImm1_7() const {
818    if (!isImm()) return false;
819    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
820    if (!CE) return false;
821    int64_t Value = CE->getValue();
822    return Value > 0 && Value < 8;
823  }
824  bool isImm1_15() const {
825    if (!isImm()) return false;
826    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
827    if (!CE) return false;
828    int64_t Value = CE->getValue();
829    return Value > 0 && Value < 16;
830  }
831  bool isImm1_31() const {
832    if (!isImm()) return false;
833    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
834    if (!CE) return false;
835    int64_t Value = CE->getValue();
836    return Value > 0 && Value < 32;
837  }
838  bool isImm1_16() const {
839    if (!isImm()) return false;
840    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
841    if (!CE) return false;
842    int64_t Value = CE->getValue();
843    return Value > 0 && Value < 17;
844  }
845  bool isImm1_32() const {
846    if (!isImm()) return false;
847    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
848    if (!CE) return false;
849    int64_t Value = CE->getValue();
850    return Value > 0 && Value < 33;
851  }
852  bool isImm0_32() const {
853    if (!isImm()) return false;
854    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
855    if (!CE) return false;
856    int64_t Value = CE->getValue();
857    return Value >= 0 && Value < 33;
858  }
859  bool isImm0_65535() const {
860    if (!isImm()) return false;
861    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
862    if (!CE) return false;
863    int64_t Value = CE->getValue();
864    return Value >= 0 && Value < 65536;
865  }
866  bool isImm256_65535Expr() const {
867    if (!isImm()) return false;
868    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
869    // If it's not a constant expression, it'll generate a fixup and be
870    // handled later.
871    if (!CE) return true;
872    int64_t Value = CE->getValue();
873    return Value >= 256 && Value < 65536;
874  }
875  bool isImm0_65535Expr() const {
876    if (!isImm()) return false;
877    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
878    // If it's not a constant expression, it'll generate a fixup and be
879    // handled later.
880    if (!CE) return true;
881    int64_t Value = CE->getValue();
882    return Value >= 0 && Value < 65536;
883  }
884  bool isImm24bit() const {
885    if (!isImm()) return false;
886    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
887    if (!CE) return false;
888    int64_t Value = CE->getValue();
889    return Value >= 0 && Value <= 0xffffff;
890  }
891  bool isImmThumbSR() const {
892    if (!isImm()) return false;
893    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
894    if (!CE) return false;
895    int64_t Value = CE->getValue();
896    return Value > 0 && Value < 33;
897  }
898  bool isPKHLSLImm() const {
899    if (!isImm()) return false;
900    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
901    if (!CE) return false;
902    int64_t Value = CE->getValue();
903    return Value >= 0 && Value < 32;
904  }
905  bool isPKHASRImm() const {
906    if (!isImm()) return false;
907    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
908    if (!CE) return false;
909    int64_t Value = CE->getValue();
910    return Value > 0 && Value <= 32;
911  }
912  bool isAdrLabel() const {
913    // If we have an immediate that's not a constant, treat it as a label
914    // reference needing a fixup. If it is a constant, but it can't fit
915    // into shift immediate encoding, we reject it.
916    if (isImm() && !isa<MCConstantExpr>(getImm())) return true;
917    else return (isARMSOImm() || isARMSOImmNeg());
918  }
919  bool isARMSOImm() const {
920    if (!isImm()) return false;
921    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
922    if (!CE) return false;
923    int64_t Value = CE->getValue();
924    return ARM_AM::getSOImmVal(Value) != -1;
925  }
926  bool isARMSOImmNot() const {
927    if (!isImm()) return false;
928    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
929    if (!CE) return false;
930    int64_t Value = CE->getValue();
931    return ARM_AM::getSOImmVal(~Value) != -1;
932  }
933  bool isARMSOImmNeg() const {
934    if (!isImm()) return false;
935    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
936    if (!CE) return false;
937    int64_t Value = CE->getValue();
938    // Only use this when not representable as a plain so_imm.
939    return ARM_AM::getSOImmVal(Value) == -1 &&
940      ARM_AM::getSOImmVal(-Value) != -1;
941  }
942  bool isT2SOImm() const {
943    if (!isImm()) return false;
944    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
945    if (!CE) return false;
946    int64_t Value = CE->getValue();
947    return ARM_AM::getT2SOImmVal(Value) != -1;
948  }
949  bool isT2SOImmNot() const {
950    if (!isImm()) return false;
951    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
952    if (!CE) return false;
953    int64_t Value = CE->getValue();
954    return ARM_AM::getT2SOImmVal(Value) == -1 &&
955      ARM_AM::getT2SOImmVal(~Value) != -1;
956  }
957  bool isT2SOImmNeg() const {
958    if (!isImm()) return false;
959    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
960    if (!CE) return false;
961    int64_t Value = CE->getValue();
962    // Only use this when not representable as a plain so_imm.
963    return ARM_AM::getT2SOImmVal(Value) == -1 &&
964      ARM_AM::getT2SOImmVal(-Value) != -1;
965  }
966  bool isSetEndImm() const {
967    if (!isImm()) return false;
968    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
969    if (!CE) return false;
970    int64_t Value = CE->getValue();
971    return Value == 1 || Value == 0;
972  }
973  bool isReg() const { return Kind == k_Register; }
974  bool isRegList() const { return Kind == k_RegisterList; }
975  bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
976  bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
977  bool isToken() const { return Kind == k_Token; }
978  bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
979  bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
980  bool isMem() const { return Kind == k_Memory; }
981  bool isShifterImm() const { return Kind == k_ShifterImmediate; }
982  bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
983  bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
984  bool isRotImm() const { return Kind == k_RotateImmediate; }
985  bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
986  bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
987  bool isPostIdxReg() const {
988    return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
989  }
990  bool isMemNoOffset(bool alignOK = false) const {
991    if (!isMem())
992      return false;
993    // No offset of any kind.
994    return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 &&
995     (alignOK || Memory.Alignment == 0);
996  }
997  bool isMemPCRelImm12() const {
998    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
999      return false;
1000    // Base register must be PC.
1001    if (Memory.BaseRegNum != ARM::PC)
1002      return false;
1003    // Immediate offset in range [-4095, 4095].
1004    if (!Memory.OffsetImm) return true;
1005    int64_t Val = Memory.OffsetImm->getValue();
1006    return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1007  }
1008  bool isAlignedMemory() const {
1009    return isMemNoOffset(true);
1010  }
1011  bool isAddrMode2() const {
1012    if (!isMem() || Memory.Alignment != 0) return false;
1013    // Check for register offset.
1014    if (Memory.OffsetRegNum) return true;
1015    // Immediate offset in range [-4095, 4095].
1016    if (!Memory.OffsetImm) return true;
1017    int64_t Val = Memory.OffsetImm->getValue();
1018    return Val > -4096 && Val < 4096;
1019  }
1020  bool isAM2OffsetImm() const {
1021    if (!isImm()) return false;
1022    // Immediate offset in range [-4095, 4095].
1023    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1024    if (!CE) return false;
1025    int64_t Val = CE->getValue();
1026    return (Val == INT32_MIN) || (Val > -4096 && Val < 4096);
1027  }
1028  bool isAddrMode3() const {
1029    // If we have an immediate that's not a constant, treat it as a label
1030    // reference needing a fixup. If it is a constant, it's something else
1031    // and we reject it.
1032    if (isImm() && !isa<MCConstantExpr>(getImm()))
1033      return true;
1034    if (!isMem() || Memory.Alignment != 0) return false;
1035    // No shifts are legal for AM3.
1036    if (Memory.ShiftType != ARM_AM::no_shift) return false;
1037    // Check for register offset.
1038    if (Memory.OffsetRegNum) return true;
1039    // Immediate offset in range [-255, 255].
1040    if (!Memory.OffsetImm) return true;
1041    int64_t Val = Memory.OffsetImm->getValue();
1042    // The #-0 offset is encoded as INT32_MIN, and we have to check
1043    // for this too.
1044    return (Val > -256 && Val < 256) || Val == INT32_MIN;
1045  }
1046  bool isAM3Offset() const {
1047    if (Kind != k_Immediate && Kind != k_PostIndexRegister)
1048      return false;
1049    if (Kind == k_PostIndexRegister)
1050      return PostIdxReg.ShiftTy == ARM_AM::no_shift;
1051    // Immediate offset in range [-255, 255].
1052    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1053    if (!CE) return false;
1054    int64_t Val = CE->getValue();
1055    // Special case, #-0 is INT32_MIN.
1056    return (Val > -256 && Val < 256) || Val == INT32_MIN;
1057  }
1058  bool isAddrMode5() const {
1059    // If we have an immediate that's not a constant, treat it as a label
1060    // reference needing a fixup. If it is a constant, it's something else
1061    // and we reject it.
1062    if (isImm() && !isa<MCConstantExpr>(getImm()))
1063      return true;
1064    if (!isMem() || Memory.Alignment != 0) return false;
1065    // Check for register offset.
1066    if (Memory.OffsetRegNum) return false;
1067    // Immediate offset in range [-1020, 1020] and a multiple of 4.
1068    if (!Memory.OffsetImm) return true;
1069    int64_t Val = Memory.OffsetImm->getValue();
1070    return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
1071      Val == INT32_MIN;
1072  }
1073  bool isMemTBB() const {
1074    if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1075        Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1076      return false;
1077    return true;
1078  }
1079  bool isMemTBH() const {
1080    if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1081        Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1082        Memory.Alignment != 0 )
1083      return false;
1084    return true;
1085  }
1086  bool isMemRegOffset() const {
1087    if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
1088      return false;
1089    return true;
1090  }
1091  bool isT2MemRegOffset() const {
1092    if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1093        Memory.Alignment != 0)
1094      return false;
1095    // Only lsl #{0, 1, 2, 3} allowed.
1096    if (Memory.ShiftType == ARM_AM::no_shift)
1097      return true;
1098    if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1099      return false;
1100    return true;
1101  }
1102  bool isMemThumbRR() const {
1103    // Thumb reg+reg addressing is simple. Just two registers, a base and
1104    // an offset. No shifts, negations or any other complicating factors.
1105    if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1106        Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1107      return false;
1108    return isARMLowRegister(Memory.BaseRegNum) &&
1109      (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
1110  }
1111  bool isMemThumbRIs4() const {
1112    if (!isMem() || Memory.OffsetRegNum != 0 ||
1113        !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1114      return false;
1115    // Immediate offset, multiple of 4 in range [0, 124].
1116    if (!Memory.OffsetImm) return true;
1117    int64_t Val = Memory.OffsetImm->getValue();
1118    return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1119  }
1120  bool isMemThumbRIs2() const {
1121    if (!isMem() || Memory.OffsetRegNum != 0 ||
1122        !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1123      return false;
1124    // Immediate offset, multiple of 4 in range [0, 62].
1125    if (!Memory.OffsetImm) return true;
1126    int64_t Val = Memory.OffsetImm->getValue();
1127    return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1128  }
1129  bool isMemThumbRIs1() const {
1130    if (!isMem() || Memory.OffsetRegNum != 0 ||
1131        !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1132      return false;
1133    // Immediate offset in range [0, 31].
1134    if (!Memory.OffsetImm) return true;
1135    int64_t Val = Memory.OffsetImm->getValue();
1136    return Val >= 0 && Val <= 31;
1137  }
1138  bool isMemThumbSPI() const {
1139    if (!isMem() || Memory.OffsetRegNum != 0 ||
1140        Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1141      return false;
1142    // Immediate offset, multiple of 4 in range [0, 1020].
1143    if (!Memory.OffsetImm) return true;
1144    int64_t Val = Memory.OffsetImm->getValue();
1145    return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1146  }
1147  bool isMemImm8s4Offset() const {
1148    // If we have an immediate that's not a constant, treat it as a label
1149    // reference needing a fixup. If it is a constant, it's something else
1150    // and we reject it.
1151    if (isImm() && !isa<MCConstantExpr>(getImm()))
1152      return true;
1153    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1154      return false;
1155    // Immediate offset a multiple of 4 in range [-1020, 1020].
1156    if (!Memory.OffsetImm) return true;
1157    int64_t Val = Memory.OffsetImm->getValue();
1158    // Special case, #-0 is INT32_MIN.
1159    return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN;
1160  }
1161  bool isMemImm0_1020s4Offset() const {
1162    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1163      return false;
1164    // Immediate offset a multiple of 4 in range [0, 1020].
1165    if (!Memory.OffsetImm) return true;
1166    int64_t Val = Memory.OffsetImm->getValue();
1167    return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1168  }
1169  bool isMemImm8Offset() const {
1170    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1171      return false;
1172    // Base reg of PC isn't allowed for these encodings.
1173    if (Memory.BaseRegNum == ARM::PC) return false;
1174    // Immediate offset in range [-255, 255].
1175    if (!Memory.OffsetImm) return true;
1176    int64_t Val = Memory.OffsetImm->getValue();
1177    return (Val == INT32_MIN) || (Val > -256 && Val < 256);
1178  }
1179  bool isMemPosImm8Offset() const {
1180    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1181      return false;
1182    // Immediate offset in range [0, 255].
1183    if (!Memory.OffsetImm) return true;
1184    int64_t Val = Memory.OffsetImm->getValue();
1185    return Val >= 0 && Val < 256;
1186  }
1187  bool isMemNegImm8Offset() const {
1188    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1189      return false;
1190    // Base reg of PC isn't allowed for these encodings.
1191    if (Memory.BaseRegNum == ARM::PC) return false;
1192    // Immediate offset in range [-255, -1].
1193    if (!Memory.OffsetImm) return false;
1194    int64_t Val = Memory.OffsetImm->getValue();
1195    return (Val == INT32_MIN) || (Val > -256 && Val < 0);
1196  }
1197  bool isMemUImm12Offset() const {
1198    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1199      return false;
1200    // Immediate offset in range [0, 4095].
1201    if (!Memory.OffsetImm) return true;
1202    int64_t Val = Memory.OffsetImm->getValue();
1203    return (Val >= 0 && Val < 4096);
1204  }
1205  bool isMemImm12Offset() const {
1206    // If we have an immediate that's not a constant, treat it as a label
1207    // reference needing a fixup. If it is a constant, it's something else
1208    // and we reject it.
1209    if (isImm() && !isa<MCConstantExpr>(getImm()))
1210      return true;
1211
1212    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1213      return false;
1214    // Immediate offset in range [-4095, 4095].
1215    if (!Memory.OffsetImm) return true;
1216    int64_t Val = Memory.OffsetImm->getValue();
1217    return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1218  }
1219  bool isPostIdxImm8() const {
1220    if (!isImm()) return false;
1221    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1222    if (!CE) return false;
1223    int64_t Val = CE->getValue();
1224    return (Val > -256 && Val < 256) || (Val == INT32_MIN);
1225  }
1226  bool isPostIdxImm8s4() const {
1227    if (!isImm()) return false;
1228    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1229    if (!CE) return false;
1230    int64_t Val = CE->getValue();
1231    return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1232      (Val == INT32_MIN);
1233  }
1234
1235  bool isMSRMask() const { return Kind == k_MSRMask; }
1236  bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1237
1238  // NEON operands.
1239  bool isSingleSpacedVectorList() const {
1240    return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1241  }
1242  bool isDoubleSpacedVectorList() const {
1243    return Kind == k_VectorList && VectorList.isDoubleSpaced;
1244  }
1245  bool isVecListOneD() const {
1246    if (!isSingleSpacedVectorList()) return false;
1247    return VectorList.Count == 1;
1248  }
1249
1250  bool isVecListDPair() const {
1251    if (!isSingleSpacedVectorList()) return false;
1252    return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1253              .contains(VectorList.RegNum));
1254  }
1255
1256  bool isVecListThreeD() const {
1257    if (!isSingleSpacedVectorList()) return false;
1258    return VectorList.Count == 3;
1259  }
1260
1261  bool isVecListFourD() const {
1262    if (!isSingleSpacedVectorList()) return false;
1263    return VectorList.Count == 4;
1264  }
1265
1266  bool isVecListDPairSpaced() const {
1267    if (isSingleSpacedVectorList()) return false;
1268    return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1269              .contains(VectorList.RegNum));
1270  }
1271
1272  bool isVecListThreeQ() const {
1273    if (!isDoubleSpacedVectorList()) return false;
1274    return VectorList.Count == 3;
1275  }
1276
1277  bool isVecListFourQ() const {
1278    if (!isDoubleSpacedVectorList()) return false;
1279    return VectorList.Count == 4;
1280  }
1281
1282  bool isSingleSpacedVectorAllLanes() const {
1283    return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1284  }
1285  bool isDoubleSpacedVectorAllLanes() const {
1286    return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1287  }
1288  bool isVecListOneDAllLanes() const {
1289    if (!isSingleSpacedVectorAllLanes()) return false;
1290    return VectorList.Count == 1;
1291  }
1292
1293  bool isVecListDPairAllLanes() const {
1294    if (!isSingleSpacedVectorAllLanes()) return false;
1295    return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1296              .contains(VectorList.RegNum));
1297  }
1298
1299  bool isVecListDPairSpacedAllLanes() const {
1300    if (!isDoubleSpacedVectorAllLanes()) return false;
1301    return VectorList.Count == 2;
1302  }
1303
1304  bool isVecListThreeDAllLanes() const {
1305    if (!isSingleSpacedVectorAllLanes()) return false;
1306    return VectorList.Count == 3;
1307  }
1308
1309  bool isVecListThreeQAllLanes() const {
1310    if (!isDoubleSpacedVectorAllLanes()) return false;
1311    return VectorList.Count == 3;
1312  }
1313
1314  bool isVecListFourDAllLanes() const {
1315    if (!isSingleSpacedVectorAllLanes()) return false;
1316    return VectorList.Count == 4;
1317  }
1318
1319  bool isVecListFourQAllLanes() const {
1320    if (!isDoubleSpacedVectorAllLanes()) return false;
1321    return VectorList.Count == 4;
1322  }
1323
1324  bool isSingleSpacedVectorIndexed() const {
1325    return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1326  }
1327  bool isDoubleSpacedVectorIndexed() const {
1328    return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1329  }
1330  bool isVecListOneDByteIndexed() const {
1331    if (!isSingleSpacedVectorIndexed()) return false;
1332    return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1333  }
1334
1335  bool isVecListOneDHWordIndexed() const {
1336    if (!isSingleSpacedVectorIndexed()) return false;
1337    return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1338  }
1339
1340  bool isVecListOneDWordIndexed() const {
1341    if (!isSingleSpacedVectorIndexed()) return false;
1342    return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1343  }
1344
1345  bool isVecListTwoDByteIndexed() const {
1346    if (!isSingleSpacedVectorIndexed()) return false;
1347    return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1348  }
1349
1350  bool isVecListTwoDHWordIndexed() const {
1351    if (!isSingleSpacedVectorIndexed()) return false;
1352    return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1353  }
1354
1355  bool isVecListTwoQWordIndexed() const {
1356    if (!isDoubleSpacedVectorIndexed()) return false;
1357    return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1358  }
1359
1360  bool isVecListTwoQHWordIndexed() const {
1361    if (!isDoubleSpacedVectorIndexed()) return false;
1362    return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1363  }
1364
1365  bool isVecListTwoDWordIndexed() const {
1366    if (!isSingleSpacedVectorIndexed()) return false;
1367    return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1368  }
1369
1370  bool isVecListThreeDByteIndexed() const {
1371    if (!isSingleSpacedVectorIndexed()) return false;
1372    return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
1373  }
1374
1375  bool isVecListThreeDHWordIndexed() const {
1376    if (!isSingleSpacedVectorIndexed()) return false;
1377    return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1378  }
1379
1380  bool isVecListThreeQWordIndexed() const {
1381    if (!isDoubleSpacedVectorIndexed()) return false;
1382    return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1383  }
1384
1385  bool isVecListThreeQHWordIndexed() const {
1386    if (!isDoubleSpacedVectorIndexed()) return false;
1387    return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1388  }
1389
1390  bool isVecListThreeDWordIndexed() const {
1391    if (!isSingleSpacedVectorIndexed()) return false;
1392    return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1393  }
1394
1395  bool isVecListFourDByteIndexed() const {
1396    if (!isSingleSpacedVectorIndexed()) return false;
1397    return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
1398  }
1399
1400  bool isVecListFourDHWordIndexed() const {
1401    if (!isSingleSpacedVectorIndexed()) return false;
1402    return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1403  }
1404
1405  bool isVecListFourQWordIndexed() const {
1406    if (!isDoubleSpacedVectorIndexed()) return false;
1407    return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1408  }
1409
1410  bool isVecListFourQHWordIndexed() const {
1411    if (!isDoubleSpacedVectorIndexed()) return false;
1412    return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1413  }
1414
1415  bool isVecListFourDWordIndexed() const {
1416    if (!isSingleSpacedVectorIndexed()) return false;
1417    return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1418  }
1419
1420  bool isVectorIndex8() const {
1421    if (Kind != k_VectorIndex) return false;
1422    return VectorIndex.Val < 8;
1423  }
1424  bool isVectorIndex16() const {
1425    if (Kind != k_VectorIndex) return false;
1426    return VectorIndex.Val < 4;
1427  }
1428  bool isVectorIndex32() const {
1429    if (Kind != k_VectorIndex) return false;
1430    return VectorIndex.Val < 2;
1431  }
1432
1433  bool isNEONi8splat() const {
1434    if (!isImm()) return false;
1435    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1436    // Must be a constant.
1437    if (!CE) return false;
1438    int64_t Value = CE->getValue();
1439    // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1440    // value.
1441    return Value >= 0 && Value < 256;
1442  }
1443
1444  bool isNEONi16splat() const {
1445    if (!isImm()) return false;
1446    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1447    // Must be a constant.
1448    if (!CE) return false;
1449    int64_t Value = CE->getValue();
1450    // i16 value in the range [0,255] or [0x0100, 0xff00]
1451    return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00);
1452  }
1453
1454  bool isNEONi32splat() const {
1455    if (!isImm()) return false;
1456    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1457    // Must be a constant.
1458    if (!CE) return false;
1459    int64_t Value = CE->getValue();
1460    // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
1461    return (Value >= 0 && Value < 256) ||
1462      (Value >= 0x0100 && Value <= 0xff00) ||
1463      (Value >= 0x010000 && Value <= 0xff0000) ||
1464      (Value >= 0x01000000 && Value <= 0xff000000);
1465  }
1466
1467  bool isNEONi32vmov() const {
1468    if (!isImm()) return false;
1469    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1470    // Must be a constant.
1471    if (!CE) return false;
1472    int64_t Value = CE->getValue();
1473    // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1474    // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1475    return (Value >= 0 && Value < 256) ||
1476      (Value >= 0x0100 && Value <= 0xff00) ||
1477      (Value >= 0x010000 && Value <= 0xff0000) ||
1478      (Value >= 0x01000000 && Value <= 0xff000000) ||
1479      (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1480      (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1481  }
1482  bool isNEONi32vmovNeg() const {
1483    if (!isImm()) return false;
1484    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1485    // Must be a constant.
1486    if (!CE) return false;
1487    int64_t Value = ~CE->getValue();
1488    // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1489    // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1490    return (Value >= 0 && Value < 256) ||
1491      (Value >= 0x0100 && Value <= 0xff00) ||
1492      (Value >= 0x010000 && Value <= 0xff0000) ||
1493      (Value >= 0x01000000 && Value <= 0xff000000) ||
1494      (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1495      (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1496  }
1497
1498  bool isNEONi64splat() const {
1499    if (!isImm()) return false;
1500    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1501    // Must be a constant.
1502    if (!CE) return false;
1503    uint64_t Value = CE->getValue();
1504    // i64 value with each byte being either 0 or 0xff.
1505    for (unsigned i = 0; i < 8; ++i)
1506      if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1507    return true;
1508  }
1509
1510  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1511    // Add as immediates when possible.  Null MCExpr = 0.
1512    if (Expr == 0)
1513      Inst.addOperand(MCOperand::CreateImm(0));
1514    else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1515      Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1516    else
1517      Inst.addOperand(MCOperand::CreateExpr(Expr));
1518  }
1519
1520  void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1521    assert(N == 2 && "Invalid number of operands!");
1522    Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1523    unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1524    Inst.addOperand(MCOperand::CreateReg(RegNum));
1525  }
1526
1527  void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1528    assert(N == 1 && "Invalid number of operands!");
1529    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1530  }
1531
1532  void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1533    assert(N == 1 && "Invalid number of operands!");
1534    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1535  }
1536
1537  void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1538    assert(N == 1 && "Invalid number of operands!");
1539    Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1540  }
1541
1542  void addITMaskOperands(MCInst &Inst, unsigned N) const {
1543    assert(N == 1 && "Invalid number of operands!");
1544    Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1545  }
1546
1547  void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1548    assert(N == 1 && "Invalid number of operands!");
1549    Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1550  }
1551
1552  void addCCOutOperands(MCInst &Inst, unsigned N) const {
1553    assert(N == 1 && "Invalid number of operands!");
1554    Inst.addOperand(MCOperand::CreateReg(getReg()));
1555  }
1556
1557  void addRegOperands(MCInst &Inst, unsigned N) const {
1558    assert(N == 1 && "Invalid number of operands!");
1559    Inst.addOperand(MCOperand::CreateReg(getReg()));
1560  }
1561
1562  void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1563    assert(N == 3 && "Invalid number of operands!");
1564    assert(isRegShiftedReg() &&
1565           "addRegShiftedRegOperands() on non RegShiftedReg!");
1566    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1567    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1568    Inst.addOperand(MCOperand::CreateImm(
1569      ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1570  }
1571
1572  void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1573    assert(N == 2 && "Invalid number of operands!");
1574    assert(isRegShiftedImm() &&
1575           "addRegShiftedImmOperands() on non RegShiftedImm!");
1576    Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1577    // Shift of #32 is encoded as 0 where permitted
1578    unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
1579    Inst.addOperand(MCOperand::CreateImm(
1580      ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
1581  }
1582
1583  void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1584    assert(N == 1 && "Invalid number of operands!");
1585    Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1586                                         ShifterImm.Imm));
1587  }
1588
1589  void addRegListOperands(MCInst &Inst, unsigned N) const {
1590    assert(N == 1 && "Invalid number of operands!");
1591    const SmallVectorImpl<unsigned> &RegList = getRegList();
1592    for (SmallVectorImpl<unsigned>::const_iterator
1593           I = RegList.begin(), E = RegList.end(); I != E; ++I)
1594      Inst.addOperand(MCOperand::CreateReg(*I));
1595  }
1596
1597  void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1598    addRegListOperands(Inst, N);
1599  }
1600
1601  void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1602    addRegListOperands(Inst, N);
1603  }
1604
1605  void addRotImmOperands(MCInst &Inst, unsigned N) const {
1606    assert(N == 1 && "Invalid number of operands!");
1607    // Encoded as val>>3. The printer handles display as 8, 16, 24.
1608    Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1609  }
1610
1611  void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1612    assert(N == 1 && "Invalid number of operands!");
1613    // Munge the lsb/width into a bitfield mask.
1614    unsigned lsb = Bitfield.LSB;
1615    unsigned width = Bitfield.Width;
1616    // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1617    uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1618                      (32 - (lsb + width)));
1619    Inst.addOperand(MCOperand::CreateImm(Mask));
1620  }
1621
1622  void addImmOperands(MCInst &Inst, unsigned N) const {
1623    assert(N == 1 && "Invalid number of operands!");
1624    addExpr(Inst, getImm());
1625  }
1626
1627  void addFBits16Operands(MCInst &Inst, unsigned N) const {
1628    assert(N == 1 && "Invalid number of operands!");
1629    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1630    Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue()));
1631  }
1632
1633  void addFBits32Operands(MCInst &Inst, unsigned N) const {
1634    assert(N == 1 && "Invalid number of operands!");
1635    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1636    Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue()));
1637  }
1638
1639  void addFPImmOperands(MCInst &Inst, unsigned N) const {
1640    assert(N == 1 && "Invalid number of operands!");
1641    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1642    int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1643    Inst.addOperand(MCOperand::CreateImm(Val));
1644  }
1645
1646  void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1647    assert(N == 1 && "Invalid number of operands!");
1648    // FIXME: We really want to scale the value here, but the LDRD/STRD
1649    // instruction don't encode operands that way yet.
1650    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1651    Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1652  }
1653
1654  void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1655    assert(N == 1 && "Invalid number of operands!");
1656    // The immediate is scaled by four in the encoding and is stored
1657    // in the MCInst as such. Lop off the low two bits here.
1658    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1659    Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1660  }
1661
1662  void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
1663    assert(N == 1 && "Invalid number of operands!");
1664    // The immediate is scaled by four in the encoding and is stored
1665    // in the MCInst as such. Lop off the low two bits here.
1666    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1667    Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4)));
1668  }
1669
1670  void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1671    assert(N == 1 && "Invalid number of operands!");
1672    // The immediate is scaled by four in the encoding and is stored
1673    // in the MCInst as such. Lop off the low two bits here.
1674    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1675    Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1676  }
1677
1678  void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1679    assert(N == 1 && "Invalid number of operands!");
1680    // The constant encodes as the immediate-1, and we store in the instruction
1681    // the bits as encoded, so subtract off one here.
1682    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1683    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1684  }
1685
1686  void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1687    assert(N == 1 && "Invalid number of operands!");
1688    // The constant encodes as the immediate-1, and we store in the instruction
1689    // the bits as encoded, so subtract off one here.
1690    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1691    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1692  }
1693
1694  void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1695    assert(N == 1 && "Invalid number of operands!");
1696    // The constant encodes as the immediate, except for 32, which encodes as
1697    // zero.
1698    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1699    unsigned Imm = CE->getValue();
1700    Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1701  }
1702
1703  void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1704    assert(N == 1 && "Invalid number of operands!");
1705    // An ASR value of 32 encodes as 0, so that's how we want to add it to
1706    // the instruction as well.
1707    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1708    int Val = CE->getValue();
1709    Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1710  }
1711
1712  void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1713    assert(N == 1 && "Invalid number of operands!");
1714    // The operand is actually a t2_so_imm, but we have its bitwise
1715    // negation in the assembly source, so twiddle it here.
1716    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1717    Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1718  }
1719
1720  void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
1721    assert(N == 1 && "Invalid number of operands!");
1722    // The operand is actually a t2_so_imm, but we have its
1723    // negation in the assembly source, so twiddle it here.
1724    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1725    Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1726  }
1727
1728  void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
1729    assert(N == 1 && "Invalid number of operands!");
1730    // The operand is actually an imm0_4095, but we have its
1731    // negation in the assembly source, so twiddle it here.
1732    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1733    Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1734  }
1735
1736  void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
1737    if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
1738      Inst.addOperand(MCOperand::CreateImm(CE->getValue() >> 2));
1739      return;
1740    }
1741
1742    const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1743    assert(SR && "Unknown value type!");
1744    Inst.addOperand(MCOperand::CreateExpr(SR));
1745  }
1746
1747  void addThumbMemPCOperands(MCInst &Inst, unsigned N) const {
1748    assert(N == 1 && "Invalid number of operands!");
1749    if (isImm()) {
1750      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1751      if (CE) {
1752        Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1753        return;
1754      }
1755
1756      const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1757      assert(SR && "Unknown value type!");
1758      Inst.addOperand(MCOperand::CreateExpr(SR));
1759      return;
1760    }
1761
1762    assert(isMem()  && "Unknown value type!");
1763    assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!");
1764    Inst.addOperand(MCOperand::CreateImm(Memory.OffsetImm->getValue()));
1765  }
1766
1767  void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
1768    assert(N == 1 && "Invalid number of operands!");
1769    // The operand is actually a so_imm, but we have its bitwise
1770    // negation in the assembly source, so twiddle it here.
1771    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1772    Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1773  }
1774
1775  void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const {
1776    assert(N == 1 && "Invalid number of operands!");
1777    // The operand is actually a so_imm, but we have its
1778    // negation in the assembly source, so twiddle it here.
1779    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1780    Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1781  }
1782
1783  void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1784    assert(N == 1 && "Invalid number of operands!");
1785    Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1786  }
1787
1788  void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
1789    assert(N == 1 && "Invalid number of operands!");
1790    Inst.addOperand(MCOperand::CreateImm(unsigned(getInstSyncBarrierOpt())));
1791  }
1792
1793  void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1794    assert(N == 1 && "Invalid number of operands!");
1795    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1796  }
1797
1798  void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
1799    assert(N == 1 && "Invalid number of operands!");
1800    int32_t Imm = Memory.OffsetImm->getValue();
1801    Inst.addOperand(MCOperand::CreateImm(Imm));
1802  }
1803
1804  void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
1805    assert(N == 1 && "Invalid number of operands!");
1806    assert(isImm() && "Not an immediate!");
1807
1808    // If we have an immediate that's not a constant, treat it as a label
1809    // reference needing a fixup.
1810    if (!isa<MCConstantExpr>(getImm())) {
1811      Inst.addOperand(MCOperand::CreateExpr(getImm()));
1812      return;
1813    }
1814
1815    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1816    int Val = CE->getValue();
1817    Inst.addOperand(MCOperand::CreateImm(Val));
1818  }
1819
1820  void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
1821    assert(N == 2 && "Invalid number of operands!");
1822    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1823    Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
1824  }
1825
1826  void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
1827    assert(N == 3 && "Invalid number of operands!");
1828    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1829    if (!Memory.OffsetRegNum) {
1830      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1831      // Special case for #-0
1832      if (Val == INT32_MIN) Val = 0;
1833      if (Val < 0) Val = -Val;
1834      Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1835    } else {
1836      // For register offset, we encode the shift type and negation flag
1837      // here.
1838      Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1839                              Memory.ShiftImm, Memory.ShiftType);
1840    }
1841    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1842    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1843    Inst.addOperand(MCOperand::CreateImm(Val));
1844  }
1845
1846  void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
1847    assert(N == 2 && "Invalid number of operands!");
1848    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1849    assert(CE && "non-constant AM2OffsetImm operand!");
1850    int32_t Val = CE->getValue();
1851    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1852    // Special case for #-0
1853    if (Val == INT32_MIN) Val = 0;
1854    if (Val < 0) Val = -Val;
1855    Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1856    Inst.addOperand(MCOperand::CreateReg(0));
1857    Inst.addOperand(MCOperand::CreateImm(Val));
1858  }
1859
1860  void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
1861    assert(N == 3 && "Invalid number of operands!");
1862    // If we have an immediate that's not a constant, treat it as a label
1863    // reference needing a fixup. If it is a constant, it's something else
1864    // and we reject it.
1865    if (isImm()) {
1866      Inst.addOperand(MCOperand::CreateExpr(getImm()));
1867      Inst.addOperand(MCOperand::CreateReg(0));
1868      Inst.addOperand(MCOperand::CreateImm(0));
1869      return;
1870    }
1871
1872    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1873    if (!Memory.OffsetRegNum) {
1874      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1875      // Special case for #-0
1876      if (Val == INT32_MIN) Val = 0;
1877      if (Val < 0) Val = -Val;
1878      Val = ARM_AM::getAM3Opc(AddSub, Val);
1879    } else {
1880      // For register offset, we encode the shift type and negation flag
1881      // here.
1882      Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
1883    }
1884    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1885    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1886    Inst.addOperand(MCOperand::CreateImm(Val));
1887  }
1888
1889  void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
1890    assert(N == 2 && "Invalid number of operands!");
1891    if (Kind == k_PostIndexRegister) {
1892      int32_t Val =
1893        ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
1894      Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1895      Inst.addOperand(MCOperand::CreateImm(Val));
1896      return;
1897    }
1898
1899    // Constant offset.
1900    const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
1901    int32_t Val = CE->getValue();
1902    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1903    // Special case for #-0
1904    if (Val == INT32_MIN) Val = 0;
1905    if (Val < 0) Val = -Val;
1906    Val = ARM_AM::getAM3Opc(AddSub, Val);
1907    Inst.addOperand(MCOperand::CreateReg(0));
1908    Inst.addOperand(MCOperand::CreateImm(Val));
1909  }
1910
1911  void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
1912    assert(N == 2 && "Invalid number of operands!");
1913    // If we have an immediate that's not a constant, treat it as a label
1914    // reference needing a fixup. If it is a constant, it's something else
1915    // and we reject it.
1916    if (isImm()) {
1917      Inst.addOperand(MCOperand::CreateExpr(getImm()));
1918      Inst.addOperand(MCOperand::CreateImm(0));
1919      return;
1920    }
1921
1922    // The lower two bits are always zero and as such are not encoded.
1923    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1924    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1925    // Special case for #-0
1926    if (Val == INT32_MIN) Val = 0;
1927    if (Val < 0) Val = -Val;
1928    Val = ARM_AM::getAM5Opc(AddSub, Val);
1929    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1930    Inst.addOperand(MCOperand::CreateImm(Val));
1931  }
1932
1933  void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
1934    assert(N == 2 && "Invalid number of operands!");
1935    // If we have an immediate that's not a constant, treat it as a label
1936    // reference needing a fixup. If it is a constant, it's something else
1937    // and we reject it.
1938    if (isImm()) {
1939      Inst.addOperand(MCOperand::CreateExpr(getImm()));
1940      Inst.addOperand(MCOperand::CreateImm(0));
1941      return;
1942    }
1943
1944    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1945    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1946    Inst.addOperand(MCOperand::CreateImm(Val));
1947  }
1948
1949  void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
1950    assert(N == 2 && "Invalid number of operands!");
1951    // The lower two bits are always zero and as such are not encoded.
1952    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1953    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1954    Inst.addOperand(MCOperand::CreateImm(Val));
1955  }
1956
1957  void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1958    assert(N == 2 && "Invalid number of operands!");
1959    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1960    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1961    Inst.addOperand(MCOperand::CreateImm(Val));
1962  }
1963
1964  void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1965    addMemImm8OffsetOperands(Inst, N);
1966  }
1967
1968  void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1969    addMemImm8OffsetOperands(Inst, N);
1970  }
1971
1972  void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1973    assert(N == 2 && "Invalid number of operands!");
1974    // If this is an immediate, it's a label reference.
1975    if (isImm()) {
1976      addExpr(Inst, getImm());
1977      Inst.addOperand(MCOperand::CreateImm(0));
1978      return;
1979    }
1980
1981    // Otherwise, it's a normal memory reg+offset.
1982    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1983    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1984    Inst.addOperand(MCOperand::CreateImm(Val));
1985  }
1986
1987  void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1988    assert(N == 2 && "Invalid number of operands!");
1989    // If this is an immediate, it's a label reference.
1990    if (isImm()) {
1991      addExpr(Inst, getImm());
1992      Inst.addOperand(MCOperand::CreateImm(0));
1993      return;
1994    }
1995
1996    // Otherwise, it's a normal memory reg+offset.
1997    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1998    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1999    Inst.addOperand(MCOperand::CreateImm(Val));
2000  }
2001
2002  void addMemTBBOperands(MCInst &Inst, unsigned N) const {
2003    assert(N == 2 && "Invalid number of operands!");
2004    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2005    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2006  }
2007
2008  void addMemTBHOperands(MCInst &Inst, unsigned N) const {
2009    assert(N == 2 && "Invalid number of operands!");
2010    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2011    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2012  }
2013
2014  void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2015    assert(N == 3 && "Invalid number of operands!");
2016    unsigned Val =
2017      ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2018                        Memory.ShiftImm, Memory.ShiftType);
2019    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2020    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2021    Inst.addOperand(MCOperand::CreateImm(Val));
2022  }
2023
2024  void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2025    assert(N == 3 && "Invalid number of operands!");
2026    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2027    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2028    Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
2029  }
2030
2031  void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
2032    assert(N == 2 && "Invalid number of operands!");
2033    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2034    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2035  }
2036
2037  void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
2038    assert(N == 2 && "Invalid number of operands!");
2039    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2040    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2041    Inst.addOperand(MCOperand::CreateImm(Val));
2042  }
2043
2044  void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
2045    assert(N == 2 && "Invalid number of operands!");
2046    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
2047    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2048    Inst.addOperand(MCOperand::CreateImm(Val));
2049  }
2050
2051  void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
2052    assert(N == 2 && "Invalid number of operands!");
2053    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
2054    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2055    Inst.addOperand(MCOperand::CreateImm(Val));
2056  }
2057
2058  void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
2059    assert(N == 2 && "Invalid number of operands!");
2060    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2061    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2062    Inst.addOperand(MCOperand::CreateImm(Val));
2063  }
2064
2065  void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
2066    assert(N == 1 && "Invalid number of operands!");
2067    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2068    assert(CE && "non-constant post-idx-imm8 operand!");
2069    int Imm = CE->getValue();
2070    bool isAdd = Imm >= 0;
2071    if (Imm == INT32_MIN) Imm = 0;
2072    Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
2073    Inst.addOperand(MCOperand::CreateImm(Imm));
2074  }
2075
2076  void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
2077    assert(N == 1 && "Invalid number of operands!");
2078    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2079    assert(CE && "non-constant post-idx-imm8s4 operand!");
2080    int Imm = CE->getValue();
2081    bool isAdd = Imm >= 0;
2082    if (Imm == INT32_MIN) Imm = 0;
2083    // Immediate is scaled by 4.
2084    Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
2085    Inst.addOperand(MCOperand::CreateImm(Imm));
2086  }
2087
2088  void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
2089    assert(N == 2 && "Invalid number of operands!");
2090    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2091    Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
2092  }
2093
2094  void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
2095    assert(N == 2 && "Invalid number of operands!");
2096    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2097    // The sign, shift type, and shift amount are encoded in a single operand
2098    // using the AM2 encoding helpers.
2099    ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
2100    unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
2101                                     PostIdxReg.ShiftTy);
2102    Inst.addOperand(MCOperand::CreateImm(Imm));
2103  }
2104
2105  void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
2106    assert(N == 1 && "Invalid number of operands!");
2107    Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
2108  }
2109
2110  void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
2111    assert(N == 1 && "Invalid number of operands!");
2112    Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
2113  }
2114
2115  void addVecListOperands(MCInst &Inst, unsigned N) const {
2116    assert(N == 1 && "Invalid number of operands!");
2117    Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2118  }
2119
2120  void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
2121    assert(N == 2 && "Invalid number of operands!");
2122    Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2123    Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex));
2124  }
2125
2126  void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
2127    assert(N == 1 && "Invalid number of operands!");
2128    Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2129  }
2130
2131  void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
2132    assert(N == 1 && "Invalid number of operands!");
2133    Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2134  }
2135
2136  void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
2137    assert(N == 1 && "Invalid number of operands!");
2138    Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2139  }
2140
2141  void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
2142    assert(N == 1 && "Invalid number of operands!");
2143    // The immediate encodes the type of constant as well as the value.
2144    // Mask in that this is an i8 splat.
2145    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2146    Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
2147  }
2148
2149  void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
2150    assert(N == 1 && "Invalid number of operands!");
2151    // The immediate encodes the type of constant as well as the value.
2152    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2153    unsigned Value = CE->getValue();
2154    if (Value >= 256)
2155      Value = (Value >> 8) | 0xa00;
2156    else
2157      Value |= 0x800;
2158    Inst.addOperand(MCOperand::CreateImm(Value));
2159  }
2160
2161  void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
2162    assert(N == 1 && "Invalid number of operands!");
2163    // The immediate encodes the type of constant as well as the value.
2164    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2165    unsigned Value = CE->getValue();
2166    if (Value >= 256 && Value <= 0xff00)
2167      Value = (Value >> 8) | 0x200;
2168    else if (Value > 0xffff && Value <= 0xff0000)
2169      Value = (Value >> 16) | 0x400;
2170    else if (Value > 0xffffff)
2171      Value = (Value >> 24) | 0x600;
2172    Inst.addOperand(MCOperand::CreateImm(Value));
2173  }
2174
2175  void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2176    assert(N == 1 && "Invalid number of operands!");
2177    // The immediate encodes the type of constant as well as the value.
2178    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2179    unsigned Value = CE->getValue();
2180    if (Value >= 256 && Value <= 0xffff)
2181      Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2182    else if (Value > 0xffff && Value <= 0xffffff)
2183      Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2184    else if (Value > 0xffffff)
2185      Value = (Value >> 24) | 0x600;
2186    Inst.addOperand(MCOperand::CreateImm(Value));
2187  }
2188
2189  void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2190    assert(N == 1 && "Invalid number of operands!");
2191    // The immediate encodes the type of constant as well as the value.
2192    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2193    unsigned Value = ~CE->getValue();
2194    if (Value >= 256 && Value <= 0xffff)
2195      Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2196    else if (Value > 0xffff && Value <= 0xffffff)
2197      Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2198    else if (Value > 0xffffff)
2199      Value = (Value >> 24) | 0x600;
2200    Inst.addOperand(MCOperand::CreateImm(Value));
2201  }
2202
2203  void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2204    assert(N == 1 && "Invalid number of operands!");
2205    // The immediate encodes the type of constant as well as the value.
2206    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2207    uint64_t Value = CE->getValue();
2208    unsigned Imm = 0;
2209    for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
2210      Imm |= (Value & 1) << i;
2211    }
2212    Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
2213  }
2214
2215  virtual void print(raw_ostream &OS) const;
2216
2217  static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
2218    ARMOperand *Op = new ARMOperand(k_ITCondMask);
2219    Op->ITMask.Mask = Mask;
2220    Op->StartLoc = S;
2221    Op->EndLoc = S;
2222    return Op;
2223  }
2224
2225  static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
2226    ARMOperand *Op = new ARMOperand(k_CondCode);
2227    Op->CC.Val = CC;
2228    Op->StartLoc = S;
2229    Op->EndLoc = S;
2230    return Op;
2231  }
2232
2233  static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
2234    ARMOperand *Op = new ARMOperand(k_CoprocNum);
2235    Op->Cop.Val = CopVal;
2236    Op->StartLoc = S;
2237    Op->EndLoc = S;
2238    return Op;
2239  }
2240
2241  static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
2242    ARMOperand *Op = new ARMOperand(k_CoprocReg);
2243    Op->Cop.Val = CopVal;
2244    Op->StartLoc = S;
2245    Op->EndLoc = S;
2246    return Op;
2247  }
2248
2249  static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) {
2250    ARMOperand *Op = new ARMOperand(k_CoprocOption);
2251    Op->Cop.Val = Val;
2252    Op->StartLoc = S;
2253    Op->EndLoc = E;
2254    return Op;
2255  }
2256
2257  static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
2258    ARMOperand *Op = new ARMOperand(k_CCOut);
2259    Op->Reg.RegNum = RegNum;
2260    Op->StartLoc = S;
2261    Op->EndLoc = S;
2262    return Op;
2263  }
2264
2265  static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
2266    ARMOperand *Op = new ARMOperand(k_Token);
2267    Op->Tok.Data = Str.data();
2268    Op->Tok.Length = Str.size();
2269    Op->StartLoc = S;
2270    Op->EndLoc = S;
2271    return Op;
2272  }
2273
2274  static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
2275    ARMOperand *Op = new ARMOperand(k_Register);
2276    Op->Reg.RegNum = RegNum;
2277    Op->StartLoc = S;
2278    Op->EndLoc = E;
2279    return Op;
2280  }
2281
2282  static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
2283                                           unsigned SrcReg,
2284                                           unsigned ShiftReg,
2285                                           unsigned ShiftImm,
2286                                           SMLoc S, SMLoc E) {
2287    ARMOperand *Op = new ARMOperand(k_ShiftedRegister);
2288    Op->RegShiftedReg.ShiftTy = ShTy;
2289    Op->RegShiftedReg.SrcReg = SrcReg;
2290    Op->RegShiftedReg.ShiftReg = ShiftReg;
2291    Op->RegShiftedReg.ShiftImm = ShiftImm;
2292    Op->StartLoc = S;
2293    Op->EndLoc = E;
2294    return Op;
2295  }
2296
2297  static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
2298                                            unsigned SrcReg,
2299                                            unsigned ShiftImm,
2300                                            SMLoc S, SMLoc E) {
2301    ARMOperand *Op = new ARMOperand(k_ShiftedImmediate);
2302    Op->RegShiftedImm.ShiftTy = ShTy;
2303    Op->RegShiftedImm.SrcReg = SrcReg;
2304    Op->RegShiftedImm.ShiftImm = ShiftImm;
2305    Op->StartLoc = S;
2306    Op->EndLoc = E;
2307    return Op;
2308  }
2309
2310  static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
2311                                   SMLoc S, SMLoc E) {
2312    ARMOperand *Op = new ARMOperand(k_ShifterImmediate);
2313    Op->ShifterImm.isASR = isASR;
2314    Op->ShifterImm.Imm = Imm;
2315    Op->StartLoc = S;
2316    Op->EndLoc = E;
2317    return Op;
2318  }
2319
2320  static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
2321    ARMOperand *Op = new ARMOperand(k_RotateImmediate);
2322    Op->RotImm.Imm = Imm;
2323    Op->StartLoc = S;
2324    Op->EndLoc = E;
2325    return Op;
2326  }
2327
2328  static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
2329                                    SMLoc S, SMLoc E) {
2330    ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor);
2331    Op->Bitfield.LSB = LSB;
2332    Op->Bitfield.Width = Width;
2333    Op->StartLoc = S;
2334    Op->EndLoc = E;
2335    return Op;
2336  }
2337
2338  static ARMOperand *
2339  CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned> > &Regs,
2340                SMLoc StartLoc, SMLoc EndLoc) {
2341    assert (Regs.size() > 0 && "RegList contains no registers?");
2342    KindTy Kind = k_RegisterList;
2343
2344    if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second))
2345      Kind = k_DPRRegisterList;
2346    else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
2347             contains(Regs.front().second))
2348      Kind = k_SPRRegisterList;
2349
2350    // Sort based on the register encoding values.
2351    array_pod_sort(Regs.begin(), Regs.end());
2352
2353    ARMOperand *Op = new ARMOperand(Kind);
2354    for (SmallVectorImpl<std::pair<unsigned, unsigned> >::const_iterator
2355           I = Regs.begin(), E = Regs.end(); I != E; ++I)
2356      Op->Registers.push_back(I->second);
2357    Op->StartLoc = StartLoc;
2358    Op->EndLoc = EndLoc;
2359    return Op;
2360  }
2361
2362  static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count,
2363                                      bool isDoubleSpaced, SMLoc S, SMLoc E) {
2364    ARMOperand *Op = new ARMOperand(k_VectorList);
2365    Op->VectorList.RegNum = RegNum;
2366    Op->VectorList.Count = Count;
2367    Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2368    Op->StartLoc = S;
2369    Op->EndLoc = E;
2370    return Op;
2371  }
2372
2373  static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count,
2374                                              bool isDoubleSpaced,
2375                                              SMLoc S, SMLoc E) {
2376    ARMOperand *Op = new ARMOperand(k_VectorListAllLanes);
2377    Op->VectorList.RegNum = RegNum;
2378    Op->VectorList.Count = Count;
2379    Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2380    Op->StartLoc = S;
2381    Op->EndLoc = E;
2382    return Op;
2383  }
2384
2385  static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count,
2386                                             unsigned Index,
2387                                             bool isDoubleSpaced,
2388                                             SMLoc S, SMLoc E) {
2389    ARMOperand *Op = new ARMOperand(k_VectorListIndexed);
2390    Op->VectorList.RegNum = RegNum;
2391    Op->VectorList.Count = Count;
2392    Op->VectorList.LaneIndex = Index;
2393    Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2394    Op->StartLoc = S;
2395    Op->EndLoc = E;
2396    return Op;
2397  }
2398
2399  static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E,
2400                                       MCContext &Ctx) {
2401    ARMOperand *Op = new ARMOperand(k_VectorIndex);
2402    Op->VectorIndex.Val = Idx;
2403    Op->StartLoc = S;
2404    Op->EndLoc = E;
2405    return Op;
2406  }
2407
2408  static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
2409    ARMOperand *Op = new ARMOperand(k_Immediate);
2410    Op->Imm.Val = Val;
2411    Op->StartLoc = S;
2412    Op->EndLoc = E;
2413    return Op;
2414  }
2415
2416  static ARMOperand *CreateMem(unsigned BaseRegNum,
2417                               const MCConstantExpr *OffsetImm,
2418                               unsigned OffsetRegNum,
2419                               ARM_AM::ShiftOpc ShiftType,
2420                               unsigned ShiftImm,
2421                               unsigned Alignment,
2422                               bool isNegative,
2423                               SMLoc S, SMLoc E) {
2424    ARMOperand *Op = new ARMOperand(k_Memory);
2425    Op->Memory.BaseRegNum = BaseRegNum;
2426    Op->Memory.OffsetImm = OffsetImm;
2427    Op->Memory.OffsetRegNum = OffsetRegNum;
2428    Op->Memory.ShiftType = ShiftType;
2429    Op->Memory.ShiftImm = ShiftImm;
2430    Op->Memory.Alignment = Alignment;
2431    Op->Memory.isNegative = isNegative;
2432    Op->StartLoc = S;
2433    Op->EndLoc = E;
2434    return Op;
2435  }
2436
2437  static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
2438                                      ARM_AM::ShiftOpc ShiftTy,
2439                                      unsigned ShiftImm,
2440                                      SMLoc S, SMLoc E) {
2441    ARMOperand *Op = new ARMOperand(k_PostIndexRegister);
2442    Op->PostIdxReg.RegNum = RegNum;
2443    Op->PostIdxReg.isAdd = isAdd;
2444    Op->PostIdxReg.ShiftTy = ShiftTy;
2445    Op->PostIdxReg.ShiftImm = ShiftImm;
2446    Op->StartLoc = S;
2447    Op->EndLoc = E;
2448    return Op;
2449  }
2450
2451  static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
2452    ARMOperand *Op = new ARMOperand(k_MemBarrierOpt);
2453    Op->MBOpt.Val = Opt;
2454    Op->StartLoc = S;
2455    Op->EndLoc = S;
2456    return Op;
2457  }
2458
2459  static ARMOperand *CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt,
2460                                              SMLoc S) {
2461    ARMOperand *Op = new ARMOperand(k_InstSyncBarrierOpt);
2462    Op->ISBOpt.Val = Opt;
2463    Op->StartLoc = S;
2464    Op->EndLoc = S;
2465    return Op;
2466  }
2467
2468  static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
2469    ARMOperand *Op = new ARMOperand(k_ProcIFlags);
2470    Op->IFlags.Val = IFlags;
2471    Op->StartLoc = S;
2472    Op->EndLoc = S;
2473    return Op;
2474  }
2475
2476  static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
2477    ARMOperand *Op = new ARMOperand(k_MSRMask);
2478    Op->MMask.Val = MMask;
2479    Op->StartLoc = S;
2480    Op->EndLoc = S;
2481    return Op;
2482  }
2483};
2484
2485} // end anonymous namespace.
2486
2487void ARMOperand::print(raw_ostream &OS) const {
2488  switch (Kind) {
2489  case k_CondCode:
2490    OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
2491    break;
2492  case k_CCOut:
2493    OS << "<ccout " << getReg() << ">";
2494    break;
2495  case k_ITCondMask: {
2496    static const char *const MaskStr[] = {
2497      "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
2498      "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
2499    };
2500    assert((ITMask.Mask & 0xf) == ITMask.Mask);
2501    OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
2502    break;
2503  }
2504  case k_CoprocNum:
2505    OS << "<coprocessor number: " << getCoproc() << ">";
2506    break;
2507  case k_CoprocReg:
2508    OS << "<coprocessor register: " << getCoproc() << ">";
2509    break;
2510  case k_CoprocOption:
2511    OS << "<coprocessor option: " << CoprocOption.Val << ">";
2512    break;
2513  case k_MSRMask:
2514    OS << "<mask: " << getMSRMask() << ">";
2515    break;
2516  case k_Immediate:
2517    getImm()->print(OS);
2518    break;
2519  case k_MemBarrierOpt:
2520    OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt(), false) << ">";
2521    break;
2522  case k_InstSyncBarrierOpt:
2523    OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">";
2524    break;
2525  case k_Memory:
2526    OS << "<memory "
2527       << " base:" << Memory.BaseRegNum;
2528    OS << ">";
2529    break;
2530  case k_PostIndexRegister:
2531    OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
2532       << PostIdxReg.RegNum;
2533    if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
2534      OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
2535         << PostIdxReg.ShiftImm;
2536    OS << ">";
2537    break;
2538  case k_ProcIFlags: {
2539    OS << "<ARM_PROC::";
2540    unsigned IFlags = getProcIFlags();
2541    for (int i=2; i >= 0; --i)
2542      if (IFlags & (1 << i))
2543        OS << ARM_PROC::IFlagsToString(1 << i);
2544    OS << ">";
2545    break;
2546  }
2547  case k_Register:
2548    OS << "<register " << getReg() << ">";
2549    break;
2550  case k_ShifterImmediate:
2551    OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
2552       << " #" << ShifterImm.Imm << ">";
2553    break;
2554  case k_ShiftedRegister:
2555    OS << "<so_reg_reg "
2556       << RegShiftedReg.SrcReg << " "
2557       << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
2558       << " " << RegShiftedReg.ShiftReg << ">";
2559    break;
2560  case k_ShiftedImmediate:
2561    OS << "<so_reg_imm "
2562       << RegShiftedImm.SrcReg << " "
2563       << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
2564       << " #" << RegShiftedImm.ShiftImm << ">";
2565    break;
2566  case k_RotateImmediate:
2567    OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
2568    break;
2569  case k_BitfieldDescriptor:
2570    OS << "<bitfield " << "lsb: " << Bitfield.LSB
2571       << ", width: " << Bitfield.Width << ">";
2572    break;
2573  case k_RegisterList:
2574  case k_DPRRegisterList:
2575  case k_SPRRegisterList: {
2576    OS << "<register_list ";
2577
2578    const SmallVectorImpl<unsigned> &RegList = getRegList();
2579    for (SmallVectorImpl<unsigned>::const_iterator
2580           I = RegList.begin(), E = RegList.end(); I != E; ) {
2581      OS << *I;
2582      if (++I < E) OS << ", ";
2583    }
2584
2585    OS << ">";
2586    break;
2587  }
2588  case k_VectorList:
2589    OS << "<vector_list " << VectorList.Count << " * "
2590       << VectorList.RegNum << ">";
2591    break;
2592  case k_VectorListAllLanes:
2593    OS << "<vector_list(all lanes) " << VectorList.Count << " * "
2594       << VectorList.RegNum << ">";
2595    break;
2596  case k_VectorListIndexed:
2597    OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
2598       << VectorList.Count << " * " << VectorList.RegNum << ">";
2599    break;
2600  case k_Token:
2601    OS << "'" << getToken() << "'";
2602    break;
2603  case k_VectorIndex:
2604    OS << "<vectorindex " << getVectorIndex() << ">";
2605    break;
2606  }
2607}
2608
2609/// @name Auto-generated Match Functions
2610/// {
2611
2612static unsigned MatchRegisterName(StringRef Name);
2613
2614/// }
2615
2616bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2617                                 SMLoc &StartLoc, SMLoc &EndLoc) {
2618  StartLoc = Parser.getTok().getLoc();
2619  EndLoc = Parser.getTok().getEndLoc();
2620  RegNo = tryParseRegister();
2621
2622  return (RegNo == (unsigned)-1);
2623}
2624
2625/// Try to parse a register name.  The token must be an Identifier when called,
2626/// and if it is a register name the token is eaten and the register number is
2627/// returned.  Otherwise return -1.
2628///
2629int ARMAsmParser::tryParseRegister() {
2630  const AsmToken &Tok = Parser.getTok();
2631  if (Tok.isNot(AsmToken::Identifier)) return -1;
2632
2633  std::string lowerCase = Tok.getString().lower();
2634  unsigned RegNum = MatchRegisterName(lowerCase);
2635  if (!RegNum) {
2636    RegNum = StringSwitch<unsigned>(lowerCase)
2637      .Case("r13", ARM::SP)
2638      .Case("r14", ARM::LR)
2639      .Case("r15", ARM::PC)
2640      .Case("ip", ARM::R12)
2641      // Additional register name aliases for 'gas' compatibility.
2642      .Case("a1", ARM::R0)
2643      .Case("a2", ARM::R1)
2644      .Case("a3", ARM::R2)
2645      .Case("a4", ARM::R3)
2646      .Case("v1", ARM::R4)
2647      .Case("v2", ARM::R5)
2648      .Case("v3", ARM::R6)
2649      .Case("v4", ARM::R7)
2650      .Case("v5", ARM::R8)
2651      .Case("v6", ARM::R9)
2652      .Case("v7", ARM::R10)
2653      .Case("v8", ARM::R11)
2654      .Case("sb", ARM::R9)
2655      .Case("sl", ARM::R10)
2656      .Case("fp", ARM::R11)
2657      .Default(0);
2658  }
2659  if (!RegNum) {
2660    // Check for aliases registered via .req. Canonicalize to lower case.
2661    // That's more consistent since register names are case insensitive, and
2662    // it's how the original entry was passed in from MC/MCParser/AsmParser.
2663    StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
2664    // If no match, return failure.
2665    if (Entry == RegisterReqs.end())
2666      return -1;
2667    Parser.Lex(); // Eat identifier token.
2668    return Entry->getValue();
2669  }
2670
2671  Parser.Lex(); // Eat identifier token.
2672
2673  return RegNum;
2674}
2675
2676// Try to parse a shifter  (e.g., "lsl <amt>"). On success, return 0.
2677// If a recoverable error occurs, return 1. If an irrecoverable error
2678// occurs, return -1. An irrecoverable error is one where tokens have been
2679// consumed in the process of trying to parse the shifter (i.e., when it is
2680// indeed a shifter operand, but malformed).
2681int ARMAsmParser::tryParseShiftRegister(
2682                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2683  SMLoc S = Parser.getTok().getLoc();
2684  const AsmToken &Tok = Parser.getTok();
2685  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2686
2687  std::string lowerCase = Tok.getString().lower();
2688  ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
2689      .Case("asl", ARM_AM::lsl)
2690      .Case("lsl", ARM_AM::lsl)
2691      .Case("lsr", ARM_AM::lsr)
2692      .Case("asr", ARM_AM::asr)
2693      .Case("ror", ARM_AM::ror)
2694      .Case("rrx", ARM_AM::rrx)
2695      .Default(ARM_AM::no_shift);
2696
2697  if (ShiftTy == ARM_AM::no_shift)
2698    return 1;
2699
2700  Parser.Lex(); // Eat the operator.
2701
2702  // The source register for the shift has already been added to the
2703  // operand list, so we need to pop it off and combine it into the shifted
2704  // register operand instead.
2705  OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
2706  if (!PrevOp->isReg())
2707    return Error(PrevOp->getStartLoc(), "shift must be of a register");
2708  int SrcReg = PrevOp->getReg();
2709
2710  SMLoc EndLoc;
2711  int64_t Imm = 0;
2712  int ShiftReg = 0;
2713  if (ShiftTy == ARM_AM::rrx) {
2714    // RRX Doesn't have an explicit shift amount. The encoder expects
2715    // the shift register to be the same as the source register. Seems odd,
2716    // but OK.
2717    ShiftReg = SrcReg;
2718  } else {
2719    // Figure out if this is shifted by a constant or a register (for non-RRX).
2720    if (Parser.getTok().is(AsmToken::Hash) ||
2721        Parser.getTok().is(AsmToken::Dollar)) {
2722      Parser.Lex(); // Eat hash.
2723      SMLoc ImmLoc = Parser.getTok().getLoc();
2724      const MCExpr *ShiftExpr = 0;
2725      if (getParser().parseExpression(ShiftExpr, EndLoc)) {
2726        Error(ImmLoc, "invalid immediate shift value");
2727        return -1;
2728      }
2729      // The expression must be evaluatable as an immediate.
2730      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
2731      if (!CE) {
2732        Error(ImmLoc, "invalid immediate shift value");
2733        return -1;
2734      }
2735      // Range check the immediate.
2736      // lsl, ror: 0 <= imm <= 31
2737      // lsr, asr: 0 <= imm <= 32
2738      Imm = CE->getValue();
2739      if (Imm < 0 ||
2740          ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
2741          ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
2742        Error(ImmLoc, "immediate shift value out of range");
2743        return -1;
2744      }
2745      // shift by zero is a nop. Always send it through as lsl.
2746      // ('as' compatibility)
2747      if (Imm == 0)
2748        ShiftTy = ARM_AM::lsl;
2749    } else if (Parser.getTok().is(AsmToken::Identifier)) {
2750      SMLoc L = Parser.getTok().getLoc();
2751      EndLoc = Parser.getTok().getEndLoc();
2752      ShiftReg = tryParseRegister();
2753      if (ShiftReg == -1) {
2754        Error (L, "expected immediate or register in shift operand");
2755        return -1;
2756      }
2757    } else {
2758      Error (Parser.getTok().getLoc(),
2759                    "expected immediate or register in shift operand");
2760      return -1;
2761    }
2762  }
2763
2764  if (ShiftReg && ShiftTy != ARM_AM::rrx)
2765    Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
2766                                                         ShiftReg, Imm,
2767                                                         S, EndLoc));
2768  else
2769    Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
2770                                                          S, EndLoc));
2771
2772  return 0;
2773}
2774
2775
2776/// Try to parse a register name.  The token must be an Identifier when called.
2777/// If it's a register, an AsmOperand is created. Another AsmOperand is created
2778/// if there is a "writeback". 'true' if it's not a register.
2779///
2780/// TODO this is likely to change to allow different register types and or to
2781/// parse for a specific register type.
2782bool ARMAsmParser::
2783tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2784  const AsmToken &RegTok = Parser.getTok();
2785  int RegNo = tryParseRegister();
2786  if (RegNo == -1)
2787    return true;
2788
2789  Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(),
2790                                           RegTok.getEndLoc()));
2791
2792  const AsmToken &ExclaimTok = Parser.getTok();
2793  if (ExclaimTok.is(AsmToken::Exclaim)) {
2794    Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
2795                                               ExclaimTok.getLoc()));
2796    Parser.Lex(); // Eat exclaim token
2797    return false;
2798  }
2799
2800  // Also check for an index operand. This is only legal for vector registers,
2801  // but that'll get caught OK in operand matching, so we don't need to
2802  // explicitly filter everything else out here.
2803  if (Parser.getTok().is(AsmToken::LBrac)) {
2804    SMLoc SIdx = Parser.getTok().getLoc();
2805    Parser.Lex(); // Eat left bracket token.
2806
2807    const MCExpr *ImmVal;
2808    if (getParser().parseExpression(ImmVal))
2809      return true;
2810    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
2811    if (!MCE)
2812      return TokError("immediate value expected for vector index");
2813
2814    if (Parser.getTok().isNot(AsmToken::RBrac))
2815      return Error(Parser.getTok().getLoc(), "']' expected");
2816
2817    SMLoc E = Parser.getTok().getEndLoc();
2818    Parser.Lex(); // Eat right bracket token.
2819
2820    Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
2821                                                     SIdx, E,
2822                                                     getContext()));
2823  }
2824
2825  return false;
2826}
2827
2828/// MatchCoprocessorOperandName - Try to parse an coprocessor related
2829/// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
2830/// "c5", ...
2831static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
2832  // Use the same layout as the tablegen'erated register name matcher. Ugly,
2833  // but efficient.
2834  switch (Name.size()) {
2835  default: return -1;
2836  case 2:
2837    if (Name[0] != CoprocOp)
2838      return -1;
2839    switch (Name[1]) {
2840    default:  return -1;
2841    case '0': return 0;
2842    case '1': return 1;
2843    case '2': return 2;
2844    case '3': return 3;
2845    case '4': return 4;
2846    case '5': return 5;
2847    case '6': return 6;
2848    case '7': return 7;
2849    case '8': return 8;
2850    case '9': return 9;
2851    }
2852  case 3:
2853    if (Name[0] != CoprocOp || Name[1] != '1')
2854      return -1;
2855    switch (Name[2]) {
2856    default:  return -1;
2857    case '0': return 10;
2858    case '1': return 11;
2859    case '2': return 12;
2860    case '3': return 13;
2861    case '4': return 14;
2862    case '5': return 15;
2863    }
2864  }
2865}
2866
2867/// parseITCondCode - Try to parse a condition code for an IT instruction.
2868ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2869parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2870  SMLoc S = Parser.getTok().getLoc();
2871  const AsmToken &Tok = Parser.getTok();
2872  if (!Tok.is(AsmToken::Identifier))
2873    return MatchOperand_NoMatch;
2874  unsigned CC = StringSwitch<unsigned>(Tok.getString().lower())
2875    .Case("eq", ARMCC::EQ)
2876    .Case("ne", ARMCC::NE)
2877    .Case("hs", ARMCC::HS)
2878    .Case("cs", ARMCC::HS)
2879    .Case("lo", ARMCC::LO)
2880    .Case("cc", ARMCC::LO)
2881    .Case("mi", ARMCC::MI)
2882    .Case("pl", ARMCC::PL)
2883    .Case("vs", ARMCC::VS)
2884    .Case("vc", ARMCC::VC)
2885    .Case("hi", ARMCC::HI)
2886    .Case("ls", ARMCC::LS)
2887    .Case("ge", ARMCC::GE)
2888    .Case("lt", ARMCC::LT)
2889    .Case("gt", ARMCC::GT)
2890    .Case("le", ARMCC::LE)
2891    .Case("al", ARMCC::AL)
2892    .Default(~0U);
2893  if (CC == ~0U)
2894    return MatchOperand_NoMatch;
2895  Parser.Lex(); // Eat the token.
2896
2897  Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
2898
2899  return MatchOperand_Success;
2900}
2901
2902/// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
2903/// token must be an Identifier when called, and if it is a coprocessor
2904/// number, the token is eaten and the operand is added to the operand list.
2905ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2906parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2907  SMLoc S = Parser.getTok().getLoc();
2908  const AsmToken &Tok = Parser.getTok();
2909  if (Tok.isNot(AsmToken::Identifier))
2910    return MatchOperand_NoMatch;
2911
2912  int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
2913  if (Num == -1)
2914    return MatchOperand_NoMatch;
2915
2916  Parser.Lex(); // Eat identifier token.
2917  Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
2918  return MatchOperand_Success;
2919}
2920
2921/// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
2922/// token must be an Identifier when called, and if it is a coprocessor
2923/// number, the token is eaten and the operand is added to the operand list.
2924ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2925parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2926  SMLoc S = Parser.getTok().getLoc();
2927  const AsmToken &Tok = Parser.getTok();
2928  if (Tok.isNot(AsmToken::Identifier))
2929    return MatchOperand_NoMatch;
2930
2931  int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
2932  if (Reg == -1)
2933    return MatchOperand_NoMatch;
2934
2935  Parser.Lex(); // Eat identifier token.
2936  Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
2937  return MatchOperand_Success;
2938}
2939
2940/// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
2941/// coproc_option : '{' imm0_255 '}'
2942ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2943parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2944  SMLoc S = Parser.getTok().getLoc();
2945
2946  // If this isn't a '{', this isn't a coprocessor immediate operand.
2947  if (Parser.getTok().isNot(AsmToken::LCurly))
2948    return MatchOperand_NoMatch;
2949  Parser.Lex(); // Eat the '{'
2950
2951  const MCExpr *Expr;
2952  SMLoc Loc = Parser.getTok().getLoc();
2953  if (getParser().parseExpression(Expr)) {
2954    Error(Loc, "illegal expression");
2955    return MatchOperand_ParseFail;
2956  }
2957  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2958  if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
2959    Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
2960    return MatchOperand_ParseFail;
2961  }
2962  int Val = CE->getValue();
2963
2964  // Check for and consume the closing '}'
2965  if (Parser.getTok().isNot(AsmToken::RCurly))
2966    return MatchOperand_ParseFail;
2967  SMLoc E = Parser.getTok().getEndLoc();
2968  Parser.Lex(); // Eat the '}'
2969
2970  Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
2971  return MatchOperand_Success;
2972}
2973
2974// For register list parsing, we need to map from raw GPR register numbering
2975// to the enumeration values. The enumeration values aren't sorted by
2976// register number due to our using "sp", "lr" and "pc" as canonical names.
2977static unsigned getNextRegister(unsigned Reg) {
2978  // If this is a GPR, we need to do it manually, otherwise we can rely
2979  // on the sort ordering of the enumeration since the other reg-classes
2980  // are sane.
2981  if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2982    return Reg + 1;
2983  switch(Reg) {
2984  default: llvm_unreachable("Invalid GPR number!");
2985  case ARM::R0:  return ARM::R1;  case ARM::R1:  return ARM::R2;
2986  case ARM::R2:  return ARM::R3;  case ARM::R3:  return ARM::R4;
2987  case ARM::R4:  return ARM::R5;  case ARM::R5:  return ARM::R6;
2988  case ARM::R6:  return ARM::R7;  case ARM::R7:  return ARM::R8;
2989  case ARM::R8:  return ARM::R9;  case ARM::R9:  return ARM::R10;
2990  case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
2991  case ARM::R12: return ARM::SP;  case ARM::SP:  return ARM::LR;
2992  case ARM::LR:  return ARM::PC;  case ARM::PC:  return ARM::R0;
2993  }
2994}
2995
2996// Return the low-subreg of a given Q register.
2997static unsigned getDRegFromQReg(unsigned QReg) {
2998  switch (QReg) {
2999  default: llvm_unreachable("expected a Q register!");
3000  case ARM::Q0:  return ARM::D0;
3001  case ARM::Q1:  return ARM::D2;
3002  case ARM::Q2:  return ARM::D4;
3003  case ARM::Q3:  return ARM::D6;
3004  case ARM::Q4:  return ARM::D8;
3005  case ARM::Q5:  return ARM::D10;
3006  case ARM::Q6:  return ARM::D12;
3007  case ARM::Q7:  return ARM::D14;
3008  case ARM::Q8:  return ARM::D16;
3009  case ARM::Q9:  return ARM::D18;
3010  case ARM::Q10: return ARM::D20;
3011  case ARM::Q11: return ARM::D22;
3012  case ARM::Q12: return ARM::D24;
3013  case ARM::Q13: return ARM::D26;
3014  case ARM::Q14: return ARM::D28;
3015  case ARM::Q15: return ARM::D30;
3016  }
3017}
3018
3019/// Parse a register list.
3020bool ARMAsmParser::
3021parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3022  assert(Parser.getTok().is(AsmToken::LCurly) &&
3023         "Token is not a Left Curly Brace");
3024  SMLoc S = Parser.getTok().getLoc();
3025  Parser.Lex(); // Eat '{' token.
3026  SMLoc RegLoc = Parser.getTok().getLoc();
3027
3028  // Check the first register in the list to see what register class
3029  // this is a list of.
3030  int Reg = tryParseRegister();
3031  if (Reg == -1)
3032    return Error(RegLoc, "register expected");
3033
3034  // The reglist instructions have at most 16 registers, so reserve
3035  // space for that many.
3036  int EReg = 0;
3037  SmallVector<std::pair<unsigned, unsigned>, 16> Registers;
3038
3039  // Allow Q regs and just interpret them as the two D sub-registers.
3040  if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3041    Reg = getDRegFromQReg(Reg);
3042    EReg = MRI->getEncodingValue(Reg);
3043    Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3044    ++Reg;
3045  }
3046  const MCRegisterClass *RC;
3047  if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3048    RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
3049  else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
3050    RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
3051  else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
3052    RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
3053  else
3054    return Error(RegLoc, "invalid register in register list");
3055
3056  // Store the register.
3057  EReg = MRI->getEncodingValue(Reg);
3058  Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3059
3060  // This starts immediately after the first register token in the list,
3061  // so we can see either a comma or a minus (range separator) as a legal
3062  // next token.
3063  while (Parser.getTok().is(AsmToken::Comma) ||
3064         Parser.getTok().is(AsmToken::Minus)) {
3065    if (Parser.getTok().is(AsmToken::Minus)) {
3066      Parser.Lex(); // Eat the minus.
3067      SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3068      int EndReg = tryParseRegister();
3069      if (EndReg == -1)
3070        return Error(AfterMinusLoc, "register expected");
3071      // Allow Q regs and just interpret them as the two D sub-registers.
3072      if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3073        EndReg = getDRegFromQReg(EndReg) + 1;
3074      // If the register is the same as the start reg, there's nothing
3075      // more to do.
3076      if (Reg == EndReg)
3077        continue;
3078      // The register must be in the same register class as the first.
3079      if (!RC->contains(EndReg))
3080        return Error(AfterMinusLoc, "invalid register in register list");
3081      // Ranges must go from low to high.
3082      if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
3083        return Error(AfterMinusLoc, "bad range in register list");
3084
3085      // Add all the registers in the range to the register list.
3086      while (Reg != EndReg) {
3087        Reg = getNextRegister(Reg);
3088        EReg = MRI->getEncodingValue(Reg);
3089        Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3090      }
3091      continue;
3092    }
3093    Parser.Lex(); // Eat the comma.
3094    RegLoc = Parser.getTok().getLoc();
3095    int OldReg = Reg;
3096    const AsmToken RegTok = Parser.getTok();
3097    Reg = tryParseRegister();
3098    if (Reg == -1)
3099      return Error(RegLoc, "register expected");
3100    // Allow Q regs and just interpret them as the two D sub-registers.
3101    bool isQReg = false;
3102    if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3103      Reg = getDRegFromQReg(Reg);
3104      isQReg = true;
3105    }
3106    // The register must be in the same register class as the first.
3107    if (!RC->contains(Reg))
3108      return Error(RegLoc, "invalid register in register list");
3109    // List must be monotonically increasing.
3110    if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
3111      if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3112        Warning(RegLoc, "register list not in ascending order");
3113      else
3114        return Error(RegLoc, "register list not in ascending order");
3115    }
3116    if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
3117      Warning(RegLoc, "duplicated register (" + RegTok.getString() +
3118              ") in register list");
3119      continue;
3120    }
3121    // VFP register lists must also be contiguous.
3122    if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
3123        Reg != OldReg + 1)
3124      return Error(RegLoc, "non-contiguous register range");
3125    EReg = MRI->getEncodingValue(Reg);
3126    Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3127    if (isQReg) {
3128      EReg = MRI->getEncodingValue(++Reg);
3129      Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3130    }
3131  }
3132
3133  if (Parser.getTok().isNot(AsmToken::RCurly))
3134    return Error(Parser.getTok().getLoc(), "'}' expected");
3135  SMLoc E = Parser.getTok().getEndLoc();
3136  Parser.Lex(); // Eat '}' token.
3137
3138  // Push the register list operand.
3139  Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
3140
3141  // The ARM system instruction variants for LDM/STM have a '^' token here.
3142  if (Parser.getTok().is(AsmToken::Caret)) {
3143    Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
3144    Parser.Lex(); // Eat '^' token.
3145  }
3146
3147  return false;
3148}
3149
3150// Helper function to parse the lane index for vector lists.
3151ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3152parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
3153  Index = 0; // Always return a defined index value.
3154  if (Parser.getTok().is(AsmToken::LBrac)) {
3155    Parser.Lex(); // Eat the '['.
3156    if (Parser.getTok().is(AsmToken::RBrac)) {
3157      // "Dn[]" is the 'all lanes' syntax.
3158      LaneKind = AllLanes;
3159      EndLoc = Parser.getTok().getEndLoc();
3160      Parser.Lex(); // Eat the ']'.
3161      return MatchOperand_Success;
3162    }
3163
3164    // There's an optional '#' token here. Normally there wouldn't be, but
3165    // inline assemble puts one in, and it's friendly to accept that.
3166    if (Parser.getTok().is(AsmToken::Hash))
3167      Parser.Lex(); // Eat '#' or '$'.
3168
3169    const MCExpr *LaneIndex;
3170    SMLoc Loc = Parser.getTok().getLoc();
3171    if (getParser().parseExpression(LaneIndex)) {
3172      Error(Loc, "illegal expression");
3173      return MatchOperand_ParseFail;
3174    }
3175    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
3176    if (!CE) {
3177      Error(Loc, "lane index must be empty or an integer");
3178      return MatchOperand_ParseFail;
3179    }
3180    if (Parser.getTok().isNot(AsmToken::RBrac)) {
3181      Error(Parser.getTok().getLoc(), "']' expected");
3182      return MatchOperand_ParseFail;
3183    }
3184    EndLoc = Parser.getTok().getEndLoc();
3185    Parser.Lex(); // Eat the ']'.
3186    int64_t Val = CE->getValue();
3187
3188    // FIXME: Make this range check context sensitive for .8, .16, .32.
3189    if (Val < 0 || Val > 7) {
3190      Error(Parser.getTok().getLoc(), "lane index out of range");
3191      return MatchOperand_ParseFail;
3192    }
3193    Index = Val;
3194    LaneKind = IndexedLane;
3195    return MatchOperand_Success;
3196  }
3197  LaneKind = NoLanes;
3198  return MatchOperand_Success;
3199}
3200
3201// parse a vector register list
3202ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3203parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3204  VectorLaneTy LaneKind;
3205  unsigned LaneIndex;
3206  SMLoc S = Parser.getTok().getLoc();
3207  // As an extension (to match gas), support a plain D register or Q register
3208  // (without encosing curly braces) as a single or double entry list,
3209  // respectively.
3210  if (Parser.getTok().is(AsmToken::Identifier)) {
3211    SMLoc E = Parser.getTok().getEndLoc();
3212    int Reg = tryParseRegister();
3213    if (Reg == -1)
3214      return MatchOperand_NoMatch;
3215    if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
3216      OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3217      if (Res != MatchOperand_Success)
3218        return Res;
3219      switch (LaneKind) {
3220      case NoLanes:
3221        Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
3222        break;
3223      case AllLanes:
3224        Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
3225                                                                S, E));
3226        break;
3227      case IndexedLane:
3228        Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
3229                                                               LaneIndex,
3230                                                               false, S, E));
3231        break;
3232      }
3233      return MatchOperand_Success;
3234    }
3235    if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3236      Reg = getDRegFromQReg(Reg);
3237      OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3238      if (Res != MatchOperand_Success)
3239        return Res;
3240      switch (LaneKind) {
3241      case NoLanes:
3242        Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3243                                   &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3244        Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
3245        break;
3246      case AllLanes:
3247        Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3248                                   &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3249        Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
3250                                                                S, E));
3251        break;
3252      case IndexedLane:
3253        Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
3254                                                               LaneIndex,
3255                                                               false, S, E));
3256        break;
3257      }
3258      return MatchOperand_Success;
3259    }
3260    Error(S, "vector register expected");
3261    return MatchOperand_ParseFail;
3262  }
3263
3264  if (Parser.getTok().isNot(AsmToken::LCurly))
3265    return MatchOperand_NoMatch;
3266
3267  Parser.Lex(); // Eat '{' token.
3268  SMLoc RegLoc = Parser.getTok().getLoc();
3269
3270  int Reg = tryParseRegister();
3271  if (Reg == -1) {
3272    Error(RegLoc, "register expected");
3273    return MatchOperand_ParseFail;
3274  }
3275  unsigned Count = 1;
3276  int Spacing = 0;
3277  unsigned FirstReg = Reg;
3278  // The list is of D registers, but we also allow Q regs and just interpret
3279  // them as the two D sub-registers.
3280  if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3281    FirstReg = Reg = getDRegFromQReg(Reg);
3282    Spacing = 1; // double-spacing requires explicit D registers, otherwise
3283                 // it's ambiguous with four-register single spaced.
3284    ++Reg;
3285    ++Count;
3286  }
3287
3288  SMLoc E;
3289  if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success)
3290    return MatchOperand_ParseFail;
3291
3292  while (Parser.getTok().is(AsmToken::Comma) ||
3293         Parser.getTok().is(AsmToken::Minus)) {
3294    if (Parser.getTok().is(AsmToken::Minus)) {
3295      if (!Spacing)
3296        Spacing = 1; // Register range implies a single spaced list.
3297      else if (Spacing == 2) {
3298        Error(Parser.getTok().getLoc(),
3299              "sequential registers in double spaced list");
3300        return MatchOperand_ParseFail;
3301      }
3302      Parser.Lex(); // Eat the minus.
3303      SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3304      int EndReg = tryParseRegister();
3305      if (EndReg == -1) {
3306        Error(AfterMinusLoc, "register expected");
3307        return MatchOperand_ParseFail;
3308      }
3309      // Allow Q regs and just interpret them as the two D sub-registers.
3310      if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3311        EndReg = getDRegFromQReg(EndReg) + 1;
3312      // If the register is the same as the start reg, there's nothing
3313      // more to do.
3314      if (Reg == EndReg)
3315        continue;
3316      // The register must be in the same register class as the first.
3317      if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
3318        Error(AfterMinusLoc, "invalid register in register list");
3319        return MatchOperand_ParseFail;
3320      }
3321      // Ranges must go from low to high.
3322      if (Reg > EndReg) {
3323        Error(AfterMinusLoc, "bad range in register list");
3324        return MatchOperand_ParseFail;
3325      }
3326      // Parse the lane specifier if present.
3327      VectorLaneTy NextLaneKind;
3328      unsigned NextLaneIndex;
3329      if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3330          MatchOperand_Success)
3331        return MatchOperand_ParseFail;
3332      if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3333        Error(AfterMinusLoc, "mismatched lane index in register list");
3334        return MatchOperand_ParseFail;
3335      }
3336
3337      // Add all the registers in the range to the register list.
3338      Count += EndReg - Reg;
3339      Reg = EndReg;
3340      continue;
3341    }
3342    Parser.Lex(); // Eat the comma.
3343    RegLoc = Parser.getTok().getLoc();
3344    int OldReg = Reg;
3345    Reg = tryParseRegister();
3346    if (Reg == -1) {
3347      Error(RegLoc, "register expected");
3348      return MatchOperand_ParseFail;
3349    }
3350    // vector register lists must be contiguous.
3351    // It's OK to use the enumeration values directly here rather, as the
3352    // VFP register classes have the enum sorted properly.
3353    //
3354    // The list is of D registers, but we also allow Q regs and just interpret
3355    // them as the two D sub-registers.
3356    if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3357      if (!Spacing)
3358        Spacing = 1; // Register range implies a single spaced list.
3359      else if (Spacing == 2) {
3360        Error(RegLoc,
3361              "invalid register in double-spaced list (must be 'D' register')");
3362        return MatchOperand_ParseFail;
3363      }
3364      Reg = getDRegFromQReg(Reg);
3365      if (Reg != OldReg + 1) {
3366        Error(RegLoc, "non-contiguous register range");
3367        return MatchOperand_ParseFail;
3368      }
3369      ++Reg;
3370      Count += 2;
3371      // Parse the lane specifier if present.
3372      VectorLaneTy NextLaneKind;
3373      unsigned NextLaneIndex;
3374      SMLoc LaneLoc = Parser.getTok().getLoc();
3375      if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3376          MatchOperand_Success)
3377        return MatchOperand_ParseFail;
3378      if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3379        Error(LaneLoc, "mismatched lane index in register list");
3380        return MatchOperand_ParseFail;
3381      }
3382      continue;
3383    }
3384    // Normal D register.
3385    // Figure out the register spacing (single or double) of the list if
3386    // we don't know it already.
3387    if (!Spacing)
3388      Spacing = 1 + (Reg == OldReg + 2);
3389
3390    // Just check that it's contiguous and keep going.
3391    if (Reg != OldReg + Spacing) {
3392      Error(RegLoc, "non-contiguous register range");
3393      return MatchOperand_ParseFail;
3394    }
3395    ++Count;
3396    // Parse the lane specifier if present.
3397    VectorLaneTy NextLaneKind;
3398    unsigned NextLaneIndex;
3399    SMLoc EndLoc = Parser.getTok().getLoc();
3400    if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success)
3401      return MatchOperand_ParseFail;
3402    if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3403      Error(EndLoc, "mismatched lane index in register list");
3404      return MatchOperand_ParseFail;
3405    }
3406  }
3407
3408  if (Parser.getTok().isNot(AsmToken::RCurly)) {
3409    Error(Parser.getTok().getLoc(), "'}' expected");
3410    return MatchOperand_ParseFail;
3411  }
3412  E = Parser.getTok().getEndLoc();
3413  Parser.Lex(); // Eat '}' token.
3414
3415  switch (LaneKind) {
3416  case NoLanes:
3417    // Two-register operands have been converted to the
3418    // composite register classes.
3419    if (Count == 2) {
3420      const MCRegisterClass *RC = (Spacing == 1) ?
3421        &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3422        &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3423      FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3424    }
3425
3426    Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
3427                                                    (Spacing == 2), S, E));
3428    break;
3429  case AllLanes:
3430    // Two-register operands have been converted to the
3431    // composite register classes.
3432    if (Count == 2) {
3433      const MCRegisterClass *RC = (Spacing == 1) ?
3434        &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3435        &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3436      FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3437    }
3438    Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
3439                                                            (Spacing == 2),
3440                                                            S, E));
3441    break;
3442  case IndexedLane:
3443    Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
3444                                                           LaneIndex,
3445                                                           (Spacing == 2),
3446                                                           S, E));
3447    break;
3448  }
3449  return MatchOperand_Success;
3450}
3451
3452/// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
3453ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3454parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3455  SMLoc S = Parser.getTok().getLoc();
3456  const AsmToken &Tok = Parser.getTok();
3457  unsigned Opt;
3458
3459  if (Tok.is(AsmToken::Identifier)) {
3460    StringRef OptStr = Tok.getString();
3461
3462    Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
3463      .Case("sy",    ARM_MB::SY)
3464      .Case("st",    ARM_MB::ST)
3465      .Case("ld",    ARM_MB::LD)
3466      .Case("sh",    ARM_MB::ISH)
3467      .Case("ish",   ARM_MB::ISH)
3468      .Case("shst",  ARM_MB::ISHST)
3469      .Case("ishst", ARM_MB::ISHST)
3470      .Case("ishld", ARM_MB::ISHLD)
3471      .Case("nsh",   ARM_MB::NSH)
3472      .Case("un",    ARM_MB::NSH)
3473      .Case("nshst", ARM_MB::NSHST)
3474      .Case("nshld", ARM_MB::NSHLD)
3475      .Case("unst",  ARM_MB::NSHST)
3476      .Case("osh",   ARM_MB::OSH)
3477      .Case("oshst", ARM_MB::OSHST)
3478      .Case("oshld", ARM_MB::OSHLD)
3479      .Default(~0U);
3480
3481    // ishld, oshld, nshld and ld are only available from ARMv8.
3482    if (!hasV8Ops() && (Opt == ARM_MB::ISHLD || Opt == ARM_MB::OSHLD ||
3483                        Opt == ARM_MB::NSHLD || Opt == ARM_MB::LD))
3484      Opt = ~0U;
3485
3486    if (Opt == ~0U)
3487      return MatchOperand_NoMatch;
3488
3489    Parser.Lex(); // Eat identifier token.
3490  } else if (Tok.is(AsmToken::Hash) ||
3491             Tok.is(AsmToken::Dollar) ||
3492             Tok.is(AsmToken::Integer)) {
3493    if (Parser.getTok().isNot(AsmToken::Integer))
3494      Parser.Lex(); // Eat '#' or '$'.
3495    SMLoc Loc = Parser.getTok().getLoc();
3496
3497    const MCExpr *MemBarrierID;
3498    if (getParser().parseExpression(MemBarrierID)) {
3499      Error(Loc, "illegal expression");
3500      return MatchOperand_ParseFail;
3501    }
3502
3503    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
3504    if (!CE) {
3505      Error(Loc, "constant expression expected");
3506      return MatchOperand_ParseFail;
3507    }
3508
3509    int Val = CE->getValue();
3510    if (Val & ~0xf) {
3511      Error(Loc, "immediate value out of range");
3512      return MatchOperand_ParseFail;
3513    }
3514
3515    Opt = ARM_MB::RESERVED_0 + Val;
3516  } else
3517    return MatchOperand_ParseFail;
3518
3519  Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
3520  return MatchOperand_Success;
3521}
3522
3523/// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options.
3524ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3525parseInstSyncBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3526  SMLoc S = Parser.getTok().getLoc();
3527  const AsmToken &Tok = Parser.getTok();
3528  unsigned Opt;
3529
3530  if (Tok.is(AsmToken::Identifier)) {
3531    StringRef OptStr = Tok.getString();
3532
3533    if (OptStr.lower() == "sy")
3534      Opt = ARM_ISB::SY;
3535    else
3536      return MatchOperand_NoMatch;
3537
3538    Parser.Lex(); // Eat identifier token.
3539  } else if (Tok.is(AsmToken::Hash) ||
3540             Tok.is(AsmToken::Dollar) ||
3541             Tok.is(AsmToken::Integer)) {
3542    if (Parser.getTok().isNot(AsmToken::Integer))
3543      Parser.Lex(); // Eat '#' or '$'.
3544    SMLoc Loc = Parser.getTok().getLoc();
3545
3546    const MCExpr *ISBarrierID;
3547    if (getParser().parseExpression(ISBarrierID)) {
3548      Error(Loc, "illegal expression");
3549      return MatchOperand_ParseFail;
3550    }
3551
3552    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID);
3553    if (!CE) {
3554      Error(Loc, "constant expression expected");
3555      return MatchOperand_ParseFail;
3556    }
3557
3558    int Val = CE->getValue();
3559    if (Val & ~0xf) {
3560      Error(Loc, "immediate value out of range");
3561      return MatchOperand_ParseFail;
3562    }
3563
3564    Opt = ARM_ISB::RESERVED_0 + Val;
3565  } else
3566    return MatchOperand_ParseFail;
3567
3568  Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt(
3569          (ARM_ISB::InstSyncBOpt)Opt, S));
3570  return MatchOperand_Success;
3571}
3572
3573
3574/// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
3575ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3576parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3577  SMLoc S = Parser.getTok().getLoc();
3578  const AsmToken &Tok = Parser.getTok();
3579  if (!Tok.is(AsmToken::Identifier))
3580    return MatchOperand_NoMatch;
3581  StringRef IFlagsStr = Tok.getString();
3582
3583  // An iflags string of "none" is interpreted to mean that none of the AIF
3584  // bits are set.  Not a terribly useful instruction, but a valid encoding.
3585  unsigned IFlags = 0;
3586  if (IFlagsStr != "none") {
3587        for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
3588      unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
3589        .Case("a", ARM_PROC::A)
3590        .Case("i", ARM_PROC::I)
3591        .Case("f", ARM_PROC::F)
3592        .Default(~0U);
3593
3594      // If some specific iflag is already set, it means that some letter is
3595      // present more than once, this is not acceptable.
3596      if (Flag == ~0U || (IFlags & Flag))
3597        return MatchOperand_NoMatch;
3598
3599      IFlags |= Flag;
3600    }
3601  }
3602
3603  Parser.Lex(); // Eat identifier token.
3604  Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
3605  return MatchOperand_Success;
3606}
3607
3608/// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
3609ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3610parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3611  SMLoc S = Parser.getTok().getLoc();
3612  const AsmToken &Tok = Parser.getTok();
3613  if (!Tok.is(AsmToken::Identifier))
3614    return MatchOperand_NoMatch;
3615  StringRef Mask = Tok.getString();
3616
3617  if (isMClass()) {
3618    // See ARMv6-M 10.1.1
3619    std::string Name = Mask.lower();
3620    unsigned FlagsVal = StringSwitch<unsigned>(Name)
3621      // Note: in the documentation:
3622      //  ARM deprecates using MSR APSR without a _<bits> qualifier as an alias
3623      //  for MSR APSR_nzcvq.
3624      // but we do make it an alias here.  This is so to get the "mask encoding"
3625      // bits correct on MSR APSR writes.
3626      //
3627      // FIXME: Note the 0xc00 "mask encoding" bits version of the registers
3628      // should really only be allowed when writing a special register.  Note
3629      // they get dropped in the MRS instruction reading a special register as
3630      // the SYSm field is only 8 bits.
3631      //
3632      // FIXME: the _g and _nzcvqg versions are only allowed if the processor
3633      // includes the DSP extension but that is not checked.
3634      .Case("apsr", 0x800)
3635      .Case("apsr_nzcvq", 0x800)
3636      .Case("apsr_g", 0x400)
3637      .Case("apsr_nzcvqg", 0xc00)
3638      .Case("iapsr", 0x801)
3639      .Case("iapsr_nzcvq", 0x801)
3640      .Case("iapsr_g", 0x401)
3641      .Case("iapsr_nzcvqg", 0xc01)
3642      .Case("eapsr", 0x802)
3643      .Case("eapsr_nzcvq", 0x802)
3644      .Case("eapsr_g", 0x402)
3645      .Case("eapsr_nzcvqg", 0xc02)
3646      .Case("xpsr", 0x803)
3647      .Case("xpsr_nzcvq", 0x803)
3648      .Case("xpsr_g", 0x403)
3649      .Case("xpsr_nzcvqg", 0xc03)
3650      .Case("ipsr", 0x805)
3651      .Case("epsr", 0x806)
3652      .Case("iepsr", 0x807)
3653      .Case("msp", 0x808)
3654      .Case("psp", 0x809)
3655      .Case("primask", 0x810)
3656      .Case("basepri", 0x811)
3657      .Case("basepri_max", 0x812)
3658      .Case("faultmask", 0x813)
3659      .Case("control", 0x814)
3660      .Default(~0U);
3661
3662    if (FlagsVal == ~0U)
3663      return MatchOperand_NoMatch;
3664
3665    if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813)
3666      // basepri, basepri_max and faultmask only valid for V7m.
3667      return MatchOperand_NoMatch;
3668
3669    Parser.Lex(); // Eat identifier token.
3670    Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3671    return MatchOperand_Success;
3672  }
3673
3674  // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
3675  size_t Start = 0, Next = Mask.find('_');
3676  StringRef Flags = "";
3677  std::string SpecReg = Mask.slice(Start, Next).lower();
3678  if (Next != StringRef::npos)
3679    Flags = Mask.slice(Next+1, Mask.size());
3680
3681  // FlagsVal contains the complete mask:
3682  // 3-0: Mask
3683  // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3684  unsigned FlagsVal = 0;
3685
3686  if (SpecReg == "apsr") {
3687    FlagsVal = StringSwitch<unsigned>(Flags)
3688    .Case("nzcvq",  0x8) // same as CPSR_f
3689    .Case("g",      0x4) // same as CPSR_s
3690    .Case("nzcvqg", 0xc) // same as CPSR_fs
3691    .Default(~0U);
3692
3693    if (FlagsVal == ~0U) {
3694      if (!Flags.empty())
3695        return MatchOperand_NoMatch;
3696      else
3697        FlagsVal = 8; // No flag
3698    }
3699  } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
3700    // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
3701    if (Flags == "all" || Flags == "")
3702      Flags = "fc";
3703    for (int i = 0, e = Flags.size(); i != e; ++i) {
3704      unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
3705      .Case("c", 1)
3706      .Case("x", 2)
3707      .Case("s", 4)
3708      .Case("f", 8)
3709      .Default(~0U);
3710
3711      // If some specific flag is already set, it means that some letter is
3712      // present more than once, this is not acceptable.
3713      if (FlagsVal == ~0U || (FlagsVal & Flag))
3714        return MatchOperand_NoMatch;
3715      FlagsVal |= Flag;
3716    }
3717  } else // No match for special register.
3718    return MatchOperand_NoMatch;
3719
3720  // Special register without flags is NOT equivalent to "fc" flags.
3721  // NOTE: This is a divergence from gas' behavior.  Uncommenting the following
3722  // two lines would enable gas compatibility at the expense of breaking
3723  // round-tripping.
3724  //
3725  // if (!FlagsVal)
3726  //  FlagsVal = 0x9;
3727
3728  // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3729  if (SpecReg == "spsr")
3730    FlagsVal |= 16;
3731
3732  Parser.Lex(); // Eat identifier token.
3733  Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3734  return MatchOperand_Success;
3735}
3736
3737ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3738parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
3739            int Low, int High) {
3740  const AsmToken &Tok = Parser.getTok();
3741  if (Tok.isNot(AsmToken::Identifier)) {
3742    Error(Parser.getTok().getLoc(), Op + " operand expected.");
3743    return MatchOperand_ParseFail;
3744  }
3745  StringRef ShiftName = Tok.getString();
3746  std::string LowerOp = Op.lower();
3747  std::string UpperOp = Op.upper();
3748  if (ShiftName != LowerOp && ShiftName != UpperOp) {
3749    Error(Parser.getTok().getLoc(), Op + " operand expected.");
3750    return MatchOperand_ParseFail;
3751  }
3752  Parser.Lex(); // Eat shift type token.
3753
3754  // There must be a '#' and a shift amount.
3755  if (Parser.getTok().isNot(AsmToken::Hash) &&
3756      Parser.getTok().isNot(AsmToken::Dollar)) {
3757    Error(Parser.getTok().getLoc(), "'#' expected");
3758    return MatchOperand_ParseFail;
3759  }
3760  Parser.Lex(); // Eat hash token.
3761
3762  const MCExpr *ShiftAmount;
3763  SMLoc Loc = Parser.getTok().getLoc();
3764  SMLoc EndLoc;
3765  if (getParser().parseExpression(ShiftAmount, EndLoc)) {
3766    Error(Loc, "illegal expression");
3767    return MatchOperand_ParseFail;
3768  }
3769  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3770  if (!CE) {
3771    Error(Loc, "constant expression expected");
3772    return MatchOperand_ParseFail;
3773  }
3774  int Val = CE->getValue();
3775  if (Val < Low || Val > High) {
3776    Error(Loc, "immediate value out of range");
3777    return MatchOperand_ParseFail;
3778  }
3779
3780  Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc));
3781
3782  return MatchOperand_Success;
3783}
3784
3785ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3786parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3787  const AsmToken &Tok = Parser.getTok();
3788  SMLoc S = Tok.getLoc();
3789  if (Tok.isNot(AsmToken::Identifier)) {
3790    Error(S, "'be' or 'le' operand expected");
3791    return MatchOperand_ParseFail;
3792  }
3793  int Val = StringSwitch<int>(Tok.getString().lower())
3794    .Case("be", 1)
3795    .Case("le", 0)
3796    .Default(-1);
3797  Parser.Lex(); // Eat the token.
3798
3799  if (Val == -1) {
3800    Error(S, "'be' or 'le' operand expected");
3801    return MatchOperand_ParseFail;
3802  }
3803  Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
3804                                                                  getContext()),
3805                                           S, Tok.getEndLoc()));
3806  return MatchOperand_Success;
3807}
3808
3809/// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
3810/// instructions. Legal values are:
3811///     lsl #n  'n' in [0,31]
3812///     asr #n  'n' in [1,32]
3813///             n == 32 encoded as n == 0.
3814ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3815parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3816  const AsmToken &Tok = Parser.getTok();
3817  SMLoc S = Tok.getLoc();
3818  if (Tok.isNot(AsmToken::Identifier)) {
3819    Error(S, "shift operator 'asr' or 'lsl' expected");
3820    return MatchOperand_ParseFail;
3821  }
3822  StringRef ShiftName = Tok.getString();
3823  bool isASR;
3824  if (ShiftName == "lsl" || ShiftName == "LSL")
3825    isASR = false;
3826  else if (ShiftName == "asr" || ShiftName == "ASR")
3827    isASR = true;
3828  else {
3829    Error(S, "shift operator 'asr' or 'lsl' expected");
3830    return MatchOperand_ParseFail;
3831  }
3832  Parser.Lex(); // Eat the operator.
3833
3834  // A '#' and a shift amount.
3835  if (Parser.getTok().isNot(AsmToken::Hash) &&
3836      Parser.getTok().isNot(AsmToken::Dollar)) {
3837    Error(Parser.getTok().getLoc(), "'#' expected");
3838    return MatchOperand_ParseFail;
3839  }
3840  Parser.Lex(); // Eat hash token.
3841  SMLoc ExLoc = Parser.getTok().getLoc();
3842
3843  const MCExpr *ShiftAmount;
3844  SMLoc EndLoc;
3845  if (getParser().parseExpression(ShiftAmount, EndLoc)) {
3846    Error(ExLoc, "malformed shift expression");
3847    return MatchOperand_ParseFail;
3848  }
3849  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3850  if (!CE) {
3851    Error(ExLoc, "shift amount must be an immediate");
3852    return MatchOperand_ParseFail;
3853  }
3854
3855  int64_t Val = CE->getValue();
3856  if (isASR) {
3857    // Shift amount must be in [1,32]
3858    if (Val < 1 || Val > 32) {
3859      Error(ExLoc, "'asr' shift amount must be in range [1,32]");
3860      return MatchOperand_ParseFail;
3861    }
3862    // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
3863    if (isThumb() && Val == 32) {
3864      Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode");
3865      return MatchOperand_ParseFail;
3866    }
3867    if (Val == 32) Val = 0;
3868  } else {
3869    // Shift amount must be in [1,32]
3870    if (Val < 0 || Val > 31) {
3871      Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
3872      return MatchOperand_ParseFail;
3873    }
3874  }
3875
3876  Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc));
3877
3878  return MatchOperand_Success;
3879}
3880
3881/// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
3882/// of instructions. Legal values are:
3883///     ror #n  'n' in {0, 8, 16, 24}
3884ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3885parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3886  const AsmToken &Tok = Parser.getTok();
3887  SMLoc S = Tok.getLoc();
3888  if (Tok.isNot(AsmToken::Identifier))
3889    return MatchOperand_NoMatch;
3890  StringRef ShiftName = Tok.getString();
3891  if (ShiftName != "ror" && ShiftName != "ROR")
3892    return MatchOperand_NoMatch;
3893  Parser.Lex(); // Eat the operator.
3894
3895  // A '#' and a rotate amount.
3896  if (Parser.getTok().isNot(AsmToken::Hash) &&
3897      Parser.getTok().isNot(AsmToken::Dollar)) {
3898    Error(Parser.getTok().getLoc(), "'#' expected");
3899    return MatchOperand_ParseFail;
3900  }
3901  Parser.Lex(); // Eat hash token.
3902  SMLoc ExLoc = Parser.getTok().getLoc();
3903
3904  const MCExpr *ShiftAmount;
3905  SMLoc EndLoc;
3906  if (getParser().parseExpression(ShiftAmount, EndLoc)) {
3907    Error(ExLoc, "malformed rotate expression");
3908    return MatchOperand_ParseFail;
3909  }
3910  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3911  if (!CE) {
3912    Error(ExLoc, "rotate amount must be an immediate");
3913    return MatchOperand_ParseFail;
3914  }
3915
3916  int64_t Val = CE->getValue();
3917  // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
3918  // normally, zero is represented in asm by omitting the rotate operand
3919  // entirely.
3920  if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
3921    Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24");
3922    return MatchOperand_ParseFail;
3923  }
3924
3925  Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc));
3926
3927  return MatchOperand_Success;
3928}
3929
3930ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3931parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3932  SMLoc S = Parser.getTok().getLoc();
3933  // The bitfield descriptor is really two operands, the LSB and the width.
3934  if (Parser.getTok().isNot(AsmToken::Hash) &&
3935      Parser.getTok().isNot(AsmToken::Dollar)) {
3936    Error(Parser.getTok().getLoc(), "'#' expected");
3937    return MatchOperand_ParseFail;
3938  }
3939  Parser.Lex(); // Eat hash token.
3940
3941  const MCExpr *LSBExpr;
3942  SMLoc E = Parser.getTok().getLoc();
3943  if (getParser().parseExpression(LSBExpr)) {
3944    Error(E, "malformed immediate expression");
3945    return MatchOperand_ParseFail;
3946  }
3947  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
3948  if (!CE) {
3949    Error(E, "'lsb' operand must be an immediate");
3950    return MatchOperand_ParseFail;
3951  }
3952
3953  int64_t LSB = CE->getValue();
3954  // The LSB must be in the range [0,31]
3955  if (LSB < 0 || LSB > 31) {
3956    Error(E, "'lsb' operand must be in the range [0,31]");
3957    return MatchOperand_ParseFail;
3958  }
3959  E = Parser.getTok().getLoc();
3960
3961  // Expect another immediate operand.
3962  if (Parser.getTok().isNot(AsmToken::Comma)) {
3963    Error(Parser.getTok().getLoc(), "too few operands");
3964    return MatchOperand_ParseFail;
3965  }
3966  Parser.Lex(); // Eat hash token.
3967  if (Parser.getTok().isNot(AsmToken::Hash) &&
3968      Parser.getTok().isNot(AsmToken::Dollar)) {
3969    Error(Parser.getTok().getLoc(), "'#' expected");
3970    return MatchOperand_ParseFail;
3971  }
3972  Parser.Lex(); // Eat hash token.
3973
3974  const MCExpr *WidthExpr;
3975  SMLoc EndLoc;
3976  if (getParser().parseExpression(WidthExpr, EndLoc)) {
3977    Error(E, "malformed immediate expression");
3978    return MatchOperand_ParseFail;
3979  }
3980  CE = dyn_cast<MCConstantExpr>(WidthExpr);
3981  if (!CE) {
3982    Error(E, "'width' operand must be an immediate");
3983    return MatchOperand_ParseFail;
3984  }
3985
3986  int64_t Width = CE->getValue();
3987  // The LSB must be in the range [1,32-lsb]
3988  if (Width < 1 || Width > 32 - LSB) {
3989    Error(E, "'width' operand must be in the range [1,32-lsb]");
3990    return MatchOperand_ParseFail;
3991  }
3992
3993  Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc));
3994
3995  return MatchOperand_Success;
3996}
3997
3998ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3999parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4000  // Check for a post-index addressing register operand. Specifically:
4001  // postidx_reg := '+' register {, shift}
4002  //              | '-' register {, shift}
4003  //              | register {, shift}
4004
4005  // This method must return MatchOperand_NoMatch without consuming any tokens
4006  // in the case where there is no match, as other alternatives take other
4007  // parse methods.
4008  AsmToken Tok = Parser.getTok();
4009  SMLoc S = Tok.getLoc();
4010  bool haveEaten = false;
4011  bool isAdd = true;
4012  if (Tok.is(AsmToken::Plus)) {
4013    Parser.Lex(); // Eat the '+' token.
4014    haveEaten = true;
4015  } else if (Tok.is(AsmToken::Minus)) {
4016    Parser.Lex(); // Eat the '-' token.
4017    isAdd = false;
4018    haveEaten = true;
4019  }
4020
4021  SMLoc E = Parser.getTok().getEndLoc();
4022  int Reg = tryParseRegister();
4023  if (Reg == -1) {
4024    if (!haveEaten)
4025      return MatchOperand_NoMatch;
4026    Error(Parser.getTok().getLoc(), "register expected");
4027    return MatchOperand_ParseFail;
4028  }
4029
4030  ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
4031  unsigned ShiftImm = 0;
4032  if (Parser.getTok().is(AsmToken::Comma)) {
4033    Parser.Lex(); // Eat the ','.
4034    if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
4035      return MatchOperand_ParseFail;
4036
4037    // FIXME: Only approximates end...may include intervening whitespace.
4038    E = Parser.getTok().getLoc();
4039  }
4040
4041  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
4042                                                  ShiftImm, S, E));
4043
4044  return MatchOperand_Success;
4045}
4046
4047ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4048parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4049  // Check for a post-index addressing register operand. Specifically:
4050  // am3offset := '+' register
4051  //              | '-' register
4052  //              | register
4053  //              | # imm
4054  //              | # + imm
4055  //              | # - imm
4056
4057  // This method must return MatchOperand_NoMatch without consuming any tokens
4058  // in the case where there is no match, as other alternatives take other
4059  // parse methods.
4060  AsmToken Tok = Parser.getTok();
4061  SMLoc S = Tok.getLoc();
4062
4063  // Do immediates first, as we always parse those if we have a '#'.
4064  if (Parser.getTok().is(AsmToken::Hash) ||
4065      Parser.getTok().is(AsmToken::Dollar)) {
4066    Parser.Lex(); // Eat '#' or '$'.
4067    // Explicitly look for a '-', as we need to encode negative zero
4068    // differently.
4069    bool isNegative = Parser.getTok().is(AsmToken::Minus);
4070    const MCExpr *Offset;
4071    SMLoc E;
4072    if (getParser().parseExpression(Offset, E))
4073      return MatchOperand_ParseFail;
4074    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4075    if (!CE) {
4076      Error(S, "constant expression expected");
4077      return MatchOperand_ParseFail;
4078    }
4079    // Negative zero is encoded as the flag value INT32_MIN.
4080    int32_t Val = CE->getValue();
4081    if (isNegative && Val == 0)
4082      Val = INT32_MIN;
4083
4084    Operands.push_back(
4085      ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
4086
4087    return MatchOperand_Success;
4088  }
4089
4090
4091  bool haveEaten = false;
4092  bool isAdd = true;
4093  if (Tok.is(AsmToken::Plus)) {
4094    Parser.Lex(); // Eat the '+' token.
4095    haveEaten = true;
4096  } else if (Tok.is(AsmToken::Minus)) {
4097    Parser.Lex(); // Eat the '-' token.
4098    isAdd = false;
4099    haveEaten = true;
4100  }
4101
4102  Tok = Parser.getTok();
4103  int Reg = tryParseRegister();
4104  if (Reg == -1) {
4105    if (!haveEaten)
4106      return MatchOperand_NoMatch;
4107    Error(Tok.getLoc(), "register expected");
4108    return MatchOperand_ParseFail;
4109  }
4110
4111  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
4112                                                  0, S, Tok.getEndLoc()));
4113
4114  return MatchOperand_Success;
4115}
4116
4117/// Convert parsed operands to MCInst.  Needed here because this instruction
4118/// only has two register operands, but multiplication is commutative so
4119/// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN".
4120void ARMAsmParser::
4121cvtThumbMultiply(MCInst &Inst,
4122           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4123  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4124  ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
4125  // If we have a three-operand form, make sure to set Rn to be the operand
4126  // that isn't the same as Rd.
4127  unsigned RegOp = 4;
4128  if (Operands.size() == 6 &&
4129      ((ARMOperand*)Operands[4])->getReg() ==
4130        ((ARMOperand*)Operands[3])->getReg())
4131    RegOp = 5;
4132  ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1);
4133  Inst.addOperand(Inst.getOperand(0));
4134  ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
4135}
4136
4137void ARMAsmParser::
4138cvtThumbBranches(MCInst &Inst,
4139           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4140  int CondOp = -1, ImmOp = -1;
4141  switch(Inst.getOpcode()) {
4142    case ARM::tB:
4143    case ARM::tBcc:  CondOp = 1; ImmOp = 2; break;
4144
4145    case ARM::t2B:
4146    case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break;
4147
4148    default: llvm_unreachable("Unexpected instruction in cvtThumbBranches");
4149  }
4150  // first decide whether or not the branch should be conditional
4151  // by looking at it's location relative to an IT block
4152  if(inITBlock()) {
4153    // inside an IT block we cannot have any conditional branches. any
4154    // such instructions needs to be converted to unconditional form
4155    switch(Inst.getOpcode()) {
4156      case ARM::tBcc: Inst.setOpcode(ARM::tB); break;
4157      case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break;
4158    }
4159  } else {
4160    // outside IT blocks we can only have unconditional branches with AL
4161    // condition code or conditional branches with non-AL condition code
4162    unsigned Cond = static_cast<ARMOperand*>(Operands[CondOp])->getCondCode();
4163    switch(Inst.getOpcode()) {
4164      case ARM::tB:
4165      case ARM::tBcc:
4166        Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc);
4167        break;
4168      case ARM::t2B:
4169      case ARM::t2Bcc:
4170        Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc);
4171        break;
4172    }
4173  }
4174
4175  // now decide on encoding size based on branch target range
4176  switch(Inst.getOpcode()) {
4177    // classify tB as either t2B or t1B based on range of immediate operand
4178    case ARM::tB: {
4179      ARMOperand* op = static_cast<ARMOperand*>(Operands[ImmOp]);
4180      if(!op->isSignedOffset<11, 1>() && isThumbTwo())
4181        Inst.setOpcode(ARM::t2B);
4182      break;
4183    }
4184    // classify tBcc as either t2Bcc or t1Bcc based on range of immediate operand
4185    case ARM::tBcc: {
4186      ARMOperand* op = static_cast<ARMOperand*>(Operands[ImmOp]);
4187      if(!op->isSignedOffset<8, 1>() && isThumbTwo())
4188        Inst.setOpcode(ARM::t2Bcc);
4189      break;
4190    }
4191  }
4192  ((ARMOperand*)Operands[ImmOp])->addImmOperands(Inst, 1);
4193  ((ARMOperand*)Operands[CondOp])->addCondCodeOperands(Inst, 2);
4194}
4195
4196/// Parse an ARM memory expression, return false if successful else return true
4197/// or an error.  The first token must be a '[' when called.
4198bool ARMAsmParser::
4199parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4200  SMLoc S, E;
4201  assert(Parser.getTok().is(AsmToken::LBrac) &&
4202         "Token is not a Left Bracket");
4203  S = Parser.getTok().getLoc();
4204  Parser.Lex(); // Eat left bracket token.
4205
4206  const AsmToken &BaseRegTok = Parser.getTok();
4207  int BaseRegNum = tryParseRegister();
4208  if (BaseRegNum == -1)
4209    return Error(BaseRegTok.getLoc(), "register expected");
4210
4211  // The next token must either be a comma, a colon or a closing bracket.
4212  const AsmToken &Tok = Parser.getTok();
4213  if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) &&
4214      !Tok.is(AsmToken::RBrac))
4215    return Error(Tok.getLoc(), "malformed memory operand");
4216
4217  if (Tok.is(AsmToken::RBrac)) {
4218    E = Tok.getEndLoc();
4219    Parser.Lex(); // Eat right bracket token.
4220
4221    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
4222                                             0, 0, false, S, E));
4223
4224    // If there's a pre-indexing writeback marker, '!', just add it as a token
4225    // operand. It's rather odd, but syntactically valid.
4226    if (Parser.getTok().is(AsmToken::Exclaim)) {
4227      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4228      Parser.Lex(); // Eat the '!'.
4229    }
4230
4231    return false;
4232  }
4233
4234  assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) &&
4235         "Lost colon or comma in memory operand?!");
4236  if (Tok.is(AsmToken::Comma)) {
4237    Parser.Lex(); // Eat the comma.
4238  }
4239
4240  // If we have a ':', it's an alignment specifier.
4241  if (Parser.getTok().is(AsmToken::Colon)) {
4242    Parser.Lex(); // Eat the ':'.
4243    E = Parser.getTok().getLoc();
4244
4245    const MCExpr *Expr;
4246    if (getParser().parseExpression(Expr))
4247     return true;
4248
4249    // The expression has to be a constant. Memory references with relocations
4250    // don't come through here, as they use the <label> forms of the relevant
4251    // instructions.
4252    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4253    if (!CE)
4254      return Error (E, "constant expression expected");
4255
4256    unsigned Align = 0;
4257    switch (CE->getValue()) {
4258    default:
4259      return Error(E,
4260                   "alignment specifier must be 16, 32, 64, 128, or 256 bits");
4261    case 16:  Align = 2; break;
4262    case 32:  Align = 4; break;
4263    case 64:  Align = 8; break;
4264    case 128: Align = 16; break;
4265    case 256: Align = 32; break;
4266    }
4267
4268    // Now we should have the closing ']'
4269    if (Parser.getTok().isNot(AsmToken::RBrac))
4270      return Error(Parser.getTok().getLoc(), "']' expected");
4271    E = Parser.getTok().getEndLoc();
4272    Parser.Lex(); // Eat right bracket token.
4273
4274    // Don't worry about range checking the value here. That's handled by
4275    // the is*() predicates.
4276    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0,
4277                                             ARM_AM::no_shift, 0, Align,
4278                                             false, S, E));
4279
4280    // If there's a pre-indexing writeback marker, '!', just add it as a token
4281    // operand.
4282    if (Parser.getTok().is(AsmToken::Exclaim)) {
4283      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4284      Parser.Lex(); // Eat the '!'.
4285    }
4286
4287    return false;
4288  }
4289
4290  // If we have a '#', it's an immediate offset, else assume it's a register
4291  // offset. Be friendly and also accept a plain integer (without a leading
4292  // hash) for gas compatibility.
4293  if (Parser.getTok().is(AsmToken::Hash) ||
4294      Parser.getTok().is(AsmToken::Dollar) ||
4295      Parser.getTok().is(AsmToken::Integer)) {
4296    if (Parser.getTok().isNot(AsmToken::Integer))
4297      Parser.Lex(); // Eat '#' or '$'.
4298    E = Parser.getTok().getLoc();
4299
4300    bool isNegative = getParser().getTok().is(AsmToken::Minus);
4301    const MCExpr *Offset;
4302    if (getParser().parseExpression(Offset))
4303     return true;
4304
4305    // The expression has to be a constant. Memory references with relocations
4306    // don't come through here, as they use the <label> forms of the relevant
4307    // instructions.
4308    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4309    if (!CE)
4310      return Error (E, "constant expression expected");
4311
4312    // If the constant was #-0, represent it as INT32_MIN.
4313    int32_t Val = CE->getValue();
4314    if (isNegative && Val == 0)
4315      CE = MCConstantExpr::Create(INT32_MIN, getContext());
4316
4317    // Now we should have the closing ']'
4318    if (Parser.getTok().isNot(AsmToken::RBrac))
4319      return Error(Parser.getTok().getLoc(), "']' expected");
4320    E = Parser.getTok().getEndLoc();
4321    Parser.Lex(); // Eat right bracket token.
4322
4323    // Don't worry about range checking the value here. That's handled by
4324    // the is*() predicates.
4325    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
4326                                             ARM_AM::no_shift, 0, 0,
4327                                             false, S, E));
4328
4329    // If there's a pre-indexing writeback marker, '!', just add it as a token
4330    // operand.
4331    if (Parser.getTok().is(AsmToken::Exclaim)) {
4332      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4333      Parser.Lex(); // Eat the '!'.
4334    }
4335
4336    return false;
4337  }
4338
4339  // The register offset is optionally preceded by a '+' or '-'
4340  bool isNegative = false;
4341  if (Parser.getTok().is(AsmToken::Minus)) {
4342    isNegative = true;
4343    Parser.Lex(); // Eat the '-'.
4344  } else if (Parser.getTok().is(AsmToken::Plus)) {
4345    // Nothing to do.
4346    Parser.Lex(); // Eat the '+'.
4347  }
4348
4349  E = Parser.getTok().getLoc();
4350  int OffsetRegNum = tryParseRegister();
4351  if (OffsetRegNum == -1)
4352    return Error(E, "register expected");
4353
4354  // If there's a shift operator, handle it.
4355  ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
4356  unsigned ShiftImm = 0;
4357  if (Parser.getTok().is(AsmToken::Comma)) {
4358    Parser.Lex(); // Eat the ','.
4359    if (parseMemRegOffsetShift(ShiftType, ShiftImm))
4360      return true;
4361  }
4362
4363  // Now we should have the closing ']'
4364  if (Parser.getTok().isNot(AsmToken::RBrac))
4365    return Error(Parser.getTok().getLoc(), "']' expected");
4366  E = Parser.getTok().getEndLoc();
4367  Parser.Lex(); // Eat right bracket token.
4368
4369  Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
4370                                           ShiftType, ShiftImm, 0, isNegative,
4371                                           S, E));
4372
4373  // If there's a pre-indexing writeback marker, '!', just add it as a token
4374  // operand.
4375  if (Parser.getTok().is(AsmToken::Exclaim)) {
4376    Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4377    Parser.Lex(); // Eat the '!'.
4378  }
4379
4380  return false;
4381}
4382
4383/// parseMemRegOffsetShift - one of these two:
4384///   ( lsl | lsr | asr | ror ) , # shift_amount
4385///   rrx
4386/// return true if it parses a shift otherwise it returns false.
4387bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
4388                                          unsigned &Amount) {
4389  SMLoc Loc = Parser.getTok().getLoc();
4390  const AsmToken &Tok = Parser.getTok();
4391  if (Tok.isNot(AsmToken::Identifier))
4392    return true;
4393  StringRef ShiftName = Tok.getString();
4394  if (ShiftName == "lsl" || ShiftName == "LSL" ||
4395      ShiftName == "asl" || ShiftName == "ASL")
4396    St = ARM_AM::lsl;
4397  else if (ShiftName == "lsr" || ShiftName == "LSR")
4398    St = ARM_AM::lsr;
4399  else if (ShiftName == "asr" || ShiftName == "ASR")
4400    St = ARM_AM::asr;
4401  else if (ShiftName == "ror" || ShiftName == "ROR")
4402    St = ARM_AM::ror;
4403  else if (ShiftName == "rrx" || ShiftName == "RRX")
4404    St = ARM_AM::rrx;
4405  else
4406    return Error(Loc, "illegal shift operator");
4407  Parser.Lex(); // Eat shift type token.
4408
4409  // rrx stands alone.
4410  Amount = 0;
4411  if (St != ARM_AM::rrx) {
4412    Loc = Parser.getTok().getLoc();
4413    // A '#' and a shift amount.
4414    const AsmToken &HashTok = Parser.getTok();
4415    if (HashTok.isNot(AsmToken::Hash) &&
4416        HashTok.isNot(AsmToken::Dollar))
4417      return Error(HashTok.getLoc(), "'#' expected");
4418    Parser.Lex(); // Eat hash token.
4419
4420    const MCExpr *Expr;
4421    if (getParser().parseExpression(Expr))
4422      return true;
4423    // Range check the immediate.
4424    // lsl, ror: 0 <= imm <= 31
4425    // lsr, asr: 0 <= imm <= 32
4426    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4427    if (!CE)
4428      return Error(Loc, "shift amount must be an immediate");
4429    int64_t Imm = CE->getValue();
4430    if (Imm < 0 ||
4431        ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
4432        ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
4433      return Error(Loc, "immediate shift value out of range");
4434    // If <ShiftTy> #0, turn it into a no_shift.
4435    if (Imm == 0)
4436      St = ARM_AM::lsl;
4437    // For consistency, treat lsr #32 and asr #32 as having immediate value 0.
4438    if (Imm == 32)
4439      Imm = 0;
4440    Amount = Imm;
4441  }
4442
4443  return false;
4444}
4445
4446/// parseFPImm - A floating point immediate expression operand.
4447ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4448parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4449  // Anything that can accept a floating point constant as an operand
4450  // needs to go through here, as the regular parseExpression is
4451  // integer only.
4452  //
4453  // This routine still creates a generic Immediate operand, containing
4454  // a bitcast of the 64-bit floating point value. The various operands
4455  // that accept floats can check whether the value is valid for them
4456  // via the standard is*() predicates.
4457
4458  SMLoc S = Parser.getTok().getLoc();
4459
4460  if (Parser.getTok().isNot(AsmToken::Hash) &&
4461      Parser.getTok().isNot(AsmToken::Dollar))
4462    return MatchOperand_NoMatch;
4463
4464  // Disambiguate the VMOV forms that can accept an FP immediate.
4465  // vmov.f32 <sreg>, #imm
4466  // vmov.f64 <dreg>, #imm
4467  // vmov.f32 <dreg>, #imm  @ vector f32x2
4468  // vmov.f32 <qreg>, #imm  @ vector f32x4
4469  //
4470  // There are also the NEON VMOV instructions which expect an
4471  // integer constant. Make sure we don't try to parse an FPImm
4472  // for these:
4473  // vmov.i{8|16|32|64} <dreg|qreg>, #imm
4474  ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]);
4475  if (!TyOp->isToken() || (TyOp->getToken() != ".f32" &&
4476                           TyOp->getToken() != ".f64"))
4477    return MatchOperand_NoMatch;
4478
4479  Parser.Lex(); // Eat '#' or '$'.
4480
4481  // Handle negation, as that still comes through as a separate token.
4482  bool isNegative = false;
4483  if (Parser.getTok().is(AsmToken::Minus)) {
4484    isNegative = true;
4485    Parser.Lex();
4486  }
4487  const AsmToken &Tok = Parser.getTok();
4488  SMLoc Loc = Tok.getLoc();
4489  if (Tok.is(AsmToken::Real)) {
4490    APFloat RealVal(APFloat::IEEEsingle, Tok.getString());
4491    uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
4492    // If we had a '-' in front, toggle the sign bit.
4493    IntVal ^= (uint64_t)isNegative << 31;
4494    Parser.Lex(); // Eat the token.
4495    Operands.push_back(ARMOperand::CreateImm(
4496          MCConstantExpr::Create(IntVal, getContext()),
4497          S, Parser.getTok().getLoc()));
4498    return MatchOperand_Success;
4499  }
4500  // Also handle plain integers. Instructions which allow floating point
4501  // immediates also allow a raw encoded 8-bit value.
4502  if (Tok.is(AsmToken::Integer)) {
4503    int64_t Val = Tok.getIntVal();
4504    Parser.Lex(); // Eat the token.
4505    if (Val > 255 || Val < 0) {
4506      Error(Loc, "encoded floating point value out of range");
4507      return MatchOperand_ParseFail;
4508    }
4509    double RealVal = ARM_AM::getFPImmFloat(Val);
4510    Val = APFloat(APFloat::IEEEdouble, RealVal).bitcastToAPInt().getZExtValue();
4511    Operands.push_back(ARMOperand::CreateImm(
4512        MCConstantExpr::Create(Val, getContext()), S,
4513        Parser.getTok().getLoc()));
4514    return MatchOperand_Success;
4515  }
4516
4517  Error(Loc, "invalid floating point immediate");
4518  return MatchOperand_ParseFail;
4519}
4520
4521/// Parse a arm instruction operand.  For now this parses the operand regardless
4522/// of the mnemonic.
4523bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
4524                                StringRef Mnemonic) {
4525  SMLoc S, E;
4526
4527  // Check if the current operand has a custom associated parser, if so, try to
4528  // custom parse the operand, or fallback to the general approach.
4529  OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
4530  if (ResTy == MatchOperand_Success)
4531    return false;
4532  // If there wasn't a custom match, try the generic matcher below. Otherwise,
4533  // there was a match, but an error occurred, in which case, just return that
4534  // the operand parsing failed.
4535  if (ResTy == MatchOperand_ParseFail)
4536    return true;
4537
4538  switch (getLexer().getKind()) {
4539  default:
4540    Error(Parser.getTok().getLoc(), "unexpected token in operand");
4541    return true;
4542  case AsmToken::Identifier: {
4543    // If we've seen a branch mnemonic, the next operand must be a label.  This
4544    // is true even if the label is a register name.  So "br r1" means branch to
4545    // label "r1".
4546    bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl";
4547    if (!ExpectLabel) {
4548      if (!tryParseRegisterWithWriteBack(Operands))
4549        return false;
4550      int Res = tryParseShiftRegister(Operands);
4551      if (Res == 0) // success
4552        return false;
4553      else if (Res == -1) // irrecoverable error
4554        return true;
4555      // If this is VMRS, check for the apsr_nzcv operand.
4556      if (Mnemonic == "vmrs" &&
4557          Parser.getTok().getString().equals_lower("apsr_nzcv")) {
4558        S = Parser.getTok().getLoc();
4559        Parser.Lex();
4560        Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
4561        return false;
4562      }
4563    }
4564
4565    // Fall though for the Identifier case that is not a register or a
4566    // special name.
4567  }
4568  case AsmToken::LParen:  // parenthesized expressions like (_strcmp-4)
4569  case AsmToken::Integer: // things like 1f and 2b as a branch targets
4570  case AsmToken::String:  // quoted label names.
4571  case AsmToken::Dot: {   // . as a branch target
4572    // This was not a register so parse other operands that start with an
4573    // identifier (like labels) as expressions and create them as immediates.
4574    const MCExpr *IdVal;
4575    S = Parser.getTok().getLoc();
4576    if (getParser().parseExpression(IdVal))
4577      return true;
4578    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4579    Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
4580    return false;
4581  }
4582  case AsmToken::LBrac:
4583    return parseMemory(Operands);
4584  case AsmToken::LCurly:
4585    return parseRegisterList(Operands);
4586  case AsmToken::Dollar:
4587  case AsmToken::Hash: {
4588    // #42 -> immediate.
4589    S = Parser.getTok().getLoc();
4590    Parser.Lex();
4591
4592    if (Parser.getTok().isNot(AsmToken::Colon)) {
4593      bool isNegative = Parser.getTok().is(AsmToken::Minus);
4594      const MCExpr *ImmVal;
4595      if (getParser().parseExpression(ImmVal))
4596        return true;
4597      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
4598      if (CE) {
4599        int32_t Val = CE->getValue();
4600        if (isNegative && Val == 0)
4601          ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
4602      }
4603      E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4604      Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
4605
4606      // There can be a trailing '!' on operands that we want as a separate
4607      // '!' Token operand. Handle that here. For example, the compatibilty
4608      // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'.
4609      if (Parser.getTok().is(AsmToken::Exclaim)) {
4610        Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(),
4611                                                   Parser.getTok().getLoc()));
4612        Parser.Lex(); // Eat exclaim token
4613      }
4614      return false;
4615    }
4616    // w/ a ':' after the '#', it's just like a plain ':'.
4617    // FALLTHROUGH
4618  }
4619  case AsmToken::Colon: {
4620    // ":lower16:" and ":upper16:" expression prefixes
4621    // FIXME: Check it's an expression prefix,
4622    // e.g. (FOO - :lower16:BAR) isn't legal.
4623    ARMMCExpr::VariantKind RefKind;
4624    if (parsePrefix(RefKind))
4625      return true;
4626
4627    const MCExpr *SubExprVal;
4628    if (getParser().parseExpression(SubExprVal))
4629      return true;
4630
4631    const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
4632                                              getContext());
4633    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4634    Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
4635    return false;
4636  }
4637  }
4638}
4639
4640// parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
4641//  :lower16: and :upper16:.
4642bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
4643  RefKind = ARMMCExpr::VK_ARM_None;
4644
4645  // :lower16: and :upper16: modifiers
4646  assert(getLexer().is(AsmToken::Colon) && "expected a :");
4647  Parser.Lex(); // Eat ':'
4648
4649  if (getLexer().isNot(AsmToken::Identifier)) {
4650    Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
4651    return true;
4652  }
4653
4654  StringRef IDVal = Parser.getTok().getIdentifier();
4655  if (IDVal == "lower16") {
4656    RefKind = ARMMCExpr::VK_ARM_LO16;
4657  } else if (IDVal == "upper16") {
4658    RefKind = ARMMCExpr::VK_ARM_HI16;
4659  } else {
4660    Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
4661    return true;
4662  }
4663  Parser.Lex();
4664
4665  if (getLexer().isNot(AsmToken::Colon)) {
4666    Error(Parser.getTok().getLoc(), "unexpected token after prefix");
4667    return true;
4668  }
4669  Parser.Lex(); // Eat the last ':'
4670  return false;
4671}
4672
4673/// \brief Given a mnemonic, split out possible predication code and carry
4674/// setting letters to form a canonical mnemonic and flags.
4675//
4676// FIXME: Would be nice to autogen this.
4677// FIXME: This is a bit of a maze of special cases.
4678StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
4679                                      unsigned &PredicationCode,
4680                                      bool &CarrySetting,
4681                                      unsigned &ProcessorIMod,
4682                                      StringRef &ITMask) {
4683  PredicationCode = ARMCC::AL;
4684  CarrySetting = false;
4685  ProcessorIMod = 0;
4686
4687  // Ignore some mnemonics we know aren't predicated forms.
4688  //
4689  // FIXME: Would be nice to autogen this.
4690  if ((Mnemonic == "movs" && isThumb()) ||
4691      Mnemonic == "teq"   || Mnemonic == "vceq"   || Mnemonic == "svc"   ||
4692      Mnemonic == "mls"   || Mnemonic == "smmls"  || Mnemonic == "vcls"  ||
4693      Mnemonic == "vmls"  || Mnemonic == "vnmls"  || Mnemonic == "vacge" ||
4694      Mnemonic == "vcge"  || Mnemonic == "vclt"   || Mnemonic == "vacgt" ||
4695      Mnemonic == "vaclt" || Mnemonic == "vacle"  || Mnemonic == "hlt" ||
4696      Mnemonic == "vcgt"  || Mnemonic == "vcle"   || Mnemonic == "smlal" ||
4697      Mnemonic == "umaal" || Mnemonic == "umlal"  || Mnemonic == "vabal" ||
4698      Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
4699      Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" ||
4700      Mnemonic == "vcvta" || Mnemonic == "vcvtn"  || Mnemonic == "vcvtp" ||
4701      Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" ||
4702      Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic.startswith("vsel"))
4703    return Mnemonic;
4704
4705  // First, split out any predication code. Ignore mnemonics we know aren't
4706  // predicated but do have a carry-set and so weren't caught above.
4707  if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
4708      Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
4709      Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
4710      Mnemonic != "sbcs" && Mnemonic != "rscs") {
4711    unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
4712      .Case("eq", ARMCC::EQ)
4713      .Case("ne", ARMCC::NE)
4714      .Case("hs", ARMCC::HS)
4715      .Case("cs", ARMCC::HS)
4716      .Case("lo", ARMCC::LO)
4717      .Case("cc", ARMCC::LO)
4718      .Case("mi", ARMCC::MI)
4719      .Case("pl", ARMCC::PL)
4720      .Case("vs", ARMCC::VS)
4721      .Case("vc", ARMCC::VC)
4722      .Case("hi", ARMCC::HI)
4723      .Case("ls", ARMCC::LS)
4724      .Case("ge", ARMCC::GE)
4725      .Case("lt", ARMCC::LT)
4726      .Case("gt", ARMCC::GT)
4727      .Case("le", ARMCC::LE)
4728      .Case("al", ARMCC::AL)
4729      .Default(~0U);
4730    if (CC != ~0U) {
4731      Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
4732      PredicationCode = CC;
4733    }
4734  }
4735
4736  // Next, determine if we have a carry setting bit. We explicitly ignore all
4737  // the instructions we know end in 's'.
4738  if (Mnemonic.endswith("s") &&
4739      !(Mnemonic == "cps" || Mnemonic == "mls" ||
4740        Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
4741        Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
4742        Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
4743        Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
4744        Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
4745        Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
4746        Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
4747        Mnemonic == "vfms" || Mnemonic == "vfnms" ||
4748        (Mnemonic == "movs" && isThumb()))) {
4749    Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
4750    CarrySetting = true;
4751  }
4752
4753  // The "cps" instruction can have a interrupt mode operand which is glued into
4754  // the mnemonic. Check if this is the case, split it and parse the imod op
4755  if (Mnemonic.startswith("cps")) {
4756    // Split out any imod code.
4757    unsigned IMod =
4758      StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
4759      .Case("ie", ARM_PROC::IE)
4760      .Case("id", ARM_PROC::ID)
4761      .Default(~0U);
4762    if (IMod != ~0U) {
4763      Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
4764      ProcessorIMod = IMod;
4765    }
4766  }
4767
4768  // The "it" instruction has the condition mask on the end of the mnemonic.
4769  if (Mnemonic.startswith("it")) {
4770    ITMask = Mnemonic.slice(2, Mnemonic.size());
4771    Mnemonic = Mnemonic.slice(0, 2);
4772  }
4773
4774  return Mnemonic;
4775}
4776
4777/// \brief Given a canonical mnemonic, determine if the instruction ever allows
4778/// inclusion of carry set or predication code operands.
4779//
4780// FIXME: It would be nice to autogen this.
4781void ARMAsmParser::
4782getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
4783                     bool &CanAcceptCarrySet, bool &CanAcceptPredicationCode) {
4784  if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
4785      Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
4786      Mnemonic == "add" || Mnemonic == "adc" ||
4787      Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
4788      Mnemonic == "orr" || Mnemonic == "mvn" ||
4789      Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
4790      Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
4791      Mnemonic == "vfm" || Mnemonic == "vfnm" ||
4792      (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
4793                      Mnemonic == "mla" || Mnemonic == "smlal" ||
4794                      Mnemonic == "umlal" || Mnemonic == "umull"))) {
4795    CanAcceptCarrySet = true;
4796  } else
4797    CanAcceptCarrySet = false;
4798
4799  if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
4800      Mnemonic == "cps" ||  Mnemonic == "it" ||  Mnemonic == "cbz" ||
4801      Mnemonic == "trap" || Mnemonic == "hlt" || Mnemonic.startswith("crc32") ||
4802      Mnemonic.startswith("cps") || Mnemonic.startswith("vsel") ||
4803      Mnemonic == "vmaxnm" || Mnemonic == "vminnm" || Mnemonic == "vcvta" ||
4804      Mnemonic == "vcvtn" || Mnemonic == "vcvtp" || Mnemonic == "vcvtm" ||
4805      Mnemonic == "vrinta" || Mnemonic == "vrintn" || Mnemonic == "vrintp" ||
4806      Mnemonic == "vrintm" || Mnemonic.startswith("aes") ||
4807      Mnemonic.startswith("sha1") || Mnemonic.startswith("sha256") ||
4808      (FullInst.startswith("vmull") && FullInst.endswith(".p64"))) {
4809    // These mnemonics are never predicable
4810    CanAcceptPredicationCode = false;
4811  } else if (!isThumb()) {
4812    // Some instructions are only predicable in Thumb mode
4813    CanAcceptPredicationCode
4814      = Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" &&
4815        Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" &&
4816        Mnemonic != "dmb" && Mnemonic != "dsb" && Mnemonic != "isb" &&
4817        Mnemonic != "pld" && Mnemonic != "pli" && Mnemonic != "pldw" &&
4818        Mnemonic != "ldc2" && Mnemonic != "ldc2l" &&
4819        Mnemonic != "stc2" && Mnemonic != "stc2l" &&
4820        !Mnemonic.startswith("rfe") && !Mnemonic.startswith("srs");
4821  } else if (isThumbOne()) {
4822    CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs";
4823  } else
4824    CanAcceptPredicationCode = true;
4825}
4826
4827bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
4828                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4829  // FIXME: This is all horribly hacky. We really need a better way to deal
4830  // with optional operands like this in the matcher table.
4831
4832  // The 'mov' mnemonic is special. One variant has a cc_out operand, while
4833  // another does not. Specifically, the MOVW instruction does not. So we
4834  // special case it here and remove the defaulted (non-setting) cc_out
4835  // operand if that's the instruction we're trying to match.
4836  //
4837  // We do this as post-processing of the explicit operands rather than just
4838  // conditionally adding the cc_out in the first place because we need
4839  // to check the type of the parsed immediate operand.
4840  if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
4841      !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
4842      static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
4843      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4844    return true;
4845
4846  // Register-register 'add' for thumb does not have a cc_out operand
4847  // when there are only two register operands.
4848  if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
4849      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4850      static_cast<ARMOperand*>(Operands[4])->isReg() &&
4851      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4852    return true;
4853  // Register-register 'add' for thumb does not have a cc_out operand
4854  // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
4855  // have to check the immediate range here since Thumb2 has a variant
4856  // that can handle a different range and has a cc_out operand.
4857  if (((isThumb() && Mnemonic == "add") ||
4858       (isThumbTwo() && Mnemonic == "sub")) &&
4859      Operands.size() == 6 &&
4860      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4861      static_cast<ARMOperand*>(Operands[4])->isReg() &&
4862      static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
4863      static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4864      ((Mnemonic == "add" &&static_cast<ARMOperand*>(Operands[5])->isReg()) ||
4865       static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
4866    return true;
4867  // For Thumb2, add/sub immediate does not have a cc_out operand for the
4868  // imm0_4095 variant. That's the least-preferred variant when
4869  // selecting via the generic "add" mnemonic, so to know that we
4870  // should remove the cc_out operand, we have to explicitly check that
4871  // it's not one of the other variants. Ugh.
4872  if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
4873      Operands.size() == 6 &&
4874      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4875      static_cast<ARMOperand*>(Operands[4])->isReg() &&
4876      static_cast<ARMOperand*>(Operands[5])->isImm()) {
4877    // Nest conditions rather than one big 'if' statement for readability.
4878    //
4879    // If both registers are low, we're in an IT block, and the immediate is
4880    // in range, we should use encoding T1 instead, which has a cc_out.
4881    if (inITBlock() &&
4882        isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
4883        isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
4884        static_cast<ARMOperand*>(Operands[5])->isImm0_7())
4885      return false;
4886    // Check against T3. If the second register is the PC, this is an
4887    // alternate form of ADR, which uses encoding T4, so check for that too.
4888    if (static_cast<ARMOperand*>(Operands[4])->getReg() != ARM::PC &&
4889        static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
4890      return false;
4891
4892    // Otherwise, we use encoding T4, which does not have a cc_out
4893    // operand.
4894    return true;
4895  }
4896
4897  // The thumb2 multiply instruction doesn't have a CCOut register, so
4898  // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
4899  // use the 16-bit encoding or not.
4900  if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
4901      static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4902      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4903      static_cast<ARMOperand*>(Operands[4])->isReg() &&
4904      static_cast<ARMOperand*>(Operands[5])->isReg() &&
4905      // If the registers aren't low regs, the destination reg isn't the
4906      // same as one of the source regs, or the cc_out operand is zero
4907      // outside of an IT block, we have to use the 32-bit encoding, so
4908      // remove the cc_out operand.
4909      (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4910       !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4911       !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) ||
4912       !inITBlock() ||
4913       (static_cast<ARMOperand*>(Operands[3])->getReg() !=
4914        static_cast<ARMOperand*>(Operands[5])->getReg() &&
4915        static_cast<ARMOperand*>(Operands[3])->getReg() !=
4916        static_cast<ARMOperand*>(Operands[4])->getReg())))
4917    return true;
4918
4919  // Also check the 'mul' syntax variant that doesn't specify an explicit
4920  // destination register.
4921  if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
4922      static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4923      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4924      static_cast<ARMOperand*>(Operands[4])->isReg() &&
4925      // If the registers aren't low regs  or the cc_out operand is zero
4926      // outside of an IT block, we have to use the 32-bit encoding, so
4927      // remove the cc_out operand.
4928      (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4929       !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4930       !inITBlock()))
4931    return true;
4932
4933
4934
4935  // Register-register 'add/sub' for thumb does not have a cc_out operand
4936  // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
4937  // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
4938  // right, this will result in better diagnostics (which operand is off)
4939  // anyway.
4940  if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
4941      (Operands.size() == 5 || Operands.size() == 6) &&
4942      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4943      static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
4944      static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4945      (static_cast<ARMOperand*>(Operands[4])->isImm() ||
4946       (Operands.size() == 6 &&
4947        static_cast<ARMOperand*>(Operands[5])->isImm())))
4948    return true;
4949
4950  return false;
4951}
4952
4953bool ARMAsmParser::shouldOmitPredicateOperand(
4954    StringRef Mnemonic, SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
4955  // VRINT{Z, R, X} have a predicate operand in VFP, but not in NEON
4956  unsigned RegIdx = 3;
4957  if ((Mnemonic == "vrintz" || Mnemonic == "vrintx" || Mnemonic == "vrintr") &&
4958      static_cast<ARMOperand *>(Operands[2])->getToken() == ".f32") {
4959    if (static_cast<ARMOperand *>(Operands[3])->isToken() &&
4960        static_cast<ARMOperand *>(Operands[3])->getToken() == ".f32")
4961      RegIdx = 4;
4962
4963    if (static_cast<ARMOperand *>(Operands[RegIdx])->isReg() &&
4964        (ARMMCRegisterClasses[ARM::DPRRegClassID]
4965             .contains(static_cast<ARMOperand *>(Operands[RegIdx])->getReg()) ||
4966         ARMMCRegisterClasses[ARM::QPRRegClassID]
4967             .contains(static_cast<ARMOperand *>(Operands[RegIdx])->getReg())))
4968      return true;
4969  }
4970  return false;
4971}
4972
4973static bool isDataTypeToken(StringRef Tok) {
4974  return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
4975    Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
4976    Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
4977    Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
4978    Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
4979    Tok == ".f" || Tok == ".d";
4980}
4981
4982// FIXME: This bit should probably be handled via an explicit match class
4983// in the .td files that matches the suffix instead of having it be
4984// a literal string token the way it is now.
4985static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
4986  return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
4987}
4988static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features,
4989                                 unsigned VariantID);
4990/// Parse an arm instruction mnemonic followed by its operands.
4991bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
4992                                    SMLoc NameLoc,
4993                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4994  // Apply mnemonic aliases before doing anything else, as the destination
4995  // mnemnonic may include suffices and we want to handle them normally.
4996  // The generic tblgen'erated code does this later, at the start of
4997  // MatchInstructionImpl(), but that's too late for aliases that include
4998  // any sort of suffix.
4999  unsigned AvailableFeatures = getAvailableFeatures();
5000  unsigned AssemblerDialect = getParser().getAssemblerDialect();
5001  applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect);
5002
5003  // First check for the ARM-specific .req directive.
5004  if (Parser.getTok().is(AsmToken::Identifier) &&
5005      Parser.getTok().getIdentifier() == ".req") {
5006    parseDirectiveReq(Name, NameLoc);
5007    // We always return 'error' for this, as we're done with this
5008    // statement and don't need to match the 'instruction."
5009    return true;
5010  }
5011
5012  // Create the leading tokens for the mnemonic, split by '.' characters.
5013  size_t Start = 0, Next = Name.find('.');
5014  StringRef Mnemonic = Name.slice(Start, Next);
5015
5016  // Split out the predication code and carry setting flag from the mnemonic.
5017  unsigned PredicationCode;
5018  unsigned ProcessorIMod;
5019  bool CarrySetting;
5020  StringRef ITMask;
5021  Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
5022                           ProcessorIMod, ITMask);
5023
5024  // In Thumb1, only the branch (B) instruction can be predicated.
5025  if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
5026    Parser.eatToEndOfStatement();
5027    return Error(NameLoc, "conditional execution not supported in Thumb1");
5028  }
5029
5030  Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
5031
5032  // Handle the IT instruction ITMask. Convert it to a bitmask. This
5033  // is the mask as it will be for the IT encoding if the conditional
5034  // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
5035  // where the conditional bit0 is zero, the instruction post-processing
5036  // will adjust the mask accordingly.
5037  if (Mnemonic == "it") {
5038    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
5039    if (ITMask.size() > 3) {
5040      Parser.eatToEndOfStatement();
5041      return Error(Loc, "too many conditions on IT instruction");
5042    }
5043    unsigned Mask = 8;
5044    for (unsigned i = ITMask.size(); i != 0; --i) {
5045      char pos = ITMask[i - 1];
5046      if (pos != 't' && pos != 'e') {
5047        Parser.eatToEndOfStatement();
5048        return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
5049      }
5050      Mask >>= 1;
5051      if (ITMask[i - 1] == 't')
5052        Mask |= 8;
5053    }
5054    Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
5055  }
5056
5057  // FIXME: This is all a pretty gross hack. We should automatically handle
5058  // optional operands like this via tblgen.
5059
5060  // Next, add the CCOut and ConditionCode operands, if needed.
5061  //
5062  // For mnemonics which can ever incorporate a carry setting bit or predication
5063  // code, our matching model involves us always generating CCOut and
5064  // ConditionCode operands to match the mnemonic "as written" and then we let
5065  // the matcher deal with finding the right instruction or generating an
5066  // appropriate error.
5067  bool CanAcceptCarrySet, CanAcceptPredicationCode;
5068  getMnemonicAcceptInfo(Mnemonic, Name, CanAcceptCarrySet, CanAcceptPredicationCode);
5069
5070  // If we had a carry-set on an instruction that can't do that, issue an
5071  // error.
5072  if (!CanAcceptCarrySet && CarrySetting) {
5073    Parser.eatToEndOfStatement();
5074    return Error(NameLoc, "instruction '" + Mnemonic +
5075                 "' can not set flags, but 's' suffix specified");
5076  }
5077  // If we had a predication code on an instruction that can't do that, issue an
5078  // error.
5079  if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
5080    Parser.eatToEndOfStatement();
5081    return Error(NameLoc, "instruction '" + Mnemonic +
5082                 "' is not predicable, but condition code specified");
5083  }
5084
5085  // Add the carry setting operand, if necessary.
5086  if (CanAcceptCarrySet) {
5087    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
5088    Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
5089                                               Loc));
5090  }
5091
5092  // Add the predication code operand, if necessary.
5093  if (CanAcceptPredicationCode) {
5094    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
5095                                      CarrySetting);
5096    Operands.push_back(ARMOperand::CreateCondCode(
5097                         ARMCC::CondCodes(PredicationCode), Loc));
5098  }
5099
5100  // Add the processor imod operand, if necessary.
5101  if (ProcessorIMod) {
5102    Operands.push_back(ARMOperand::CreateImm(
5103          MCConstantExpr::Create(ProcessorIMod, getContext()),
5104                                 NameLoc, NameLoc));
5105  }
5106
5107  // Add the remaining tokens in the mnemonic.
5108  while (Next != StringRef::npos) {
5109    Start = Next;
5110    Next = Name.find('.', Start + 1);
5111    StringRef ExtraToken = Name.slice(Start, Next);
5112
5113    // Some NEON instructions have an optional datatype suffix that is
5114    // completely ignored. Check for that.
5115    if (isDataTypeToken(ExtraToken) &&
5116        doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
5117      continue;
5118
5119    // For for ARM mode generate an error if the .n qualifier is used.
5120    if (ExtraToken == ".n" && !isThumb()) {
5121      SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5122      return Error(Loc, "instruction with .n (narrow) qualifier not allowed in "
5123                   "arm mode");
5124    }
5125
5126    // The .n qualifier is always discarded as that is what the tables
5127    // and matcher expect.  In ARM mode the .w qualifier has no effect,
5128    // so discard it to avoid errors that can be caused by the matcher.
5129    if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) {
5130      SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5131      Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
5132    }
5133  }
5134
5135  // Read the remaining operands.
5136  if (getLexer().isNot(AsmToken::EndOfStatement)) {
5137    // Read the first operand.
5138    if (parseOperand(Operands, Mnemonic)) {
5139      Parser.eatToEndOfStatement();
5140      return true;
5141    }
5142
5143    while (getLexer().is(AsmToken::Comma)) {
5144      Parser.Lex();  // Eat the comma.
5145
5146      // Parse and remember the operand.
5147      if (parseOperand(Operands, Mnemonic)) {
5148        Parser.eatToEndOfStatement();
5149        return true;
5150      }
5151    }
5152  }
5153
5154  if (getLexer().isNot(AsmToken::EndOfStatement)) {
5155    SMLoc Loc = getLexer().getLoc();
5156    Parser.eatToEndOfStatement();
5157    return Error(Loc, "unexpected token in argument list");
5158  }
5159
5160  Parser.Lex(); // Consume the EndOfStatement
5161
5162  // Some instructions, mostly Thumb, have forms for the same mnemonic that
5163  // do and don't have a cc_out optional-def operand. With some spot-checks
5164  // of the operand list, we can figure out which variant we're trying to
5165  // parse and adjust accordingly before actually matching. We shouldn't ever
5166  // try to remove a cc_out operand that was explicitly set on the the
5167  // mnemonic, of course (CarrySetting == true). Reason number #317 the
5168  // table driven matcher doesn't fit well with the ARM instruction set.
5169  if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
5170    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5171    Operands.erase(Operands.begin() + 1);
5172    delete Op;
5173  }
5174
5175  // Some instructions have the same mnemonic, but don't always
5176  // have a predicate. Distinguish them here and delete the
5177  // predicate if needed.
5178  if (shouldOmitPredicateOperand(Mnemonic, Operands)) {
5179    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5180    Operands.erase(Operands.begin() + 1);
5181    delete Op;
5182  }
5183
5184  // ARM mode 'blx' need special handling, as the register operand version
5185  // is predicable, but the label operand version is not. So, we can't rely
5186  // on the Mnemonic based checking to correctly figure out when to put
5187  // a k_CondCode operand in the list. If we're trying to match the label
5188  // version, remove the k_CondCode operand here.
5189  if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
5190      static_cast<ARMOperand*>(Operands[2])->isImm()) {
5191    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5192    Operands.erase(Operands.begin() + 1);
5193    delete Op;
5194  }
5195
5196  // Adjust operands of ldrexd/strexd to MCK_GPRPair.
5197  // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
5198  // a single GPRPair reg operand is used in the .td file to replace the two
5199  // GPRs. However, when parsing from asm, the two GRPs cannot be automatically
5200  // expressed as a GPRPair, so we have to manually merge them.
5201  // FIXME: We would really like to be able to tablegen'erate this.
5202  if (!isThumb() && Operands.size() > 4 &&
5203      (Mnemonic == "ldrexd" || Mnemonic == "strexd" || Mnemonic == "ldaexd" ||
5204       Mnemonic == "stlexd")) {
5205    bool isLoad = (Mnemonic == "ldrexd" || Mnemonic == "ldaexd");
5206    unsigned Idx = isLoad ? 2 : 3;
5207    ARMOperand* Op1 = static_cast<ARMOperand*>(Operands[Idx]);
5208    ARMOperand* Op2 = static_cast<ARMOperand*>(Operands[Idx+1]);
5209
5210    const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID);
5211    // Adjust only if Op1 and Op2 are GPRs.
5212    if (Op1->isReg() && Op2->isReg() && MRC.contains(Op1->getReg()) &&
5213        MRC.contains(Op2->getReg())) {
5214      unsigned Reg1 = Op1->getReg();
5215      unsigned Reg2 = Op2->getReg();
5216      unsigned Rt = MRI->getEncodingValue(Reg1);
5217      unsigned Rt2 = MRI->getEncodingValue(Reg2);
5218
5219      // Rt2 must be Rt + 1 and Rt must be even.
5220      if (Rt + 1 != Rt2 || (Rt & 1)) {
5221        Error(Op2->getStartLoc(), isLoad ?
5222            "destination operands must be sequential" :
5223            "source operands must be sequential");
5224        return true;
5225      }
5226      unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0,
5227          &(MRI->getRegClass(ARM::GPRPairRegClassID)));
5228      Operands.erase(Operands.begin() + Idx, Operands.begin() + Idx + 2);
5229      Operands.insert(Operands.begin() + Idx, ARMOperand::CreateReg(
5230            NewReg, Op1->getStartLoc(), Op2->getEndLoc()));
5231      delete Op1;
5232      delete Op2;
5233    }
5234  }
5235
5236  // FIXME: As said above, this is all a pretty gross hack.  This instruction
5237  // does not fit with other "subs" and tblgen.
5238  // Adjust operands of B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction
5239  // so the Mnemonic is the original name "subs" and delete the predicate
5240  // operand so it will match the table entry.
5241  if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 &&
5242      static_cast<ARMOperand*>(Operands[3])->isReg() &&
5243      static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::PC &&
5244      static_cast<ARMOperand*>(Operands[4])->isReg() &&
5245      static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::LR &&
5246      static_cast<ARMOperand*>(Operands[5])->isImm()) {
5247    ARMOperand *Op0 = static_cast<ARMOperand*>(Operands[0]);
5248    Operands.erase(Operands.begin());
5249    delete Op0;
5250    Operands.insert(Operands.begin(), ARMOperand::CreateToken(Name, NameLoc));
5251
5252    ARMOperand *Op1 = static_cast<ARMOperand*>(Operands[1]);
5253    Operands.erase(Operands.begin() + 1);
5254    delete Op1;
5255  }
5256  return false;
5257}
5258
5259// Validate context-sensitive operand constraints.
5260
5261// return 'true' if register list contains non-low GPR registers,
5262// 'false' otherwise. If Reg is in the register list or is HiReg, set
5263// 'containsReg' to true.
5264static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
5265                                 unsigned HiReg, bool &containsReg) {
5266  containsReg = false;
5267  for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5268    unsigned OpReg = Inst.getOperand(i).getReg();
5269    if (OpReg == Reg)
5270      containsReg = true;
5271    // Anything other than a low register isn't legal here.
5272    if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
5273      return true;
5274  }
5275  return false;
5276}
5277
5278// Check if the specified regisgter is in the register list of the inst,
5279// starting at the indicated operand number.
5280static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
5281  for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5282    unsigned OpReg = Inst.getOperand(i).getReg();
5283    if (OpReg == Reg)
5284      return true;
5285  }
5286  return false;
5287}
5288
5289// Return true if instruction has the interesting property of being
5290// allowed in IT blocks, but not being predicable.
5291static bool instIsBreakpoint(const MCInst &Inst) {
5292    return Inst.getOpcode() == ARM::tBKPT ||
5293           Inst.getOpcode() == ARM::BKPT ||
5294           Inst.getOpcode() == ARM::tHLT ||
5295           Inst.getOpcode() == ARM::HLT;
5296
5297}
5298
5299// FIXME: We would really like to be able to tablegen'erate this.
5300bool ARMAsmParser::
5301validateInstruction(MCInst &Inst,
5302                    const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5303  const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
5304  SMLoc Loc = Operands[0]->getStartLoc();
5305
5306  // Check the IT block state first.
5307  // NOTE: BKPT and HLT instructions have the interesting property of being
5308  // allowed in IT blocks, but not being predicable. They just always execute.
5309  if (inITBlock() && !instIsBreakpoint(Inst)) {
5310    unsigned Bit = 1;
5311    if (ITState.FirstCond)
5312      ITState.FirstCond = false;
5313    else
5314      Bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
5315    // The instruction must be predicable.
5316    if (!MCID.isPredicable())
5317      return Error(Loc, "instructions in IT block must be predicable");
5318    unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
5319    unsigned ITCond = Bit ? ITState.Cond :
5320      ARMCC::getOppositeCondition(ITState.Cond);
5321    if (Cond != ITCond) {
5322      // Find the condition code Operand to get its SMLoc information.
5323      SMLoc CondLoc;
5324      for (unsigned I = 1; I < Operands.size(); ++I)
5325        if (static_cast<ARMOperand*>(Operands[I])->isCondCode())
5326          CondLoc = Operands[I]->getStartLoc();
5327      return Error(CondLoc, "incorrect condition in IT block; got '" +
5328                   StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
5329                   "', but expected '" +
5330                   ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
5331    }
5332  // Check for non-'al' condition codes outside of the IT block.
5333  } else if (isThumbTwo() && MCID.isPredicable() &&
5334             Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
5335             ARMCC::AL && Inst.getOpcode() != ARM::tBcc &&
5336             Inst.getOpcode() != ARM::t2Bcc)
5337    return Error(Loc, "predicated instructions must be in IT block");
5338
5339  const unsigned Opcode = Inst.getOpcode();
5340  switch (Opcode) {
5341  case ARM::LDRD:
5342  case ARM::LDRD_PRE:
5343  case ARM::LDRD_POST: {
5344    const unsigned RtReg = Inst.getOperand(0).getReg();
5345
5346    // Rt can't be R14.
5347    if (RtReg == ARM::LR)
5348      return Error(Operands[3]->getStartLoc(),
5349                   "Rt can't be R14");
5350
5351    const unsigned Rt = MRI->getEncodingValue(RtReg);
5352    // Rt must be even-numbered.
5353    if ((Rt & 1) == 1)
5354      return Error(Operands[3]->getStartLoc(),
5355                   "Rt must be even-numbered");
5356
5357    // Rt2 must be Rt + 1.
5358    const unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5359    if (Rt2 != Rt + 1)
5360      return Error(Operands[3]->getStartLoc(),
5361                   "destination operands must be sequential");
5362
5363    if (Opcode == ARM::LDRD_PRE || Opcode == ARM::LDRD_POST) {
5364      const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg());
5365      // For addressing modes with writeback, the base register needs to be
5366      // different from the destination registers.
5367      if (Rn == Rt || Rn == Rt2)
5368        return Error(Operands[3]->getStartLoc(),
5369                     "base register needs to be different from destination "
5370                     "registers");
5371    }
5372
5373    return false;
5374  }
5375  case ARM::t2LDRDi8:
5376  case ARM::t2LDRD_PRE:
5377  case ARM::t2LDRD_POST: {
5378    // Rt2 must be different from Rt.
5379    unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5380    unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5381    if (Rt2 == Rt)
5382      return Error(Operands[3]->getStartLoc(),
5383                   "destination operands can't be identical");
5384    return false;
5385  }
5386  case ARM::STRD: {
5387    // Rt2 must be Rt + 1.
5388    unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5389    unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5390    if (Rt2 != Rt + 1)
5391      return Error(Operands[3]->getStartLoc(),
5392                   "source operands must be sequential");
5393    return false;
5394  }
5395  case ARM::STRD_PRE:
5396  case ARM::STRD_POST: {
5397    // Rt2 must be Rt + 1.
5398    unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5399    unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
5400    if (Rt2 != Rt + 1)
5401      return Error(Operands[3]->getStartLoc(),
5402                   "source operands must be sequential");
5403    return false;
5404  }
5405  case ARM::SBFX:
5406  case ARM::UBFX: {
5407    // Width must be in range [1, 32-lsb].
5408    unsigned LSB = Inst.getOperand(2).getImm();
5409    unsigned Widthm1 = Inst.getOperand(3).getImm();
5410    if (Widthm1 >= 32 - LSB)
5411      return Error(Operands[5]->getStartLoc(),
5412                   "bitfield width must be in range [1,32-lsb]");
5413    return false;
5414  }
5415  case ARM::tLDMIA: {
5416    // If we're parsing Thumb2, the .w variant is available and handles
5417    // most cases that are normally illegal for a Thumb1 LDM instruction.
5418    // We'll make the transformation in processInstruction() if necessary.
5419    //
5420    // Thumb LDM instructions are writeback iff the base register is not
5421    // in the register list.
5422    unsigned Rn = Inst.getOperand(0).getReg();
5423    bool HasWritebackToken =
5424      (static_cast<ARMOperand*>(Operands[3])->isToken() &&
5425       static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
5426    bool ListContainsBase;
5427    if (checkLowRegisterList(Inst, 3, Rn, 0, ListContainsBase) && !isThumbTwo())
5428      return Error(Operands[3 + HasWritebackToken]->getStartLoc(),
5429                   "registers must be in range r0-r7");
5430    // If we should have writeback, then there should be a '!' token.
5431    if (!ListContainsBase && !HasWritebackToken && !isThumbTwo())
5432      return Error(Operands[2]->getStartLoc(),
5433                   "writeback operator '!' expected");
5434    // If we should not have writeback, there must not be a '!'. This is
5435    // true even for the 32-bit wide encodings.
5436    if (ListContainsBase && HasWritebackToken)
5437      return Error(Operands[3]->getStartLoc(),
5438                   "writeback operator '!' not allowed when base register "
5439                   "in register list");
5440
5441    break;
5442  }
5443  case ARM::t2LDMIA_UPD: {
5444    if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
5445      return Error(Operands[4]->getStartLoc(),
5446                   "writeback operator '!' not allowed when base register "
5447                   "in register list");
5448    break;
5449  }
5450  case ARM::tMUL: {
5451    // The second source operand must be the same register as the destination
5452    // operand.
5453    //
5454    // In this case, we must directly check the parsed operands because the
5455    // cvtThumbMultiply() function is written in such a way that it guarantees
5456    // this first statement is always true for the new Inst.  Essentially, the
5457    // destination is unconditionally copied into the second source operand
5458    // without checking to see if it matches what we actually parsed.
5459    if (Operands.size() == 6 &&
5460        (((ARMOperand*)Operands[3])->getReg() !=
5461         ((ARMOperand*)Operands[5])->getReg()) &&
5462        (((ARMOperand*)Operands[3])->getReg() !=
5463         ((ARMOperand*)Operands[4])->getReg())) {
5464      return Error(Operands[3]->getStartLoc(),
5465                   "destination register must match source register");
5466    }
5467    break;
5468  }
5469  // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
5470  // so only issue a diagnostic for thumb1. The instructions will be
5471  // switched to the t2 encodings in processInstruction() if necessary.
5472  case ARM::tPOP: {
5473    bool ListContainsBase;
5474    if (checkLowRegisterList(Inst, 2, 0, ARM::PC, ListContainsBase) &&
5475        !isThumbTwo())
5476      return Error(Operands[2]->getStartLoc(),
5477                   "registers must be in range r0-r7 or pc");
5478    break;
5479  }
5480  case ARM::tPUSH: {
5481    bool ListContainsBase;
5482    if (checkLowRegisterList(Inst, 2, 0, ARM::LR, ListContainsBase) &&
5483        !isThumbTwo())
5484      return Error(Operands[2]->getStartLoc(),
5485                   "registers must be in range r0-r7 or lr");
5486    break;
5487  }
5488  case ARM::tSTMIA_UPD: {
5489    bool ListContainsBase;
5490    if (checkLowRegisterList(Inst, 4, 0, 0, ListContainsBase) && !isThumbTwo())
5491      return Error(Operands[4]->getStartLoc(),
5492                   "registers must be in range r0-r7");
5493    break;
5494  }
5495  case ARM::tADDrSP: {
5496    // If the non-SP source operand and the destination operand are not the
5497    // same, we need thumb2 (for the wide encoding), or we have an error.
5498    if (!isThumbTwo() &&
5499        Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
5500      return Error(Operands[4]->getStartLoc(),
5501                   "source register must be the same as destination");
5502    }
5503    break;
5504  }
5505  // Final range checking for Thumb unconditional branch instructions.
5506  case ARM::tB:
5507    if (!(static_cast<ARMOperand*>(Operands[2]))->isSignedOffset<11, 1>())
5508      return Error(Operands[2]->getStartLoc(), "branch target out of range");
5509    break;
5510  case ARM::t2B: {
5511    int op = (Operands[2]->isImm()) ? 2 : 3;
5512    if (!(static_cast<ARMOperand*>(Operands[op]))->isSignedOffset<24, 1>())
5513      return Error(Operands[op]->getStartLoc(), "branch target out of range");
5514    break;
5515  }
5516  // Final range checking for Thumb conditional branch instructions.
5517  case ARM::tBcc:
5518    if (!(static_cast<ARMOperand*>(Operands[2]))->isSignedOffset<8, 1>())
5519      return Error(Operands[2]->getStartLoc(), "branch target out of range");
5520    break;
5521  case ARM::t2Bcc: {
5522    int Op = (Operands[2]->isImm()) ? 2 : 3;
5523    if (!(static_cast<ARMOperand*>(Operands[Op]))->isSignedOffset<20, 1>())
5524      return Error(Operands[Op]->getStartLoc(), "branch target out of range");
5525    break;
5526  }
5527  }
5528
5529  return false;
5530}
5531
5532static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
5533  switch(Opc) {
5534  default: llvm_unreachable("unexpected opcode!");
5535  // VST1LN
5536  case ARM::VST1LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST1LNd8_UPD;
5537  case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5538  case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5539  case ARM::VST1LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST1LNd8_UPD;
5540  case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5541  case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5542  case ARM::VST1LNdAsm_8:  Spacing = 1; return ARM::VST1LNd8;
5543  case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
5544  case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
5545
5546  // VST2LN
5547  case ARM::VST2LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST2LNd8_UPD;
5548  case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5549  case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5550  case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5551  case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5552
5553  case ARM::VST2LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST2LNd8_UPD;
5554  case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5555  case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5556  case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5557  case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5558
5559  case ARM::VST2LNdAsm_8:  Spacing = 1; return ARM::VST2LNd8;
5560  case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
5561  case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
5562  case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
5563  case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
5564
5565  // VST3LN
5566  case ARM::VST3LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST3LNd8_UPD;
5567  case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5568  case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5569  case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
5570  case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5571  case ARM::VST3LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST3LNd8_UPD;
5572  case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5573  case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5574  case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
5575  case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5576  case ARM::VST3LNdAsm_8:  Spacing = 1; return ARM::VST3LNd8;
5577  case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
5578  case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
5579  case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
5580  case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
5581
5582  // VST3
5583  case ARM::VST3dWB_fixed_Asm_8:  Spacing = 1; return ARM::VST3d8_UPD;
5584  case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5585  case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5586  case ARM::VST3qWB_fixed_Asm_8:  Spacing = 2; return ARM::VST3q8_UPD;
5587  case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5588  case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5589  case ARM::VST3dWB_register_Asm_8:  Spacing = 1; return ARM::VST3d8_UPD;
5590  case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5591  case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5592  case ARM::VST3qWB_register_Asm_8:  Spacing = 2; return ARM::VST3q8_UPD;
5593  case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5594  case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5595  case ARM::VST3dAsm_8:  Spacing = 1; return ARM::VST3d8;
5596  case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
5597  case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
5598  case ARM::VST3qAsm_8:  Spacing = 2; return ARM::VST3q8;
5599  case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
5600  case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
5601
5602  // VST4LN
5603  case ARM::VST4LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST4LNd8_UPD;
5604  case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5605  case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5606  case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
5607  case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5608  case ARM::VST4LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST4LNd8_UPD;
5609  case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5610  case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5611  case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
5612  case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5613  case ARM::VST4LNdAsm_8:  Spacing = 1; return ARM::VST4LNd8;
5614  case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
5615  case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
5616  case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
5617  case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
5618
5619  // VST4
5620  case ARM::VST4dWB_fixed_Asm_8:  Spacing = 1; return ARM::VST4d8_UPD;
5621  case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5622  case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5623  case ARM::VST4qWB_fixed_Asm_8:  Spacing = 2; return ARM::VST4q8_UPD;
5624  case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5625  case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5626  case ARM::VST4dWB_register_Asm_8:  Spacing = 1; return ARM::VST4d8_UPD;
5627  case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5628  case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5629  case ARM::VST4qWB_register_Asm_8:  Spacing = 2; return ARM::VST4q8_UPD;
5630  case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5631  case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5632  case ARM::VST4dAsm_8:  Spacing = 1; return ARM::VST4d8;
5633  case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
5634  case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
5635  case ARM::VST4qAsm_8:  Spacing = 2; return ARM::VST4q8;
5636  case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
5637  case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
5638  }
5639}
5640
5641static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
5642  switch(Opc) {
5643  default: llvm_unreachable("unexpected opcode!");
5644  // VLD1LN
5645  case ARM::VLD1LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD1LNd8_UPD;
5646  case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5647  case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5648  case ARM::VLD1LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD1LNd8_UPD;
5649  case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5650  case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5651  case ARM::VLD1LNdAsm_8:  Spacing = 1; return ARM::VLD1LNd8;
5652  case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
5653  case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
5654
5655  // VLD2LN
5656  case ARM::VLD2LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD2LNd8_UPD;
5657  case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5658  case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5659  case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
5660  case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5661  case ARM::VLD2LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD2LNd8_UPD;
5662  case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5663  case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5664  case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
5665  case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5666  case ARM::VLD2LNdAsm_8:  Spacing = 1; return ARM::VLD2LNd8;
5667  case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
5668  case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
5669  case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
5670  case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
5671
5672  // VLD3DUP
5673  case ARM::VLD3DUPdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3DUPd8_UPD;
5674  case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5675  case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5676  case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
5677  case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPq16_UPD;
5678  case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5679  case ARM::VLD3DUPdWB_register_Asm_8:  Spacing = 1; return ARM::VLD3DUPd8_UPD;
5680  case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5681  case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5682  case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
5683  case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
5684  case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5685  case ARM::VLD3DUPdAsm_8:  Spacing = 1; return ARM::VLD3DUPd8;
5686  case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
5687  case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
5688  case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
5689  case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
5690  case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
5691
5692  // VLD3LN
5693  case ARM::VLD3LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3LNd8_UPD;
5694  case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5695  case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5696  case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
5697  case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5698  case ARM::VLD3LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD3LNd8_UPD;
5699  case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5700  case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5701  case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
5702  case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5703  case ARM::VLD3LNdAsm_8:  Spacing = 1; return ARM::VLD3LNd8;
5704  case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
5705  case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
5706  case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
5707  case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
5708
5709  // VLD3
5710  case ARM::VLD3dWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3d8_UPD;
5711  case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5712  case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5713  case ARM::VLD3qWB_fixed_Asm_8:  Spacing = 2; return ARM::VLD3q8_UPD;
5714  case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5715  case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5716  case ARM::VLD3dWB_register_Asm_8:  Spacing = 1; return ARM::VLD3d8_UPD;
5717  case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5718  case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5719  case ARM::VLD3qWB_register_Asm_8:  Spacing = 2; return ARM::VLD3q8_UPD;
5720  case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5721  case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5722  case ARM::VLD3dAsm_8:  Spacing = 1; return ARM::VLD3d8;
5723  case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
5724  case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
5725  case ARM::VLD3qAsm_8:  Spacing = 2; return ARM::VLD3q8;
5726  case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
5727  case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
5728
5729  // VLD4LN
5730  case ARM::VLD4LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4LNd8_UPD;
5731  case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5732  case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5733  case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNq16_UPD;
5734  case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5735  case ARM::VLD4LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD4LNd8_UPD;
5736  case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5737  case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5738  case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
5739  case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5740  case ARM::VLD4LNdAsm_8:  Spacing = 1; return ARM::VLD4LNd8;
5741  case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
5742  case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
5743  case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
5744  case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
5745
5746  // VLD4DUP
5747  case ARM::VLD4DUPdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4DUPd8_UPD;
5748  case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5749  case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5750  case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
5751  case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
5752  case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5753  case ARM::VLD4DUPdWB_register_Asm_8:  Spacing = 1; return ARM::VLD4DUPd8_UPD;
5754  case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5755  case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5756  case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
5757  case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
5758  case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5759  case ARM::VLD4DUPdAsm_8:  Spacing = 1; return ARM::VLD4DUPd8;
5760  case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
5761  case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
5762  case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
5763  case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
5764  case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
5765
5766  // VLD4
5767  case ARM::VLD4dWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4d8_UPD;
5768  case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5769  case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5770  case ARM::VLD4qWB_fixed_Asm_8:  Spacing = 2; return ARM::VLD4q8_UPD;
5771  case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5772  case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5773  case ARM::VLD4dWB_register_Asm_8:  Spacing = 1; return ARM::VLD4d8_UPD;
5774  case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5775  case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5776  case ARM::VLD4qWB_register_Asm_8:  Spacing = 2; return ARM::VLD4q8_UPD;
5777  case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5778  case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5779  case ARM::VLD4dAsm_8:  Spacing = 1; return ARM::VLD4d8;
5780  case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
5781  case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
5782  case ARM::VLD4qAsm_8:  Spacing = 2; return ARM::VLD4q8;
5783  case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
5784  case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
5785  }
5786}
5787
5788bool ARMAsmParser::
5789processInstruction(MCInst &Inst,
5790                   const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5791  switch (Inst.getOpcode()) {
5792  // Alias for alternate form of 'ADR Rd, #imm' instruction.
5793  case ARM::ADDri: {
5794    if (Inst.getOperand(1).getReg() != ARM::PC ||
5795        Inst.getOperand(5).getReg() != 0)
5796      return false;
5797    MCInst TmpInst;
5798    TmpInst.setOpcode(ARM::ADR);
5799    TmpInst.addOperand(Inst.getOperand(0));
5800    TmpInst.addOperand(Inst.getOperand(2));
5801    TmpInst.addOperand(Inst.getOperand(3));
5802    TmpInst.addOperand(Inst.getOperand(4));
5803    Inst = TmpInst;
5804    return true;
5805  }
5806  // Aliases for alternate PC+imm syntax of LDR instructions.
5807  case ARM::t2LDRpcrel:
5808    // Select the narrow version if the immediate will fit.
5809    if (Inst.getOperand(1).getImm() > 0 &&
5810        Inst.getOperand(1).getImm() <= 0xff &&
5811        !(static_cast<ARMOperand*>(Operands[2])->isToken() &&
5812         static_cast<ARMOperand*>(Operands[2])->getToken() == ".w"))
5813      Inst.setOpcode(ARM::tLDRpci);
5814    else
5815      Inst.setOpcode(ARM::t2LDRpci);
5816    return true;
5817  case ARM::t2LDRBpcrel:
5818    Inst.setOpcode(ARM::t2LDRBpci);
5819    return true;
5820  case ARM::t2LDRHpcrel:
5821    Inst.setOpcode(ARM::t2LDRHpci);
5822    return true;
5823  case ARM::t2LDRSBpcrel:
5824    Inst.setOpcode(ARM::t2LDRSBpci);
5825    return true;
5826  case ARM::t2LDRSHpcrel:
5827    Inst.setOpcode(ARM::t2LDRSHpci);
5828    return true;
5829  // Handle NEON VST complex aliases.
5830  case ARM::VST1LNdWB_register_Asm_8:
5831  case ARM::VST1LNdWB_register_Asm_16:
5832  case ARM::VST1LNdWB_register_Asm_32: {
5833    MCInst TmpInst;
5834    // Shuffle the operands around so the lane index operand is in the
5835    // right place.
5836    unsigned Spacing;
5837    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5838    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5839    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5840    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5841    TmpInst.addOperand(Inst.getOperand(4)); // Rm
5842    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5843    TmpInst.addOperand(Inst.getOperand(1)); // lane
5844    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5845    TmpInst.addOperand(Inst.getOperand(6));
5846    Inst = TmpInst;
5847    return true;
5848  }
5849
5850  case ARM::VST2LNdWB_register_Asm_8:
5851  case ARM::VST2LNdWB_register_Asm_16:
5852  case ARM::VST2LNdWB_register_Asm_32:
5853  case ARM::VST2LNqWB_register_Asm_16:
5854  case ARM::VST2LNqWB_register_Asm_32: {
5855    MCInst TmpInst;
5856    // Shuffle the operands around so the lane index operand is in the
5857    // right place.
5858    unsigned Spacing;
5859    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5860    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5861    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5862    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5863    TmpInst.addOperand(Inst.getOperand(4)); // Rm
5864    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5865    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5866                                            Spacing));
5867    TmpInst.addOperand(Inst.getOperand(1)); // lane
5868    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5869    TmpInst.addOperand(Inst.getOperand(6));
5870    Inst = TmpInst;
5871    return true;
5872  }
5873
5874  case ARM::VST3LNdWB_register_Asm_8:
5875  case ARM::VST3LNdWB_register_Asm_16:
5876  case ARM::VST3LNdWB_register_Asm_32:
5877  case ARM::VST3LNqWB_register_Asm_16:
5878  case ARM::VST3LNqWB_register_Asm_32: {
5879    MCInst TmpInst;
5880    // Shuffle the operands around so the lane index operand is in the
5881    // right place.
5882    unsigned Spacing;
5883    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5884    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5885    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5886    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5887    TmpInst.addOperand(Inst.getOperand(4)); // Rm
5888    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5889    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5890                                            Spacing));
5891    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5892                                            Spacing * 2));
5893    TmpInst.addOperand(Inst.getOperand(1)); // lane
5894    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5895    TmpInst.addOperand(Inst.getOperand(6));
5896    Inst = TmpInst;
5897    return true;
5898  }
5899
5900  case ARM::VST4LNdWB_register_Asm_8:
5901  case ARM::VST4LNdWB_register_Asm_16:
5902  case ARM::VST4LNdWB_register_Asm_32:
5903  case ARM::VST4LNqWB_register_Asm_16:
5904  case ARM::VST4LNqWB_register_Asm_32: {
5905    MCInst TmpInst;
5906    // Shuffle the operands around so the lane index operand is in the
5907    // right place.
5908    unsigned Spacing;
5909    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5910    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5911    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5912    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5913    TmpInst.addOperand(Inst.getOperand(4)); // Rm
5914    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5915    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5916                                            Spacing));
5917    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5918                                            Spacing * 2));
5919    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5920                                            Spacing * 3));
5921    TmpInst.addOperand(Inst.getOperand(1)); // lane
5922    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5923    TmpInst.addOperand(Inst.getOperand(6));
5924    Inst = TmpInst;
5925    return true;
5926  }
5927
5928  case ARM::VST1LNdWB_fixed_Asm_8:
5929  case ARM::VST1LNdWB_fixed_Asm_16:
5930  case ARM::VST1LNdWB_fixed_Asm_32: {
5931    MCInst TmpInst;
5932    // Shuffle the operands around so the lane index operand is in the
5933    // right place.
5934    unsigned Spacing;
5935    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5936    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5937    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5938    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5939    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5940    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5941    TmpInst.addOperand(Inst.getOperand(1)); // lane
5942    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5943    TmpInst.addOperand(Inst.getOperand(5));
5944    Inst = TmpInst;
5945    return true;
5946  }
5947
5948  case ARM::VST2LNdWB_fixed_Asm_8:
5949  case ARM::VST2LNdWB_fixed_Asm_16:
5950  case ARM::VST2LNdWB_fixed_Asm_32:
5951  case ARM::VST2LNqWB_fixed_Asm_16:
5952  case ARM::VST2LNqWB_fixed_Asm_32: {
5953    MCInst TmpInst;
5954    // Shuffle the operands around so the lane index operand is in the
5955    // right place.
5956    unsigned Spacing;
5957    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5958    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5959    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5960    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5961    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5962    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5963    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5964                                            Spacing));
5965    TmpInst.addOperand(Inst.getOperand(1)); // lane
5966    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5967    TmpInst.addOperand(Inst.getOperand(5));
5968    Inst = TmpInst;
5969    return true;
5970  }
5971
5972  case ARM::VST3LNdWB_fixed_Asm_8:
5973  case ARM::VST3LNdWB_fixed_Asm_16:
5974  case ARM::VST3LNdWB_fixed_Asm_32:
5975  case ARM::VST3LNqWB_fixed_Asm_16:
5976  case ARM::VST3LNqWB_fixed_Asm_32: {
5977    MCInst TmpInst;
5978    // Shuffle the operands around so the lane index operand is in the
5979    // right place.
5980    unsigned Spacing;
5981    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5982    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5983    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5984    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5985    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5986    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5987    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5988                                            Spacing));
5989    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5990                                            Spacing * 2));
5991    TmpInst.addOperand(Inst.getOperand(1)); // lane
5992    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5993    TmpInst.addOperand(Inst.getOperand(5));
5994    Inst = TmpInst;
5995    return true;
5996  }
5997
5998  case ARM::VST4LNdWB_fixed_Asm_8:
5999  case ARM::VST4LNdWB_fixed_Asm_16:
6000  case ARM::VST4LNdWB_fixed_Asm_32:
6001  case ARM::VST4LNqWB_fixed_Asm_16:
6002  case ARM::VST4LNqWB_fixed_Asm_32: {
6003    MCInst TmpInst;
6004    // Shuffle the operands around so the lane index operand is in the
6005    // right place.
6006    unsigned Spacing;
6007    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6008    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6009    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6010    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6011    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6012    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6013    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6014                                            Spacing));
6015    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6016                                            Spacing * 2));
6017    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6018                                            Spacing * 3));
6019    TmpInst.addOperand(Inst.getOperand(1)); // lane
6020    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6021    TmpInst.addOperand(Inst.getOperand(5));
6022    Inst = TmpInst;
6023    return true;
6024  }
6025
6026  case ARM::VST1LNdAsm_8:
6027  case ARM::VST1LNdAsm_16:
6028  case ARM::VST1LNdAsm_32: {
6029    MCInst TmpInst;
6030    // Shuffle the operands around so the lane index operand is in the
6031    // right place.
6032    unsigned Spacing;
6033    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6034    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6035    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6036    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6037    TmpInst.addOperand(Inst.getOperand(1)); // lane
6038    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6039    TmpInst.addOperand(Inst.getOperand(5));
6040    Inst = TmpInst;
6041    return true;
6042  }
6043
6044  case ARM::VST2LNdAsm_8:
6045  case ARM::VST2LNdAsm_16:
6046  case ARM::VST2LNdAsm_32:
6047  case ARM::VST2LNqAsm_16:
6048  case ARM::VST2LNqAsm_32: {
6049    MCInst TmpInst;
6050    // Shuffle the operands around so the lane index operand is in the
6051    // right place.
6052    unsigned Spacing;
6053    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6054    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6055    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6056    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6057    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6058                                            Spacing));
6059    TmpInst.addOperand(Inst.getOperand(1)); // lane
6060    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6061    TmpInst.addOperand(Inst.getOperand(5));
6062    Inst = TmpInst;
6063    return true;
6064  }
6065
6066  case ARM::VST3LNdAsm_8:
6067  case ARM::VST3LNdAsm_16:
6068  case ARM::VST3LNdAsm_32:
6069  case ARM::VST3LNqAsm_16:
6070  case ARM::VST3LNqAsm_32: {
6071    MCInst TmpInst;
6072    // Shuffle the operands around so the lane index operand is in the
6073    // right place.
6074    unsigned Spacing;
6075    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6076    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6077    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6078    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6079    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6080                                            Spacing));
6081    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6082                                            Spacing * 2));
6083    TmpInst.addOperand(Inst.getOperand(1)); // lane
6084    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6085    TmpInst.addOperand(Inst.getOperand(5));
6086    Inst = TmpInst;
6087    return true;
6088  }
6089
6090  case ARM::VST4LNdAsm_8:
6091  case ARM::VST4LNdAsm_16:
6092  case ARM::VST4LNdAsm_32:
6093  case ARM::VST4LNqAsm_16:
6094  case ARM::VST4LNqAsm_32: {
6095    MCInst TmpInst;
6096    // Shuffle the operands around so the lane index operand is in the
6097    // right place.
6098    unsigned Spacing;
6099    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6100    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6101    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6102    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6103    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6104                                            Spacing));
6105    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6106                                            Spacing * 2));
6107    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6108                                            Spacing * 3));
6109    TmpInst.addOperand(Inst.getOperand(1)); // lane
6110    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6111    TmpInst.addOperand(Inst.getOperand(5));
6112    Inst = TmpInst;
6113    return true;
6114  }
6115
6116  // Handle NEON VLD complex aliases.
6117  case ARM::VLD1LNdWB_register_Asm_8:
6118  case ARM::VLD1LNdWB_register_Asm_16:
6119  case ARM::VLD1LNdWB_register_Asm_32: {
6120    MCInst TmpInst;
6121    // Shuffle the operands around so the lane index operand is in the
6122    // right place.
6123    unsigned Spacing;
6124    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6125    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6126    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6127    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6128    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6129    TmpInst.addOperand(Inst.getOperand(4)); // Rm
6130    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6131    TmpInst.addOperand(Inst.getOperand(1)); // lane
6132    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6133    TmpInst.addOperand(Inst.getOperand(6));
6134    Inst = TmpInst;
6135    return true;
6136  }
6137
6138  case ARM::VLD2LNdWB_register_Asm_8:
6139  case ARM::VLD2LNdWB_register_Asm_16:
6140  case ARM::VLD2LNdWB_register_Asm_32:
6141  case ARM::VLD2LNqWB_register_Asm_16:
6142  case ARM::VLD2LNqWB_register_Asm_32: {
6143    MCInst TmpInst;
6144    // Shuffle the operands around so the lane index operand is in the
6145    // right place.
6146    unsigned Spacing;
6147    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6148    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6149    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6150                                            Spacing));
6151    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6152    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6153    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6154    TmpInst.addOperand(Inst.getOperand(4)); // Rm
6155    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6156    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6157                                            Spacing));
6158    TmpInst.addOperand(Inst.getOperand(1)); // lane
6159    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6160    TmpInst.addOperand(Inst.getOperand(6));
6161    Inst = TmpInst;
6162    return true;
6163  }
6164
6165  case ARM::VLD3LNdWB_register_Asm_8:
6166  case ARM::VLD3LNdWB_register_Asm_16:
6167  case ARM::VLD3LNdWB_register_Asm_32:
6168  case ARM::VLD3LNqWB_register_Asm_16:
6169  case ARM::VLD3LNqWB_register_Asm_32: {
6170    MCInst TmpInst;
6171    // Shuffle the operands around so the lane index operand is in the
6172    // right place.
6173    unsigned Spacing;
6174    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6175    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6176    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6177                                            Spacing));
6178    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6179                                            Spacing * 2));
6180    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6181    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6182    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6183    TmpInst.addOperand(Inst.getOperand(4)); // Rm
6184    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6185    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6186                                            Spacing));
6187    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6188                                            Spacing * 2));
6189    TmpInst.addOperand(Inst.getOperand(1)); // lane
6190    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6191    TmpInst.addOperand(Inst.getOperand(6));
6192    Inst = TmpInst;
6193    return true;
6194  }
6195
6196  case ARM::VLD4LNdWB_register_Asm_8:
6197  case ARM::VLD4LNdWB_register_Asm_16:
6198  case ARM::VLD4LNdWB_register_Asm_32:
6199  case ARM::VLD4LNqWB_register_Asm_16:
6200  case ARM::VLD4LNqWB_register_Asm_32: {
6201    MCInst TmpInst;
6202    // Shuffle the operands around so the lane index operand is in the
6203    // right place.
6204    unsigned Spacing;
6205    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6206    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6207    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6208                                            Spacing));
6209    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6210                                            Spacing * 2));
6211    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6212                                            Spacing * 3));
6213    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6214    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6215    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6216    TmpInst.addOperand(Inst.getOperand(4)); // Rm
6217    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6218    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6219                                            Spacing));
6220    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6221                                            Spacing * 2));
6222    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6223                                            Spacing * 3));
6224    TmpInst.addOperand(Inst.getOperand(1)); // lane
6225    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6226    TmpInst.addOperand(Inst.getOperand(6));
6227    Inst = TmpInst;
6228    return true;
6229  }
6230
6231  case ARM::VLD1LNdWB_fixed_Asm_8:
6232  case ARM::VLD1LNdWB_fixed_Asm_16:
6233  case ARM::VLD1LNdWB_fixed_Asm_32: {
6234    MCInst TmpInst;
6235    // Shuffle the operands around so the lane index operand is in the
6236    // right place.
6237    unsigned Spacing;
6238    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6239    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6240    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6241    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6242    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6243    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6244    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6245    TmpInst.addOperand(Inst.getOperand(1)); // lane
6246    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6247    TmpInst.addOperand(Inst.getOperand(5));
6248    Inst = TmpInst;
6249    return true;
6250  }
6251
6252  case ARM::VLD2LNdWB_fixed_Asm_8:
6253  case ARM::VLD2LNdWB_fixed_Asm_16:
6254  case ARM::VLD2LNdWB_fixed_Asm_32:
6255  case ARM::VLD2LNqWB_fixed_Asm_16:
6256  case ARM::VLD2LNqWB_fixed_Asm_32: {
6257    MCInst TmpInst;
6258    // Shuffle the operands around so the lane index operand is in the
6259    // right place.
6260    unsigned Spacing;
6261    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6262    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6263    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6264                                            Spacing));
6265    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6266    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6267    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6268    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6269    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6270    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6271                                            Spacing));
6272    TmpInst.addOperand(Inst.getOperand(1)); // lane
6273    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6274    TmpInst.addOperand(Inst.getOperand(5));
6275    Inst = TmpInst;
6276    return true;
6277  }
6278
6279  case ARM::VLD3LNdWB_fixed_Asm_8:
6280  case ARM::VLD3LNdWB_fixed_Asm_16:
6281  case ARM::VLD3LNdWB_fixed_Asm_32:
6282  case ARM::VLD3LNqWB_fixed_Asm_16:
6283  case ARM::VLD3LNqWB_fixed_Asm_32: {
6284    MCInst TmpInst;
6285    // Shuffle the operands around so the lane index operand is in the
6286    // right place.
6287    unsigned Spacing;
6288    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6289    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6290    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6291                                            Spacing));
6292    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6293                                            Spacing * 2));
6294    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6295    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6296    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6297    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6298    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6299    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6300                                            Spacing));
6301    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6302                                            Spacing * 2));
6303    TmpInst.addOperand(Inst.getOperand(1)); // lane
6304    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6305    TmpInst.addOperand(Inst.getOperand(5));
6306    Inst = TmpInst;
6307    return true;
6308  }
6309
6310  case ARM::VLD4LNdWB_fixed_Asm_8:
6311  case ARM::VLD4LNdWB_fixed_Asm_16:
6312  case ARM::VLD4LNdWB_fixed_Asm_32:
6313  case ARM::VLD4LNqWB_fixed_Asm_16:
6314  case ARM::VLD4LNqWB_fixed_Asm_32: {
6315    MCInst TmpInst;
6316    // Shuffle the operands around so the lane index operand is in the
6317    // right place.
6318    unsigned Spacing;
6319    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6320    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6321    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6322                                            Spacing));
6323    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6324                                            Spacing * 2));
6325    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6326                                            Spacing * 3));
6327    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6328    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6329    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6330    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6331    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6332    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6333                                            Spacing));
6334    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6335                                            Spacing * 2));
6336    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6337                                            Spacing * 3));
6338    TmpInst.addOperand(Inst.getOperand(1)); // lane
6339    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6340    TmpInst.addOperand(Inst.getOperand(5));
6341    Inst = TmpInst;
6342    return true;
6343  }
6344
6345  case ARM::VLD1LNdAsm_8:
6346  case ARM::VLD1LNdAsm_16:
6347  case ARM::VLD1LNdAsm_32: {
6348    MCInst TmpInst;
6349    // Shuffle the operands around so the lane index operand is in the
6350    // right place.
6351    unsigned Spacing;
6352    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6353    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6354    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6355    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6356    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6357    TmpInst.addOperand(Inst.getOperand(1)); // lane
6358    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6359    TmpInst.addOperand(Inst.getOperand(5));
6360    Inst = TmpInst;
6361    return true;
6362  }
6363
6364  case ARM::VLD2LNdAsm_8:
6365  case ARM::VLD2LNdAsm_16:
6366  case ARM::VLD2LNdAsm_32:
6367  case ARM::VLD2LNqAsm_16:
6368  case ARM::VLD2LNqAsm_32: {
6369    MCInst TmpInst;
6370    // Shuffle the operands around so the lane index operand is in the
6371    // right place.
6372    unsigned Spacing;
6373    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6374    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6375    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6376                                            Spacing));
6377    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6378    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6379    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6380    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6381                                            Spacing));
6382    TmpInst.addOperand(Inst.getOperand(1)); // lane
6383    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6384    TmpInst.addOperand(Inst.getOperand(5));
6385    Inst = TmpInst;
6386    return true;
6387  }
6388
6389  case ARM::VLD3LNdAsm_8:
6390  case ARM::VLD3LNdAsm_16:
6391  case ARM::VLD3LNdAsm_32:
6392  case ARM::VLD3LNqAsm_16:
6393  case ARM::VLD3LNqAsm_32: {
6394    MCInst TmpInst;
6395    // Shuffle the operands around so the lane index operand is in the
6396    // right place.
6397    unsigned Spacing;
6398    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6399    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6400    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6401                                            Spacing));
6402    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6403                                            Spacing * 2));
6404    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6405    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6406    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6407    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6408                                            Spacing));
6409    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6410                                            Spacing * 2));
6411    TmpInst.addOperand(Inst.getOperand(1)); // lane
6412    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6413    TmpInst.addOperand(Inst.getOperand(5));
6414    Inst = TmpInst;
6415    return true;
6416  }
6417
6418  case ARM::VLD4LNdAsm_8:
6419  case ARM::VLD4LNdAsm_16:
6420  case ARM::VLD4LNdAsm_32:
6421  case ARM::VLD4LNqAsm_16:
6422  case ARM::VLD4LNqAsm_32: {
6423    MCInst TmpInst;
6424    // Shuffle the operands around so the lane index operand is in the
6425    // right place.
6426    unsigned Spacing;
6427    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6428    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6429    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6430                                            Spacing));
6431    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6432                                            Spacing * 2));
6433    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6434                                            Spacing * 3));
6435    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6436    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6437    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6438    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6439                                            Spacing));
6440    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6441                                            Spacing * 2));
6442    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6443                                            Spacing * 3));
6444    TmpInst.addOperand(Inst.getOperand(1)); // lane
6445    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6446    TmpInst.addOperand(Inst.getOperand(5));
6447    Inst = TmpInst;
6448    return true;
6449  }
6450
6451  // VLD3DUP single 3-element structure to all lanes instructions.
6452  case ARM::VLD3DUPdAsm_8:
6453  case ARM::VLD3DUPdAsm_16:
6454  case ARM::VLD3DUPdAsm_32:
6455  case ARM::VLD3DUPqAsm_8:
6456  case ARM::VLD3DUPqAsm_16:
6457  case ARM::VLD3DUPqAsm_32: {
6458    MCInst TmpInst;
6459    unsigned Spacing;
6460    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6461    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6462    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6463                                            Spacing));
6464    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6465                                            Spacing * 2));
6466    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6467    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6468    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6469    TmpInst.addOperand(Inst.getOperand(4));
6470    Inst = TmpInst;
6471    return true;
6472  }
6473
6474  case ARM::VLD3DUPdWB_fixed_Asm_8:
6475  case ARM::VLD3DUPdWB_fixed_Asm_16:
6476  case ARM::VLD3DUPdWB_fixed_Asm_32:
6477  case ARM::VLD3DUPqWB_fixed_Asm_8:
6478  case ARM::VLD3DUPqWB_fixed_Asm_16:
6479  case ARM::VLD3DUPqWB_fixed_Asm_32: {
6480    MCInst TmpInst;
6481    unsigned Spacing;
6482    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6483    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6484    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6485                                            Spacing));
6486    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6487                                            Spacing * 2));
6488    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6489    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6490    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6491    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6492    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6493    TmpInst.addOperand(Inst.getOperand(4));
6494    Inst = TmpInst;
6495    return true;
6496  }
6497
6498  case ARM::VLD3DUPdWB_register_Asm_8:
6499  case ARM::VLD3DUPdWB_register_Asm_16:
6500  case ARM::VLD3DUPdWB_register_Asm_32:
6501  case ARM::VLD3DUPqWB_register_Asm_8:
6502  case ARM::VLD3DUPqWB_register_Asm_16:
6503  case ARM::VLD3DUPqWB_register_Asm_32: {
6504    MCInst TmpInst;
6505    unsigned Spacing;
6506    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6507    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6508    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6509                                            Spacing));
6510    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6511                                            Spacing * 2));
6512    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6513    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6514    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6515    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6516    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6517    TmpInst.addOperand(Inst.getOperand(5));
6518    Inst = TmpInst;
6519    return true;
6520  }
6521
6522  // VLD3 multiple 3-element structure instructions.
6523  case ARM::VLD3dAsm_8:
6524  case ARM::VLD3dAsm_16:
6525  case ARM::VLD3dAsm_32:
6526  case ARM::VLD3qAsm_8:
6527  case ARM::VLD3qAsm_16:
6528  case ARM::VLD3qAsm_32: {
6529    MCInst TmpInst;
6530    unsigned Spacing;
6531    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6532    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6533    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6534                                            Spacing));
6535    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6536                                            Spacing * 2));
6537    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6538    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6539    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6540    TmpInst.addOperand(Inst.getOperand(4));
6541    Inst = TmpInst;
6542    return true;
6543  }
6544
6545  case ARM::VLD3dWB_fixed_Asm_8:
6546  case ARM::VLD3dWB_fixed_Asm_16:
6547  case ARM::VLD3dWB_fixed_Asm_32:
6548  case ARM::VLD3qWB_fixed_Asm_8:
6549  case ARM::VLD3qWB_fixed_Asm_16:
6550  case ARM::VLD3qWB_fixed_Asm_32: {
6551    MCInst TmpInst;
6552    unsigned Spacing;
6553    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6554    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6555    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6556                                            Spacing));
6557    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6558                                            Spacing * 2));
6559    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6560    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6561    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6562    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6563    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6564    TmpInst.addOperand(Inst.getOperand(4));
6565    Inst = TmpInst;
6566    return true;
6567  }
6568
6569  case ARM::VLD3dWB_register_Asm_8:
6570  case ARM::VLD3dWB_register_Asm_16:
6571  case ARM::VLD3dWB_register_Asm_32:
6572  case ARM::VLD3qWB_register_Asm_8:
6573  case ARM::VLD3qWB_register_Asm_16:
6574  case ARM::VLD3qWB_register_Asm_32: {
6575    MCInst TmpInst;
6576    unsigned Spacing;
6577    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6578    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6579    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6580                                            Spacing));
6581    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6582                                            Spacing * 2));
6583    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6584    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6585    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6586    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6587    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6588    TmpInst.addOperand(Inst.getOperand(5));
6589    Inst = TmpInst;
6590    return true;
6591  }
6592
6593  // VLD4DUP single 3-element structure to all lanes instructions.
6594  case ARM::VLD4DUPdAsm_8:
6595  case ARM::VLD4DUPdAsm_16:
6596  case ARM::VLD4DUPdAsm_32:
6597  case ARM::VLD4DUPqAsm_8:
6598  case ARM::VLD4DUPqAsm_16:
6599  case ARM::VLD4DUPqAsm_32: {
6600    MCInst TmpInst;
6601    unsigned Spacing;
6602    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6603    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6604    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6605                                            Spacing));
6606    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6607                                            Spacing * 2));
6608    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6609                                            Spacing * 3));
6610    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6611    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6612    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6613    TmpInst.addOperand(Inst.getOperand(4));
6614    Inst = TmpInst;
6615    return true;
6616  }
6617
6618  case ARM::VLD4DUPdWB_fixed_Asm_8:
6619  case ARM::VLD4DUPdWB_fixed_Asm_16:
6620  case ARM::VLD4DUPdWB_fixed_Asm_32:
6621  case ARM::VLD4DUPqWB_fixed_Asm_8:
6622  case ARM::VLD4DUPqWB_fixed_Asm_16:
6623  case ARM::VLD4DUPqWB_fixed_Asm_32: {
6624    MCInst TmpInst;
6625    unsigned Spacing;
6626    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6627    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6628    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6629                                            Spacing));
6630    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6631                                            Spacing * 2));
6632    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6633                                            Spacing * 3));
6634    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6635    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6636    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6637    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6638    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6639    TmpInst.addOperand(Inst.getOperand(4));
6640    Inst = TmpInst;
6641    return true;
6642  }
6643
6644  case ARM::VLD4DUPdWB_register_Asm_8:
6645  case ARM::VLD4DUPdWB_register_Asm_16:
6646  case ARM::VLD4DUPdWB_register_Asm_32:
6647  case ARM::VLD4DUPqWB_register_Asm_8:
6648  case ARM::VLD4DUPqWB_register_Asm_16:
6649  case ARM::VLD4DUPqWB_register_Asm_32: {
6650    MCInst TmpInst;
6651    unsigned Spacing;
6652    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6653    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6654    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6655                                            Spacing));
6656    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6657                                            Spacing * 2));
6658    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6659                                            Spacing * 3));
6660    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6661    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6662    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6663    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6664    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6665    TmpInst.addOperand(Inst.getOperand(5));
6666    Inst = TmpInst;
6667    return true;
6668  }
6669
6670  // VLD4 multiple 4-element structure instructions.
6671  case ARM::VLD4dAsm_8:
6672  case ARM::VLD4dAsm_16:
6673  case ARM::VLD4dAsm_32:
6674  case ARM::VLD4qAsm_8:
6675  case ARM::VLD4qAsm_16:
6676  case ARM::VLD4qAsm_32: {
6677    MCInst TmpInst;
6678    unsigned Spacing;
6679    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6680    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6681    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6682                                            Spacing));
6683    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6684                                            Spacing * 2));
6685    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6686                                            Spacing * 3));
6687    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6688    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6689    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6690    TmpInst.addOperand(Inst.getOperand(4));
6691    Inst = TmpInst;
6692    return true;
6693  }
6694
6695  case ARM::VLD4dWB_fixed_Asm_8:
6696  case ARM::VLD4dWB_fixed_Asm_16:
6697  case ARM::VLD4dWB_fixed_Asm_32:
6698  case ARM::VLD4qWB_fixed_Asm_8:
6699  case ARM::VLD4qWB_fixed_Asm_16:
6700  case ARM::VLD4qWB_fixed_Asm_32: {
6701    MCInst TmpInst;
6702    unsigned Spacing;
6703    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6704    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6705    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6706                                            Spacing));
6707    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6708                                            Spacing * 2));
6709    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6710                                            Spacing * 3));
6711    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6712    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6713    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6714    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6715    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6716    TmpInst.addOperand(Inst.getOperand(4));
6717    Inst = TmpInst;
6718    return true;
6719  }
6720
6721  case ARM::VLD4dWB_register_Asm_8:
6722  case ARM::VLD4dWB_register_Asm_16:
6723  case ARM::VLD4dWB_register_Asm_32:
6724  case ARM::VLD4qWB_register_Asm_8:
6725  case ARM::VLD4qWB_register_Asm_16:
6726  case ARM::VLD4qWB_register_Asm_32: {
6727    MCInst TmpInst;
6728    unsigned Spacing;
6729    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6730    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6731    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6732                                            Spacing));
6733    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6734                                            Spacing * 2));
6735    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6736                                            Spacing * 3));
6737    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6738    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6739    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6740    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6741    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6742    TmpInst.addOperand(Inst.getOperand(5));
6743    Inst = TmpInst;
6744    return true;
6745  }
6746
6747  // VST3 multiple 3-element structure instructions.
6748  case ARM::VST3dAsm_8:
6749  case ARM::VST3dAsm_16:
6750  case ARM::VST3dAsm_32:
6751  case ARM::VST3qAsm_8:
6752  case ARM::VST3qAsm_16:
6753  case ARM::VST3qAsm_32: {
6754    MCInst TmpInst;
6755    unsigned Spacing;
6756    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6757    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6758    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6759    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6760    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6761                                            Spacing));
6762    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6763                                            Spacing * 2));
6764    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6765    TmpInst.addOperand(Inst.getOperand(4));
6766    Inst = TmpInst;
6767    return true;
6768  }
6769
6770  case ARM::VST3dWB_fixed_Asm_8:
6771  case ARM::VST3dWB_fixed_Asm_16:
6772  case ARM::VST3dWB_fixed_Asm_32:
6773  case ARM::VST3qWB_fixed_Asm_8:
6774  case ARM::VST3qWB_fixed_Asm_16:
6775  case ARM::VST3qWB_fixed_Asm_32: {
6776    MCInst TmpInst;
6777    unsigned Spacing;
6778    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6779    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6780    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6781    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6782    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6783    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6784    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6785                                            Spacing));
6786    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6787                                            Spacing * 2));
6788    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6789    TmpInst.addOperand(Inst.getOperand(4));
6790    Inst = TmpInst;
6791    return true;
6792  }
6793
6794  case ARM::VST3dWB_register_Asm_8:
6795  case ARM::VST3dWB_register_Asm_16:
6796  case ARM::VST3dWB_register_Asm_32:
6797  case ARM::VST3qWB_register_Asm_8:
6798  case ARM::VST3qWB_register_Asm_16:
6799  case ARM::VST3qWB_register_Asm_32: {
6800    MCInst TmpInst;
6801    unsigned Spacing;
6802    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6803    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6804    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6805    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6806    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6807    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6808    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6809                                            Spacing));
6810    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6811                                            Spacing * 2));
6812    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6813    TmpInst.addOperand(Inst.getOperand(5));
6814    Inst = TmpInst;
6815    return true;
6816  }
6817
6818  // VST4 multiple 3-element structure instructions.
6819  case ARM::VST4dAsm_8:
6820  case ARM::VST4dAsm_16:
6821  case ARM::VST4dAsm_32:
6822  case ARM::VST4qAsm_8:
6823  case ARM::VST4qAsm_16:
6824  case ARM::VST4qAsm_32: {
6825    MCInst TmpInst;
6826    unsigned Spacing;
6827    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6828    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6829    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6830    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6831    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6832                                            Spacing));
6833    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6834                                            Spacing * 2));
6835    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6836                                            Spacing * 3));
6837    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6838    TmpInst.addOperand(Inst.getOperand(4));
6839    Inst = TmpInst;
6840    return true;
6841  }
6842
6843  case ARM::VST4dWB_fixed_Asm_8:
6844  case ARM::VST4dWB_fixed_Asm_16:
6845  case ARM::VST4dWB_fixed_Asm_32:
6846  case ARM::VST4qWB_fixed_Asm_8:
6847  case ARM::VST4qWB_fixed_Asm_16:
6848  case ARM::VST4qWB_fixed_Asm_32: {
6849    MCInst TmpInst;
6850    unsigned Spacing;
6851    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6852    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6853    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6854    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6855    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6856    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6857    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6858                                            Spacing));
6859    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6860                                            Spacing * 2));
6861    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6862                                            Spacing * 3));
6863    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6864    TmpInst.addOperand(Inst.getOperand(4));
6865    Inst = TmpInst;
6866    return true;
6867  }
6868
6869  case ARM::VST4dWB_register_Asm_8:
6870  case ARM::VST4dWB_register_Asm_16:
6871  case ARM::VST4dWB_register_Asm_32:
6872  case ARM::VST4qWB_register_Asm_8:
6873  case ARM::VST4qWB_register_Asm_16:
6874  case ARM::VST4qWB_register_Asm_32: {
6875    MCInst TmpInst;
6876    unsigned Spacing;
6877    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6878    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6879    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6880    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6881    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6882    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6883    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6884                                            Spacing));
6885    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6886                                            Spacing * 2));
6887    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6888                                            Spacing * 3));
6889    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6890    TmpInst.addOperand(Inst.getOperand(5));
6891    Inst = TmpInst;
6892    return true;
6893  }
6894
6895  // Handle encoding choice for the shift-immediate instructions.
6896  case ARM::t2LSLri:
6897  case ARM::t2LSRri:
6898  case ARM::t2ASRri: {
6899    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6900        Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
6901        Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
6902        !(static_cast<ARMOperand*>(Operands[3])->isToken() &&
6903         static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) {
6904      unsigned NewOpc;
6905      switch (Inst.getOpcode()) {
6906      default: llvm_unreachable("unexpected opcode");
6907      case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
6908      case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
6909      case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
6910      }
6911      // The Thumb1 operands aren't in the same order. Awesome, eh?
6912      MCInst TmpInst;
6913      TmpInst.setOpcode(NewOpc);
6914      TmpInst.addOperand(Inst.getOperand(0));
6915      TmpInst.addOperand(Inst.getOperand(5));
6916      TmpInst.addOperand(Inst.getOperand(1));
6917      TmpInst.addOperand(Inst.getOperand(2));
6918      TmpInst.addOperand(Inst.getOperand(3));
6919      TmpInst.addOperand(Inst.getOperand(4));
6920      Inst = TmpInst;
6921      return true;
6922    }
6923    return false;
6924  }
6925
6926  // Handle the Thumb2 mode MOV complex aliases.
6927  case ARM::t2MOVsr:
6928  case ARM::t2MOVSsr: {
6929    // Which instruction to expand to depends on the CCOut operand and
6930    // whether we're in an IT block if the register operands are low
6931    // registers.
6932    bool isNarrow = false;
6933    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6934        isARMLowRegister(Inst.getOperand(1).getReg()) &&
6935        isARMLowRegister(Inst.getOperand(2).getReg()) &&
6936        Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
6937        inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
6938      isNarrow = true;
6939    MCInst TmpInst;
6940    unsigned newOpc;
6941    switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
6942    default: llvm_unreachable("unexpected opcode!");
6943    case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
6944    case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
6945    case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
6946    case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR   : ARM::t2RORrr; break;
6947    }
6948    TmpInst.setOpcode(newOpc);
6949    TmpInst.addOperand(Inst.getOperand(0)); // Rd
6950    if (isNarrow)
6951      TmpInst.addOperand(MCOperand::CreateReg(
6952          Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
6953    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6954    TmpInst.addOperand(Inst.getOperand(2)); // Rm
6955    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6956    TmpInst.addOperand(Inst.getOperand(5));
6957    if (!isNarrow)
6958      TmpInst.addOperand(MCOperand::CreateReg(
6959          Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
6960    Inst = TmpInst;
6961    return true;
6962  }
6963  case ARM::t2MOVsi:
6964  case ARM::t2MOVSsi: {
6965    // Which instruction to expand to depends on the CCOut operand and
6966    // whether we're in an IT block if the register operands are low
6967    // registers.
6968    bool isNarrow = false;
6969    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6970        isARMLowRegister(Inst.getOperand(1).getReg()) &&
6971        inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
6972      isNarrow = true;
6973    MCInst TmpInst;
6974    unsigned newOpc;
6975    switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
6976    default: llvm_unreachable("unexpected opcode!");
6977    case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
6978    case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
6979    case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
6980    case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
6981    case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
6982    }
6983    unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
6984    if (Amount == 32) Amount = 0;
6985    TmpInst.setOpcode(newOpc);
6986    TmpInst.addOperand(Inst.getOperand(0)); // Rd
6987    if (isNarrow)
6988      TmpInst.addOperand(MCOperand::CreateReg(
6989          Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
6990    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6991    if (newOpc != ARM::t2RRX)
6992      TmpInst.addOperand(MCOperand::CreateImm(Amount));
6993    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6994    TmpInst.addOperand(Inst.getOperand(4));
6995    if (!isNarrow)
6996      TmpInst.addOperand(MCOperand::CreateReg(
6997          Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
6998    Inst = TmpInst;
6999    return true;
7000  }
7001  // Handle the ARM mode MOV complex aliases.
7002  case ARM::ASRr:
7003  case ARM::LSRr:
7004  case ARM::LSLr:
7005  case ARM::RORr: {
7006    ARM_AM::ShiftOpc ShiftTy;
7007    switch(Inst.getOpcode()) {
7008    default: llvm_unreachable("unexpected opcode!");
7009    case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
7010    case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
7011    case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
7012    case ARM::RORr: ShiftTy = ARM_AM::ror; break;
7013    }
7014    unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
7015    MCInst TmpInst;
7016    TmpInst.setOpcode(ARM::MOVsr);
7017    TmpInst.addOperand(Inst.getOperand(0)); // Rd
7018    TmpInst.addOperand(Inst.getOperand(1)); // Rn
7019    TmpInst.addOperand(Inst.getOperand(2)); // Rm
7020    TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7021    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7022    TmpInst.addOperand(Inst.getOperand(4));
7023    TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7024    Inst = TmpInst;
7025    return true;
7026  }
7027  case ARM::ASRi:
7028  case ARM::LSRi:
7029  case ARM::LSLi:
7030  case ARM::RORi: {
7031    ARM_AM::ShiftOpc ShiftTy;
7032    switch(Inst.getOpcode()) {
7033    default: llvm_unreachable("unexpected opcode!");
7034    case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
7035    case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
7036    case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
7037    case ARM::RORi: ShiftTy = ARM_AM::ror; break;
7038    }
7039    // A shift by zero is a plain MOVr, not a MOVsi.
7040    unsigned Amt = Inst.getOperand(2).getImm();
7041    unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
7042    // A shift by 32 should be encoded as 0 when permitted
7043    if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
7044      Amt = 0;
7045    unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
7046    MCInst TmpInst;
7047    TmpInst.setOpcode(Opc);
7048    TmpInst.addOperand(Inst.getOperand(0)); // Rd
7049    TmpInst.addOperand(Inst.getOperand(1)); // Rn
7050    if (Opc == ARM::MOVsi)
7051      TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7052    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7053    TmpInst.addOperand(Inst.getOperand(4));
7054    TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7055    Inst = TmpInst;
7056    return true;
7057  }
7058  case ARM::RRXi: {
7059    unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
7060    MCInst TmpInst;
7061    TmpInst.setOpcode(ARM::MOVsi);
7062    TmpInst.addOperand(Inst.getOperand(0)); // Rd
7063    TmpInst.addOperand(Inst.getOperand(1)); // Rn
7064    TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7065    TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7066    TmpInst.addOperand(Inst.getOperand(3));
7067    TmpInst.addOperand(Inst.getOperand(4)); // cc_out
7068    Inst = TmpInst;
7069    return true;
7070  }
7071  case ARM::t2LDMIA_UPD: {
7072    // If this is a load of a single register, then we should use
7073    // a post-indexed LDR instruction instead, per the ARM ARM.
7074    if (Inst.getNumOperands() != 5)
7075      return false;
7076    MCInst TmpInst;
7077    TmpInst.setOpcode(ARM::t2LDR_POST);
7078    TmpInst.addOperand(Inst.getOperand(4)); // Rt
7079    TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7080    TmpInst.addOperand(Inst.getOperand(1)); // Rn
7081    TmpInst.addOperand(MCOperand::CreateImm(4));
7082    TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7083    TmpInst.addOperand(Inst.getOperand(3));
7084    Inst = TmpInst;
7085    return true;
7086  }
7087  case ARM::t2STMDB_UPD: {
7088    // If this is a store of a single register, then we should use
7089    // a pre-indexed STR instruction instead, per the ARM ARM.
7090    if (Inst.getNumOperands() != 5)
7091      return false;
7092    MCInst TmpInst;
7093    TmpInst.setOpcode(ARM::t2STR_PRE);
7094    TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7095    TmpInst.addOperand(Inst.getOperand(4)); // Rt
7096    TmpInst.addOperand(Inst.getOperand(1)); // Rn
7097    TmpInst.addOperand(MCOperand::CreateImm(-4));
7098    TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7099    TmpInst.addOperand(Inst.getOperand(3));
7100    Inst = TmpInst;
7101    return true;
7102  }
7103  case ARM::LDMIA_UPD:
7104    // If this is a load of a single register via a 'pop', then we should use
7105    // a post-indexed LDR instruction instead, per the ARM ARM.
7106    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
7107        Inst.getNumOperands() == 5) {
7108      MCInst TmpInst;
7109      TmpInst.setOpcode(ARM::LDR_POST_IMM);
7110      TmpInst.addOperand(Inst.getOperand(4)); // Rt
7111      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7112      TmpInst.addOperand(Inst.getOperand(1)); // Rn
7113      TmpInst.addOperand(MCOperand::CreateReg(0));  // am2offset
7114      TmpInst.addOperand(MCOperand::CreateImm(4));
7115      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7116      TmpInst.addOperand(Inst.getOperand(3));
7117      Inst = TmpInst;
7118      return true;
7119    }
7120    break;
7121  case ARM::STMDB_UPD:
7122    // If this is a store of a single register via a 'push', then we should use
7123    // a pre-indexed STR instruction instead, per the ARM ARM.
7124    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
7125        Inst.getNumOperands() == 5) {
7126      MCInst TmpInst;
7127      TmpInst.setOpcode(ARM::STR_PRE_IMM);
7128      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7129      TmpInst.addOperand(Inst.getOperand(4)); // Rt
7130      TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
7131      TmpInst.addOperand(MCOperand::CreateImm(-4));
7132      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7133      TmpInst.addOperand(Inst.getOperand(3));
7134      Inst = TmpInst;
7135    }
7136    break;
7137  case ARM::t2ADDri12:
7138    // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
7139    // mnemonic was used (not "addw"), encoding T3 is preferred.
7140    if (static_cast<ARMOperand*>(Operands[0])->getToken() != "add" ||
7141        ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7142      break;
7143    Inst.setOpcode(ARM::t2ADDri);
7144    Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7145    break;
7146  case ARM::t2SUBri12:
7147    // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
7148    // mnemonic was used (not "subw"), encoding T3 is preferred.
7149    if (static_cast<ARMOperand*>(Operands[0])->getToken() != "sub" ||
7150        ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7151      break;
7152    Inst.setOpcode(ARM::t2SUBri);
7153    Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7154    break;
7155  case ARM::tADDi8:
7156    // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7157    // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7158    // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7159    // to encoding T1 if <Rd> is omitted."
7160    if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7161      Inst.setOpcode(ARM::tADDi3);
7162      return true;
7163    }
7164    break;
7165  case ARM::tSUBi8:
7166    // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7167    // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7168    // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7169    // to encoding T1 if <Rd> is omitted."
7170    if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7171      Inst.setOpcode(ARM::tSUBi3);
7172      return true;
7173    }
7174    break;
7175  case ARM::t2ADDri:
7176  case ARM::t2SUBri: {
7177    // If the destination and first source operand are the same, and
7178    // the flags are compatible with the current IT status, use encoding T2
7179    // instead of T3. For compatibility with the system 'as'. Make sure the
7180    // wide encoding wasn't explicit.
7181    if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7182        !isARMLowRegister(Inst.getOperand(0).getReg()) ||
7183        (unsigned)Inst.getOperand(2).getImm() > 255 ||
7184        ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
7185        (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
7186        (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7187         static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7188      break;
7189    MCInst TmpInst;
7190    TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
7191                      ARM::tADDi8 : ARM::tSUBi8);
7192    TmpInst.addOperand(Inst.getOperand(0));
7193    TmpInst.addOperand(Inst.getOperand(5));
7194    TmpInst.addOperand(Inst.getOperand(0));
7195    TmpInst.addOperand(Inst.getOperand(2));
7196    TmpInst.addOperand(Inst.getOperand(3));
7197    TmpInst.addOperand(Inst.getOperand(4));
7198    Inst = TmpInst;
7199    return true;
7200  }
7201  case ARM::t2ADDrr: {
7202    // If the destination and first source operand are the same, and
7203    // there's no setting of the flags, use encoding T2 instead of T3.
7204    // Note that this is only for ADD, not SUB. This mirrors the system
7205    // 'as' behaviour. Make sure the wide encoding wasn't explicit.
7206    if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7207        Inst.getOperand(5).getReg() != 0 ||
7208        (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7209         static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7210      break;
7211    MCInst TmpInst;
7212    TmpInst.setOpcode(ARM::tADDhirr);
7213    TmpInst.addOperand(Inst.getOperand(0));
7214    TmpInst.addOperand(Inst.getOperand(0));
7215    TmpInst.addOperand(Inst.getOperand(2));
7216    TmpInst.addOperand(Inst.getOperand(3));
7217    TmpInst.addOperand(Inst.getOperand(4));
7218    Inst = TmpInst;
7219    return true;
7220  }
7221  case ARM::tADDrSP: {
7222    // If the non-SP source operand and the destination operand are not the
7223    // same, we need to use the 32-bit encoding if it's available.
7224    if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
7225      Inst.setOpcode(ARM::t2ADDrr);
7226      Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7227      return true;
7228    }
7229    break;
7230  }
7231  case ARM::tB:
7232    // A Thumb conditional branch outside of an IT block is a tBcc.
7233    if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
7234      Inst.setOpcode(ARM::tBcc);
7235      return true;
7236    }
7237    break;
7238  case ARM::t2B:
7239    // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
7240    if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
7241      Inst.setOpcode(ARM::t2Bcc);
7242      return true;
7243    }
7244    break;
7245  case ARM::t2Bcc:
7246    // If the conditional is AL or we're in an IT block, we really want t2B.
7247    if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
7248      Inst.setOpcode(ARM::t2B);
7249      return true;
7250    }
7251    break;
7252  case ARM::tBcc:
7253    // If the conditional is AL, we really want tB.
7254    if (Inst.getOperand(1).getImm() == ARMCC::AL) {
7255      Inst.setOpcode(ARM::tB);
7256      return true;
7257    }
7258    break;
7259  case ARM::tLDMIA: {
7260    // If the register list contains any high registers, or if the writeback
7261    // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
7262    // instead if we're in Thumb2. Otherwise, this should have generated
7263    // an error in validateInstruction().
7264    unsigned Rn = Inst.getOperand(0).getReg();
7265    bool hasWritebackToken =
7266      (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7267       static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
7268    bool listContainsBase;
7269    if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
7270        (!listContainsBase && !hasWritebackToken) ||
7271        (listContainsBase && hasWritebackToken)) {
7272      // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7273      assert (isThumbTwo());
7274      Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
7275      // If we're switching to the updating version, we need to insert
7276      // the writeback tied operand.
7277      if (hasWritebackToken)
7278        Inst.insert(Inst.begin(),
7279                    MCOperand::CreateReg(Inst.getOperand(0).getReg()));
7280      return true;
7281    }
7282    break;
7283  }
7284  case ARM::tSTMIA_UPD: {
7285    // If the register list contains any high registers, we need to use
7286    // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7287    // should have generated an error in validateInstruction().
7288    unsigned Rn = Inst.getOperand(0).getReg();
7289    bool listContainsBase;
7290    if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
7291      // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7292      assert (isThumbTwo());
7293      Inst.setOpcode(ARM::t2STMIA_UPD);
7294      return true;
7295    }
7296    break;
7297  }
7298  case ARM::tPOP: {
7299    bool listContainsBase;
7300    // If the register list contains any high registers, we need to use
7301    // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7302    // should have generated an error in validateInstruction().
7303    if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
7304      return false;
7305    assert (isThumbTwo());
7306    Inst.setOpcode(ARM::t2LDMIA_UPD);
7307    // Add the base register and writeback operands.
7308    Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7309    Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7310    return true;
7311  }
7312  case ARM::tPUSH: {
7313    bool listContainsBase;
7314    if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
7315      return false;
7316    assert (isThumbTwo());
7317    Inst.setOpcode(ARM::t2STMDB_UPD);
7318    // Add the base register and writeback operands.
7319    Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7320    Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7321    return true;
7322  }
7323  case ARM::t2MOVi: {
7324    // If we can use the 16-bit encoding and the user didn't explicitly
7325    // request the 32-bit variant, transform it here.
7326    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7327        (unsigned)Inst.getOperand(1).getImm() <= 255 &&
7328        ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
7329         Inst.getOperand(4).getReg() == ARM::CPSR) ||
7330        (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
7331        (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7332         static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7333      // The operands aren't in the same order for tMOVi8...
7334      MCInst TmpInst;
7335      TmpInst.setOpcode(ARM::tMOVi8);
7336      TmpInst.addOperand(Inst.getOperand(0));
7337      TmpInst.addOperand(Inst.getOperand(4));
7338      TmpInst.addOperand(Inst.getOperand(1));
7339      TmpInst.addOperand(Inst.getOperand(2));
7340      TmpInst.addOperand(Inst.getOperand(3));
7341      Inst = TmpInst;
7342      return true;
7343    }
7344    break;
7345  }
7346  case ARM::t2MOVr: {
7347    // If we can use the 16-bit encoding and the user didn't explicitly
7348    // request the 32-bit variant, transform it here.
7349    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7350        isARMLowRegister(Inst.getOperand(1).getReg()) &&
7351        Inst.getOperand(2).getImm() == ARMCC::AL &&
7352        Inst.getOperand(4).getReg() == ARM::CPSR &&
7353        (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7354         static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7355      // The operands aren't the same for tMOV[S]r... (no cc_out)
7356      MCInst TmpInst;
7357      TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
7358      TmpInst.addOperand(Inst.getOperand(0));
7359      TmpInst.addOperand(Inst.getOperand(1));
7360      TmpInst.addOperand(Inst.getOperand(2));
7361      TmpInst.addOperand(Inst.getOperand(3));
7362      Inst = TmpInst;
7363      return true;
7364    }
7365    break;
7366  }
7367  case ARM::t2SXTH:
7368  case ARM::t2SXTB:
7369  case ARM::t2UXTH:
7370  case ARM::t2UXTB: {
7371    // If we can use the 16-bit encoding and the user didn't explicitly
7372    // request the 32-bit variant, transform it here.
7373    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7374        isARMLowRegister(Inst.getOperand(1).getReg()) &&
7375        Inst.getOperand(2).getImm() == 0 &&
7376        (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7377         static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7378      unsigned NewOpc;
7379      switch (Inst.getOpcode()) {
7380      default: llvm_unreachable("Illegal opcode!");
7381      case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
7382      case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
7383      case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
7384      case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
7385      }
7386      // The operands aren't the same for thumb1 (no rotate operand).
7387      MCInst TmpInst;
7388      TmpInst.setOpcode(NewOpc);
7389      TmpInst.addOperand(Inst.getOperand(0));
7390      TmpInst.addOperand(Inst.getOperand(1));
7391      TmpInst.addOperand(Inst.getOperand(3));
7392      TmpInst.addOperand(Inst.getOperand(4));
7393      Inst = TmpInst;
7394      return true;
7395    }
7396    break;
7397  }
7398  case ARM::MOVsi: {
7399    ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
7400    // rrx shifts and asr/lsr of #32 is encoded as 0
7401    if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
7402      return false;
7403    if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
7404      // Shifting by zero is accepted as a vanilla 'MOVr'
7405      MCInst TmpInst;
7406      TmpInst.setOpcode(ARM::MOVr);
7407      TmpInst.addOperand(Inst.getOperand(0));
7408      TmpInst.addOperand(Inst.getOperand(1));
7409      TmpInst.addOperand(Inst.getOperand(3));
7410      TmpInst.addOperand(Inst.getOperand(4));
7411      TmpInst.addOperand(Inst.getOperand(5));
7412      Inst = TmpInst;
7413      return true;
7414    }
7415    return false;
7416  }
7417  case ARM::ANDrsi:
7418  case ARM::ORRrsi:
7419  case ARM::EORrsi:
7420  case ARM::BICrsi:
7421  case ARM::SUBrsi:
7422  case ARM::ADDrsi: {
7423    unsigned newOpc;
7424    ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
7425    if (SOpc == ARM_AM::rrx) return false;
7426    switch (Inst.getOpcode()) {
7427    default: llvm_unreachable("unexpected opcode!");
7428    case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
7429    case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
7430    case ARM::EORrsi: newOpc = ARM::EORrr; break;
7431    case ARM::BICrsi: newOpc = ARM::BICrr; break;
7432    case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
7433    case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
7434    }
7435    // If the shift is by zero, use the non-shifted instruction definition.
7436    // The exception is for right shifts, where 0 == 32
7437    if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
7438        !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
7439      MCInst TmpInst;
7440      TmpInst.setOpcode(newOpc);
7441      TmpInst.addOperand(Inst.getOperand(0));
7442      TmpInst.addOperand(Inst.getOperand(1));
7443      TmpInst.addOperand(Inst.getOperand(2));
7444      TmpInst.addOperand(Inst.getOperand(4));
7445      TmpInst.addOperand(Inst.getOperand(5));
7446      TmpInst.addOperand(Inst.getOperand(6));
7447      Inst = TmpInst;
7448      return true;
7449    }
7450    return false;
7451  }
7452  case ARM::ITasm:
7453  case ARM::t2IT: {
7454    // The mask bits for all but the first condition are represented as
7455    // the low bit of the condition code value implies 't'. We currently
7456    // always have 1 implies 't', so XOR toggle the bits if the low bit
7457    // of the condition code is zero.
7458    MCOperand &MO = Inst.getOperand(1);
7459    unsigned Mask = MO.getImm();
7460    unsigned OrigMask = Mask;
7461    unsigned TZ = countTrailingZeros(Mask);
7462    if ((Inst.getOperand(0).getImm() & 1) == 0) {
7463      assert(Mask && TZ <= 3 && "illegal IT mask value!");
7464      Mask ^= (0xE << TZ) & 0xF;
7465    }
7466    MO.setImm(Mask);
7467
7468    // Set up the IT block state according to the IT instruction we just
7469    // matched.
7470    assert(!inITBlock() && "nested IT blocks?!");
7471    ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
7472    ITState.Mask = OrigMask; // Use the original mask, not the updated one.
7473    ITState.CurPosition = 0;
7474    ITState.FirstCond = true;
7475    break;
7476  }
7477  case ARM::t2LSLrr:
7478  case ARM::t2LSRrr:
7479  case ARM::t2ASRrr:
7480  case ARM::t2SBCrr:
7481  case ARM::t2RORrr:
7482  case ARM::t2BICrr:
7483  {
7484    // Assemblers should use the narrow encodings of these instructions when permissible.
7485    if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7486         isARMLowRegister(Inst.getOperand(2).getReg())) &&
7487        Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7488        ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7489         (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7490        (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7491         !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7492      unsigned NewOpc;
7493      switch (Inst.getOpcode()) {
7494        default: llvm_unreachable("unexpected opcode");
7495        case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
7496        case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
7497        case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
7498        case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
7499        case ARM::t2RORrr: NewOpc = ARM::tROR; break;
7500        case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
7501      }
7502      MCInst TmpInst;
7503      TmpInst.setOpcode(NewOpc);
7504      TmpInst.addOperand(Inst.getOperand(0));
7505      TmpInst.addOperand(Inst.getOperand(5));
7506      TmpInst.addOperand(Inst.getOperand(1));
7507      TmpInst.addOperand(Inst.getOperand(2));
7508      TmpInst.addOperand(Inst.getOperand(3));
7509      TmpInst.addOperand(Inst.getOperand(4));
7510      Inst = TmpInst;
7511      return true;
7512    }
7513    return false;
7514  }
7515  case ARM::t2ANDrr:
7516  case ARM::t2EORrr:
7517  case ARM::t2ADCrr:
7518  case ARM::t2ORRrr:
7519  {
7520    // Assemblers should use the narrow encodings of these instructions when permissible.
7521    // These instructions are special in that they are commutable, so shorter encodings
7522    // are available more often.
7523    if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7524         isARMLowRegister(Inst.getOperand(2).getReg())) &&
7525        (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
7526         Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
7527        ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7528         (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7529        (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7530         !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7531      unsigned NewOpc;
7532      switch (Inst.getOpcode()) {
7533        default: llvm_unreachable("unexpected opcode");
7534        case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
7535        case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
7536        case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
7537        case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
7538      }
7539      MCInst TmpInst;
7540      TmpInst.setOpcode(NewOpc);
7541      TmpInst.addOperand(Inst.getOperand(0));
7542      TmpInst.addOperand(Inst.getOperand(5));
7543      if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
7544        TmpInst.addOperand(Inst.getOperand(1));
7545        TmpInst.addOperand(Inst.getOperand(2));
7546      } else {
7547        TmpInst.addOperand(Inst.getOperand(2));
7548        TmpInst.addOperand(Inst.getOperand(1));
7549      }
7550      TmpInst.addOperand(Inst.getOperand(3));
7551      TmpInst.addOperand(Inst.getOperand(4));
7552      Inst = TmpInst;
7553      return true;
7554    }
7555    return false;
7556  }
7557  }
7558  return false;
7559}
7560
7561unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
7562  // 16-bit thumb arithmetic instructions either require or preclude the 'S'
7563  // suffix depending on whether they're in an IT block or not.
7564  unsigned Opc = Inst.getOpcode();
7565  const MCInstrDesc &MCID = MII.get(Opc);
7566  if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
7567    assert(MCID.hasOptionalDef() &&
7568           "optionally flag setting instruction missing optional def operand");
7569    assert(MCID.NumOperands == Inst.getNumOperands() &&
7570           "operand count mismatch!");
7571    // Find the optional-def operand (cc_out).
7572    unsigned OpNo;
7573    for (OpNo = 0;
7574         !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
7575         ++OpNo)
7576      ;
7577    // If we're parsing Thumb1, reject it completely.
7578    if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
7579      return Match_MnemonicFail;
7580    // If we're parsing Thumb2, which form is legal depends on whether we're
7581    // in an IT block.
7582    if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
7583        !inITBlock())
7584      return Match_RequiresITBlock;
7585    if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
7586        inITBlock())
7587      return Match_RequiresNotITBlock;
7588  }
7589  // Some high-register supporting Thumb1 encodings only allow both registers
7590  // to be from r0-r7 when in Thumb2.
7591  else if (Opc == ARM::tADDhirr && isThumbOne() &&
7592           isARMLowRegister(Inst.getOperand(1).getReg()) &&
7593           isARMLowRegister(Inst.getOperand(2).getReg()))
7594    return Match_RequiresThumb2;
7595  // Others only require ARMv6 or later.
7596  else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
7597           isARMLowRegister(Inst.getOperand(0).getReg()) &&
7598           isARMLowRegister(Inst.getOperand(1).getReg()))
7599    return Match_RequiresV6;
7600  return Match_Success;
7601}
7602
7603static const char *getSubtargetFeatureName(unsigned Val);
7604bool ARMAsmParser::
7605MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
7606                        SmallVectorImpl<MCParsedAsmOperand*> &Operands,
7607                        MCStreamer &Out, unsigned &ErrorInfo,
7608                        bool MatchingInlineAsm) {
7609  MCInst Inst;
7610  unsigned MatchResult;
7611
7612  MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
7613                                     MatchingInlineAsm);
7614  switch (MatchResult) {
7615  default: break;
7616  case Match_Success:
7617    // Context sensitive operand constraints aren't handled by the matcher,
7618    // so check them here.
7619    if (validateInstruction(Inst, Operands)) {
7620      // Still progress the IT block, otherwise one wrong condition causes
7621      // nasty cascading errors.
7622      forwardITPosition();
7623      return true;
7624    }
7625
7626    { // processInstruction() updates inITBlock state, we need to save it away
7627      bool wasInITBlock = inITBlock();
7628
7629      // Some instructions need post-processing to, for example, tweak which
7630      // encoding is selected. Loop on it while changes happen so the
7631      // individual transformations can chain off each other. E.g.,
7632      // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
7633      while (processInstruction(Inst, Operands))
7634        ;
7635
7636      // Only after the instruction is fully processed, we can validate it
7637      if (wasInITBlock && hasV8Ops() && isThumb() &&
7638          !isV8EligibleForIT(&Inst, 2)) {
7639        Warning(IDLoc, "deprecated instruction in IT block");
7640      }
7641    }
7642
7643    // Only move forward at the very end so that everything in validate
7644    // and process gets a consistent answer about whether we're in an IT
7645    // block.
7646    forwardITPosition();
7647
7648    // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
7649    // doesn't actually encode.
7650    if (Inst.getOpcode() == ARM::ITasm)
7651      return false;
7652
7653    Inst.setLoc(IDLoc);
7654    Out.EmitInstruction(Inst);
7655    return false;
7656  case Match_MissingFeature: {
7657    assert(ErrorInfo && "Unknown missing feature!");
7658    // Special case the error message for the very common case where only
7659    // a single subtarget feature is missing (Thumb vs. ARM, e.g.).
7660    std::string Msg = "instruction requires:";
7661    unsigned Mask = 1;
7662    for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
7663      if (ErrorInfo & Mask) {
7664        Msg += " ";
7665        Msg += getSubtargetFeatureName(ErrorInfo & Mask);
7666      }
7667      Mask <<= 1;
7668    }
7669    return Error(IDLoc, Msg);
7670  }
7671  case Match_InvalidOperand: {
7672    SMLoc ErrorLoc = IDLoc;
7673    if (ErrorInfo != ~0U) {
7674      if (ErrorInfo >= Operands.size())
7675        return Error(IDLoc, "too few operands for instruction");
7676
7677      ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7678      if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7679    }
7680
7681    return Error(ErrorLoc, "invalid operand for instruction");
7682  }
7683  case Match_MnemonicFail:
7684    return Error(IDLoc, "invalid instruction",
7685                 ((ARMOperand*)Operands[0])->getLocRange());
7686  case Match_RequiresNotITBlock:
7687    return Error(IDLoc, "flag setting instruction only valid outside IT block");
7688  case Match_RequiresITBlock:
7689    return Error(IDLoc, "instruction only valid inside IT block");
7690  case Match_RequiresV6:
7691    return Error(IDLoc, "instruction variant requires ARMv6 or later");
7692  case Match_RequiresThumb2:
7693    return Error(IDLoc, "instruction variant requires Thumb2");
7694  case Match_ImmRange0_15: {
7695    SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7696    if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7697    return Error(ErrorLoc, "immediate operand must be in the range [0,15]");
7698  }
7699  }
7700
7701  llvm_unreachable("Implement any new match types added!");
7702}
7703
7704/// parseDirective parses the arm specific directives
7705bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
7706  StringRef IDVal = DirectiveID.getIdentifier();
7707  if (IDVal == ".word")
7708    return parseDirectiveWord(4, DirectiveID.getLoc());
7709  else if (IDVal == ".thumb")
7710    return parseDirectiveThumb(DirectiveID.getLoc());
7711  else if (IDVal == ".arm")
7712    return parseDirectiveARM(DirectiveID.getLoc());
7713  else if (IDVal == ".thumb_func")
7714    return parseDirectiveThumbFunc(DirectiveID.getLoc());
7715  else if (IDVal == ".code")
7716    return parseDirectiveCode(DirectiveID.getLoc());
7717  else if (IDVal == ".syntax")
7718    return parseDirectiveSyntax(DirectiveID.getLoc());
7719  else if (IDVal == ".unreq")
7720    return parseDirectiveUnreq(DirectiveID.getLoc());
7721  else if (IDVal == ".arch")
7722    return parseDirectiveArch(DirectiveID.getLoc());
7723  else if (IDVal == ".eabi_attribute")
7724    return parseDirectiveEabiAttr(DirectiveID.getLoc());
7725  else if (IDVal == ".fnstart")
7726    return parseDirectiveFnStart(DirectiveID.getLoc());
7727  else if (IDVal == ".fnend")
7728    return parseDirectiveFnEnd(DirectiveID.getLoc());
7729  else if (IDVal == ".cantunwind")
7730    return parseDirectiveCantUnwind(DirectiveID.getLoc());
7731  else if (IDVal == ".personality")
7732    return parseDirectivePersonality(DirectiveID.getLoc());
7733  else if (IDVal == ".handlerdata")
7734    return parseDirectiveHandlerData(DirectiveID.getLoc());
7735  else if (IDVal == ".setfp")
7736    return parseDirectiveSetFP(DirectiveID.getLoc());
7737  else if (IDVal == ".pad")
7738    return parseDirectivePad(DirectiveID.getLoc());
7739  else if (IDVal == ".save")
7740    return parseDirectiveRegSave(DirectiveID.getLoc(), false);
7741  else if (IDVal == ".vsave")
7742    return parseDirectiveRegSave(DirectiveID.getLoc(), true);
7743  return true;
7744}
7745
7746/// parseDirectiveWord
7747///  ::= .word [ expression (, expression)* ]
7748bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
7749  if (getLexer().isNot(AsmToken::EndOfStatement)) {
7750    for (;;) {
7751      const MCExpr *Value;
7752      if (getParser().parseExpression(Value))
7753        return true;
7754
7755      getParser().getStreamer().EmitValue(Value, Size);
7756
7757      if (getLexer().is(AsmToken::EndOfStatement))
7758        break;
7759
7760      // FIXME: Improve diagnostic.
7761      if (getLexer().isNot(AsmToken::Comma))
7762        return Error(L, "unexpected token in directive");
7763      Parser.Lex();
7764    }
7765  }
7766
7767  Parser.Lex();
7768  return false;
7769}
7770
7771/// parseDirectiveThumb
7772///  ::= .thumb
7773bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
7774  if (getLexer().isNot(AsmToken::EndOfStatement))
7775    return Error(L, "unexpected token in directive");
7776  Parser.Lex();
7777
7778  if (!hasThumb())
7779    return Error(L, "target does not support Thumb mode");
7780
7781  if (!isThumb())
7782    SwitchMode();
7783  getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
7784  return false;
7785}
7786
7787/// parseDirectiveARM
7788///  ::= .arm
7789bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
7790  if (getLexer().isNot(AsmToken::EndOfStatement))
7791    return Error(L, "unexpected token in directive");
7792  Parser.Lex();
7793
7794  if (!hasARM())
7795    return Error(L, "target does not support ARM mode");
7796
7797  if (isThumb())
7798    SwitchMode();
7799  getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
7800  return false;
7801}
7802
7803/// parseDirectiveThumbFunc
7804///  ::= .thumbfunc symbol_name
7805bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
7806  const MCAsmInfo *MAI = getParser().getStreamer().getContext().getAsmInfo();
7807  bool isMachO = MAI->hasSubsectionsViaSymbols();
7808  StringRef Name;
7809  bool needFuncName = true;
7810
7811  // Darwin asm has (optionally) function name after .thumb_func direction
7812  // ELF doesn't
7813  if (isMachO) {
7814    const AsmToken &Tok = Parser.getTok();
7815    if (Tok.isNot(AsmToken::EndOfStatement)) {
7816      if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
7817        return Error(L, "unexpected token in .thumb_func directive");
7818      Name = Tok.getIdentifier();
7819      Parser.Lex(); // Consume the identifier token.
7820      needFuncName = false;
7821    }
7822  }
7823
7824  if (getLexer().isNot(AsmToken::EndOfStatement))
7825    return Error(L, "unexpected token in directive");
7826
7827  // Eat the end of statement and any blank lines that follow.
7828  while (getLexer().is(AsmToken::EndOfStatement))
7829    Parser.Lex();
7830
7831  // FIXME: assuming function name will be the line following .thumb_func
7832  // We really should be checking the next symbol definition even if there's
7833  // stuff in between.
7834  if (needFuncName) {
7835    Name = Parser.getTok().getIdentifier();
7836  }
7837
7838  // Mark symbol as a thumb symbol.
7839  MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
7840  getParser().getStreamer().EmitThumbFunc(Func);
7841  return false;
7842}
7843
7844/// parseDirectiveSyntax
7845///  ::= .syntax unified | divided
7846bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
7847  const AsmToken &Tok = Parser.getTok();
7848  if (Tok.isNot(AsmToken::Identifier))
7849    return Error(L, "unexpected token in .syntax directive");
7850  StringRef Mode = Tok.getString();
7851  if (Mode == "unified" || Mode == "UNIFIED")
7852    Parser.Lex();
7853  else if (Mode == "divided" || Mode == "DIVIDED")
7854    return Error(L, "'.syntax divided' arm asssembly not supported");
7855  else
7856    return Error(L, "unrecognized syntax mode in .syntax directive");
7857
7858  if (getLexer().isNot(AsmToken::EndOfStatement))
7859    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
7860  Parser.Lex();
7861
7862  // TODO tell the MC streamer the mode
7863  // getParser().getStreamer().Emit???();
7864  return false;
7865}
7866
7867/// parseDirectiveCode
7868///  ::= .code 16 | 32
7869bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
7870  const AsmToken &Tok = Parser.getTok();
7871  if (Tok.isNot(AsmToken::Integer))
7872    return Error(L, "unexpected token in .code directive");
7873  int64_t Val = Parser.getTok().getIntVal();
7874  if (Val == 16)
7875    Parser.Lex();
7876  else if (Val == 32)
7877    Parser.Lex();
7878  else
7879    return Error(L, "invalid operand to .code directive");
7880
7881  if (getLexer().isNot(AsmToken::EndOfStatement))
7882    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
7883  Parser.Lex();
7884
7885  if (Val == 16) {
7886    if (!hasThumb())
7887      return Error(L, "target does not support Thumb mode");
7888
7889    if (!isThumb())
7890      SwitchMode();
7891    getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
7892  } else {
7893    if (!hasARM())
7894      return Error(L, "target does not support ARM mode");
7895
7896    if (isThumb())
7897      SwitchMode();
7898    getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
7899  }
7900
7901  return false;
7902}
7903
7904/// parseDirectiveReq
7905///  ::= name .req registername
7906bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
7907  Parser.Lex(); // Eat the '.req' token.
7908  unsigned Reg;
7909  SMLoc SRegLoc, ERegLoc;
7910  if (ParseRegister(Reg, SRegLoc, ERegLoc)) {
7911    Parser.eatToEndOfStatement();
7912    return Error(SRegLoc, "register name expected");
7913  }
7914
7915  // Shouldn't be anything else.
7916  if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
7917    Parser.eatToEndOfStatement();
7918    return Error(Parser.getTok().getLoc(),
7919                 "unexpected input in .req directive.");
7920  }
7921
7922  Parser.Lex(); // Consume the EndOfStatement
7923
7924  if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg)
7925    return Error(SRegLoc, "redefinition of '" + Name +
7926                          "' does not match original.");
7927
7928  return false;
7929}
7930
7931/// parseDirectiveUneq
7932///  ::= .unreq registername
7933bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
7934  if (Parser.getTok().isNot(AsmToken::Identifier)) {
7935    Parser.eatToEndOfStatement();
7936    return Error(L, "unexpected input in .unreq directive.");
7937  }
7938  RegisterReqs.erase(Parser.getTok().getIdentifier());
7939  Parser.Lex(); // Eat the identifier.
7940  return false;
7941}
7942
7943/// parseDirectiveArch
7944///  ::= .arch token
7945bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
7946  return true;
7947}
7948
7949/// parseDirectiveEabiAttr
7950///  ::= .eabi_attribute int, int
7951bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
7952  return true;
7953}
7954
7955/// parseDirectiveFnStart
7956///  ::= .fnstart
7957bool ARMAsmParser::parseDirectiveFnStart(SMLoc L) {
7958  if (FnStartLoc.isValid()) {
7959    Error(L, ".fnstart starts before the end of previous one");
7960    Error(FnStartLoc, "previous .fnstart starts here");
7961    return true;
7962  }
7963
7964  FnStartLoc = L;
7965  getParser().getStreamer().EmitFnStart();
7966  return false;
7967}
7968
7969/// parseDirectiveFnEnd
7970///  ::= .fnend
7971bool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) {
7972  // Check the ordering of unwind directives
7973  if (!FnStartLoc.isValid())
7974    return Error(L, ".fnstart must precede .fnend directive");
7975
7976  // Reset the unwind directives parser state
7977  resetUnwindDirectiveParserState();
7978
7979  getParser().getStreamer().EmitFnEnd();
7980  return false;
7981}
7982
7983/// parseDirectiveCantUnwind
7984///  ::= .cantunwind
7985bool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) {
7986  // Check the ordering of unwind directives
7987  CantUnwindLoc = L;
7988  if (!FnStartLoc.isValid())
7989    return Error(L, ".fnstart must precede .cantunwind directive");
7990  if (HandlerDataLoc.isValid()) {
7991    Error(L, ".cantunwind can't be used with .handlerdata directive");
7992    Error(HandlerDataLoc, ".handlerdata was specified here");
7993    return true;
7994  }
7995  if (PersonalityLoc.isValid()) {
7996    Error(L, ".cantunwind can't be used with .personality directive");
7997    Error(PersonalityLoc, ".personality was specified here");
7998    return true;
7999  }
8000
8001  getParser().getStreamer().EmitCantUnwind();
8002  return false;
8003}
8004
8005/// parseDirectivePersonality
8006///  ::= .personality name
8007bool ARMAsmParser::parseDirectivePersonality(SMLoc L) {
8008  // Check the ordering of unwind directives
8009  PersonalityLoc = L;
8010  if (!FnStartLoc.isValid())
8011    return Error(L, ".fnstart must precede .personality directive");
8012  if (CantUnwindLoc.isValid()) {
8013    Error(L, ".personality can't be used with .cantunwind directive");
8014    Error(CantUnwindLoc, ".cantunwind was specified here");
8015    return true;
8016  }
8017  if (HandlerDataLoc.isValid()) {
8018    Error(L, ".personality must precede .handlerdata directive");
8019    Error(HandlerDataLoc, ".handlerdata was specified here");
8020    return true;
8021  }
8022
8023  // Parse the name of the personality routine
8024  if (Parser.getTok().isNot(AsmToken::Identifier)) {
8025    Parser.eatToEndOfStatement();
8026    return Error(L, "unexpected input in .personality directive.");
8027  }
8028  StringRef Name(Parser.getTok().getIdentifier());
8029  Parser.Lex();
8030
8031  MCSymbol *PR = getParser().getContext().GetOrCreateSymbol(Name);
8032  getParser().getStreamer().EmitPersonality(PR);
8033  return false;
8034}
8035
8036/// parseDirectiveHandlerData
8037///  ::= .handlerdata
8038bool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) {
8039  // Check the ordering of unwind directives
8040  HandlerDataLoc = L;
8041  if (!FnStartLoc.isValid())
8042    return Error(L, ".fnstart must precede .personality directive");
8043  if (CantUnwindLoc.isValid()) {
8044    Error(L, ".handlerdata can't be used with .cantunwind directive");
8045    Error(CantUnwindLoc, ".cantunwind was specified here");
8046    return true;
8047  }
8048
8049  getParser().getStreamer().EmitHandlerData();
8050  return false;
8051}
8052
8053/// parseDirectiveSetFP
8054///  ::= .setfp fpreg, spreg [, offset]
8055bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) {
8056  // Check the ordering of unwind directives
8057  if (!FnStartLoc.isValid())
8058    return Error(L, ".fnstart must precede .setfp directive");
8059  if (HandlerDataLoc.isValid())
8060    return Error(L, ".setfp must precede .handlerdata directive");
8061
8062  // Parse fpreg
8063  SMLoc NewFPRegLoc = Parser.getTok().getLoc();
8064  int NewFPReg = tryParseRegister();
8065  if (NewFPReg == -1)
8066    return Error(NewFPRegLoc, "frame pointer register expected");
8067
8068  // Consume comma
8069  if (!Parser.getTok().is(AsmToken::Comma))
8070    return Error(Parser.getTok().getLoc(), "comma expected");
8071  Parser.Lex(); // skip comma
8072
8073  // Parse spreg
8074  SMLoc NewSPRegLoc = Parser.getTok().getLoc();
8075  int NewSPReg = tryParseRegister();
8076  if (NewSPReg == -1)
8077    return Error(NewSPRegLoc, "stack pointer register expected");
8078
8079  if (NewSPReg != ARM::SP && NewSPReg != FPReg)
8080    return Error(NewSPRegLoc,
8081                 "register should be either $sp or the latest fp register");
8082
8083  // Update the frame pointer register
8084  FPReg = NewFPReg;
8085
8086  // Parse offset
8087  int64_t Offset = 0;
8088  if (Parser.getTok().is(AsmToken::Comma)) {
8089    Parser.Lex(); // skip comma
8090
8091    if (Parser.getTok().isNot(AsmToken::Hash) &&
8092        Parser.getTok().isNot(AsmToken::Dollar)) {
8093      return Error(Parser.getTok().getLoc(), "'#' expected");
8094    }
8095    Parser.Lex(); // skip hash token.
8096
8097    const MCExpr *OffsetExpr;
8098    SMLoc ExLoc = Parser.getTok().getLoc();
8099    SMLoc EndLoc;
8100    if (getParser().parseExpression(OffsetExpr, EndLoc))
8101      return Error(ExLoc, "malformed setfp offset");
8102    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
8103    if (!CE)
8104      return Error(ExLoc, "setfp offset must be an immediate");
8105
8106    Offset = CE->getValue();
8107  }
8108
8109  getParser().getStreamer().EmitSetFP(static_cast<unsigned>(NewFPReg),
8110                                      static_cast<unsigned>(NewSPReg),
8111                                      Offset);
8112  return false;
8113}
8114
8115/// parseDirective
8116///  ::= .pad offset
8117bool ARMAsmParser::parseDirectivePad(SMLoc L) {
8118  // Check the ordering of unwind directives
8119  if (!FnStartLoc.isValid())
8120    return Error(L, ".fnstart must precede .pad directive");
8121  if (HandlerDataLoc.isValid())
8122    return Error(L, ".pad must precede .handlerdata directive");
8123
8124  // Parse the offset
8125  if (Parser.getTok().isNot(AsmToken::Hash) &&
8126      Parser.getTok().isNot(AsmToken::Dollar)) {
8127    return Error(Parser.getTok().getLoc(), "'#' expected");
8128  }
8129  Parser.Lex(); // skip hash token.
8130
8131  const MCExpr *OffsetExpr;
8132  SMLoc ExLoc = Parser.getTok().getLoc();
8133  SMLoc EndLoc;
8134  if (getParser().parseExpression(OffsetExpr, EndLoc))
8135    return Error(ExLoc, "malformed pad offset");
8136  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
8137  if (!CE)
8138    return Error(ExLoc, "pad offset must be an immediate");
8139
8140  getParser().getStreamer().EmitPad(CE->getValue());
8141  return false;
8142}
8143
8144/// parseDirectiveRegSave
8145///  ::= .save  { registers }
8146///  ::= .vsave { registers }
8147bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) {
8148  // Check the ordering of unwind directives
8149  if (!FnStartLoc.isValid())
8150    return Error(L, ".fnstart must precede .save or .vsave directives");
8151  if (HandlerDataLoc.isValid())
8152    return Error(L, ".save or .vsave must precede .handlerdata directive");
8153
8154  // RAII object to make sure parsed operands are deleted.
8155  struct CleanupObject {
8156    SmallVector<MCParsedAsmOperand *, 1> Operands;
8157    ~CleanupObject() {
8158      for (unsigned I = 0, E = Operands.size(); I != E; ++I)
8159        delete Operands[I];
8160    }
8161  } CO;
8162
8163  // Parse the register list
8164  if (parseRegisterList(CO.Operands))
8165    return true;
8166  ARMOperand *Op = (ARMOperand*)CO.Operands[0];
8167  if (!IsVector && !Op->isRegList())
8168    return Error(L, ".save expects GPR registers");
8169  if (IsVector && !Op->isDPRRegList())
8170    return Error(L, ".vsave expects DPR registers");
8171
8172  getParser().getStreamer().EmitRegSave(Op->getRegList(), IsVector);
8173  return false;
8174}
8175
8176/// Force static initialization.
8177extern "C" void LLVMInitializeARMAsmParser() {
8178  RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
8179  RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
8180}
8181
8182#define GET_REGISTER_MATCHER
8183#define GET_SUBTARGET_FEATURE_NAME
8184#define GET_MATCHER_IMPLEMENTATION
8185#include "ARMGenAsmMatcher.inc"
8186
8187// Define this matcher function after the auto-generated include so we
8188// have the match class enum definitions.
8189unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand *AsmOp,
8190                                                  unsigned Kind) {
8191  ARMOperand *Op = static_cast<ARMOperand*>(AsmOp);
8192  // If the kind is a token for a literal immediate, check if our asm
8193  // operand matches. This is for InstAliases which have a fixed-value
8194  // immediate in the syntax.
8195  if (Kind == MCK__35_0 && Op->isImm()) {
8196    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
8197    if (!CE)
8198      return Match_InvalidOperand;
8199    if (CE->getValue() == 0)
8200      return Match_Success;
8201  }
8202  return Match_InvalidOperand;
8203}
8204