ARMAsmParser.cpp revision 715d98d657491b3fb8ea0e14643e9801b2f9628c 
1//===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "llvm/MC/MCTargetAsmParser.h"
11#include "MCTargetDesc/ARMAddressingModes.h"
12#include "MCTargetDesc/ARMBaseInfo.h"
13#include "MCTargetDesc/ARMMCExpr.h"
14#include "llvm/ADT/BitVector.h"
15#include "llvm/ADT/OwningPtr.h"
16#include "llvm/ADT/STLExtras.h"
17#include "llvm/ADT/SmallVector.h"
18#include "llvm/ADT/StringSwitch.h"
19#include "llvm/ADT/Twine.h"
20#include "llvm/MC/MCAsmInfo.h"
21#include "llvm/MC/MCAssembler.h"
22#include "llvm/MC/MCContext.h"
23#include "llvm/MC/MCELFStreamer.h"
24#include "llvm/MC/MCExpr.h"
25#include "llvm/MC/MCInst.h"
26#include "llvm/MC/MCInstrDesc.h"
27#include "llvm/MC/MCInstrInfo.h"
28#include "llvm/MC/MCParser/MCAsmLexer.h"
29#include "llvm/MC/MCParser/MCAsmParser.h"
30#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
31#include "llvm/MC/MCRegisterInfo.h"
32#include "llvm/MC/MCStreamer.h"
33#include "llvm/MC/MCSubtargetInfo.h"
34#include "llvm/Support/ELF.h"
35#include "llvm/Support/MathExtras.h"
36#include "llvm/Support/SourceMgr.h"
37#include "llvm/Support/TargetRegistry.h"
38#include "llvm/Support/raw_ostream.h"
39
40using namespace llvm;
41
42namespace {
43
44class ARMOperand;
45
46enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
47
48class ARMAsmParser : public MCTargetAsmParser {
49  MCSubtargetInfo &STI;
50  MCAsmParser &Parser;
51  const MCInstrInfo &MII;
52  const MCRegisterInfo *MRI;
53
54  // Unwind directives state
55  SMLoc FnStartLoc;
56  SMLoc CantUnwindLoc;
57  SMLoc PersonalityLoc;
58  SMLoc HandlerDataLoc;
59  int FPReg;
60  void resetUnwindDirectiveParserState() {
61    FnStartLoc = SMLoc();
62    CantUnwindLoc = SMLoc();
63    PersonalityLoc = SMLoc();
64    HandlerDataLoc = SMLoc();
65    FPReg = -1;
66  }
67
68  // Map of register aliases registers via the .req directive.
69  StringMap<unsigned> RegisterReqs;
70
71  struct {
72    ARMCC::CondCodes Cond;    // Condition for IT block.
73    unsigned Mask:4;          // Condition mask for instructions.
74                              // Starting at first 1 (from lsb).
75                              //   '1'  condition as indicated in IT.
76                              //   '0'  inverse of condition (else).
77                              // Count of instructions in IT block is
78                              // 4 - trailingzeroes(mask)
79
80    bool FirstCond;           // Explicit flag for when we're parsing the
81                              // First instruction in the IT block. It's
82                              // implied in the mask, so needs special
83                              // handling.
84
85    unsigned CurPosition;     // Current position in parsing of IT
86                              // block. In range [0,3]. Initialized
87                              // according to count of instructions in block.
88                              // ~0U if no active IT block.
89  } ITState;
90  bool inITBlock() { return ITState.CurPosition != ~0U;}
91  void forwardITPosition() {
92    if (!inITBlock()) return;
93    // Move to the next instruction in the IT block, if there is one. If not,
94    // mark the block as done.
95    unsigned TZ = countTrailingZeros(ITState.Mask);
96    if (++ITState.CurPosition == 5 - TZ)
97      ITState.CurPosition = ~0U; // Done with the IT block after this.
98  }
99
100
101  MCAsmParser &getParser() const { return Parser; }
102  MCAsmLexer &getLexer() const { return Parser.getLexer(); }
103
104  bool Warning(SMLoc L, const Twine &Msg,
105               ArrayRef<SMRange> Ranges = None) {
106    return Parser.Warning(L, Msg, Ranges);
107  }
108  bool Error(SMLoc L, const Twine &Msg,
109             ArrayRef<SMRange> Ranges = None) {
110    return Parser.Error(L, Msg, Ranges);
111  }
112
113  int tryParseRegister();
114  bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
115  int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
116  bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
117  bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
118  bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
119  bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
120  bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
121                              unsigned &ShiftAmount);
122  bool parseDirectiveWord(unsigned Size, SMLoc L);
123  bool parseDirectiveThumb(SMLoc L);
124  bool parseDirectiveARM(SMLoc L);
125  bool parseDirectiveThumbFunc(SMLoc L);
126  bool parseDirectiveCode(SMLoc L);
127  bool parseDirectiveSyntax(SMLoc L);
128  bool parseDirectiveReq(StringRef Name, SMLoc L);
129  bool parseDirectiveUnreq(SMLoc L);
130  bool parseDirectiveArch(SMLoc L);
131  bool parseDirectiveEabiAttr(SMLoc L);
132  bool parseDirectiveFnStart(SMLoc L);
133  bool parseDirectiveFnEnd(SMLoc L);
134  bool parseDirectiveCantUnwind(SMLoc L);
135  bool parseDirectivePersonality(SMLoc L);
136  bool parseDirectiveHandlerData(SMLoc L);
137  bool parseDirectiveSetFP(SMLoc L);
138  bool parseDirectivePad(SMLoc L);
139  bool parseDirectiveRegSave(SMLoc L, bool IsVector);
140
141  StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
142                          bool &CarrySetting, unsigned &ProcessorIMod,
143                          StringRef &ITMask);
144  void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
145                             bool &CanAcceptPredicationCode);
146
147  bool isThumb() const {
148    // FIXME: Can tablegen auto-generate this?
149    return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
150  }
151  bool isThumbOne() const {
152    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
153  }
154  bool isThumbTwo() const {
155    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
156  }
157  bool hasThumb() const {
158    return STI.getFeatureBits() & ARM::HasV4TOps;
159  }
160  bool hasV6Ops() const {
161    return STI.getFeatureBits() & ARM::HasV6Ops;
162  }
163  bool hasV7Ops() const {
164    return STI.getFeatureBits() & ARM::HasV7Ops;
165  }
166  bool hasV8Ops() const {
167    return STI.getFeatureBits() & ARM::HasV8Ops;
168  }
169  bool hasARM() const {
170    return !(STI.getFeatureBits() & ARM::FeatureNoARM);
171  }
172
173  void SwitchMode() {
174    unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
175    setAvailableFeatures(FB);
176  }
177  bool isMClass() const {
178    return STI.getFeatureBits() & ARM::FeatureMClass;
179  }
180
181  /// @name Auto-generated Match Functions
182  /// {
183
184#define GET_ASSEMBLER_HEADER
185#include "ARMGenAsmMatcher.inc"
186
187  /// }
188
189  OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
190  OperandMatchResultTy parseCoprocNumOperand(
191    SmallVectorImpl<MCParsedAsmOperand*>&);
192  OperandMatchResultTy parseCoprocRegOperand(
193    SmallVectorImpl<MCParsedAsmOperand*>&);
194  OperandMatchResultTy parseCoprocOptionOperand(
195    SmallVectorImpl<MCParsedAsmOperand*>&);
196  OperandMatchResultTy parseMemBarrierOptOperand(
197    SmallVectorImpl<MCParsedAsmOperand*>&);
198  OperandMatchResultTy parseInstSyncBarrierOptOperand(
199    SmallVectorImpl<MCParsedAsmOperand*>&);
200  OperandMatchResultTy parseProcIFlagsOperand(
201    SmallVectorImpl<MCParsedAsmOperand*>&);
202  OperandMatchResultTy parseMSRMaskOperand(
203    SmallVectorImpl<MCParsedAsmOperand*>&);
204  OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
205                                   StringRef Op, int Low, int High);
206  OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
207    return parsePKHImm(O, "lsl", 0, 31);
208  }
209  OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
210    return parsePKHImm(O, "asr", 1, 32);
211  }
212  OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
213  OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
214  OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
215  OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
216  OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
217  OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
218  OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&);
219  OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&);
220  OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
221                                       SMLoc &EndLoc);
222
223  // Asm Match Converter Methods
224  void cvtThumbMultiply(MCInst &Inst,
225                        const SmallVectorImpl<MCParsedAsmOperand*> &);
226  void cvtThumbBranches(MCInst &Inst,
227                        const SmallVectorImpl<MCParsedAsmOperand*> &);
228
229  bool validateInstruction(MCInst &Inst,
230                           const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
231  bool processInstruction(MCInst &Inst,
232                          const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
233  bool shouldOmitCCOutOperand(StringRef Mnemonic,
234                              SmallVectorImpl<MCParsedAsmOperand*> &Operands);
235  bool shouldOmitPredicateOperand(StringRef Mnemonic,
236                              SmallVectorImpl<MCParsedAsmOperand*> &Operands);
237public:
238  enum ARMMatchResultTy {
239    Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
240    Match_RequiresNotITBlock,
241    Match_RequiresV6,
242    Match_RequiresThumb2,
243#define GET_OPERAND_DIAGNOSTIC_TYPES
244#include "ARMGenAsmMatcher.inc"
245
246  };
247
248  ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser,
249               const MCInstrInfo &MII)
250      : MCTargetAsmParser(), STI(_STI), Parser(_Parser), MII(MII), FPReg(-1) {
251    MCAsmParserExtension::Initialize(_Parser);
252
253    // Cache the MCRegisterInfo.
254    MRI = getContext().getRegisterInfo();
255
256    // Initialize the set of available features.
257    setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
258
259    // Not in an ITBlock to start with.
260    ITState.CurPosition = ~0U;
261
262    // Set ELF header flags.
263    // FIXME: This should eventually end up somewhere else where more
264    // intelligent flag decisions can be made. For now we are just maintaining
265    // the statu/parseDirects quo for ARM and setting EF_ARM_EABI_VER5 as the default.
266    if (MCELFStreamer *MES = dyn_cast<MCELFStreamer>(&Parser.getStreamer()))
267      MES->getAssembler().setELFHeaderEFlags(ELF::EF_ARM_EABI_VER5);
268  }
269
270  // Implementation of the MCTargetAsmParser interface:
271  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
272  bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
273                        SMLoc NameLoc,
274                        SmallVectorImpl<MCParsedAsmOperand*> &Operands);
275  bool ParseDirective(AsmToken DirectiveID);
276
277  unsigned validateTargetOperandClass(MCParsedAsmOperand *Op, unsigned Kind);
278  unsigned checkTargetMatchPredicate(MCInst &Inst);
279
280  bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
281                               SmallVectorImpl<MCParsedAsmOperand*> &Operands,
282                               MCStreamer &Out, unsigned &ErrorInfo,
283                               bool MatchingInlineAsm);
284};
285} // end anonymous namespace
286
287namespace {
288
289/// ARMOperand - Instances of this class represent a parsed ARM machine
290/// operand.
291class ARMOperand : public MCParsedAsmOperand {
292  enum KindTy {
293    k_CondCode,
294    k_CCOut,
295    k_ITCondMask,
296    k_CoprocNum,
297    k_CoprocReg,
298    k_CoprocOption,
299    k_Immediate,
300    k_MemBarrierOpt,
301    k_InstSyncBarrierOpt,
302    k_Memory,
303    k_PostIndexRegister,
304    k_MSRMask,
305    k_ProcIFlags,
306    k_VectorIndex,
307    k_Register,
308    k_RegisterList,
309    k_DPRRegisterList,
310    k_SPRRegisterList,
311    k_VectorList,
312    k_VectorListAllLanes,
313    k_VectorListIndexed,
314    k_ShiftedRegister,
315    k_ShiftedImmediate,
316    k_ShifterImmediate,
317    k_RotateImmediate,
318    k_BitfieldDescriptor,
319    k_Token
320  } Kind;
321
322  SMLoc StartLoc, EndLoc;
323  SmallVector<unsigned, 8> Registers;
324
325  struct CCOp {
326    ARMCC::CondCodes Val;
327  };
328
329  struct CopOp {
330    unsigned Val;
331  };
332
333  struct CoprocOptionOp {
334    unsigned Val;
335  };
336
337  struct ITMaskOp {
338    unsigned Mask:4;
339  };
340
341  struct MBOptOp {
342    ARM_MB::MemBOpt Val;
343  };
344
345  struct ISBOptOp {
346    ARM_ISB::InstSyncBOpt Val;
347  };
348
349  struct IFlagsOp {
350    ARM_PROC::IFlags Val;
351  };
352
353  struct MMaskOp {
354    unsigned Val;
355  };
356
357  struct TokOp {
358    const char *Data;
359    unsigned Length;
360  };
361
362  struct RegOp {
363    unsigned RegNum;
364  };
365
366  // A vector register list is a sequential list of 1 to 4 registers.
367  struct VectorListOp {
368    unsigned RegNum;
369    unsigned Count;
370    unsigned LaneIndex;
371    bool isDoubleSpaced;
372  };
373
374  struct VectorIndexOp {
375    unsigned Val;
376  };
377
378  struct ImmOp {
379    const MCExpr *Val;
380  };
381
382  /// Combined record for all forms of ARM address expressions.
383  struct MemoryOp {
384    unsigned BaseRegNum;
385    // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
386    // was specified.
387    const MCConstantExpr *OffsetImm;  // Offset immediate value
388    unsigned OffsetRegNum;    // Offset register num, when OffsetImm == NULL
389    ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
390    unsigned ShiftImm;        // shift for OffsetReg.
391    unsigned Alignment;       // 0 = no alignment specified
392    // n = alignment in bytes (2, 4, 8, 16, or 32)
393    unsigned isNegative : 1;  // Negated OffsetReg? (~'U' bit)
394  };
395
396  struct PostIdxRegOp {
397    unsigned RegNum;
398    bool isAdd;
399    ARM_AM::ShiftOpc ShiftTy;
400    unsigned ShiftImm;
401  };
402
403  struct ShifterImmOp {
404    bool isASR;
405    unsigned Imm;
406  };
407
408  struct RegShiftedRegOp {
409    ARM_AM::ShiftOpc ShiftTy;
410    unsigned SrcReg;
411    unsigned ShiftReg;
412    unsigned ShiftImm;
413  };
414
415  struct RegShiftedImmOp {
416    ARM_AM::ShiftOpc ShiftTy;
417    unsigned SrcReg;
418    unsigned ShiftImm;
419  };
420
421  struct RotImmOp {
422    unsigned Imm;
423  };
424
425  struct BitfieldOp {
426    unsigned LSB;
427    unsigned Width;
428  };
429
430  union {
431    struct CCOp CC;
432    struct CopOp Cop;
433    struct CoprocOptionOp CoprocOption;
434    struct MBOptOp MBOpt;
435    struct ISBOptOp ISBOpt;
436    struct ITMaskOp ITMask;
437    struct IFlagsOp IFlags;
438    struct MMaskOp MMask;
439    struct TokOp Tok;
440    struct RegOp Reg;
441    struct VectorListOp VectorList;
442    struct VectorIndexOp VectorIndex;
443    struct ImmOp Imm;
444    struct MemoryOp Memory;
445    struct PostIdxRegOp PostIdxReg;
446    struct ShifterImmOp ShifterImm;
447    struct RegShiftedRegOp RegShiftedReg;
448    struct RegShiftedImmOp RegShiftedImm;
449    struct RotImmOp RotImm;
450    struct BitfieldOp Bitfield;
451  };
452
453  ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
454public:
455  ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
456    Kind = o.Kind;
457    StartLoc = o.StartLoc;
458    EndLoc = o.EndLoc;
459    switch (Kind) {
460    case k_CondCode:
461      CC = o.CC;
462      break;
463    case k_ITCondMask:
464      ITMask = o.ITMask;
465      break;
466    case k_Token:
467      Tok = o.Tok;
468      break;
469    case k_CCOut:
470    case k_Register:
471      Reg = o.Reg;
472      break;
473    case k_RegisterList:
474    case k_DPRRegisterList:
475    case k_SPRRegisterList:
476      Registers = o.Registers;
477      break;
478    case k_VectorList:
479    case k_VectorListAllLanes:
480    case k_VectorListIndexed:
481      VectorList = o.VectorList;
482      break;
483    case k_CoprocNum:
484    case k_CoprocReg:
485      Cop = o.Cop;
486      break;
487    case k_CoprocOption:
488      CoprocOption = o.CoprocOption;
489      break;
490    case k_Immediate:
491      Imm = o.Imm;
492      break;
493    case k_MemBarrierOpt:
494      MBOpt = o.MBOpt;
495      break;
496    case k_InstSyncBarrierOpt:
497      ISBOpt = o.ISBOpt;
498    case k_Memory:
499      Memory = o.Memory;
500      break;
501    case k_PostIndexRegister:
502      PostIdxReg = o.PostIdxReg;
503      break;
504    case k_MSRMask:
505      MMask = o.MMask;
506      break;
507    case k_ProcIFlags:
508      IFlags = o.IFlags;
509      break;
510    case k_ShifterImmediate:
511      ShifterImm = o.ShifterImm;
512      break;
513    case k_ShiftedRegister:
514      RegShiftedReg = o.RegShiftedReg;
515      break;
516    case k_ShiftedImmediate:
517      RegShiftedImm = o.RegShiftedImm;
518      break;
519    case k_RotateImmediate:
520      RotImm = o.RotImm;
521      break;
522    case k_BitfieldDescriptor:
523      Bitfield = o.Bitfield;
524      break;
525    case k_VectorIndex:
526      VectorIndex = o.VectorIndex;
527      break;
528    }
529  }
530
531  /// getStartLoc - Get the location of the first token of this operand.
532  SMLoc getStartLoc() const { return StartLoc; }
533  /// getEndLoc - Get the location of the last token of this operand.
534  SMLoc getEndLoc() const { return EndLoc; }
535  /// getLocRange - Get the range between the first and last token of this
536  /// operand.
537  SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
538
539  ARMCC::CondCodes getCondCode() const {
540    assert(Kind == k_CondCode && "Invalid access!");
541    return CC.Val;
542  }
543
544  unsigned getCoproc() const {
545    assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
546    return Cop.Val;
547  }
548
549  StringRef getToken() const {
550    assert(Kind == k_Token && "Invalid access!");
551    return StringRef(Tok.Data, Tok.Length);
552  }
553
554  unsigned getReg() const {
555    assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
556    return Reg.RegNum;
557  }
558
559  const SmallVectorImpl<unsigned> &getRegList() const {
560    assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
561            Kind == k_SPRRegisterList) && "Invalid access!");
562    return Registers;
563  }
564
565  const MCExpr *getImm() const {
566    assert(isImm() && "Invalid access!");
567    return Imm.Val;
568  }
569
570  unsigned getVectorIndex() const {
571    assert(Kind == k_VectorIndex && "Invalid access!");
572    return VectorIndex.Val;
573  }
574
575  ARM_MB::MemBOpt getMemBarrierOpt() const {
576    assert(Kind == k_MemBarrierOpt && "Invalid access!");
577    return MBOpt.Val;
578  }
579
580  ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const {
581    assert(Kind == k_InstSyncBarrierOpt && "Invalid access!");
582    return ISBOpt.Val;
583  }
584
585  ARM_PROC::IFlags getProcIFlags() const {
586    assert(Kind == k_ProcIFlags && "Invalid access!");
587    return IFlags.Val;
588  }
589
590  unsigned getMSRMask() const {
591    assert(Kind == k_MSRMask && "Invalid access!");
592    return MMask.Val;
593  }
594
595  bool isCoprocNum() const { return Kind == k_CoprocNum; }
596  bool isCoprocReg() const { return Kind == k_CoprocReg; }
597  bool isCoprocOption() const { return Kind == k_CoprocOption; }
598  bool isCondCode() const { return Kind == k_CondCode; }
599  bool isCCOut() const { return Kind == k_CCOut; }
600  bool isITMask() const { return Kind == k_ITCondMask; }
601  bool isITCondCode() const { return Kind == k_CondCode; }
602  bool isImm() const { return Kind == k_Immediate; }
603  // checks whether this operand is an unsigned offset which fits is a field
604  // of specified width and scaled by a specific number of bits
605  template<unsigned width, unsigned scale>
606  bool isUnsignedOffset() const {
607    if (!isImm()) return false;
608    if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
609    if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
610      int64_t Val = CE->getValue();
611      int64_t Align = 1LL << scale;
612      int64_t Max = Align * ((1LL << width) - 1);
613      return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max);
614    }
615    return false;
616  }
617  // checks whether this operand is an signed offset which fits is a field
618  // of specified width and scaled by a specific number of bits
619  template<unsigned width, unsigned scale>
620  bool isSignedOffset() const {
621    if (!isImm()) return false;
622    if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
623    if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
624      int64_t Val = CE->getValue();
625      int64_t Align = 1LL << scale;
626      int64_t Max = Align * ((1LL << (width-1)) - 1);
627      int64_t Min = -Align * (1LL << (width-1));
628      return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max);
629    }
630    return false;
631  }
632
633  // checks whether this operand is a memory operand computed as an offset
634  // applied to PC. the offset may have 8 bits of magnitude and is represented
635  // with two bits of shift. textually it may be either [pc, #imm], #imm or
636  // relocable expression...
637  bool isThumbMemPC() const {
638    int64_t Val = 0;
639    if (isImm()) {
640      if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
641      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val);
642      if (!CE) return false;
643      Val = CE->getValue();
644    }
645    else if (isMem()) {
646      if(!Memory.OffsetImm || Memory.OffsetRegNum) return false;
647      if(Memory.BaseRegNum != ARM::PC) return false;
648      Val = Memory.OffsetImm->getValue();
649    }
650    else return false;
651    return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020);
652  }
653  bool isFPImm() const {
654    if (!isImm()) return false;
655    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
656    if (!CE) return false;
657    int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
658    return Val != -1;
659  }
660  bool isFBits16() const {
661    if (!isImm()) return false;
662    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
663    if (!CE) return false;
664    int64_t Value = CE->getValue();
665    return Value >= 0 && Value <= 16;
666  }
667  bool isFBits32() const {
668    if (!isImm()) return false;
669    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
670    if (!CE) return false;
671    int64_t Value = CE->getValue();
672    return Value >= 1 && Value <= 32;
673  }
674  bool isImm8s4() const {
675    if (!isImm()) return false;
676    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
677    if (!CE) return false;
678    int64_t Value = CE->getValue();
679    return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
680  }
681  bool isImm0_4() const {
682    if (!isImm()) return false;
683    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
684    if (!CE) return false;
685    int64_t Value = CE->getValue();
686    return Value >= 0 && Value < 5;
687  }
688  bool isImm0_1020s4() const {
689    if (!isImm()) return false;
690    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
691    if (!CE) return false;
692    int64_t Value = CE->getValue();
693    return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
694  }
695  bool isImm0_508s4() const {
696    if (!isImm()) return false;
697    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
698    if (!CE) return false;
699    int64_t Value = CE->getValue();
700    return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
701  }
702  bool isImm0_508s4Neg() const {
703    if (!isImm()) return false;
704    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
705    if (!CE) return false;
706    int64_t Value = -CE->getValue();
707    // explicitly exclude zero. we want that to use the normal 0_508 version.
708    return ((Value & 3) == 0) && Value > 0 && Value <= 508;
709  }
710  bool isImm0_255() const {
711    if (!isImm()) return false;
712    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
713    if (!CE) return false;
714    int64_t Value = CE->getValue();
715    return Value >= 0 && Value < 256;
716  }
717  bool isImm0_4095() const {
718    if (!isImm()) return false;
719    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
720    if (!CE) return false;
721    int64_t Value = CE->getValue();
722    return Value >= 0 && Value < 4096;
723  }
724  bool isImm0_4095Neg() const {
725    if (!isImm()) return false;
726    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
727    if (!CE) return false;
728    int64_t Value = -CE->getValue();
729    return Value > 0 && Value < 4096;
730  }
731  bool isImm0_1() const {
732    if (!isImm()) return false;
733    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
734    if (!CE) return false;
735    int64_t Value = CE->getValue();
736    return Value >= 0 && Value < 2;
737  }
738  bool isImm0_3() const {
739    if (!isImm()) return false;
740    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
741    if (!CE) return false;
742    int64_t Value = CE->getValue();
743    return Value >= 0 && Value < 4;
744  }
745  bool isImm0_7() const {
746    if (!isImm()) return false;
747    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
748    if (!CE) return false;
749    int64_t Value = CE->getValue();
750    return Value >= 0 && Value < 8;
751  }
752  bool isImm0_15() const {
753    if (!isImm()) return false;
754    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
755    if (!CE) return false;
756    int64_t Value = CE->getValue();
757    return Value >= 0 && Value < 16;
758  }
759  bool isImm0_31() const {
760    if (!isImm()) return false;
761    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
762    if (!CE) return false;
763    int64_t Value = CE->getValue();
764    return Value >= 0 && Value < 32;
765  }
766  bool isImm0_63() const {
767    if (!isImm()) return false;
768    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
769    if (!CE) return false;
770    int64_t Value = CE->getValue();
771    return Value >= 0 && Value < 64;
772  }
773  bool isImm8() const {
774    if (!isImm()) return false;
775    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
776    if (!CE) return false;
777    int64_t Value = CE->getValue();
778    return Value == 8;
779  }
780  bool isImm16() const {
781    if (!isImm()) return false;
782    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
783    if (!CE) return false;
784    int64_t Value = CE->getValue();
785    return Value == 16;
786  }
787  bool isImm32() const {
788    if (!isImm()) return false;
789    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
790    if (!CE) return false;
791    int64_t Value = CE->getValue();
792    return Value == 32;
793  }
794  bool isShrImm8() const {
795    if (!isImm()) return false;
796    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
797    if (!CE) return false;
798    int64_t Value = CE->getValue();
799    return Value > 0 && Value <= 8;
800  }
801  bool isShrImm16() const {
802    if (!isImm()) return false;
803    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
804    if (!CE) return false;
805    int64_t Value = CE->getValue();
806    return Value > 0 && Value <= 16;
807  }
808  bool isShrImm32() const {
809    if (!isImm()) return false;
810    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
811    if (!CE) return false;
812    int64_t Value = CE->getValue();
813    return Value > 0 && Value <= 32;
814  }
815  bool isShrImm64() const {
816    if (!isImm()) return false;
817    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
818    if (!CE) return false;
819    int64_t Value = CE->getValue();
820    return Value > 0 && Value <= 64;
821  }
822  bool isImm1_7() const {
823    if (!isImm()) return false;
824    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
825    if (!CE) return false;
826    int64_t Value = CE->getValue();
827    return Value > 0 && Value < 8;
828  }
829  bool isImm1_15() const {
830    if (!isImm()) return false;
831    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
832    if (!CE) return false;
833    int64_t Value = CE->getValue();
834    return Value > 0 && Value < 16;
835  }
836  bool isImm1_31() const {
837    if (!isImm()) return false;
838    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
839    if (!CE) return false;
840    int64_t Value = CE->getValue();
841    return Value > 0 && Value < 32;
842  }
843  bool isImm1_16() const {
844    if (!isImm()) return false;
845    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
846    if (!CE) return false;
847    int64_t Value = CE->getValue();
848    return Value > 0 && Value < 17;
849  }
850  bool isImm1_32() const {
851    if (!isImm()) return false;
852    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
853    if (!CE) return false;
854    int64_t Value = CE->getValue();
855    return Value > 0 && Value < 33;
856  }
857  bool isImm0_32() const {
858    if (!isImm()) return false;
859    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
860    if (!CE) return false;
861    int64_t Value = CE->getValue();
862    return Value >= 0 && Value < 33;
863  }
864  bool isImm0_65535() const {
865    if (!isImm()) return false;
866    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
867    if (!CE) return false;
868    int64_t Value = CE->getValue();
869    return Value >= 0 && Value < 65536;
870  }
871  bool isImm256_65535Expr() const {
872    if (!isImm()) return false;
873    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
874    // If it's not a constant expression, it'll generate a fixup and be
875    // handled later.
876    if (!CE) return true;
877    int64_t Value = CE->getValue();
878    return Value >= 256 && Value < 65536;
879  }
880  bool isImm0_65535Expr() const {
881    if (!isImm()) return false;
882    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
883    // If it's not a constant expression, it'll generate a fixup and be
884    // handled later.
885    if (!CE) return true;
886    int64_t Value = CE->getValue();
887    return Value >= 0 && Value < 65536;
888  }
889  bool isImm24bit() const {
890    if (!isImm()) return false;
891    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
892    if (!CE) return false;
893    int64_t Value = CE->getValue();
894    return Value >= 0 && Value <= 0xffffff;
895  }
896  bool isImmThumbSR() const {
897    if (!isImm()) return false;
898    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
899    if (!CE) return false;
900    int64_t Value = CE->getValue();
901    return Value > 0 && Value < 33;
902  }
903  bool isPKHLSLImm() const {
904    if (!isImm()) return false;
905    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
906    if (!CE) return false;
907    int64_t Value = CE->getValue();
908    return Value >= 0 && Value < 32;
909  }
910  bool isPKHASRImm() const {
911    if (!isImm()) return false;
912    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
913    if (!CE) return false;
914    int64_t Value = CE->getValue();
915    return Value > 0 && Value <= 32;
916  }
917  bool isAdrLabel() const {
918    // If we have an immediate that's not a constant, treat it as a label
919    // reference needing a fixup. If it is a constant, but it can't fit
920    // into shift immediate encoding, we reject it.
921    if (isImm() && !isa<MCConstantExpr>(getImm())) return true;
922    else return (isARMSOImm() || isARMSOImmNeg());
923  }
924  bool isARMSOImm() const {
925    if (!isImm()) return false;
926    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
927    if (!CE) return false;
928    int64_t Value = CE->getValue();
929    return ARM_AM::getSOImmVal(Value) != -1;
930  }
931  bool isARMSOImmNot() const {
932    if (!isImm()) return false;
933    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
934    if (!CE) return false;
935    int64_t Value = CE->getValue();
936    return ARM_AM::getSOImmVal(~Value) != -1;
937  }
938  bool isARMSOImmNeg() const {
939    if (!isImm()) return false;
940    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
941    if (!CE) return false;
942    int64_t Value = CE->getValue();
943    // Only use this when not representable as a plain so_imm.
944    return ARM_AM::getSOImmVal(Value) == -1 &&
945      ARM_AM::getSOImmVal(-Value) != -1;
946  }
947  bool isT2SOImm() const {
948    if (!isImm()) return false;
949    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
950    if (!CE) return false;
951    int64_t Value = CE->getValue();
952    return ARM_AM::getT2SOImmVal(Value) != -1;
953  }
954  bool isT2SOImmNot() const {
955    if (!isImm()) return false;
956    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
957    if (!CE) return false;
958    int64_t Value = CE->getValue();
959    return ARM_AM::getT2SOImmVal(Value) == -1 &&
960      ARM_AM::getT2SOImmVal(~Value) != -1;
961  }
962  bool isT2SOImmNeg() const {
963    if (!isImm()) return false;
964    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
965    if (!CE) return false;
966    int64_t Value = CE->getValue();
967    // Only use this when not representable as a plain so_imm.
968    return ARM_AM::getT2SOImmVal(Value) == -1 &&
969      ARM_AM::getT2SOImmVal(-Value) != -1;
970  }
971  bool isSetEndImm() const {
972    if (!isImm()) return false;
973    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
974    if (!CE) return false;
975    int64_t Value = CE->getValue();
976    return Value == 1 || Value == 0;
977  }
978  bool isReg() const { return Kind == k_Register; }
979  bool isRegList() const { return Kind == k_RegisterList; }
980  bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
981  bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
982  bool isToken() const { return Kind == k_Token; }
983  bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
984  bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
985  bool isMem() const { return Kind == k_Memory; }
986  bool isShifterImm() const { return Kind == k_ShifterImmediate; }
987  bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
988  bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
989  bool isRotImm() const { return Kind == k_RotateImmediate; }
990  bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
991  bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
992  bool isPostIdxReg() const {
993    return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
994  }
995  bool isMemNoOffset(bool alignOK = false) const {
996    if (!isMem())
997      return false;
998    // No offset of any kind.
999    return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 &&
1000     (alignOK || Memory.Alignment == 0);
1001  }
1002  bool isMemPCRelImm12() const {
1003    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1004      return false;
1005    // Base register must be PC.
1006    if (Memory.BaseRegNum != ARM::PC)
1007      return false;
1008    // Immediate offset in range [-4095, 4095].
1009    if (!Memory.OffsetImm) return true;
1010    int64_t Val = Memory.OffsetImm->getValue();
1011    return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1012  }
1013  bool isAlignedMemory() const {
1014    return isMemNoOffset(true);
1015  }
1016  bool isAddrMode2() const {
1017    if (!isMem() || Memory.Alignment != 0) return false;
1018    // Check for register offset.
1019    if (Memory.OffsetRegNum) return true;
1020    // Immediate offset in range [-4095, 4095].
1021    if (!Memory.OffsetImm) return true;
1022    int64_t Val = Memory.OffsetImm->getValue();
1023    return Val > -4096 && Val < 4096;
1024  }
1025  bool isAM2OffsetImm() const {
1026    if (!isImm()) return false;
1027    // Immediate offset in range [-4095, 4095].
1028    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1029    if (!CE) return false;
1030    int64_t Val = CE->getValue();
1031    return (Val == INT32_MIN) || (Val > -4096 && Val < 4096);
1032  }
1033  bool isAddrMode3() const {
1034    // If we have an immediate that's not a constant, treat it as a label
1035    // reference needing a fixup. If it is a constant, it's something else
1036    // and we reject it.
1037    if (isImm() && !isa<MCConstantExpr>(getImm()))
1038      return true;
1039    if (!isMem() || Memory.Alignment != 0) return false;
1040    // No shifts are legal for AM3.
1041    if (Memory.ShiftType != ARM_AM::no_shift) return false;
1042    // Check for register offset.
1043    if (Memory.OffsetRegNum) return true;
1044    // Immediate offset in range [-255, 255].
1045    if (!Memory.OffsetImm) return true;
1046    int64_t Val = Memory.OffsetImm->getValue();
1047    // The #-0 offset is encoded as INT32_MIN, and we have to check
1048    // for this too.
1049    return (Val > -256 && Val < 256) || Val == INT32_MIN;
1050  }
1051  bool isAM3Offset() const {
1052    if (Kind != k_Immediate && Kind != k_PostIndexRegister)
1053      return false;
1054    if (Kind == k_PostIndexRegister)
1055      return PostIdxReg.ShiftTy == ARM_AM::no_shift;
1056    // Immediate offset in range [-255, 255].
1057    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1058    if (!CE) return false;
1059    int64_t Val = CE->getValue();
1060    // Special case, #-0 is INT32_MIN.
1061    return (Val > -256 && Val < 256) || Val == INT32_MIN;
1062  }
1063  bool isAddrMode5() const {
1064    // If we have an immediate that's not a constant, treat it as a label
1065    // reference needing a fixup. If it is a constant, it's something else
1066    // and we reject it.
1067    if (isImm() && !isa<MCConstantExpr>(getImm()))
1068      return true;
1069    if (!isMem() || Memory.Alignment != 0) return false;
1070    // Check for register offset.
1071    if (Memory.OffsetRegNum) return false;
1072    // Immediate offset in range [-1020, 1020] and a multiple of 4.
1073    if (!Memory.OffsetImm) return true;
1074    int64_t Val = Memory.OffsetImm->getValue();
1075    return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
1076      Val == INT32_MIN;
1077  }
1078  bool isMemTBB() const {
1079    if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1080        Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1081      return false;
1082    return true;
1083  }
1084  bool isMemTBH() const {
1085    if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1086        Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1087        Memory.Alignment != 0 )
1088      return false;
1089    return true;
1090  }
1091  bool isMemRegOffset() const {
1092    if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
1093      return false;
1094    return true;
1095  }
1096  bool isT2MemRegOffset() const {
1097    if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1098        Memory.Alignment != 0)
1099      return false;
1100    // Only lsl #{0, 1, 2, 3} allowed.
1101    if (Memory.ShiftType == ARM_AM::no_shift)
1102      return true;
1103    if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1104      return false;
1105    return true;
1106  }
1107  bool isMemThumbRR() const {
1108    // Thumb reg+reg addressing is simple. Just two registers, a base and
1109    // an offset. No shifts, negations or any other complicating factors.
1110    if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1111        Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1112      return false;
1113    return isARMLowRegister(Memory.BaseRegNum) &&
1114      (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
1115  }
1116  bool isMemThumbRIs4() const {
1117    if (!isMem() || Memory.OffsetRegNum != 0 ||
1118        !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1119      return false;
1120    // Immediate offset, multiple of 4 in range [0, 124].
1121    if (!Memory.OffsetImm) return true;
1122    int64_t Val = Memory.OffsetImm->getValue();
1123    return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1124  }
1125  bool isMemThumbRIs2() const {
1126    if (!isMem() || Memory.OffsetRegNum != 0 ||
1127        !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1128      return false;
1129    // Immediate offset, multiple of 4 in range [0, 62].
1130    if (!Memory.OffsetImm) return true;
1131    int64_t Val = Memory.OffsetImm->getValue();
1132    return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1133  }
1134  bool isMemThumbRIs1() const {
1135    if (!isMem() || Memory.OffsetRegNum != 0 ||
1136        !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1137      return false;
1138    // Immediate offset in range [0, 31].
1139    if (!Memory.OffsetImm) return true;
1140    int64_t Val = Memory.OffsetImm->getValue();
1141    return Val >= 0 && Val <= 31;
1142  }
1143  bool isMemThumbSPI() const {
1144    if (!isMem() || Memory.OffsetRegNum != 0 ||
1145        Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1146      return false;
1147    // Immediate offset, multiple of 4 in range [0, 1020].
1148    if (!Memory.OffsetImm) return true;
1149    int64_t Val = Memory.OffsetImm->getValue();
1150    return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1151  }
1152  bool isMemImm8s4Offset() const {
1153    // If we have an immediate that's not a constant, treat it as a label
1154    // reference needing a fixup. If it is a constant, it's something else
1155    // and we reject it.
1156    if (isImm() && !isa<MCConstantExpr>(getImm()))
1157      return true;
1158    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1159      return false;
1160    // Immediate offset a multiple of 4 in range [-1020, 1020].
1161    if (!Memory.OffsetImm) return true;
1162    int64_t Val = Memory.OffsetImm->getValue();
1163    // Special case, #-0 is INT32_MIN.
1164    return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN;
1165  }
1166  bool isMemImm0_1020s4Offset() const {
1167    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1168      return false;
1169    // Immediate offset a multiple of 4 in range [0, 1020].
1170    if (!Memory.OffsetImm) return true;
1171    int64_t Val = Memory.OffsetImm->getValue();
1172    return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1173  }
1174  bool isMemImm8Offset() const {
1175    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1176      return false;
1177    // Base reg of PC isn't allowed for these encodings.
1178    if (Memory.BaseRegNum == ARM::PC) return false;
1179    // Immediate offset in range [-255, 255].
1180    if (!Memory.OffsetImm) return true;
1181    int64_t Val = Memory.OffsetImm->getValue();
1182    return (Val == INT32_MIN) || (Val > -256 && Val < 256);
1183  }
1184  bool isMemPosImm8Offset() const {
1185    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1186      return false;
1187    // Immediate offset in range [0, 255].
1188    if (!Memory.OffsetImm) return true;
1189    int64_t Val = Memory.OffsetImm->getValue();
1190    return Val >= 0 && Val < 256;
1191  }
1192  bool isMemNegImm8Offset() const {
1193    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1194      return false;
1195    // Base reg of PC isn't allowed for these encodings.
1196    if (Memory.BaseRegNum == ARM::PC) return false;
1197    // Immediate offset in range [-255, -1].
1198    if (!Memory.OffsetImm) return false;
1199    int64_t Val = Memory.OffsetImm->getValue();
1200    return (Val == INT32_MIN) || (Val > -256 && Val < 0);
1201  }
1202  bool isMemUImm12Offset() const {
1203    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1204      return false;
1205    // Immediate offset in range [0, 4095].
1206    if (!Memory.OffsetImm) return true;
1207    int64_t Val = Memory.OffsetImm->getValue();
1208    return (Val >= 0 && Val < 4096);
1209  }
1210  bool isMemImm12Offset() const {
1211    // If we have an immediate that's not a constant, treat it as a label
1212    // reference needing a fixup. If it is a constant, it's something else
1213    // and we reject it.
1214    if (isImm() && !isa<MCConstantExpr>(getImm()))
1215      return true;
1216
1217    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1218      return false;
1219    // Immediate offset in range [-4095, 4095].
1220    if (!Memory.OffsetImm) return true;
1221    int64_t Val = Memory.OffsetImm->getValue();
1222    return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1223  }
1224  bool isPostIdxImm8() const {
1225    if (!isImm()) return false;
1226    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1227    if (!CE) return false;
1228    int64_t Val = CE->getValue();
1229    return (Val > -256 && Val < 256) || (Val == INT32_MIN);
1230  }
1231  bool isPostIdxImm8s4() const {
1232    if (!isImm()) return false;
1233    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1234    if (!CE) return false;
1235    int64_t Val = CE->getValue();
1236    return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1237      (Val == INT32_MIN);
1238  }
1239
1240  bool isMSRMask() const { return Kind == k_MSRMask; }
1241  bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1242
1243  // NEON operands.
1244  bool isSingleSpacedVectorList() const {
1245    return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1246  }
1247  bool isDoubleSpacedVectorList() const {
1248    return Kind == k_VectorList && VectorList.isDoubleSpaced;
1249  }
1250  bool isVecListOneD() const {
1251    if (!isSingleSpacedVectorList()) return false;
1252    return VectorList.Count == 1;
1253  }
1254
1255  bool isVecListDPair() const {
1256    if (!isSingleSpacedVectorList()) return false;
1257    return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1258              .contains(VectorList.RegNum));
1259  }
1260
1261  bool isVecListThreeD() const {
1262    if (!isSingleSpacedVectorList()) return false;
1263    return VectorList.Count == 3;
1264  }
1265
1266  bool isVecListFourD() const {
1267    if (!isSingleSpacedVectorList()) return false;
1268    return VectorList.Count == 4;
1269  }
1270
1271  bool isVecListDPairSpaced() const {
1272    if (isSingleSpacedVectorList()) return false;
1273    return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1274              .contains(VectorList.RegNum));
1275  }
1276
1277  bool isVecListThreeQ() const {
1278    if (!isDoubleSpacedVectorList()) return false;
1279    return VectorList.Count == 3;
1280  }
1281
1282  bool isVecListFourQ() const {
1283    if (!isDoubleSpacedVectorList()) return false;
1284    return VectorList.Count == 4;
1285  }
1286
1287  bool isSingleSpacedVectorAllLanes() const {
1288    return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1289  }
1290  bool isDoubleSpacedVectorAllLanes() const {
1291    return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1292  }
1293  bool isVecListOneDAllLanes() const {
1294    if (!isSingleSpacedVectorAllLanes()) return false;
1295    return VectorList.Count == 1;
1296  }
1297
1298  bool isVecListDPairAllLanes() const {
1299    if (!isSingleSpacedVectorAllLanes()) return false;
1300    return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1301              .contains(VectorList.RegNum));
1302  }
1303
1304  bool isVecListDPairSpacedAllLanes() const {
1305    if (!isDoubleSpacedVectorAllLanes()) return false;
1306    return VectorList.Count == 2;
1307  }
1308
1309  bool isVecListThreeDAllLanes() const {
1310    if (!isSingleSpacedVectorAllLanes()) return false;
1311    return VectorList.Count == 3;
1312  }
1313
1314  bool isVecListThreeQAllLanes() const {
1315    if (!isDoubleSpacedVectorAllLanes()) return false;
1316    return VectorList.Count == 3;
1317  }
1318
1319  bool isVecListFourDAllLanes() const {
1320    if (!isSingleSpacedVectorAllLanes()) return false;
1321    return VectorList.Count == 4;
1322  }
1323
1324  bool isVecListFourQAllLanes() const {
1325    if (!isDoubleSpacedVectorAllLanes()) return false;
1326    return VectorList.Count == 4;
1327  }
1328
1329  bool isSingleSpacedVectorIndexed() const {
1330    return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1331  }
1332  bool isDoubleSpacedVectorIndexed() const {
1333    return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1334  }
1335  bool isVecListOneDByteIndexed() const {
1336    if (!isSingleSpacedVectorIndexed()) return false;
1337    return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1338  }
1339
1340  bool isVecListOneDHWordIndexed() const {
1341    if (!isSingleSpacedVectorIndexed()) return false;
1342    return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1343  }
1344
1345  bool isVecListOneDWordIndexed() const {
1346    if (!isSingleSpacedVectorIndexed()) return false;
1347    return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1348  }
1349
1350  bool isVecListTwoDByteIndexed() const {
1351    if (!isSingleSpacedVectorIndexed()) return false;
1352    return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1353  }
1354
1355  bool isVecListTwoDHWordIndexed() const {
1356    if (!isSingleSpacedVectorIndexed()) return false;
1357    return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1358  }
1359
1360  bool isVecListTwoQWordIndexed() const {
1361    if (!isDoubleSpacedVectorIndexed()) return false;
1362    return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1363  }
1364
1365  bool isVecListTwoQHWordIndexed() const {
1366    if (!isDoubleSpacedVectorIndexed()) return false;
1367    return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1368  }
1369
1370  bool isVecListTwoDWordIndexed() const {
1371    if (!isSingleSpacedVectorIndexed()) return false;
1372    return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1373  }
1374
1375  bool isVecListThreeDByteIndexed() const {
1376    if (!isSingleSpacedVectorIndexed()) return false;
1377    return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
1378  }
1379
1380  bool isVecListThreeDHWordIndexed() const {
1381    if (!isSingleSpacedVectorIndexed()) return false;
1382    return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1383  }
1384
1385  bool isVecListThreeQWordIndexed() const {
1386    if (!isDoubleSpacedVectorIndexed()) return false;
1387    return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1388  }
1389
1390  bool isVecListThreeQHWordIndexed() const {
1391    if (!isDoubleSpacedVectorIndexed()) return false;
1392    return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1393  }
1394
1395  bool isVecListThreeDWordIndexed() const {
1396    if (!isSingleSpacedVectorIndexed()) return false;
1397    return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1398  }
1399
1400  bool isVecListFourDByteIndexed() const {
1401    if (!isSingleSpacedVectorIndexed()) return false;
1402    return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
1403  }
1404
1405  bool isVecListFourDHWordIndexed() const {
1406    if (!isSingleSpacedVectorIndexed()) return false;
1407    return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1408  }
1409
1410  bool isVecListFourQWordIndexed() const {
1411    if (!isDoubleSpacedVectorIndexed()) return false;
1412    return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1413  }
1414
1415  bool isVecListFourQHWordIndexed() const {
1416    if (!isDoubleSpacedVectorIndexed()) return false;
1417    return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1418  }
1419
1420  bool isVecListFourDWordIndexed() const {
1421    if (!isSingleSpacedVectorIndexed()) return false;
1422    return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1423  }
1424
1425  bool isVectorIndex8() const {
1426    if (Kind != k_VectorIndex) return false;
1427    return VectorIndex.Val < 8;
1428  }
1429  bool isVectorIndex16() const {
1430    if (Kind != k_VectorIndex) return false;
1431    return VectorIndex.Val < 4;
1432  }
1433  bool isVectorIndex32() const {
1434    if (Kind != k_VectorIndex) return false;
1435    return VectorIndex.Val < 2;
1436  }
1437
1438  bool isNEONi8splat() const {
1439    if (!isImm()) return false;
1440    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1441    // Must be a constant.
1442    if (!CE) return false;
1443    int64_t Value = CE->getValue();
1444    // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1445    // value.
1446    return Value >= 0 && Value < 256;
1447  }
1448
1449  bool isNEONi16splat() const {
1450    if (!isImm()) return false;
1451    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1452    // Must be a constant.
1453    if (!CE) return false;
1454    int64_t Value = CE->getValue();
1455    // i16 value in the range [0,255] or [0x0100, 0xff00]
1456    return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00);
1457  }
1458
1459  bool isNEONi32splat() const {
1460    if (!isImm()) return false;
1461    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1462    // Must be a constant.
1463    if (!CE) return false;
1464    int64_t Value = CE->getValue();
1465    // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
1466    return (Value >= 0 && Value < 256) ||
1467      (Value >= 0x0100 && Value <= 0xff00) ||
1468      (Value >= 0x010000 && Value <= 0xff0000) ||
1469      (Value >= 0x01000000 && Value <= 0xff000000);
1470  }
1471
1472  bool isNEONi32vmov() const {
1473    if (!isImm()) return false;
1474    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1475    // Must be a constant.
1476    if (!CE) return false;
1477    int64_t Value = CE->getValue();
1478    // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1479    // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1480    return (Value >= 0 && Value < 256) ||
1481      (Value >= 0x0100 && Value <= 0xff00) ||
1482      (Value >= 0x010000 && Value <= 0xff0000) ||
1483      (Value >= 0x01000000 && Value <= 0xff000000) ||
1484      (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1485      (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1486  }
1487  bool isNEONi32vmovNeg() const {
1488    if (!isImm()) return false;
1489    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1490    // Must be a constant.
1491    if (!CE) return false;
1492    int64_t Value = ~CE->getValue();
1493    // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1494    // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1495    return (Value >= 0 && Value < 256) ||
1496      (Value >= 0x0100 && Value <= 0xff00) ||
1497      (Value >= 0x010000 && Value <= 0xff0000) ||
1498      (Value >= 0x01000000 && Value <= 0xff000000) ||
1499      (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1500      (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1501  }
1502
1503  bool isNEONi64splat() const {
1504    if (!isImm()) return false;
1505    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1506    // Must be a constant.
1507    if (!CE) return false;
1508    uint64_t Value = CE->getValue();
1509    // i64 value with each byte being either 0 or 0xff.
1510    for (unsigned i = 0; i < 8; ++i)
1511      if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1512    return true;
1513  }
1514
1515  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1516    // Add as immediates when possible.  Null MCExpr = 0.
1517    if (Expr == 0)
1518      Inst.addOperand(MCOperand::CreateImm(0));
1519    else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1520      Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1521    else
1522      Inst.addOperand(MCOperand::CreateExpr(Expr));
1523  }
1524
1525  void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1526    assert(N == 2 && "Invalid number of operands!");
1527    Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1528    unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1529    Inst.addOperand(MCOperand::CreateReg(RegNum));
1530  }
1531
1532  void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1533    assert(N == 1 && "Invalid number of operands!");
1534    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1535  }
1536
1537  void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1538    assert(N == 1 && "Invalid number of operands!");
1539    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1540  }
1541
1542  void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1543    assert(N == 1 && "Invalid number of operands!");
1544    Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1545  }
1546
1547  void addITMaskOperands(MCInst &Inst, unsigned N) const {
1548    assert(N == 1 && "Invalid number of operands!");
1549    Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1550  }
1551
1552  void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1553    assert(N == 1 && "Invalid number of operands!");
1554    Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1555  }
1556
1557  void addCCOutOperands(MCInst &Inst, unsigned N) const {
1558    assert(N == 1 && "Invalid number of operands!");
1559    Inst.addOperand(MCOperand::CreateReg(getReg()));
1560  }
1561
1562  void addRegOperands(MCInst &Inst, unsigned N) const {
1563    assert(N == 1 && "Invalid number of operands!");
1564    Inst.addOperand(MCOperand::CreateReg(getReg()));
1565  }
1566
1567  void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1568    assert(N == 3 && "Invalid number of operands!");
1569    assert(isRegShiftedReg() &&
1570           "addRegShiftedRegOperands() on non RegShiftedReg!");
1571    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1572    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1573    Inst.addOperand(MCOperand::CreateImm(
1574      ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1575  }
1576
1577  void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1578    assert(N == 2 && "Invalid number of operands!");
1579    assert(isRegShiftedImm() &&
1580           "addRegShiftedImmOperands() on non RegShiftedImm!");
1581    Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1582    // Shift of #32 is encoded as 0 where permitted
1583    unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
1584    Inst.addOperand(MCOperand::CreateImm(
1585      ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
1586  }
1587
1588  void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1589    assert(N == 1 && "Invalid number of operands!");
1590    Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1591                                         ShifterImm.Imm));
1592  }
1593
1594  void addRegListOperands(MCInst &Inst, unsigned N) const {
1595    assert(N == 1 && "Invalid number of operands!");
1596    const SmallVectorImpl<unsigned> &RegList = getRegList();
1597    for (SmallVectorImpl<unsigned>::const_iterator
1598           I = RegList.begin(), E = RegList.end(); I != E; ++I)
1599      Inst.addOperand(MCOperand::CreateReg(*I));
1600  }
1601
1602  void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1603    addRegListOperands(Inst, N);
1604  }
1605
1606  void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1607    addRegListOperands(Inst, N);
1608  }
1609
1610  void addRotImmOperands(MCInst &Inst, unsigned N) const {
1611    assert(N == 1 && "Invalid number of operands!");
1612    // Encoded as val>>3. The printer handles display as 8, 16, 24.
1613    Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1614  }
1615
1616  void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1617    assert(N == 1 && "Invalid number of operands!");
1618    // Munge the lsb/width into a bitfield mask.
1619    unsigned lsb = Bitfield.LSB;
1620    unsigned width = Bitfield.Width;
1621    // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1622    uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1623                      (32 - (lsb + width)));
1624    Inst.addOperand(MCOperand::CreateImm(Mask));
1625  }
1626
1627  void addImmOperands(MCInst &Inst, unsigned N) const {
1628    assert(N == 1 && "Invalid number of operands!");
1629    addExpr(Inst, getImm());
1630  }
1631
1632  void addFBits16Operands(MCInst &Inst, unsigned N) const {
1633    assert(N == 1 && "Invalid number of operands!");
1634    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1635    Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue()));
1636  }
1637
1638  void addFBits32Operands(MCInst &Inst, unsigned N) const {
1639    assert(N == 1 && "Invalid number of operands!");
1640    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1641    Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue()));
1642  }
1643
1644  void addFPImmOperands(MCInst &Inst, unsigned N) const {
1645    assert(N == 1 && "Invalid number of operands!");
1646    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1647    int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1648    Inst.addOperand(MCOperand::CreateImm(Val));
1649  }
1650
1651  void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1652    assert(N == 1 && "Invalid number of operands!");
1653    // FIXME: We really want to scale the value here, but the LDRD/STRD
1654    // instruction don't encode operands that way yet.
1655    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1656    Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1657  }
1658
1659  void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1660    assert(N == 1 && "Invalid number of operands!");
1661    // The immediate is scaled by four in the encoding and is stored
1662    // in the MCInst as such. Lop off the low two bits here.
1663    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1664    Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1665  }
1666
1667  void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
1668    assert(N == 1 && "Invalid number of operands!");
1669    // The immediate is scaled by four in the encoding and is stored
1670    // in the MCInst as such. Lop off the low two bits here.
1671    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1672    Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4)));
1673  }
1674
1675  void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1676    assert(N == 1 && "Invalid number of operands!");
1677    // The immediate is scaled by four in the encoding and is stored
1678    // in the MCInst as such. Lop off the low two bits here.
1679    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1680    Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1681  }
1682
1683  void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1684    assert(N == 1 && "Invalid number of operands!");
1685    // The constant encodes as the immediate-1, and we store in the instruction
1686    // the bits as encoded, so subtract off one here.
1687    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1688    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1689  }
1690
1691  void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1692    assert(N == 1 && "Invalid number of operands!");
1693    // The constant encodes as the immediate-1, and we store in the instruction
1694    // the bits as encoded, so subtract off one here.
1695    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1696    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1697  }
1698
1699  void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1700    assert(N == 1 && "Invalid number of operands!");
1701    // The constant encodes as the immediate, except for 32, which encodes as
1702    // zero.
1703    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1704    unsigned Imm = CE->getValue();
1705    Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1706  }
1707
1708  void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1709    assert(N == 1 && "Invalid number of operands!");
1710    // An ASR value of 32 encodes as 0, so that's how we want to add it to
1711    // the instruction as well.
1712    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1713    int Val = CE->getValue();
1714    Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1715  }
1716
1717  void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1718    assert(N == 1 && "Invalid number of operands!");
1719    // The operand is actually a t2_so_imm, but we have its bitwise
1720    // negation in the assembly source, so twiddle it here.
1721    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1722    Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1723  }
1724
1725  void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
1726    assert(N == 1 && "Invalid number of operands!");
1727    // The operand is actually a t2_so_imm, but we have its
1728    // negation in the assembly source, so twiddle it here.
1729    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1730    Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1731  }
1732
1733  void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
1734    assert(N == 1 && "Invalid number of operands!");
1735    // The operand is actually an imm0_4095, but we have its
1736    // negation in the assembly source, so twiddle it here.
1737    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1738    Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1739  }
1740
1741  void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
1742    if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
1743      Inst.addOperand(MCOperand::CreateImm(CE->getValue() >> 2));
1744      return;
1745    }
1746
1747    const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1748    assert(SR && "Unknown value type!");
1749    Inst.addOperand(MCOperand::CreateExpr(SR));
1750  }
1751
1752  void addThumbMemPCOperands(MCInst &Inst, unsigned N) const {
1753    assert(N == 1 && "Invalid number of operands!");
1754    if (isImm()) {
1755      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1756      if (CE) {
1757        Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1758        return;
1759      }
1760
1761      const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1762      assert(SR && "Unknown value type!");
1763      Inst.addOperand(MCOperand::CreateExpr(SR));
1764      return;
1765    }
1766
1767    assert(isMem()  && "Unknown value type!");
1768    assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!");
1769    Inst.addOperand(MCOperand::CreateImm(Memory.OffsetImm->getValue()));
1770  }
1771
1772  void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
1773    assert(N == 1 && "Invalid number of operands!");
1774    // The operand is actually a so_imm, but we have its bitwise
1775    // negation in the assembly source, so twiddle it here.
1776    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1777    Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1778  }
1779
1780  void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const {
1781    assert(N == 1 && "Invalid number of operands!");
1782    // The operand is actually a so_imm, but we have its
1783    // negation in the assembly source, so twiddle it here.
1784    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1785    Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1786  }
1787
1788  void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1789    assert(N == 1 && "Invalid number of operands!");
1790    Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1791  }
1792
1793  void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
1794    assert(N == 1 && "Invalid number of operands!");
1795    Inst.addOperand(MCOperand::CreateImm(unsigned(getInstSyncBarrierOpt())));
1796  }
1797
1798  void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1799    assert(N == 1 && "Invalid number of operands!");
1800    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1801  }
1802
1803  void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
1804    assert(N == 1 && "Invalid number of operands!");
1805    int32_t Imm = Memory.OffsetImm->getValue();
1806    Inst.addOperand(MCOperand::CreateImm(Imm));
1807  }
1808
1809  void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
1810    assert(N == 1 && "Invalid number of operands!");
1811    assert(isImm() && "Not an immediate!");
1812
1813    // If we have an immediate that's not a constant, treat it as a label
1814    // reference needing a fixup.
1815    if (!isa<MCConstantExpr>(getImm())) {
1816      Inst.addOperand(MCOperand::CreateExpr(getImm()));
1817      return;
1818    }
1819
1820    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1821    int Val = CE->getValue();
1822    Inst.addOperand(MCOperand::CreateImm(Val));
1823  }
1824
1825  void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
1826    assert(N == 2 && "Invalid number of operands!");
1827    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1828    Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
1829  }
1830
1831  void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
1832    assert(N == 3 && "Invalid number of operands!");
1833    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1834    if (!Memory.OffsetRegNum) {
1835      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1836      // Special case for #-0
1837      if (Val == INT32_MIN) Val = 0;
1838      if (Val < 0) Val = -Val;
1839      Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1840    } else {
1841      // For register offset, we encode the shift type and negation flag
1842      // here.
1843      Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1844                              Memory.ShiftImm, Memory.ShiftType);
1845    }
1846    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1847    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1848    Inst.addOperand(MCOperand::CreateImm(Val));
1849  }
1850
1851  void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
1852    assert(N == 2 && "Invalid number of operands!");
1853    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1854    assert(CE && "non-constant AM2OffsetImm operand!");
1855    int32_t Val = CE->getValue();
1856    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1857    // Special case for #-0
1858    if (Val == INT32_MIN) Val = 0;
1859    if (Val < 0) Val = -Val;
1860    Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1861    Inst.addOperand(MCOperand::CreateReg(0));
1862    Inst.addOperand(MCOperand::CreateImm(Val));
1863  }
1864
1865  void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
1866    assert(N == 3 && "Invalid number of operands!");
1867    // If we have an immediate that's not a constant, treat it as a label
1868    // reference needing a fixup. If it is a constant, it's something else
1869    // and we reject it.
1870    if (isImm()) {
1871      Inst.addOperand(MCOperand::CreateExpr(getImm()));
1872      Inst.addOperand(MCOperand::CreateReg(0));
1873      Inst.addOperand(MCOperand::CreateImm(0));
1874      return;
1875    }
1876
1877    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1878    if (!Memory.OffsetRegNum) {
1879      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1880      // Special case for #-0
1881      if (Val == INT32_MIN) Val = 0;
1882      if (Val < 0) Val = -Val;
1883      Val = ARM_AM::getAM3Opc(AddSub, Val);
1884    } else {
1885      // For register offset, we encode the shift type and negation flag
1886      // here.
1887      Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
1888    }
1889    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1890    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1891    Inst.addOperand(MCOperand::CreateImm(Val));
1892  }
1893
1894  void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
1895    assert(N == 2 && "Invalid number of operands!");
1896    if (Kind == k_PostIndexRegister) {
1897      int32_t Val =
1898        ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
1899      Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1900      Inst.addOperand(MCOperand::CreateImm(Val));
1901      return;
1902    }
1903
1904    // Constant offset.
1905    const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
1906    int32_t Val = CE->getValue();
1907    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1908    // Special case for #-0
1909    if (Val == INT32_MIN) Val = 0;
1910    if (Val < 0) Val = -Val;
1911    Val = ARM_AM::getAM3Opc(AddSub, Val);
1912    Inst.addOperand(MCOperand::CreateReg(0));
1913    Inst.addOperand(MCOperand::CreateImm(Val));
1914  }
1915
1916  void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
1917    assert(N == 2 && "Invalid number of operands!");
1918    // If we have an immediate that's not a constant, treat it as a label
1919    // reference needing a fixup. If it is a constant, it's something else
1920    // and we reject it.
1921    if (isImm()) {
1922      Inst.addOperand(MCOperand::CreateExpr(getImm()));
1923      Inst.addOperand(MCOperand::CreateImm(0));
1924      return;
1925    }
1926
1927    // The lower two bits are always zero and as such are not encoded.
1928    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1929    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1930    // Special case for #-0
1931    if (Val == INT32_MIN) Val = 0;
1932    if (Val < 0) Val = -Val;
1933    Val = ARM_AM::getAM5Opc(AddSub, Val);
1934    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1935    Inst.addOperand(MCOperand::CreateImm(Val));
1936  }
1937
1938  void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
1939    assert(N == 2 && "Invalid number of operands!");
1940    // If we have an immediate that's not a constant, treat it as a label
1941    // reference needing a fixup. If it is a constant, it's something else
1942    // and we reject it.
1943    if (isImm()) {
1944      Inst.addOperand(MCOperand::CreateExpr(getImm()));
1945      Inst.addOperand(MCOperand::CreateImm(0));
1946      return;
1947    }
1948
1949    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1950    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1951    Inst.addOperand(MCOperand::CreateImm(Val));
1952  }
1953
1954  void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
1955    assert(N == 2 && "Invalid number of operands!");
1956    // The lower two bits are always zero and as such are not encoded.
1957    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1958    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1959    Inst.addOperand(MCOperand::CreateImm(Val));
1960  }
1961
1962  void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1963    assert(N == 2 && "Invalid number of operands!");
1964    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1965    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1966    Inst.addOperand(MCOperand::CreateImm(Val));
1967  }
1968
1969  void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1970    addMemImm8OffsetOperands(Inst, N);
1971  }
1972
1973  void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1974    addMemImm8OffsetOperands(Inst, N);
1975  }
1976
1977  void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1978    assert(N == 2 && "Invalid number of operands!");
1979    // If this is an immediate, it's a label reference.
1980    if (isImm()) {
1981      addExpr(Inst, getImm());
1982      Inst.addOperand(MCOperand::CreateImm(0));
1983      return;
1984    }
1985
1986    // Otherwise, it's a normal memory reg+offset.
1987    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1988    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1989    Inst.addOperand(MCOperand::CreateImm(Val));
1990  }
1991
1992  void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1993    assert(N == 2 && "Invalid number of operands!");
1994    // If this is an immediate, it's a label reference.
1995    if (isImm()) {
1996      addExpr(Inst, getImm());
1997      Inst.addOperand(MCOperand::CreateImm(0));
1998      return;
1999    }
2000
2001    // Otherwise, it's a normal memory reg+offset.
2002    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2003    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2004    Inst.addOperand(MCOperand::CreateImm(Val));
2005  }
2006
2007  void addMemTBBOperands(MCInst &Inst, unsigned N) const {
2008    assert(N == 2 && "Invalid number of operands!");
2009    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2010    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2011  }
2012
2013  void addMemTBHOperands(MCInst &Inst, unsigned N) const {
2014    assert(N == 2 && "Invalid number of operands!");
2015    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2016    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2017  }
2018
2019  void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2020    assert(N == 3 && "Invalid number of operands!");
2021    unsigned Val =
2022      ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2023                        Memory.ShiftImm, Memory.ShiftType);
2024    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2025    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2026    Inst.addOperand(MCOperand::CreateImm(Val));
2027  }
2028
2029  void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2030    assert(N == 3 && "Invalid number of operands!");
2031    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2032    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2033    Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
2034  }
2035
2036  void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
2037    assert(N == 2 && "Invalid number of operands!");
2038    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2039    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2040  }
2041
2042  void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
2043    assert(N == 2 && "Invalid number of operands!");
2044    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2045    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2046    Inst.addOperand(MCOperand::CreateImm(Val));
2047  }
2048
2049  void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
2050    assert(N == 2 && "Invalid number of operands!");
2051    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
2052    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2053    Inst.addOperand(MCOperand::CreateImm(Val));
2054  }
2055
2056  void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
2057    assert(N == 2 && "Invalid number of operands!");
2058    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
2059    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2060    Inst.addOperand(MCOperand::CreateImm(Val));
2061  }
2062
2063  void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
2064    assert(N == 2 && "Invalid number of operands!");
2065    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2066    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2067    Inst.addOperand(MCOperand::CreateImm(Val));
2068  }
2069
2070  void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
2071    assert(N == 1 && "Invalid number of operands!");
2072    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2073    assert(CE && "non-constant post-idx-imm8 operand!");
2074    int Imm = CE->getValue();
2075    bool isAdd = Imm >= 0;
2076    if (Imm == INT32_MIN) Imm = 0;
2077    Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
2078    Inst.addOperand(MCOperand::CreateImm(Imm));
2079  }
2080
2081  void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
2082    assert(N == 1 && "Invalid number of operands!");
2083    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2084    assert(CE && "non-constant post-idx-imm8s4 operand!");
2085    int Imm = CE->getValue();
2086    bool isAdd = Imm >= 0;
2087    if (Imm == INT32_MIN) Imm = 0;
2088    // Immediate is scaled by 4.
2089    Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
2090    Inst.addOperand(MCOperand::CreateImm(Imm));
2091  }
2092
2093  void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
2094    assert(N == 2 && "Invalid number of operands!");
2095    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2096    Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
2097  }
2098
2099  void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
2100    assert(N == 2 && "Invalid number of operands!");
2101    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2102    // The sign, shift type, and shift amount are encoded in a single operand
2103    // using the AM2 encoding helpers.
2104    ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
2105    unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
2106                                     PostIdxReg.ShiftTy);
2107    Inst.addOperand(MCOperand::CreateImm(Imm));
2108  }
2109
2110  void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
2111    assert(N == 1 && "Invalid number of operands!");
2112    Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
2113  }
2114
2115  void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
2116    assert(N == 1 && "Invalid number of operands!");
2117    Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
2118  }
2119
2120  void addVecListOperands(MCInst &Inst, unsigned N) const {
2121    assert(N == 1 && "Invalid number of operands!");
2122    Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2123  }
2124
2125  void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
2126    assert(N == 2 && "Invalid number of operands!");
2127    Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2128    Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex));
2129  }
2130
2131  void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
2132    assert(N == 1 && "Invalid number of operands!");
2133    Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2134  }
2135
2136  void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
2137    assert(N == 1 && "Invalid number of operands!");
2138    Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2139  }
2140
2141  void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
2142    assert(N == 1 && "Invalid number of operands!");
2143    Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2144  }
2145
2146  void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
2147    assert(N == 1 && "Invalid number of operands!");
2148    // The immediate encodes the type of constant as well as the value.
2149    // Mask in that this is an i8 splat.
2150    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2151    Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
2152  }
2153
2154  void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
2155    assert(N == 1 && "Invalid number of operands!");
2156    // The immediate encodes the type of constant as well as the value.
2157    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2158    unsigned Value = CE->getValue();
2159    if (Value >= 256)
2160      Value = (Value >> 8) | 0xa00;
2161    else
2162      Value |= 0x800;
2163    Inst.addOperand(MCOperand::CreateImm(Value));
2164  }
2165
2166  void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
2167    assert(N == 1 && "Invalid number of operands!");
2168    // The immediate encodes the type of constant as well as the value.
2169    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2170    unsigned Value = CE->getValue();
2171    if (Value >= 256 && Value <= 0xff00)
2172      Value = (Value >> 8) | 0x200;
2173    else if (Value > 0xffff && Value <= 0xff0000)
2174      Value = (Value >> 16) | 0x400;
2175    else if (Value > 0xffffff)
2176      Value = (Value >> 24) | 0x600;
2177    Inst.addOperand(MCOperand::CreateImm(Value));
2178  }
2179
2180  void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2181    assert(N == 1 && "Invalid number of operands!");
2182    // The immediate encodes the type of constant as well as the value.
2183    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2184    unsigned Value = CE->getValue();
2185    if (Value >= 256 && Value <= 0xffff)
2186      Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2187    else if (Value > 0xffff && Value <= 0xffffff)
2188      Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2189    else if (Value > 0xffffff)
2190      Value = (Value >> 24) | 0x600;
2191    Inst.addOperand(MCOperand::CreateImm(Value));
2192  }
2193
2194  void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2195    assert(N == 1 && "Invalid number of operands!");
2196    // The immediate encodes the type of constant as well as the value.
2197    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2198    unsigned Value = ~CE->getValue();
2199    if (Value >= 256 && Value <= 0xffff)
2200      Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2201    else if (Value > 0xffff && Value <= 0xffffff)
2202      Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2203    else if (Value > 0xffffff)
2204      Value = (Value >> 24) | 0x600;
2205    Inst.addOperand(MCOperand::CreateImm(Value));
2206  }
2207
2208  void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2209    assert(N == 1 && "Invalid number of operands!");
2210    // The immediate encodes the type of constant as well as the value.
2211    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2212    uint64_t Value = CE->getValue();
2213    unsigned Imm = 0;
2214    for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
2215      Imm |= (Value & 1) << i;
2216    }
2217    Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
2218  }
2219
2220  virtual void print(raw_ostream &OS) const;
2221
2222  static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
2223    ARMOperand *Op = new ARMOperand(k_ITCondMask);
2224    Op->ITMask.Mask = Mask;
2225    Op->StartLoc = S;
2226    Op->EndLoc = S;
2227    return Op;
2228  }
2229
2230  static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
2231    ARMOperand *Op = new ARMOperand(k_CondCode);
2232    Op->CC.Val = CC;
2233    Op->StartLoc = S;
2234    Op->EndLoc = S;
2235    return Op;
2236  }
2237
2238  static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
2239    ARMOperand *Op = new ARMOperand(k_CoprocNum);
2240    Op->Cop.Val = CopVal;
2241    Op->StartLoc = S;
2242    Op->EndLoc = S;
2243    return Op;
2244  }
2245
2246  static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
2247    ARMOperand *Op = new ARMOperand(k_CoprocReg);
2248    Op->Cop.Val = CopVal;
2249    Op->StartLoc = S;
2250    Op->EndLoc = S;
2251    return Op;
2252  }
2253
2254  static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) {
2255    ARMOperand *Op = new ARMOperand(k_CoprocOption);
2256    Op->Cop.Val = Val;
2257    Op->StartLoc = S;
2258    Op->EndLoc = E;
2259    return Op;
2260  }
2261
2262  static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
2263    ARMOperand *Op = new ARMOperand(k_CCOut);
2264    Op->Reg.RegNum = RegNum;
2265    Op->StartLoc = S;
2266    Op->EndLoc = S;
2267    return Op;
2268  }
2269
2270  static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
2271    ARMOperand *Op = new ARMOperand(k_Token);
2272    Op->Tok.Data = Str.data();
2273    Op->Tok.Length = Str.size();
2274    Op->StartLoc = S;
2275    Op->EndLoc = S;
2276    return Op;
2277  }
2278
2279  static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
2280    ARMOperand *Op = new ARMOperand(k_Register);
2281    Op->Reg.RegNum = RegNum;
2282    Op->StartLoc = S;
2283    Op->EndLoc = E;
2284    return Op;
2285  }
2286
2287  static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
2288                                           unsigned SrcReg,
2289                                           unsigned ShiftReg,
2290                                           unsigned ShiftImm,
2291                                           SMLoc S, SMLoc E) {
2292    ARMOperand *Op = new ARMOperand(k_ShiftedRegister);
2293    Op->RegShiftedReg.ShiftTy = ShTy;
2294    Op->RegShiftedReg.SrcReg = SrcReg;
2295    Op->RegShiftedReg.ShiftReg = ShiftReg;
2296    Op->RegShiftedReg.ShiftImm = ShiftImm;
2297    Op->StartLoc = S;
2298    Op->EndLoc = E;
2299    return Op;
2300  }
2301
2302  static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
2303                                            unsigned SrcReg,
2304                                            unsigned ShiftImm,
2305                                            SMLoc S, SMLoc E) {
2306    ARMOperand *Op = new ARMOperand(k_ShiftedImmediate);
2307    Op->RegShiftedImm.ShiftTy = ShTy;
2308    Op->RegShiftedImm.SrcReg = SrcReg;
2309    Op->RegShiftedImm.ShiftImm = ShiftImm;
2310    Op->StartLoc = S;
2311    Op->EndLoc = E;
2312    return Op;
2313  }
2314
2315  static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
2316                                   SMLoc S, SMLoc E) {
2317    ARMOperand *Op = new ARMOperand(k_ShifterImmediate);
2318    Op->ShifterImm.isASR = isASR;
2319    Op->ShifterImm.Imm = Imm;
2320    Op->StartLoc = S;
2321    Op->EndLoc = E;
2322    return Op;
2323  }
2324
2325  static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
2326    ARMOperand *Op = new ARMOperand(k_RotateImmediate);
2327    Op->RotImm.Imm = Imm;
2328    Op->StartLoc = S;
2329    Op->EndLoc = E;
2330    return Op;
2331  }
2332
2333  static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
2334                                    SMLoc S, SMLoc E) {
2335    ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor);
2336    Op->Bitfield.LSB = LSB;
2337    Op->Bitfield.Width = Width;
2338    Op->StartLoc = S;
2339    Op->EndLoc = E;
2340    return Op;
2341  }
2342
2343  static ARMOperand *
2344  CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned> > &Regs,
2345                SMLoc StartLoc, SMLoc EndLoc) {
2346    assert (Regs.size() > 0 && "RegList contains no registers?");
2347    KindTy Kind = k_RegisterList;
2348
2349    if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second))
2350      Kind = k_DPRRegisterList;
2351    else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
2352             contains(Regs.front().second))
2353      Kind = k_SPRRegisterList;
2354
2355    // Sort based on the register encoding values.
2356    array_pod_sort(Regs.begin(), Regs.end());
2357
2358    ARMOperand *Op = new ARMOperand(Kind);
2359    for (SmallVectorImpl<std::pair<unsigned, unsigned> >::const_iterator
2360           I = Regs.begin(), E = Regs.end(); I != E; ++I)
2361      Op->Registers.push_back(I->second);
2362    Op->StartLoc = StartLoc;
2363    Op->EndLoc = EndLoc;
2364    return Op;
2365  }
2366
2367  static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count,
2368                                      bool isDoubleSpaced, SMLoc S, SMLoc E) {
2369    ARMOperand *Op = new ARMOperand(k_VectorList);
2370    Op->VectorList.RegNum = RegNum;
2371    Op->VectorList.Count = Count;
2372    Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2373    Op->StartLoc = S;
2374    Op->EndLoc = E;
2375    return Op;
2376  }
2377
2378  static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count,
2379                                              bool isDoubleSpaced,
2380                                              SMLoc S, SMLoc E) {
2381    ARMOperand *Op = new ARMOperand(k_VectorListAllLanes);
2382    Op->VectorList.RegNum = RegNum;
2383    Op->VectorList.Count = Count;
2384    Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2385    Op->StartLoc = S;
2386    Op->EndLoc = E;
2387    return Op;
2388  }
2389
2390  static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count,
2391                                             unsigned Index,
2392                                             bool isDoubleSpaced,
2393                                             SMLoc S, SMLoc E) {
2394    ARMOperand *Op = new ARMOperand(k_VectorListIndexed);
2395    Op->VectorList.RegNum = RegNum;
2396    Op->VectorList.Count = Count;
2397    Op->VectorList.LaneIndex = Index;
2398    Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2399    Op->StartLoc = S;
2400    Op->EndLoc = E;
2401    return Op;
2402  }
2403
2404  static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E,
2405                                       MCContext &Ctx) {
2406    ARMOperand *Op = new ARMOperand(k_VectorIndex);
2407    Op->VectorIndex.Val = Idx;
2408    Op->StartLoc = S;
2409    Op->EndLoc = E;
2410    return Op;
2411  }
2412
2413  static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
2414    ARMOperand *Op = new ARMOperand(k_Immediate);
2415    Op->Imm.Val = Val;
2416    Op->StartLoc = S;
2417    Op->EndLoc = E;
2418    return Op;
2419  }
2420
2421  static ARMOperand *CreateMem(unsigned BaseRegNum,
2422                               const MCConstantExpr *OffsetImm,
2423                               unsigned OffsetRegNum,
2424                               ARM_AM::ShiftOpc ShiftType,
2425                               unsigned ShiftImm,
2426                               unsigned Alignment,
2427                               bool isNegative,
2428                               SMLoc S, SMLoc E) {
2429    ARMOperand *Op = new ARMOperand(k_Memory);
2430    Op->Memory.BaseRegNum = BaseRegNum;
2431    Op->Memory.OffsetImm = OffsetImm;
2432    Op->Memory.OffsetRegNum = OffsetRegNum;
2433    Op->Memory.ShiftType = ShiftType;
2434    Op->Memory.ShiftImm = ShiftImm;
2435    Op->Memory.Alignment = Alignment;
2436    Op->Memory.isNegative = isNegative;
2437    Op->StartLoc = S;
2438    Op->EndLoc = E;
2439    return Op;
2440  }
2441
2442  static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
2443                                      ARM_AM::ShiftOpc ShiftTy,
2444                                      unsigned ShiftImm,
2445                                      SMLoc S, SMLoc E) {
2446    ARMOperand *Op = new ARMOperand(k_PostIndexRegister);
2447    Op->PostIdxReg.RegNum = RegNum;
2448    Op->PostIdxReg.isAdd = isAdd;
2449    Op->PostIdxReg.ShiftTy = ShiftTy;
2450    Op->PostIdxReg.ShiftImm = ShiftImm;
2451    Op->StartLoc = S;
2452    Op->EndLoc = E;
2453    return Op;
2454  }
2455
2456  static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
2457    ARMOperand *Op = new ARMOperand(k_MemBarrierOpt);
2458    Op->MBOpt.Val = Opt;
2459    Op->StartLoc = S;
2460    Op->EndLoc = S;
2461    return Op;
2462  }
2463
2464  static ARMOperand *CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt,
2465                                              SMLoc S) {
2466    ARMOperand *Op = new ARMOperand(k_InstSyncBarrierOpt);
2467    Op->ISBOpt.Val = Opt;
2468    Op->StartLoc = S;
2469    Op->EndLoc = S;
2470    return Op;
2471  }
2472
2473  static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
2474    ARMOperand *Op = new ARMOperand(k_ProcIFlags);
2475    Op->IFlags.Val = IFlags;
2476    Op->StartLoc = S;
2477    Op->EndLoc = S;
2478    return Op;
2479  }
2480
2481  static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
2482    ARMOperand *Op = new ARMOperand(k_MSRMask);
2483    Op->MMask.Val = MMask;
2484    Op->StartLoc = S;
2485    Op->EndLoc = S;
2486    return Op;
2487  }
2488};
2489
2490} // end anonymous namespace.
2491
2492void ARMOperand::print(raw_ostream &OS) const {
2493  switch (Kind) {
2494  case k_CondCode:
2495    OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
2496    break;
2497  case k_CCOut:
2498    OS << "<ccout " << getReg() << ">";
2499    break;
2500  case k_ITCondMask: {
2501    static const char *const MaskStr[] = {
2502      "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
2503      "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
2504    };
2505    assert((ITMask.Mask & 0xf) == ITMask.Mask);
2506    OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
2507    break;
2508  }
2509  case k_CoprocNum:
2510    OS << "<coprocessor number: " << getCoproc() << ">";
2511    break;
2512  case k_CoprocReg:
2513    OS << "<coprocessor register: " << getCoproc() << ">";
2514    break;
2515  case k_CoprocOption:
2516    OS << "<coprocessor option: " << CoprocOption.Val << ">";
2517    break;
2518  case k_MSRMask:
2519    OS << "<mask: " << getMSRMask() << ">";
2520    break;
2521  case k_Immediate:
2522    getImm()->print(OS);
2523    break;
2524  case k_MemBarrierOpt:
2525    OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt(), false) << ">";
2526    break;
2527  case k_InstSyncBarrierOpt:
2528    OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">";
2529    break;
2530  case k_Memory:
2531    OS << "<memory "
2532       << " base:" << Memory.BaseRegNum;
2533    OS << ">";
2534    break;
2535  case k_PostIndexRegister:
2536    OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
2537       << PostIdxReg.RegNum;
2538    if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
2539      OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
2540         << PostIdxReg.ShiftImm;
2541    OS << ">";
2542    break;
2543  case k_ProcIFlags: {
2544    OS << "<ARM_PROC::";
2545    unsigned IFlags = getProcIFlags();
2546    for (int i=2; i >= 0; --i)
2547      if (IFlags & (1 << i))
2548        OS << ARM_PROC::IFlagsToString(1 << i);
2549    OS << ">";
2550    break;
2551  }
2552  case k_Register:
2553    OS << "<register " << getReg() << ">";
2554    break;
2555  case k_ShifterImmediate:
2556    OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
2557       << " #" << ShifterImm.Imm << ">";
2558    break;
2559  case k_ShiftedRegister:
2560    OS << "<so_reg_reg "
2561       << RegShiftedReg.SrcReg << " "
2562       << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
2563       << " " << RegShiftedReg.ShiftReg << ">";
2564    break;
2565  case k_ShiftedImmediate:
2566    OS << "<so_reg_imm "
2567       << RegShiftedImm.SrcReg << " "
2568       << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
2569       << " #" << RegShiftedImm.ShiftImm << ">";
2570    break;
2571  case k_RotateImmediate:
2572    OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
2573    break;
2574  case k_BitfieldDescriptor:
2575    OS << "<bitfield " << "lsb: " << Bitfield.LSB
2576       << ", width: " << Bitfield.Width << ">";
2577    break;
2578  case k_RegisterList:
2579  case k_DPRRegisterList:
2580  case k_SPRRegisterList: {
2581    OS << "<register_list ";
2582
2583    const SmallVectorImpl<unsigned> &RegList = getRegList();
2584    for (SmallVectorImpl<unsigned>::const_iterator
2585           I = RegList.begin(), E = RegList.end(); I != E; ) {
2586      OS << *I;
2587      if (++I < E) OS << ", ";
2588    }
2589
2590    OS << ">";
2591    break;
2592  }
2593  case k_VectorList:
2594    OS << "<vector_list " << VectorList.Count << " * "
2595       << VectorList.RegNum << ">";
2596    break;
2597  case k_VectorListAllLanes:
2598    OS << "<vector_list(all lanes) " << VectorList.Count << " * "
2599       << VectorList.RegNum << ">";
2600    break;
2601  case k_VectorListIndexed:
2602    OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
2603       << VectorList.Count << " * " << VectorList.RegNum << ">";
2604    break;
2605  case k_Token:
2606    OS << "'" << getToken() << "'";
2607    break;
2608  case k_VectorIndex:
2609    OS << "<vectorindex " << getVectorIndex() << ">";
2610    break;
2611  }
2612}
2613
2614/// @name Auto-generated Match Functions
2615/// {
2616
2617static unsigned MatchRegisterName(StringRef Name);
2618
2619/// }
2620
2621bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2622                                 SMLoc &StartLoc, SMLoc &EndLoc) {
2623  StartLoc = Parser.getTok().getLoc();
2624  EndLoc = Parser.getTok().getEndLoc();
2625  RegNo = tryParseRegister();
2626
2627  return (RegNo == (unsigned)-1);
2628}
2629
2630/// Try to parse a register name.  The token must be an Identifier when called,
2631/// and if it is a register name the token is eaten and the register number is
2632/// returned.  Otherwise return -1.
2633///
2634int ARMAsmParser::tryParseRegister() {
2635  const AsmToken &Tok = Parser.getTok();
2636  if (Tok.isNot(AsmToken::Identifier)) return -1;
2637
2638  std::string lowerCase = Tok.getString().lower();
2639  unsigned RegNum = MatchRegisterName(lowerCase);
2640  if (!RegNum) {
2641    RegNum = StringSwitch<unsigned>(lowerCase)
2642      .Case("r13", ARM::SP)
2643      .Case("r14", ARM::LR)
2644      .Case("r15", ARM::PC)
2645      .Case("ip", ARM::R12)
2646      // Additional register name aliases for 'gas' compatibility.
2647      .Case("a1", ARM::R0)
2648      .Case("a2", ARM::R1)
2649      .Case("a3", ARM::R2)
2650      .Case("a4", ARM::R3)
2651      .Case("v1", ARM::R4)
2652      .Case("v2", ARM::R5)
2653      .Case("v3", ARM::R6)
2654      .Case("v4", ARM::R7)
2655      .Case("v5", ARM::R8)
2656      .Case("v6", ARM::R9)
2657      .Case("v7", ARM::R10)
2658      .Case("v8", ARM::R11)
2659      .Case("sb", ARM::R9)
2660      .Case("sl", ARM::R10)
2661      .Case("fp", ARM::R11)
2662      .Default(0);
2663  }
2664  if (!RegNum) {
2665    // Check for aliases registered via .req. Canonicalize to lower case.
2666    // That's more consistent since register names are case insensitive, and
2667    // it's how the original entry was passed in from MC/MCParser/AsmParser.
2668    StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
2669    // If no match, return failure.
2670    if (Entry == RegisterReqs.end())
2671      return -1;
2672    Parser.Lex(); // Eat identifier token.
2673    return Entry->getValue();
2674  }
2675
2676  Parser.Lex(); // Eat identifier token.
2677
2678  return RegNum;
2679}
2680
2681// Try to parse a shifter  (e.g., "lsl <amt>"). On success, return 0.
2682// If a recoverable error occurs, return 1. If an irrecoverable error
2683// occurs, return -1. An irrecoverable error is one where tokens have been
2684// consumed in the process of trying to parse the shifter (i.e., when it is
2685// indeed a shifter operand, but malformed).
2686int ARMAsmParser::tryParseShiftRegister(
2687                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2688  SMLoc S = Parser.getTok().getLoc();
2689  const AsmToken &Tok = Parser.getTok();
2690  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2691
2692  std::string lowerCase = Tok.getString().lower();
2693  ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
2694      .Case("asl", ARM_AM::lsl)
2695      .Case("lsl", ARM_AM::lsl)
2696      .Case("lsr", ARM_AM::lsr)
2697      .Case("asr", ARM_AM::asr)
2698      .Case("ror", ARM_AM::ror)
2699      .Case("rrx", ARM_AM::rrx)
2700      .Default(ARM_AM::no_shift);
2701
2702  if (ShiftTy == ARM_AM::no_shift)
2703    return 1;
2704
2705  Parser.Lex(); // Eat the operator.
2706
2707  // The source register for the shift has already been added to the
2708  // operand list, so we need to pop it off and combine it into the shifted
2709  // register operand instead.
2710  OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
2711  if (!PrevOp->isReg())
2712    return Error(PrevOp->getStartLoc(), "shift must be of a register");
2713  int SrcReg = PrevOp->getReg();
2714
2715  SMLoc EndLoc;
2716  int64_t Imm = 0;
2717  int ShiftReg = 0;
2718  if (ShiftTy == ARM_AM::rrx) {
2719    // RRX Doesn't have an explicit shift amount. The encoder expects
2720    // the shift register to be the same as the source register. Seems odd,
2721    // but OK.
2722    ShiftReg = SrcReg;
2723  } else {
2724    // Figure out if this is shifted by a constant or a register (for non-RRX).
2725    if (Parser.getTok().is(AsmToken::Hash) ||
2726        Parser.getTok().is(AsmToken::Dollar)) {
2727      Parser.Lex(); // Eat hash.
2728      SMLoc ImmLoc = Parser.getTok().getLoc();
2729      const MCExpr *ShiftExpr = 0;
2730      if (getParser().parseExpression(ShiftExpr, EndLoc)) {
2731        Error(ImmLoc, "invalid immediate shift value");
2732        return -1;
2733      }
2734      // The expression must be evaluatable as an immediate.
2735      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
2736      if (!CE) {
2737        Error(ImmLoc, "invalid immediate shift value");
2738        return -1;
2739      }
2740      // Range check the immediate.
2741      // lsl, ror: 0 <= imm <= 31
2742      // lsr, asr: 0 <= imm <= 32
2743      Imm = CE->getValue();
2744      if (Imm < 0 ||
2745          ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
2746          ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
2747        Error(ImmLoc, "immediate shift value out of range");
2748        return -1;
2749      }
2750      // shift by zero is a nop. Always send it through as lsl.
2751      // ('as' compatibility)
2752      if (Imm == 0)
2753        ShiftTy = ARM_AM::lsl;
2754    } else if (Parser.getTok().is(AsmToken::Identifier)) {
2755      SMLoc L = Parser.getTok().getLoc();
2756      EndLoc = Parser.getTok().getEndLoc();
2757      ShiftReg = tryParseRegister();
2758      if (ShiftReg == -1) {
2759        Error (L, "expected immediate or register in shift operand");
2760        return -1;
2761      }
2762    } else {
2763      Error (Parser.getTok().getLoc(),
2764                    "expected immediate or register in shift operand");
2765      return -1;
2766    }
2767  }
2768
2769  if (ShiftReg && ShiftTy != ARM_AM::rrx)
2770    Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
2771                                                         ShiftReg, Imm,
2772                                                         S, EndLoc));
2773  else
2774    Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
2775                                                          S, EndLoc));
2776
2777  return 0;
2778}
2779
2780
2781/// Try to parse a register name.  The token must be an Identifier when called.
2782/// If it's a register, an AsmOperand is created. Another AsmOperand is created
2783/// if there is a "writeback". 'true' if it's not a register.
2784///
2785/// TODO this is likely to change to allow different register types and or to
2786/// parse for a specific register type.
2787bool ARMAsmParser::
2788tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2789  const AsmToken &RegTok = Parser.getTok();
2790  int RegNo = tryParseRegister();
2791  if (RegNo == -1)
2792    return true;
2793
2794  Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(),
2795                                           RegTok.getEndLoc()));
2796
2797  const AsmToken &ExclaimTok = Parser.getTok();
2798  if (ExclaimTok.is(AsmToken::Exclaim)) {
2799    Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
2800                                               ExclaimTok.getLoc()));
2801    Parser.Lex(); // Eat exclaim token
2802    return false;
2803  }
2804
2805  // Also check for an index operand. This is only legal for vector registers,
2806  // but that'll get caught OK in operand matching, so we don't need to
2807  // explicitly filter everything else out here.
2808  if (Parser.getTok().is(AsmToken::LBrac)) {
2809    SMLoc SIdx = Parser.getTok().getLoc();
2810    Parser.Lex(); // Eat left bracket token.
2811
2812    const MCExpr *ImmVal;
2813    if (getParser().parseExpression(ImmVal))
2814      return true;
2815    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
2816    if (!MCE)
2817      return TokError("immediate value expected for vector index");
2818
2819    if (Parser.getTok().isNot(AsmToken::RBrac))
2820      return Error(Parser.getTok().getLoc(), "']' expected");
2821
2822    SMLoc E = Parser.getTok().getEndLoc();
2823    Parser.Lex(); // Eat right bracket token.
2824
2825    Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
2826                                                     SIdx, E,
2827                                                     getContext()));
2828  }
2829
2830  return false;
2831}
2832
2833/// MatchCoprocessorOperandName - Try to parse an coprocessor related
2834/// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
2835/// "c5", ...
2836static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
2837  // Use the same layout as the tablegen'erated register name matcher. Ugly,
2838  // but efficient.
2839  switch (Name.size()) {
2840  default: return -1;
2841  case 2:
2842    if (Name[0] != CoprocOp)
2843      return -1;
2844    switch (Name[1]) {
2845    default:  return -1;
2846    case '0': return 0;
2847    case '1': return 1;
2848    case '2': return 2;
2849    case '3': return 3;
2850    case '4': return 4;
2851    case '5': return 5;
2852    case '6': return 6;
2853    case '7': return 7;
2854    case '8': return 8;
2855    case '9': return 9;
2856    }
2857  case 3:
2858    if (Name[0] != CoprocOp || Name[1] != '1')
2859      return -1;
2860    switch (Name[2]) {
2861    default:  return -1;
2862    case '0': return 10;
2863    case '1': return 11;
2864    case '2': return 12;
2865    case '3': return 13;
2866    case '4': return 14;
2867    case '5': return 15;
2868    }
2869  }
2870}
2871
2872/// parseITCondCode - Try to parse a condition code for an IT instruction.
2873ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2874parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2875  SMLoc S = Parser.getTok().getLoc();
2876  const AsmToken &Tok = Parser.getTok();
2877  if (!Tok.is(AsmToken::Identifier))
2878    return MatchOperand_NoMatch;
2879  unsigned CC = StringSwitch<unsigned>(Tok.getString().lower())
2880    .Case("eq", ARMCC::EQ)
2881    .Case("ne", ARMCC::NE)
2882    .Case("hs", ARMCC::HS)
2883    .Case("cs", ARMCC::HS)
2884    .Case("lo", ARMCC::LO)
2885    .Case("cc", ARMCC::LO)
2886    .Case("mi", ARMCC::MI)
2887    .Case("pl", ARMCC::PL)
2888    .Case("vs", ARMCC::VS)
2889    .Case("vc", ARMCC::VC)
2890    .Case("hi", ARMCC::HI)
2891    .Case("ls", ARMCC::LS)
2892    .Case("ge", ARMCC::GE)
2893    .Case("lt", ARMCC::LT)
2894    .Case("gt", ARMCC::GT)
2895    .Case("le", ARMCC::LE)
2896    .Case("al", ARMCC::AL)
2897    .Default(~0U);
2898  if (CC == ~0U)
2899    return MatchOperand_NoMatch;
2900  Parser.Lex(); // Eat the token.
2901
2902  Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
2903
2904  return MatchOperand_Success;
2905}
2906
2907/// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
2908/// token must be an Identifier when called, and if it is a coprocessor
2909/// number, the token is eaten and the operand is added to the operand list.
2910ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2911parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2912  SMLoc S = Parser.getTok().getLoc();
2913  const AsmToken &Tok = Parser.getTok();
2914  if (Tok.isNot(AsmToken::Identifier))
2915    return MatchOperand_NoMatch;
2916
2917  int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
2918  if (Num == -1)
2919    return MatchOperand_NoMatch;
2920
2921  Parser.Lex(); // Eat identifier token.
2922  Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
2923  return MatchOperand_Success;
2924}
2925
2926/// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
2927/// token must be an Identifier when called, and if it is a coprocessor
2928/// number, the token is eaten and the operand is added to the operand list.
2929ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2930parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2931  SMLoc S = Parser.getTok().getLoc();
2932  const AsmToken &Tok = Parser.getTok();
2933  if (Tok.isNot(AsmToken::Identifier))
2934    return MatchOperand_NoMatch;
2935
2936  int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
2937  if (Reg == -1)
2938    return MatchOperand_NoMatch;
2939
2940  Parser.Lex(); // Eat identifier token.
2941  Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
2942  return MatchOperand_Success;
2943}
2944
2945/// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
2946/// coproc_option : '{' imm0_255 '}'
2947ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2948parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2949  SMLoc S = Parser.getTok().getLoc();
2950
2951  // If this isn't a '{', this isn't a coprocessor immediate operand.
2952  if (Parser.getTok().isNot(AsmToken::LCurly))
2953    return MatchOperand_NoMatch;
2954  Parser.Lex(); // Eat the '{'
2955
2956  const MCExpr *Expr;
2957  SMLoc Loc = Parser.getTok().getLoc();
2958  if (getParser().parseExpression(Expr)) {
2959    Error(Loc, "illegal expression");
2960    return MatchOperand_ParseFail;
2961  }
2962  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2963  if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
2964    Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
2965    return MatchOperand_ParseFail;
2966  }
2967  int Val = CE->getValue();
2968
2969  // Check for and consume the closing '}'
2970  if (Parser.getTok().isNot(AsmToken::RCurly))
2971    return MatchOperand_ParseFail;
2972  SMLoc E = Parser.getTok().getEndLoc();
2973  Parser.Lex(); // Eat the '}'
2974
2975  Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
2976  return MatchOperand_Success;
2977}
2978
2979// For register list parsing, we need to map from raw GPR register numbering
2980// to the enumeration values. The enumeration values aren't sorted by
2981// register number due to our using "sp", "lr" and "pc" as canonical names.
2982static unsigned getNextRegister(unsigned Reg) {
2983  // If this is a GPR, we need to do it manually, otherwise we can rely
2984  // on the sort ordering of the enumeration since the other reg-classes
2985  // are sane.
2986  if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2987    return Reg + 1;
2988  switch(Reg) {
2989  default: llvm_unreachable("Invalid GPR number!");
2990  case ARM::R0:  return ARM::R1;  case ARM::R1:  return ARM::R2;
2991  case ARM::R2:  return ARM::R3;  case ARM::R3:  return ARM::R4;
2992  case ARM::R4:  return ARM::R5;  case ARM::R5:  return ARM::R6;
2993  case ARM::R6:  return ARM::R7;  case ARM::R7:  return ARM::R8;
2994  case ARM::R8:  return ARM::R9;  case ARM::R9:  return ARM::R10;
2995  case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
2996  case ARM::R12: return ARM::SP;  case ARM::SP:  return ARM::LR;
2997  case ARM::LR:  return ARM::PC;  case ARM::PC:  return ARM::R0;
2998  }
2999}
3000
3001// Return the low-subreg of a given Q register.
3002static unsigned getDRegFromQReg(unsigned QReg) {
3003  switch (QReg) {
3004  default: llvm_unreachable("expected a Q register!");
3005  case ARM::Q0:  return ARM::D0;
3006  case ARM::Q1:  return ARM::D2;
3007  case ARM::Q2:  return ARM::D4;
3008  case ARM::Q3:  return ARM::D6;
3009  case ARM::Q4:  return ARM::D8;
3010  case ARM::Q5:  return ARM::D10;
3011  case ARM::Q6:  return ARM::D12;
3012  case ARM::Q7:  return ARM::D14;
3013  case ARM::Q8:  return ARM::D16;
3014  case ARM::Q9:  return ARM::D18;
3015  case ARM::Q10: return ARM::D20;
3016  case ARM::Q11: return ARM::D22;
3017  case ARM::Q12: return ARM::D24;
3018  case ARM::Q13: return ARM::D26;
3019  case ARM::Q14: return ARM::D28;
3020  case ARM::Q15: return ARM::D30;
3021  }
3022}
3023
3024/// Parse a register list.
3025bool ARMAsmParser::
3026parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3027  assert(Parser.getTok().is(AsmToken::LCurly) &&
3028         "Token is not a Left Curly Brace");
3029  SMLoc S = Parser.getTok().getLoc();
3030  Parser.Lex(); // Eat '{' token.
3031  SMLoc RegLoc = Parser.getTok().getLoc();
3032
3033  // Check the first register in the list to see what register class
3034  // this is a list of.
3035  int Reg = tryParseRegister();
3036  if (Reg == -1)
3037    return Error(RegLoc, "register expected");
3038
3039  // The reglist instructions have at most 16 registers, so reserve
3040  // space for that many.
3041  int EReg = 0;
3042  SmallVector<std::pair<unsigned, unsigned>, 16> Registers;
3043
3044  // Allow Q regs and just interpret them as the two D sub-registers.
3045  if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3046    Reg = getDRegFromQReg(Reg);
3047    EReg = MRI->getEncodingValue(Reg);
3048    Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3049    ++Reg;
3050  }
3051  const MCRegisterClass *RC;
3052  if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3053    RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
3054  else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
3055    RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
3056  else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
3057    RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
3058  else
3059    return Error(RegLoc, "invalid register in register list");
3060
3061  // Store the register.
3062  EReg = MRI->getEncodingValue(Reg);
3063  Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3064
3065  // This starts immediately after the first register token in the list,
3066  // so we can see either a comma or a minus (range separator) as a legal
3067  // next token.
3068  while (Parser.getTok().is(AsmToken::Comma) ||
3069         Parser.getTok().is(AsmToken::Minus)) {
3070    if (Parser.getTok().is(AsmToken::Minus)) {
3071      Parser.Lex(); // Eat the minus.
3072      SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3073      int EndReg = tryParseRegister();
3074      if (EndReg == -1)
3075        return Error(AfterMinusLoc, "register expected");
3076      // Allow Q regs and just interpret them as the two D sub-registers.
3077      if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3078        EndReg = getDRegFromQReg(EndReg) + 1;
3079      // If the register is the same as the start reg, there's nothing
3080      // more to do.
3081      if (Reg == EndReg)
3082        continue;
3083      // The register must be in the same register class as the first.
3084      if (!RC->contains(EndReg))
3085        return Error(AfterMinusLoc, "invalid register in register list");
3086      // Ranges must go from low to high.
3087      if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
3088        return Error(AfterMinusLoc, "bad range in register list");
3089
3090      // Add all the registers in the range to the register list.
3091      while (Reg != EndReg) {
3092        Reg = getNextRegister(Reg);
3093        EReg = MRI->getEncodingValue(Reg);
3094        Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3095      }
3096      continue;
3097    }
3098    Parser.Lex(); // Eat the comma.
3099    RegLoc = Parser.getTok().getLoc();
3100    int OldReg = Reg;
3101    const AsmToken RegTok = Parser.getTok();
3102    Reg = tryParseRegister();
3103    if (Reg == -1)
3104      return Error(RegLoc, "register expected");
3105    // Allow Q regs and just interpret them as the two D sub-registers.
3106    bool isQReg = false;
3107    if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3108      Reg = getDRegFromQReg(Reg);
3109      isQReg = true;
3110    }
3111    // The register must be in the same register class as the first.
3112    if (!RC->contains(Reg))
3113      return Error(RegLoc, "invalid register in register list");
3114    // List must be monotonically increasing.
3115    if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
3116      if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3117        Warning(RegLoc, "register list not in ascending order");
3118      else
3119        return Error(RegLoc, "register list not in ascending order");
3120    }
3121    if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
3122      Warning(RegLoc, "duplicated register (" + RegTok.getString() +
3123              ") in register list");
3124      continue;
3125    }
3126    // VFP register lists must also be contiguous.
3127    if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
3128        Reg != OldReg + 1)
3129      return Error(RegLoc, "non-contiguous register range");
3130    EReg = MRI->getEncodingValue(Reg);
3131    Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3132    if (isQReg) {
3133      EReg = MRI->getEncodingValue(++Reg);
3134      Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3135    }
3136  }
3137
3138  if (Parser.getTok().isNot(AsmToken::RCurly))
3139    return Error(Parser.getTok().getLoc(), "'}' expected");
3140  SMLoc E = Parser.getTok().getEndLoc();
3141  Parser.Lex(); // Eat '}' token.
3142
3143  // Push the register list operand.
3144  Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
3145
3146  // The ARM system instruction variants for LDM/STM have a '^' token here.
3147  if (Parser.getTok().is(AsmToken::Caret)) {
3148    Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
3149    Parser.Lex(); // Eat '^' token.
3150  }
3151
3152  return false;
3153}
3154
3155// Helper function to parse the lane index for vector lists.
3156ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3157parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
3158  Index = 0; // Always return a defined index value.
3159  if (Parser.getTok().is(AsmToken::LBrac)) {
3160    Parser.Lex(); // Eat the '['.
3161    if (Parser.getTok().is(AsmToken::RBrac)) {
3162      // "Dn[]" is the 'all lanes' syntax.
3163      LaneKind = AllLanes;
3164      EndLoc = Parser.getTok().getEndLoc();
3165      Parser.Lex(); // Eat the ']'.
3166      return MatchOperand_Success;
3167    }
3168
3169    // There's an optional '#' token here. Normally there wouldn't be, but
3170    // inline assemble puts one in, and it's friendly to accept that.
3171    if (Parser.getTok().is(AsmToken::Hash))
3172      Parser.Lex(); // Eat '#' or '$'.
3173
3174    const MCExpr *LaneIndex;
3175    SMLoc Loc = Parser.getTok().getLoc();
3176    if (getParser().parseExpression(LaneIndex)) {
3177      Error(Loc, "illegal expression");
3178      return MatchOperand_ParseFail;
3179    }
3180    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
3181    if (!CE) {
3182      Error(Loc, "lane index must be empty or an integer");
3183      return MatchOperand_ParseFail;
3184    }
3185    if (Parser.getTok().isNot(AsmToken::RBrac)) {
3186      Error(Parser.getTok().getLoc(), "']' expected");
3187      return MatchOperand_ParseFail;
3188    }
3189    EndLoc = Parser.getTok().getEndLoc();
3190    Parser.Lex(); // Eat the ']'.
3191    int64_t Val = CE->getValue();
3192
3193    // FIXME: Make this range check context sensitive for .8, .16, .32.
3194    if (Val < 0 || Val > 7) {
3195      Error(Parser.getTok().getLoc(), "lane index out of range");
3196      return MatchOperand_ParseFail;
3197    }
3198    Index = Val;
3199    LaneKind = IndexedLane;
3200    return MatchOperand_Success;
3201  }
3202  LaneKind = NoLanes;
3203  return MatchOperand_Success;
3204}
3205
3206// parse a vector register list
3207ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3208parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3209  VectorLaneTy LaneKind;
3210  unsigned LaneIndex;
3211  SMLoc S = Parser.getTok().getLoc();
3212  // As an extension (to match gas), support a plain D register or Q register
3213  // (without encosing curly braces) as a single or double entry list,
3214  // respectively.
3215  if (Parser.getTok().is(AsmToken::Identifier)) {
3216    SMLoc E = Parser.getTok().getEndLoc();
3217    int Reg = tryParseRegister();
3218    if (Reg == -1)
3219      return MatchOperand_NoMatch;
3220    if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
3221      OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3222      if (Res != MatchOperand_Success)
3223        return Res;
3224      switch (LaneKind) {
3225      case NoLanes:
3226        Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
3227        break;
3228      case AllLanes:
3229        Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
3230                                                                S, E));
3231        break;
3232      case IndexedLane:
3233        Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
3234                                                               LaneIndex,
3235                                                               false, S, E));
3236        break;
3237      }
3238      return MatchOperand_Success;
3239    }
3240    if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3241      Reg = getDRegFromQReg(Reg);
3242      OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3243      if (Res != MatchOperand_Success)
3244        return Res;
3245      switch (LaneKind) {
3246      case NoLanes:
3247        Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3248                                   &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3249        Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
3250        break;
3251      case AllLanes:
3252        Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3253                                   &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3254        Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
3255                                                                S, E));
3256        break;
3257      case IndexedLane:
3258        Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
3259                                                               LaneIndex,
3260                                                               false, S, E));
3261        break;
3262      }
3263      return MatchOperand_Success;
3264    }
3265    Error(S, "vector register expected");
3266    return MatchOperand_ParseFail;
3267  }
3268
3269  if (Parser.getTok().isNot(AsmToken::LCurly))
3270    return MatchOperand_NoMatch;
3271
3272  Parser.Lex(); // Eat '{' token.
3273  SMLoc RegLoc = Parser.getTok().getLoc();
3274
3275  int Reg = tryParseRegister();
3276  if (Reg == -1) {
3277    Error(RegLoc, "register expected");
3278    return MatchOperand_ParseFail;
3279  }
3280  unsigned Count = 1;
3281  int Spacing = 0;
3282  unsigned FirstReg = Reg;
3283  // The list is of D registers, but we also allow Q regs and just interpret
3284  // them as the two D sub-registers.
3285  if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3286    FirstReg = Reg = getDRegFromQReg(Reg);
3287    Spacing = 1; // double-spacing requires explicit D registers, otherwise
3288                 // it's ambiguous with four-register single spaced.
3289    ++Reg;
3290    ++Count;
3291  }
3292
3293  SMLoc E;
3294  if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success)
3295    return MatchOperand_ParseFail;
3296
3297  while (Parser.getTok().is(AsmToken::Comma) ||
3298         Parser.getTok().is(AsmToken::Minus)) {
3299    if (Parser.getTok().is(AsmToken::Minus)) {
3300      if (!Spacing)
3301        Spacing = 1; // Register range implies a single spaced list.
3302      else if (Spacing == 2) {
3303        Error(Parser.getTok().getLoc(),
3304              "sequential registers in double spaced list");
3305        return MatchOperand_ParseFail;
3306      }
3307      Parser.Lex(); // Eat the minus.
3308      SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3309      int EndReg = tryParseRegister();
3310      if (EndReg == -1) {
3311        Error(AfterMinusLoc, "register expected");
3312        return MatchOperand_ParseFail;
3313      }
3314      // Allow Q regs and just interpret them as the two D sub-registers.
3315      if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3316        EndReg = getDRegFromQReg(EndReg) + 1;
3317      // If the register is the same as the start reg, there's nothing
3318      // more to do.
3319      if (Reg == EndReg)
3320        continue;
3321      // The register must be in the same register class as the first.
3322      if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
3323        Error(AfterMinusLoc, "invalid register in register list");
3324        return MatchOperand_ParseFail;
3325      }
3326      // Ranges must go from low to high.
3327      if (Reg > EndReg) {
3328        Error(AfterMinusLoc, "bad range in register list");
3329        return MatchOperand_ParseFail;
3330      }
3331      // Parse the lane specifier if present.
3332      VectorLaneTy NextLaneKind;
3333      unsigned NextLaneIndex;
3334      if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3335          MatchOperand_Success)
3336        return MatchOperand_ParseFail;
3337      if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3338        Error(AfterMinusLoc, "mismatched lane index in register list");
3339        return MatchOperand_ParseFail;
3340      }
3341
3342      // Add all the registers in the range to the register list.
3343      Count += EndReg - Reg;
3344      Reg = EndReg;
3345      continue;
3346    }
3347    Parser.Lex(); // Eat the comma.
3348    RegLoc = Parser.getTok().getLoc();
3349    int OldReg = Reg;
3350    Reg = tryParseRegister();
3351    if (Reg == -1) {
3352      Error(RegLoc, "register expected");
3353      return MatchOperand_ParseFail;
3354    }
3355    // vector register lists must be contiguous.
3356    // It's OK to use the enumeration values directly here rather, as the
3357    // VFP register classes have the enum sorted properly.
3358    //
3359    // The list is of D registers, but we also allow Q regs and just interpret
3360    // them as the two D sub-registers.
3361    if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3362      if (!Spacing)
3363        Spacing = 1; // Register range implies a single spaced list.
3364      else if (Spacing == 2) {
3365        Error(RegLoc,
3366              "invalid register in double-spaced list (must be 'D' register')");
3367        return MatchOperand_ParseFail;
3368      }
3369      Reg = getDRegFromQReg(Reg);
3370      if (Reg != OldReg + 1) {
3371        Error(RegLoc, "non-contiguous register range");
3372        return MatchOperand_ParseFail;
3373      }
3374      ++Reg;
3375      Count += 2;
3376      // Parse the lane specifier if present.
3377      VectorLaneTy NextLaneKind;
3378      unsigned NextLaneIndex;
3379      SMLoc LaneLoc = Parser.getTok().getLoc();
3380      if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3381          MatchOperand_Success)
3382        return MatchOperand_ParseFail;
3383      if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3384        Error(LaneLoc, "mismatched lane index in register list");
3385        return MatchOperand_ParseFail;
3386      }
3387      continue;
3388    }
3389    // Normal D register.
3390    // Figure out the register spacing (single or double) of the list if
3391    // we don't know it already.
3392    if (!Spacing)
3393      Spacing = 1 + (Reg == OldReg + 2);
3394
3395    // Just check that it's contiguous and keep going.
3396    if (Reg != OldReg + Spacing) {
3397      Error(RegLoc, "non-contiguous register range");
3398      return MatchOperand_ParseFail;
3399    }
3400    ++Count;
3401    // Parse the lane specifier if present.
3402    VectorLaneTy NextLaneKind;
3403    unsigned NextLaneIndex;
3404    SMLoc EndLoc = Parser.getTok().getLoc();
3405    if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success)
3406      return MatchOperand_ParseFail;
3407    if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3408      Error(EndLoc, "mismatched lane index in register list");
3409      return MatchOperand_ParseFail;
3410    }
3411  }
3412
3413  if (Parser.getTok().isNot(AsmToken::RCurly)) {
3414    Error(Parser.getTok().getLoc(), "'}' expected");
3415    return MatchOperand_ParseFail;
3416  }
3417  E = Parser.getTok().getEndLoc();
3418  Parser.Lex(); // Eat '}' token.
3419
3420  switch (LaneKind) {
3421  case NoLanes:
3422    // Two-register operands have been converted to the
3423    // composite register classes.
3424    if (Count == 2) {
3425      const MCRegisterClass *RC = (Spacing == 1) ?
3426        &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3427        &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3428      FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3429    }
3430
3431    Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
3432                                                    (Spacing == 2), S, E));
3433    break;
3434  case AllLanes:
3435    // Two-register operands have been converted to the
3436    // composite register classes.
3437    if (Count == 2) {
3438      const MCRegisterClass *RC = (Spacing == 1) ?
3439        &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3440        &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3441      FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3442    }
3443    Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
3444                                                            (Spacing == 2),
3445                                                            S, E));
3446    break;
3447  case IndexedLane:
3448    Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
3449                                                           LaneIndex,
3450                                                           (Spacing == 2),
3451                                                           S, E));
3452    break;
3453  }
3454  return MatchOperand_Success;
3455}
3456
3457/// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
3458ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3459parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3460  SMLoc S = Parser.getTok().getLoc();
3461  const AsmToken &Tok = Parser.getTok();
3462  unsigned Opt;
3463
3464  if (Tok.is(AsmToken::Identifier)) {
3465    StringRef OptStr = Tok.getString();
3466
3467    Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
3468      .Case("sy",    ARM_MB::SY)
3469      .Case("st",    ARM_MB::ST)
3470      .Case("ld",    ARM_MB::LD)
3471      .Case("sh",    ARM_MB::ISH)
3472      .Case("ish",   ARM_MB::ISH)
3473      .Case("shst",  ARM_MB::ISHST)
3474      .Case("ishst", ARM_MB::ISHST)
3475      .Case("ishld", ARM_MB::ISHLD)
3476      .Case("nsh",   ARM_MB::NSH)
3477      .Case("un",    ARM_MB::NSH)
3478      .Case("nshst", ARM_MB::NSHST)
3479      .Case("nshld", ARM_MB::NSHLD)
3480      .Case("unst",  ARM_MB::NSHST)
3481      .Case("osh",   ARM_MB::OSH)
3482      .Case("oshst", ARM_MB::OSHST)
3483      .Case("oshld", ARM_MB::OSHLD)
3484      .Default(~0U);
3485
3486    // ishld, oshld, nshld and ld are only available from ARMv8.
3487    if (!hasV8Ops() && (Opt == ARM_MB::ISHLD || Opt == ARM_MB::OSHLD ||
3488                        Opt == ARM_MB::NSHLD || Opt == ARM_MB::LD))
3489      Opt = ~0U;
3490
3491    if (Opt == ~0U)
3492      return MatchOperand_NoMatch;
3493
3494    Parser.Lex(); // Eat identifier token.
3495  } else if (Tok.is(AsmToken::Hash) ||
3496             Tok.is(AsmToken::Dollar) ||
3497             Tok.is(AsmToken::Integer)) {
3498    if (Parser.getTok().isNot(AsmToken::Integer))
3499      Parser.Lex(); // Eat '#' or '$'.
3500    SMLoc Loc = Parser.getTok().getLoc();
3501
3502    const MCExpr *MemBarrierID;
3503    if (getParser().parseExpression(MemBarrierID)) {
3504      Error(Loc, "illegal expression");
3505      return MatchOperand_ParseFail;
3506    }
3507
3508    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
3509    if (!CE) {
3510      Error(Loc, "constant expression expected");
3511      return MatchOperand_ParseFail;
3512    }
3513
3514    int Val = CE->getValue();
3515    if (Val & ~0xf) {
3516      Error(Loc, "immediate value out of range");
3517      return MatchOperand_ParseFail;
3518    }
3519
3520    Opt = ARM_MB::RESERVED_0 + Val;
3521  } else
3522    return MatchOperand_ParseFail;
3523
3524  Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
3525  return MatchOperand_Success;
3526}
3527
3528/// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options.
3529ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3530parseInstSyncBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3531  SMLoc S = Parser.getTok().getLoc();
3532  const AsmToken &Tok = Parser.getTok();
3533  unsigned Opt;
3534
3535  if (Tok.is(AsmToken::Identifier)) {
3536    StringRef OptStr = Tok.getString();
3537
3538    if (OptStr.lower() == "sy")
3539      Opt = ARM_ISB::SY;
3540    else
3541      return MatchOperand_NoMatch;
3542
3543    Parser.Lex(); // Eat identifier token.
3544  } else if (Tok.is(AsmToken::Hash) ||
3545             Tok.is(AsmToken::Dollar) ||
3546             Tok.is(AsmToken::Integer)) {
3547    if (Parser.getTok().isNot(AsmToken::Integer))
3548      Parser.Lex(); // Eat '#' or '$'.
3549    SMLoc Loc = Parser.getTok().getLoc();
3550
3551    const MCExpr *ISBarrierID;
3552    if (getParser().parseExpression(ISBarrierID)) {
3553      Error(Loc, "illegal expression");
3554      return MatchOperand_ParseFail;
3555    }
3556
3557    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID);
3558    if (!CE) {
3559      Error(Loc, "constant expression expected");
3560      return MatchOperand_ParseFail;
3561    }
3562
3563    int Val = CE->getValue();
3564    if (Val & ~0xf) {
3565      Error(Loc, "immediate value out of range");
3566      return MatchOperand_ParseFail;
3567    }
3568
3569    Opt = ARM_ISB::RESERVED_0 + Val;
3570  } else
3571    return MatchOperand_ParseFail;
3572
3573  Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt(
3574          (ARM_ISB::InstSyncBOpt)Opt, S));
3575  return MatchOperand_Success;
3576}
3577
3578
3579/// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
3580ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3581parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3582  SMLoc S = Parser.getTok().getLoc();
3583  const AsmToken &Tok = Parser.getTok();
3584  if (!Tok.is(AsmToken::Identifier))
3585    return MatchOperand_NoMatch;
3586  StringRef IFlagsStr = Tok.getString();
3587
3588  // An iflags string of "none" is interpreted to mean that none of the AIF
3589  // bits are set.  Not a terribly useful instruction, but a valid encoding.
3590  unsigned IFlags = 0;
3591  if (IFlagsStr != "none") {
3592        for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
3593      unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
3594        .Case("a", ARM_PROC::A)
3595        .Case("i", ARM_PROC::I)
3596        .Case("f", ARM_PROC::F)
3597        .Default(~0U);
3598
3599      // If some specific iflag is already set, it means that some letter is
3600      // present more than once, this is not acceptable.
3601      if (Flag == ~0U || (IFlags & Flag))
3602        return MatchOperand_NoMatch;
3603
3604      IFlags |= Flag;
3605    }
3606  }
3607
3608  Parser.Lex(); // Eat identifier token.
3609  Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
3610  return MatchOperand_Success;
3611}
3612
3613/// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
3614ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3615parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3616  SMLoc S = Parser.getTok().getLoc();
3617  const AsmToken &Tok = Parser.getTok();
3618  if (!Tok.is(AsmToken::Identifier))
3619    return MatchOperand_NoMatch;
3620  StringRef Mask = Tok.getString();
3621
3622  if (isMClass()) {
3623    // See ARMv6-M 10.1.1
3624    std::string Name = Mask.lower();
3625    unsigned FlagsVal = StringSwitch<unsigned>(Name)
3626      // Note: in the documentation:
3627      //  ARM deprecates using MSR APSR without a _<bits> qualifier as an alias
3628      //  for MSR APSR_nzcvq.
3629      // but we do make it an alias here.  This is so to get the "mask encoding"
3630      // bits correct on MSR APSR writes.
3631      //
3632      // FIXME: Note the 0xc00 "mask encoding" bits version of the registers
3633      // should really only be allowed when writing a special register.  Note
3634      // they get dropped in the MRS instruction reading a special register as
3635      // the SYSm field is only 8 bits.
3636      //
3637      // FIXME: the _g and _nzcvqg versions are only allowed if the processor
3638      // includes the DSP extension but that is not checked.
3639      .Case("apsr", 0x800)
3640      .Case("apsr_nzcvq", 0x800)
3641      .Case("apsr_g", 0x400)
3642      .Case("apsr_nzcvqg", 0xc00)
3643      .Case("iapsr", 0x801)
3644      .Case("iapsr_nzcvq", 0x801)
3645      .Case("iapsr_g", 0x401)
3646      .Case("iapsr_nzcvqg", 0xc01)
3647      .Case("eapsr", 0x802)
3648      .Case("eapsr_nzcvq", 0x802)
3649      .Case("eapsr_g", 0x402)
3650      .Case("eapsr_nzcvqg", 0xc02)
3651      .Case("xpsr", 0x803)
3652      .Case("xpsr_nzcvq", 0x803)
3653      .Case("xpsr_g", 0x403)
3654      .Case("xpsr_nzcvqg", 0xc03)
3655      .Case("ipsr", 0x805)
3656      .Case("epsr", 0x806)
3657      .Case("iepsr", 0x807)
3658      .Case("msp", 0x808)
3659      .Case("psp", 0x809)
3660      .Case("primask", 0x810)
3661      .Case("basepri", 0x811)
3662      .Case("basepri_max", 0x812)
3663      .Case("faultmask", 0x813)
3664      .Case("control", 0x814)
3665      .Default(~0U);
3666
3667    if (FlagsVal == ~0U)
3668      return MatchOperand_NoMatch;
3669
3670    if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813)
3671      // basepri, basepri_max and faultmask only valid for V7m.
3672      return MatchOperand_NoMatch;
3673
3674    Parser.Lex(); // Eat identifier token.
3675    Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3676    return MatchOperand_Success;
3677  }
3678
3679  // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
3680  size_t Start = 0, Next = Mask.find('_');
3681  StringRef Flags = "";
3682  std::string SpecReg = Mask.slice(Start, Next).lower();
3683  if (Next != StringRef::npos)
3684    Flags = Mask.slice(Next+1, Mask.size());
3685
3686  // FlagsVal contains the complete mask:
3687  // 3-0: Mask
3688  // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3689  unsigned FlagsVal = 0;
3690
3691  if (SpecReg == "apsr") {
3692    FlagsVal = StringSwitch<unsigned>(Flags)
3693    .Case("nzcvq",  0x8) // same as CPSR_f
3694    .Case("g",      0x4) // same as CPSR_s
3695    .Case("nzcvqg", 0xc) // same as CPSR_fs
3696    .Default(~0U);
3697
3698    if (FlagsVal == ~0U) {
3699      if (!Flags.empty())
3700        return MatchOperand_NoMatch;
3701      else
3702        FlagsVal = 8; // No flag
3703    }
3704  } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
3705    // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
3706    if (Flags == "all" || Flags == "")
3707      Flags = "fc";
3708    for (int i = 0, e = Flags.size(); i != e; ++i) {
3709      unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
3710      .Case("c", 1)
3711      .Case("x", 2)
3712      .Case("s", 4)
3713      .Case("f", 8)
3714      .Default(~0U);
3715
3716      // If some specific flag is already set, it means that some letter is
3717      // present more than once, this is not acceptable.
3718      if (FlagsVal == ~0U || (FlagsVal & Flag))
3719        return MatchOperand_NoMatch;
3720      FlagsVal |= Flag;
3721    }
3722  } else // No match for special register.
3723    return MatchOperand_NoMatch;
3724
3725  // Special register without flags is NOT equivalent to "fc" flags.
3726  // NOTE: This is a divergence from gas' behavior.  Uncommenting the following
3727  // two lines would enable gas compatibility at the expense of breaking
3728  // round-tripping.
3729  //
3730  // if (!FlagsVal)
3731  //  FlagsVal = 0x9;
3732
3733  // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3734  if (SpecReg == "spsr")
3735    FlagsVal |= 16;
3736
3737  Parser.Lex(); // Eat identifier token.
3738  Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3739  return MatchOperand_Success;
3740}
3741
3742ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3743parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
3744            int Low, int High) {
3745  const AsmToken &Tok = Parser.getTok();
3746  if (Tok.isNot(AsmToken::Identifier)) {
3747    Error(Parser.getTok().getLoc(), Op + " operand expected.");
3748    return MatchOperand_ParseFail;
3749  }
3750  StringRef ShiftName = Tok.getString();
3751  std::string LowerOp = Op.lower();
3752  std::string UpperOp = Op.upper();
3753  if (ShiftName != LowerOp && ShiftName != UpperOp) {
3754    Error(Parser.getTok().getLoc(), Op + " operand expected.");
3755    return MatchOperand_ParseFail;
3756  }
3757  Parser.Lex(); // Eat shift type token.
3758
3759  // There must be a '#' and a shift amount.
3760  if (Parser.getTok().isNot(AsmToken::Hash) &&
3761      Parser.getTok().isNot(AsmToken::Dollar)) {
3762    Error(Parser.getTok().getLoc(), "'#' expected");
3763    return MatchOperand_ParseFail;
3764  }
3765  Parser.Lex(); // Eat hash token.
3766
3767  const MCExpr *ShiftAmount;
3768  SMLoc Loc = Parser.getTok().getLoc();
3769  SMLoc EndLoc;
3770  if (getParser().parseExpression(ShiftAmount, EndLoc)) {
3771    Error(Loc, "illegal expression");
3772    return MatchOperand_ParseFail;
3773  }
3774  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3775  if (!CE) {
3776    Error(Loc, "constant expression expected");
3777    return MatchOperand_ParseFail;
3778  }
3779  int Val = CE->getValue();
3780  if (Val < Low || Val > High) {
3781    Error(Loc, "immediate value out of range");
3782    return MatchOperand_ParseFail;
3783  }
3784
3785  Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc));
3786
3787  return MatchOperand_Success;
3788}
3789
3790ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3791parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3792  const AsmToken &Tok = Parser.getTok();
3793  SMLoc S = Tok.getLoc();
3794  if (Tok.isNot(AsmToken::Identifier)) {
3795    Error(S, "'be' or 'le' operand expected");
3796    return MatchOperand_ParseFail;
3797  }
3798  int Val = StringSwitch<int>(Tok.getString().lower())
3799    .Case("be", 1)
3800    .Case("le", 0)
3801    .Default(-1);
3802  Parser.Lex(); // Eat the token.
3803
3804  if (Val == -1) {
3805    Error(S, "'be' or 'le' operand expected");
3806    return MatchOperand_ParseFail;
3807  }
3808  Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
3809                                                                  getContext()),
3810                                           S, Tok.getEndLoc()));
3811  return MatchOperand_Success;
3812}
3813
3814/// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
3815/// instructions. Legal values are:
3816///     lsl #n  'n' in [0,31]
3817///     asr #n  'n' in [1,32]
3818///             n == 32 encoded as n == 0.
3819ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3820parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3821  const AsmToken &Tok = Parser.getTok();
3822  SMLoc S = Tok.getLoc();
3823  if (Tok.isNot(AsmToken::Identifier)) {
3824    Error(S, "shift operator 'asr' or 'lsl' expected");
3825    return MatchOperand_ParseFail;
3826  }
3827  StringRef ShiftName = Tok.getString();
3828  bool isASR;
3829  if (ShiftName == "lsl" || ShiftName == "LSL")
3830    isASR = false;
3831  else if (ShiftName == "asr" || ShiftName == "ASR")
3832    isASR = true;
3833  else {
3834    Error(S, "shift operator 'asr' or 'lsl' expected");
3835    return MatchOperand_ParseFail;
3836  }
3837  Parser.Lex(); // Eat the operator.
3838
3839  // A '#' and a shift amount.
3840  if (Parser.getTok().isNot(AsmToken::Hash) &&
3841      Parser.getTok().isNot(AsmToken::Dollar)) {
3842    Error(Parser.getTok().getLoc(), "'#' expected");
3843    return MatchOperand_ParseFail;
3844  }
3845  Parser.Lex(); // Eat hash token.
3846  SMLoc ExLoc = Parser.getTok().getLoc();
3847
3848  const MCExpr *ShiftAmount;
3849  SMLoc EndLoc;
3850  if (getParser().parseExpression(ShiftAmount, EndLoc)) {
3851    Error(ExLoc, "malformed shift expression");
3852    return MatchOperand_ParseFail;
3853  }
3854  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3855  if (!CE) {
3856    Error(ExLoc, "shift amount must be an immediate");
3857    return MatchOperand_ParseFail;
3858  }
3859
3860  int64_t Val = CE->getValue();
3861  if (isASR) {
3862    // Shift amount must be in [1,32]
3863    if (Val < 1 || Val > 32) {
3864      Error(ExLoc, "'asr' shift amount must be in range [1,32]");
3865      return MatchOperand_ParseFail;
3866    }
3867    // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
3868    if (isThumb() && Val == 32) {
3869      Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode");
3870      return MatchOperand_ParseFail;
3871    }
3872    if (Val == 32) Val = 0;
3873  } else {
3874    // Shift amount must be in [1,32]
3875    if (Val < 0 || Val > 31) {
3876      Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
3877      return MatchOperand_ParseFail;
3878    }
3879  }
3880
3881  Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc));
3882
3883  return MatchOperand_Success;
3884}
3885
3886/// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
3887/// of instructions. Legal values are:
3888///     ror #n  'n' in {0, 8, 16, 24}
3889ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3890parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3891  const AsmToken &Tok = Parser.getTok();
3892  SMLoc S = Tok.getLoc();
3893  if (Tok.isNot(AsmToken::Identifier))
3894    return MatchOperand_NoMatch;
3895  StringRef ShiftName = Tok.getString();
3896  if (ShiftName != "ror" && ShiftName != "ROR")
3897    return MatchOperand_NoMatch;
3898  Parser.Lex(); // Eat the operator.
3899
3900  // A '#' and a rotate amount.
3901  if (Parser.getTok().isNot(AsmToken::Hash) &&
3902      Parser.getTok().isNot(AsmToken::Dollar)) {
3903    Error(Parser.getTok().getLoc(), "'#' expected");
3904    return MatchOperand_ParseFail;
3905  }
3906  Parser.Lex(); // Eat hash token.
3907  SMLoc ExLoc = Parser.getTok().getLoc();
3908
3909  const MCExpr *ShiftAmount;
3910  SMLoc EndLoc;
3911  if (getParser().parseExpression(ShiftAmount, EndLoc)) {
3912    Error(ExLoc, "malformed rotate expression");
3913    return MatchOperand_ParseFail;
3914  }
3915  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3916  if (!CE) {
3917    Error(ExLoc, "rotate amount must be an immediate");
3918    return MatchOperand_ParseFail;
3919  }
3920
3921  int64_t Val = CE->getValue();
3922  // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
3923  // normally, zero is represented in asm by omitting the rotate operand
3924  // entirely.
3925  if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
3926    Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24");
3927    return MatchOperand_ParseFail;
3928  }
3929
3930  Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc));
3931
3932  return MatchOperand_Success;
3933}
3934
3935ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3936parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3937  SMLoc S = Parser.getTok().getLoc();
3938  // The bitfield descriptor is really two operands, the LSB and the width.
3939  if (Parser.getTok().isNot(AsmToken::Hash) &&
3940      Parser.getTok().isNot(AsmToken::Dollar)) {
3941    Error(Parser.getTok().getLoc(), "'#' expected");
3942    return MatchOperand_ParseFail;
3943  }
3944  Parser.Lex(); // Eat hash token.
3945
3946  const MCExpr *LSBExpr;
3947  SMLoc E = Parser.getTok().getLoc();
3948  if (getParser().parseExpression(LSBExpr)) {
3949    Error(E, "malformed immediate expression");
3950    return MatchOperand_ParseFail;
3951  }
3952  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
3953  if (!CE) {
3954    Error(E, "'lsb' operand must be an immediate");
3955    return MatchOperand_ParseFail;
3956  }
3957
3958  int64_t LSB = CE->getValue();
3959  // The LSB must be in the range [0,31]
3960  if (LSB < 0 || LSB > 31) {
3961    Error(E, "'lsb' operand must be in the range [0,31]");
3962    return MatchOperand_ParseFail;
3963  }
3964  E = Parser.getTok().getLoc();
3965
3966  // Expect another immediate operand.
3967  if (Parser.getTok().isNot(AsmToken::Comma)) {
3968    Error(Parser.getTok().getLoc(), "too few operands");
3969    return MatchOperand_ParseFail;
3970  }
3971  Parser.Lex(); // Eat hash token.
3972  if (Parser.getTok().isNot(AsmToken::Hash) &&
3973      Parser.getTok().isNot(AsmToken::Dollar)) {
3974    Error(Parser.getTok().getLoc(), "'#' expected");
3975    return MatchOperand_ParseFail;
3976  }
3977  Parser.Lex(); // Eat hash token.
3978
3979  const MCExpr *WidthExpr;
3980  SMLoc EndLoc;
3981  if (getParser().parseExpression(WidthExpr, EndLoc)) {
3982    Error(E, "malformed immediate expression");
3983    return MatchOperand_ParseFail;
3984  }
3985  CE = dyn_cast<MCConstantExpr>(WidthExpr);
3986  if (!CE) {
3987    Error(E, "'width' operand must be an immediate");
3988    return MatchOperand_ParseFail;
3989  }
3990
3991  int64_t Width = CE->getValue();
3992  // The LSB must be in the range [1,32-lsb]
3993  if (Width < 1 || Width > 32 - LSB) {
3994    Error(E, "'width' operand must be in the range [1,32-lsb]");
3995    return MatchOperand_ParseFail;
3996  }
3997
3998  Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc));
3999
4000  return MatchOperand_Success;
4001}
4002
4003ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4004parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4005  // Check for a post-index addressing register operand. Specifically:
4006  // postidx_reg := '+' register {, shift}
4007  //              | '-' register {, shift}
4008  //              | register {, shift}
4009
4010  // This method must return MatchOperand_NoMatch without consuming any tokens
4011  // in the case where there is no match, as other alternatives take other
4012  // parse methods.
4013  AsmToken Tok = Parser.getTok();
4014  SMLoc S = Tok.getLoc();
4015  bool haveEaten = false;
4016  bool isAdd = true;
4017  if (Tok.is(AsmToken::Plus)) {
4018    Parser.Lex(); // Eat the '+' token.
4019    haveEaten = true;
4020  } else if (Tok.is(AsmToken::Minus)) {
4021    Parser.Lex(); // Eat the '-' token.
4022    isAdd = false;
4023    haveEaten = true;
4024  }
4025
4026  SMLoc E = Parser.getTok().getEndLoc();
4027  int Reg = tryParseRegister();
4028  if (Reg == -1) {
4029    if (!haveEaten)
4030      return MatchOperand_NoMatch;
4031    Error(Parser.getTok().getLoc(), "register expected");
4032    return MatchOperand_ParseFail;
4033  }
4034
4035  ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
4036  unsigned ShiftImm = 0;
4037  if (Parser.getTok().is(AsmToken::Comma)) {
4038    Parser.Lex(); // Eat the ','.
4039    if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
4040      return MatchOperand_ParseFail;
4041
4042    // FIXME: Only approximates end...may include intervening whitespace.
4043    E = Parser.getTok().getLoc();
4044  }
4045
4046  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
4047                                                  ShiftImm, S, E));
4048
4049  return MatchOperand_Success;
4050}
4051
4052ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4053parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4054  // Check for a post-index addressing register operand. Specifically:
4055  // am3offset := '+' register
4056  //              | '-' register
4057  //              | register
4058  //              | # imm
4059  //              | # + imm
4060  //              | # - imm
4061
4062  // This method must return MatchOperand_NoMatch without consuming any tokens
4063  // in the case where there is no match, as other alternatives take other
4064  // parse methods.
4065  AsmToken Tok = Parser.getTok();
4066  SMLoc S = Tok.getLoc();
4067
4068  // Do immediates first, as we always parse those if we have a '#'.
4069  if (Parser.getTok().is(AsmToken::Hash) ||
4070      Parser.getTok().is(AsmToken::Dollar)) {
4071    Parser.Lex(); // Eat '#' or '$'.
4072    // Explicitly look for a '-', as we need to encode negative zero
4073    // differently.
4074    bool isNegative = Parser.getTok().is(AsmToken::Minus);
4075    const MCExpr *Offset;
4076    SMLoc E;
4077    if (getParser().parseExpression(Offset, E))
4078      return MatchOperand_ParseFail;
4079    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4080    if (!CE) {
4081      Error(S, "constant expression expected");
4082      return MatchOperand_ParseFail;
4083    }
4084    // Negative zero is encoded as the flag value INT32_MIN.
4085    int32_t Val = CE->getValue();
4086    if (isNegative && Val == 0)
4087      Val = INT32_MIN;
4088
4089    Operands.push_back(
4090      ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
4091
4092    return MatchOperand_Success;
4093  }
4094
4095
4096  bool haveEaten = false;
4097  bool isAdd = true;
4098  if (Tok.is(AsmToken::Plus)) {
4099    Parser.Lex(); // Eat the '+' token.
4100    haveEaten = true;
4101  } else if (Tok.is(AsmToken::Minus)) {
4102    Parser.Lex(); // Eat the '-' token.
4103    isAdd = false;
4104    haveEaten = true;
4105  }
4106
4107  Tok = Parser.getTok();
4108  int Reg = tryParseRegister();
4109  if (Reg == -1) {
4110    if (!haveEaten)
4111      return MatchOperand_NoMatch;
4112    Error(Tok.getLoc(), "register expected");
4113    return MatchOperand_ParseFail;
4114  }
4115
4116  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
4117                                                  0, S, Tok.getEndLoc()));
4118
4119  return MatchOperand_Success;
4120}
4121
4122/// Convert parsed operands to MCInst.  Needed here because this instruction
4123/// only has two register operands, but multiplication is commutative so
4124/// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN".
4125void ARMAsmParser::
4126cvtThumbMultiply(MCInst &Inst,
4127           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4128  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4129  ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
4130  // If we have a three-operand form, make sure to set Rn to be the operand
4131  // that isn't the same as Rd.
4132  unsigned RegOp = 4;
4133  if (Operands.size() == 6 &&
4134      ((ARMOperand*)Operands[4])->getReg() ==
4135        ((ARMOperand*)Operands[3])->getReg())
4136    RegOp = 5;
4137  ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1);
4138  Inst.addOperand(Inst.getOperand(0));
4139  ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
4140}
4141
4142void ARMAsmParser::
4143cvtThumbBranches(MCInst &Inst,
4144           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4145  int CondOp = -1, ImmOp = -1;
4146  switch(Inst.getOpcode()) {
4147    case ARM::tB:
4148    case ARM::tBcc:  CondOp = 1; ImmOp = 2; break;
4149
4150    case ARM::t2B:
4151    case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break;
4152
4153    default: llvm_unreachable("Unexpected instruction in cvtThumbBranches");
4154  }
4155  // first decide whether or not the branch should be conditional
4156  // by looking at it's location relative to an IT block
4157  if(inITBlock()) {
4158    // inside an IT block we cannot have any conditional branches. any
4159    // such instructions needs to be converted to unconditional form
4160    switch(Inst.getOpcode()) {
4161      case ARM::tBcc: Inst.setOpcode(ARM::tB); break;
4162      case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break;
4163    }
4164  } else {
4165    // outside IT blocks we can only have unconditional branches with AL
4166    // condition code or conditional branches with non-AL condition code
4167    unsigned Cond = static_cast<ARMOperand*>(Operands[CondOp])->getCondCode();
4168    switch(Inst.getOpcode()) {
4169      case ARM::tB:
4170      case ARM::tBcc:
4171        Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc);
4172        break;
4173      case ARM::t2B:
4174      case ARM::t2Bcc:
4175        Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc);
4176        break;
4177    }
4178  }
4179
4180  // now decide on encoding size based on branch target range
4181  switch(Inst.getOpcode()) {
4182    // classify tB as either t2B or t1B based on range of immediate operand
4183    case ARM::tB: {
4184      ARMOperand* op = static_cast<ARMOperand*>(Operands[ImmOp]);
4185      if(!op->isSignedOffset<11, 1>() && isThumbTwo())
4186        Inst.setOpcode(ARM::t2B);
4187      break;
4188    }
4189    // classify tBcc as either t2Bcc or t1Bcc based on range of immediate operand
4190    case ARM::tBcc: {
4191      ARMOperand* op = static_cast<ARMOperand*>(Operands[ImmOp]);
4192      if(!op->isSignedOffset<8, 1>() && isThumbTwo())
4193        Inst.setOpcode(ARM::t2Bcc);
4194      break;
4195    }
4196  }
4197  ((ARMOperand*)Operands[ImmOp])->addImmOperands(Inst, 1);
4198  ((ARMOperand*)Operands[CondOp])->addCondCodeOperands(Inst, 2);
4199}
4200
4201/// Parse an ARM memory expression, return false if successful else return true
4202/// or an error.  The first token must be a '[' when called.
4203bool ARMAsmParser::
4204parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4205  SMLoc S, E;
4206  assert(Parser.getTok().is(AsmToken::LBrac) &&
4207         "Token is not a Left Bracket");
4208  S = Parser.getTok().getLoc();
4209  Parser.Lex(); // Eat left bracket token.
4210
4211  const AsmToken &BaseRegTok = Parser.getTok();
4212  int BaseRegNum = tryParseRegister();
4213  if (BaseRegNum == -1)
4214    return Error(BaseRegTok.getLoc(), "register expected");
4215
4216  // The next token must either be a comma, a colon or a closing bracket.
4217  const AsmToken &Tok = Parser.getTok();
4218  if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) &&
4219      !Tok.is(AsmToken::RBrac))
4220    return Error(Tok.getLoc(), "malformed memory operand");
4221
4222  if (Tok.is(AsmToken::RBrac)) {
4223    E = Tok.getEndLoc();
4224    Parser.Lex(); // Eat right bracket token.
4225
4226    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
4227                                             0, 0, false, S, E));
4228
4229    // If there's a pre-indexing writeback marker, '!', just add it as a token
4230    // operand. It's rather odd, but syntactically valid.
4231    if (Parser.getTok().is(AsmToken::Exclaim)) {
4232      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4233      Parser.Lex(); // Eat the '!'.
4234    }
4235
4236    return false;
4237  }
4238
4239  assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) &&
4240         "Lost colon or comma in memory operand?!");
4241  if (Tok.is(AsmToken::Comma)) {
4242    Parser.Lex(); // Eat the comma.
4243  }
4244
4245  // If we have a ':', it's an alignment specifier.
4246  if (Parser.getTok().is(AsmToken::Colon)) {
4247    Parser.Lex(); // Eat the ':'.
4248    E = Parser.getTok().getLoc();
4249
4250    const MCExpr *Expr;
4251    if (getParser().parseExpression(Expr))
4252     return true;
4253
4254    // The expression has to be a constant. Memory references with relocations
4255    // don't come through here, as they use the <label> forms of the relevant
4256    // instructions.
4257    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4258    if (!CE)
4259      return Error (E, "constant expression expected");
4260
4261    unsigned Align = 0;
4262    switch (CE->getValue()) {
4263    default:
4264      return Error(E,
4265                   "alignment specifier must be 16, 32, 64, 128, or 256 bits");
4266    case 16:  Align = 2; break;
4267    case 32:  Align = 4; break;
4268    case 64:  Align = 8; break;
4269    case 128: Align = 16; break;
4270    case 256: Align = 32; break;
4271    }
4272
4273    // Now we should have the closing ']'
4274    if (Parser.getTok().isNot(AsmToken::RBrac))
4275      return Error(Parser.getTok().getLoc(), "']' expected");
4276    E = Parser.getTok().getEndLoc();
4277    Parser.Lex(); // Eat right bracket token.
4278
4279    // Don't worry about range checking the value here. That's handled by
4280    // the is*() predicates.
4281    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0,
4282                                             ARM_AM::no_shift, 0, Align,
4283                                             false, S, E));
4284
4285    // If there's a pre-indexing writeback marker, '!', just add it as a token
4286    // operand.
4287    if (Parser.getTok().is(AsmToken::Exclaim)) {
4288      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4289      Parser.Lex(); // Eat the '!'.
4290    }
4291
4292    return false;
4293  }
4294
4295  // If we have a '#', it's an immediate offset, else assume it's a register
4296  // offset. Be friendly and also accept a plain integer (without a leading
4297  // hash) for gas compatibility.
4298  if (Parser.getTok().is(AsmToken::Hash) ||
4299      Parser.getTok().is(AsmToken::Dollar) ||
4300      Parser.getTok().is(AsmToken::Integer)) {
4301    if (Parser.getTok().isNot(AsmToken::Integer))
4302      Parser.Lex(); // Eat '#' or '$'.
4303    E = Parser.getTok().getLoc();
4304
4305    bool isNegative = getParser().getTok().is(AsmToken::Minus);
4306    const MCExpr *Offset;
4307    if (getParser().parseExpression(Offset))
4308     return true;
4309
4310    // The expression has to be a constant. Memory references with relocations
4311    // don't come through here, as they use the <label> forms of the relevant
4312    // instructions.
4313    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4314    if (!CE)
4315      return Error (E, "constant expression expected");
4316
4317    // If the constant was #-0, represent it as INT32_MIN.
4318    int32_t Val = CE->getValue();
4319    if (isNegative && Val == 0)
4320      CE = MCConstantExpr::Create(INT32_MIN, getContext());
4321
4322    // Now we should have the closing ']'
4323    if (Parser.getTok().isNot(AsmToken::RBrac))
4324      return Error(Parser.getTok().getLoc(), "']' expected");
4325    E = Parser.getTok().getEndLoc();
4326    Parser.Lex(); // Eat right bracket token.
4327
4328    // Don't worry about range checking the value here. That's handled by
4329    // the is*() predicates.
4330    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
4331                                             ARM_AM::no_shift, 0, 0,
4332                                             false, S, E));
4333
4334    // If there's a pre-indexing writeback marker, '!', just add it as a token
4335    // operand.
4336    if (Parser.getTok().is(AsmToken::Exclaim)) {
4337      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4338      Parser.Lex(); // Eat the '!'.
4339    }
4340
4341    return false;
4342  }
4343
4344  // The register offset is optionally preceded by a '+' or '-'
4345  bool isNegative = false;
4346  if (Parser.getTok().is(AsmToken::Minus)) {
4347    isNegative = true;
4348    Parser.Lex(); // Eat the '-'.
4349  } else if (Parser.getTok().is(AsmToken::Plus)) {
4350    // Nothing to do.
4351    Parser.Lex(); // Eat the '+'.
4352  }
4353
4354  E = Parser.getTok().getLoc();
4355  int OffsetRegNum = tryParseRegister();
4356  if (OffsetRegNum == -1)
4357    return Error(E, "register expected");
4358
4359  // If there's a shift operator, handle it.
4360  ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
4361  unsigned ShiftImm = 0;
4362  if (Parser.getTok().is(AsmToken::Comma)) {
4363    Parser.Lex(); // Eat the ','.
4364    if (parseMemRegOffsetShift(ShiftType, ShiftImm))
4365      return true;
4366  }
4367
4368  // Now we should have the closing ']'
4369  if (Parser.getTok().isNot(AsmToken::RBrac))
4370    return Error(Parser.getTok().getLoc(), "']' expected");
4371  E = Parser.getTok().getEndLoc();
4372  Parser.Lex(); // Eat right bracket token.
4373
4374  Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
4375                                           ShiftType, ShiftImm, 0, isNegative,
4376                                           S, E));
4377
4378  // If there's a pre-indexing writeback marker, '!', just add it as a token
4379  // operand.
4380  if (Parser.getTok().is(AsmToken::Exclaim)) {
4381    Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4382    Parser.Lex(); // Eat the '!'.
4383  }
4384
4385  return false;
4386}
4387
4388/// parseMemRegOffsetShift - one of these two:
4389///   ( lsl | lsr | asr | ror ) , # shift_amount
4390///   rrx
4391/// return true if it parses a shift otherwise it returns false.
4392bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
4393                                          unsigned &Amount) {
4394  SMLoc Loc = Parser.getTok().getLoc();
4395  const AsmToken &Tok = Parser.getTok();
4396  if (Tok.isNot(AsmToken::Identifier))
4397    return true;
4398  StringRef ShiftName = Tok.getString();
4399  if (ShiftName == "lsl" || ShiftName == "LSL" ||
4400      ShiftName == "asl" || ShiftName == "ASL")
4401    St = ARM_AM::lsl;
4402  else if (ShiftName == "lsr" || ShiftName == "LSR")
4403    St = ARM_AM::lsr;
4404  else if (ShiftName == "asr" || ShiftName == "ASR")
4405    St = ARM_AM::asr;
4406  else if (ShiftName == "ror" || ShiftName == "ROR")
4407    St = ARM_AM::ror;
4408  else if (ShiftName == "rrx" || ShiftName == "RRX")
4409    St = ARM_AM::rrx;
4410  else
4411    return Error(Loc, "illegal shift operator");
4412  Parser.Lex(); // Eat shift type token.
4413
4414  // rrx stands alone.
4415  Amount = 0;
4416  if (St != ARM_AM::rrx) {
4417    Loc = Parser.getTok().getLoc();
4418    // A '#' and a shift amount.
4419    const AsmToken &HashTok = Parser.getTok();
4420    if (HashTok.isNot(AsmToken::Hash) &&
4421        HashTok.isNot(AsmToken::Dollar))
4422      return Error(HashTok.getLoc(), "'#' expected");
4423    Parser.Lex(); // Eat hash token.
4424
4425    const MCExpr *Expr;
4426    if (getParser().parseExpression(Expr))
4427      return true;
4428    // Range check the immediate.
4429    // lsl, ror: 0 <= imm <= 31
4430    // lsr, asr: 0 <= imm <= 32
4431    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4432    if (!CE)
4433      return Error(Loc, "shift amount must be an immediate");
4434    int64_t Imm = CE->getValue();
4435    if (Imm < 0 ||
4436        ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
4437        ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
4438      return Error(Loc, "immediate shift value out of range");
4439    // If <ShiftTy> #0, turn it into a no_shift.
4440    if (Imm == 0)
4441      St = ARM_AM::lsl;
4442    // For consistency, treat lsr #32 and asr #32 as having immediate value 0.
4443    if (Imm == 32)
4444      Imm = 0;
4445    Amount = Imm;
4446  }
4447
4448  return false;
4449}
4450
4451/// parseFPImm - A floating point immediate expression operand.
4452ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4453parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4454  // Anything that can accept a floating point constant as an operand
4455  // needs to go through here, as the regular parseExpression is
4456  // integer only.
4457  //
4458  // This routine still creates a generic Immediate operand, containing
4459  // a bitcast of the 64-bit floating point value. The various operands
4460  // that accept floats can check whether the value is valid for them
4461  // via the standard is*() predicates.
4462
4463  SMLoc S = Parser.getTok().getLoc();
4464
4465  if (Parser.getTok().isNot(AsmToken::Hash) &&
4466      Parser.getTok().isNot(AsmToken::Dollar))
4467    return MatchOperand_NoMatch;
4468
4469  // Disambiguate the VMOV forms that can accept an FP immediate.
4470  // vmov.f32 <sreg>, #imm
4471  // vmov.f64 <dreg>, #imm
4472  // vmov.f32 <dreg>, #imm  @ vector f32x2
4473  // vmov.f32 <qreg>, #imm  @ vector f32x4
4474  //
4475  // There are also the NEON VMOV instructions which expect an
4476  // integer constant. Make sure we don't try to parse an FPImm
4477  // for these:
4478  // vmov.i{8|16|32|64} <dreg|qreg>, #imm
4479  ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]);
4480  if (!TyOp->isToken() || (TyOp->getToken() != ".f32" &&
4481                           TyOp->getToken() != ".f64"))
4482    return MatchOperand_NoMatch;
4483
4484  Parser.Lex(); // Eat '#' or '$'.
4485
4486  // Handle negation, as that still comes through as a separate token.
4487  bool isNegative = false;
4488  if (Parser.getTok().is(AsmToken::Minus)) {
4489    isNegative = true;
4490    Parser.Lex();
4491  }
4492  const AsmToken &Tok = Parser.getTok();
4493  SMLoc Loc = Tok.getLoc();
4494  if (Tok.is(AsmToken::Real)) {
4495    APFloat RealVal(APFloat::IEEEsingle, Tok.getString());
4496    uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
4497    // If we had a '-' in front, toggle the sign bit.
4498    IntVal ^= (uint64_t)isNegative << 31;
4499    Parser.Lex(); // Eat the token.
4500    Operands.push_back(ARMOperand::CreateImm(
4501          MCConstantExpr::Create(IntVal, getContext()),
4502          S, Parser.getTok().getLoc()));
4503    return MatchOperand_Success;
4504  }
4505  // Also handle plain integers. Instructions which allow floating point
4506  // immediates also allow a raw encoded 8-bit value.
4507  if (Tok.is(AsmToken::Integer)) {
4508    int64_t Val = Tok.getIntVal();
4509    Parser.Lex(); // Eat the token.
4510    if (Val > 255 || Val < 0) {
4511      Error(Loc, "encoded floating point value out of range");
4512      return MatchOperand_ParseFail;
4513    }
4514    double RealVal = ARM_AM::getFPImmFloat(Val);
4515    Val = APFloat(APFloat::IEEEdouble, RealVal).bitcastToAPInt().getZExtValue();
4516    Operands.push_back(ARMOperand::CreateImm(
4517        MCConstantExpr::Create(Val, getContext()), S,
4518        Parser.getTok().getLoc()));
4519    return MatchOperand_Success;
4520  }
4521
4522  Error(Loc, "invalid floating point immediate");
4523  return MatchOperand_ParseFail;
4524}
4525
4526/// Parse a arm instruction operand.  For now this parses the operand regardless
4527/// of the mnemonic.
4528bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
4529                                StringRef Mnemonic) {
4530  SMLoc S, E;
4531
4532  // Check if the current operand has a custom associated parser, if so, try to
4533  // custom parse the operand, or fallback to the general approach.
4534  OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
4535  if (ResTy == MatchOperand_Success)
4536    return false;
4537  // If there wasn't a custom match, try the generic matcher below. Otherwise,
4538  // there was a match, but an error occurred, in which case, just return that
4539  // the operand parsing failed.
4540  if (ResTy == MatchOperand_ParseFail)
4541    return true;
4542
4543  switch (getLexer().getKind()) {
4544  default:
4545    Error(Parser.getTok().getLoc(), "unexpected token in operand");
4546    return true;
4547  case AsmToken::Identifier: {
4548    // If we've seen a branch mnemonic, the next operand must be a label.  This
4549    // is true even if the label is a register name.  So "br r1" means branch to
4550    // label "r1".
4551    bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl";
4552    if (!ExpectLabel) {
4553      if (!tryParseRegisterWithWriteBack(Operands))
4554        return false;
4555      int Res = tryParseShiftRegister(Operands);
4556      if (Res == 0) // success
4557        return false;
4558      else if (Res == -1) // irrecoverable error
4559        return true;
4560      // If this is VMRS, check for the apsr_nzcv operand.
4561      if (Mnemonic == "vmrs" &&
4562          Parser.getTok().getString().equals_lower("apsr_nzcv")) {
4563        S = Parser.getTok().getLoc();
4564        Parser.Lex();
4565        Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
4566        return false;
4567      }
4568    }
4569
4570    // Fall though for the Identifier case that is not a register or a
4571    // special name.
4572  }
4573  case AsmToken::LParen:  // parenthesized expressions like (_strcmp-4)
4574  case AsmToken::Integer: // things like 1f and 2b as a branch targets
4575  case AsmToken::String:  // quoted label names.
4576  case AsmToken::Dot: {   // . as a branch target
4577    // This was not a register so parse other operands that start with an
4578    // identifier (like labels) as expressions and create them as immediates.
4579    const MCExpr *IdVal;
4580    S = Parser.getTok().getLoc();
4581    if (getParser().parseExpression(IdVal))
4582      return true;
4583    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4584    Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
4585    return false;
4586  }
4587  case AsmToken::LBrac:
4588    return parseMemory(Operands);
4589  case AsmToken::LCurly:
4590    return parseRegisterList(Operands);
4591  case AsmToken::Dollar:
4592  case AsmToken::Hash: {
4593    // #42 -> immediate.
4594    S = Parser.getTok().getLoc();
4595    Parser.Lex();
4596
4597    if (Parser.getTok().isNot(AsmToken::Colon)) {
4598      bool isNegative = Parser.getTok().is(AsmToken::Minus);
4599      const MCExpr *ImmVal;
4600      if (getParser().parseExpression(ImmVal))
4601        return true;
4602      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
4603      if (CE) {
4604        int32_t Val = CE->getValue();
4605        if (isNegative && Val == 0)
4606          ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
4607      }
4608      E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4609      Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
4610
4611      // There can be a trailing '!' on operands that we want as a separate
4612      // '!' Token operand. Handle that here. For example, the compatibilty
4613      // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'.
4614      if (Parser.getTok().is(AsmToken::Exclaim)) {
4615        Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(),
4616                                                   Parser.getTok().getLoc()));
4617        Parser.Lex(); // Eat exclaim token
4618      }
4619      return false;
4620    }
4621    // w/ a ':' after the '#', it's just like a plain ':'.
4622    // FALLTHROUGH
4623  }
4624  case AsmToken::Colon: {
4625    // ":lower16:" and ":upper16:" expression prefixes
4626    // FIXME: Check it's an expression prefix,
4627    // e.g. (FOO - :lower16:BAR) isn't legal.
4628    ARMMCExpr::VariantKind RefKind;
4629    if (parsePrefix(RefKind))
4630      return true;
4631
4632    const MCExpr *SubExprVal;
4633    if (getParser().parseExpression(SubExprVal))
4634      return true;
4635
4636    const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
4637                                              getContext());
4638    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4639    Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
4640    return false;
4641  }
4642  }
4643}
4644
4645// parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
4646//  :lower16: and :upper16:.
4647bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
4648  RefKind = ARMMCExpr::VK_ARM_None;
4649
4650  // :lower16: and :upper16: modifiers
4651  assert(getLexer().is(AsmToken::Colon) && "expected a :");
4652  Parser.Lex(); // Eat ':'
4653
4654  if (getLexer().isNot(AsmToken::Identifier)) {
4655    Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
4656    return true;
4657  }
4658
4659  StringRef IDVal = Parser.getTok().getIdentifier();
4660  if (IDVal == "lower16") {
4661    RefKind = ARMMCExpr::VK_ARM_LO16;
4662  } else if (IDVal == "upper16") {
4663    RefKind = ARMMCExpr::VK_ARM_HI16;
4664  } else {
4665    Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
4666    return true;
4667  }
4668  Parser.Lex();
4669
4670  if (getLexer().isNot(AsmToken::Colon)) {
4671    Error(Parser.getTok().getLoc(), "unexpected token after prefix");
4672    return true;
4673  }
4674  Parser.Lex(); // Eat the last ':'
4675  return false;
4676}
4677
4678/// \brief Given a mnemonic, split out possible predication code and carry
4679/// setting letters to form a canonical mnemonic and flags.
4680//
4681// FIXME: Would be nice to autogen this.
4682// FIXME: This is a bit of a maze of special cases.
4683StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
4684                                      unsigned &PredicationCode,
4685                                      bool &CarrySetting,
4686                                      unsigned &ProcessorIMod,
4687                                      StringRef &ITMask) {
4688  PredicationCode = ARMCC::AL;
4689  CarrySetting = false;
4690  ProcessorIMod = 0;
4691
4692  // Ignore some mnemonics we know aren't predicated forms.
4693  //
4694  // FIXME: Would be nice to autogen this.
4695  if ((Mnemonic == "movs" && isThumb()) ||
4696      Mnemonic == "teq"   || Mnemonic == "vceq"   || Mnemonic == "svc"   ||
4697      Mnemonic == "mls"   || Mnemonic == "smmls"  || Mnemonic == "vcls"  ||
4698      Mnemonic == "vmls"  || Mnemonic == "vnmls"  || Mnemonic == "vacge" ||
4699      Mnemonic == "vcge"  || Mnemonic == "vclt"   || Mnemonic == "vacgt" ||
4700      Mnemonic == "vaclt" || Mnemonic == "vacle"  || Mnemonic == "hlt" ||
4701      Mnemonic == "vcgt"  || Mnemonic == "vcle"   || Mnemonic == "smlal" ||
4702      Mnemonic == "umaal" || Mnemonic == "umlal"  || Mnemonic == "vabal" ||
4703      Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
4704      Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" ||
4705      Mnemonic == "vcvta" || Mnemonic == "vcvtn"  || Mnemonic == "vcvtp" ||
4706      Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" ||
4707      Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic.startswith("vsel"))
4708    return Mnemonic;
4709
4710  // First, split out any predication code. Ignore mnemonics we know aren't
4711  // predicated but do have a carry-set and so weren't caught above.
4712  if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
4713      Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
4714      Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
4715      Mnemonic != "sbcs" && Mnemonic != "rscs") {
4716    unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
4717      .Case("eq", ARMCC::EQ)
4718      .Case("ne", ARMCC::NE)
4719      .Case("hs", ARMCC::HS)
4720      .Case("cs", ARMCC::HS)
4721      .Case("lo", ARMCC::LO)
4722      .Case("cc", ARMCC::LO)
4723      .Case("mi", ARMCC::MI)
4724      .Case("pl", ARMCC::PL)
4725      .Case("vs", ARMCC::VS)
4726      .Case("vc", ARMCC::VC)
4727      .Case("hi", ARMCC::HI)
4728      .Case("ls", ARMCC::LS)
4729      .Case("ge", ARMCC::GE)
4730      .Case("lt", ARMCC::LT)
4731      .Case("gt", ARMCC::GT)
4732      .Case("le", ARMCC::LE)
4733      .Case("al", ARMCC::AL)
4734      .Default(~0U);
4735    if (CC != ~0U) {
4736      Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
4737      PredicationCode = CC;
4738    }
4739  }
4740
4741  // Next, determine if we have a carry setting bit. We explicitly ignore all
4742  // the instructions we know end in 's'.
4743  if (Mnemonic.endswith("s") &&
4744      !(Mnemonic == "cps" || Mnemonic == "mls" ||
4745        Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
4746        Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
4747        Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
4748        Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
4749        Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
4750        Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
4751        Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
4752        Mnemonic == "vfms" || Mnemonic == "vfnms" ||
4753        (Mnemonic == "movs" && isThumb()))) {
4754    Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
4755    CarrySetting = true;
4756  }
4757
4758  // The "cps" instruction can have a interrupt mode operand which is glued into
4759  // the mnemonic. Check if this is the case, split it and parse the imod op
4760  if (Mnemonic.startswith("cps")) {
4761    // Split out any imod code.
4762    unsigned IMod =
4763      StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
4764      .Case("ie", ARM_PROC::IE)
4765      .Case("id", ARM_PROC::ID)
4766      .Default(~0U);
4767    if (IMod != ~0U) {
4768      Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
4769      ProcessorIMod = IMod;
4770    }
4771  }
4772
4773  // The "it" instruction has the condition mask on the end of the mnemonic.
4774  if (Mnemonic.startswith("it")) {
4775    ITMask = Mnemonic.slice(2, Mnemonic.size());
4776    Mnemonic = Mnemonic.slice(0, 2);
4777  }
4778
4779  return Mnemonic;
4780}
4781
4782/// \brief Given a canonical mnemonic, determine if the instruction ever allows
4783/// inclusion of carry set or predication code operands.
4784//
4785// FIXME: It would be nice to autogen this.
4786void ARMAsmParser::
4787getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
4788                      bool &CanAcceptPredicationCode) {
4789  if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
4790      Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
4791      Mnemonic == "add" || Mnemonic == "adc" ||
4792      Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
4793      Mnemonic == "orr" || Mnemonic == "mvn" ||
4794      Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
4795      Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
4796      Mnemonic == "vfm" || Mnemonic == "vfnm" ||
4797      (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
4798                      Mnemonic == "mla" || Mnemonic == "smlal" ||
4799                      Mnemonic == "umlal" || Mnemonic == "umull"))) {
4800    CanAcceptCarrySet = true;
4801  } else
4802    CanAcceptCarrySet = false;
4803
4804  if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
4805      Mnemonic == "cps" ||  Mnemonic == "it" ||  Mnemonic == "cbz" ||
4806      Mnemonic == "trap" || Mnemonic == "hlt" ||
4807      Mnemonic.startswith("cps") || Mnemonic.startswith("vsel") ||
4808      Mnemonic == "vmaxnm" || Mnemonic == "vminnm" || Mnemonic == "vcvta" ||
4809      Mnemonic == "vcvtn" || Mnemonic == "vcvtp" || Mnemonic == "vcvtm" ||
4810      Mnemonic == "vrinta" || Mnemonic == "vrintn" || Mnemonic == "vrintp" ||
4811      Mnemonic == "vrintm") {
4812    // These mnemonics are never predicable
4813    CanAcceptPredicationCode = false;
4814  } else if (!isThumb()) {
4815    // Some instructions are only predicable in Thumb mode
4816    CanAcceptPredicationCode
4817      = Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" &&
4818        Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" &&
4819        Mnemonic != "dmb" && Mnemonic != "dsb" && Mnemonic != "isb" &&
4820        Mnemonic != "pld" && Mnemonic != "pli" && Mnemonic != "pldw" &&
4821        Mnemonic != "ldc2" && Mnemonic != "ldc2l" &&
4822        Mnemonic != "stc2" && Mnemonic != "stc2l" &&
4823        !Mnemonic.startswith("rfe") && !Mnemonic.startswith("srs");
4824  } else if (isThumbOne()) {
4825    CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs";
4826  } else
4827    CanAcceptPredicationCode = true;
4828}
4829
4830bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
4831                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4832  // FIXME: This is all horribly hacky. We really need a better way to deal
4833  // with optional operands like this in the matcher table.
4834
4835  // The 'mov' mnemonic is special. One variant has a cc_out operand, while
4836  // another does not. Specifically, the MOVW instruction does not. So we
4837  // special case it here and remove the defaulted (non-setting) cc_out
4838  // operand if that's the instruction we're trying to match.
4839  //
4840  // We do this as post-processing of the explicit operands rather than just
4841  // conditionally adding the cc_out in the first place because we need
4842  // to check the type of the parsed immediate operand.
4843  if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
4844      !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
4845      static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
4846      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4847    return true;
4848
4849  // Register-register 'add' for thumb does not have a cc_out operand
4850  // when there are only two register operands.
4851  if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
4852      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4853      static_cast<ARMOperand*>(Operands[4])->isReg() &&
4854      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4855    return true;
4856  // Register-register 'add' for thumb does not have a cc_out operand
4857  // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
4858  // have to check the immediate range here since Thumb2 has a variant
4859  // that can handle a different range and has a cc_out operand.
4860  if (((isThumb() && Mnemonic == "add") ||
4861       (isThumbTwo() && Mnemonic == "sub")) &&
4862      Operands.size() == 6 &&
4863      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4864      static_cast<ARMOperand*>(Operands[4])->isReg() &&
4865      static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
4866      static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4867      ((Mnemonic == "add" &&static_cast<ARMOperand*>(Operands[5])->isReg()) ||
4868       static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
4869    return true;
4870  // For Thumb2, add/sub immediate does not have a cc_out operand for the
4871  // imm0_4095 variant. That's the least-preferred variant when
4872  // selecting via the generic "add" mnemonic, so to know that we
4873  // should remove the cc_out operand, we have to explicitly check that
4874  // it's not one of the other variants. Ugh.
4875  if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
4876      Operands.size() == 6 &&
4877      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4878      static_cast<ARMOperand*>(Operands[4])->isReg() &&
4879      static_cast<ARMOperand*>(Operands[5])->isImm()) {
4880    // Nest conditions rather than one big 'if' statement for readability.
4881    //
4882    // If both registers are low, we're in an IT block, and the immediate is
4883    // in range, we should use encoding T1 instead, which has a cc_out.
4884    if (inITBlock() &&
4885        isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
4886        isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
4887        static_cast<ARMOperand*>(Operands[5])->isImm0_7())
4888      return false;
4889    // Check against T3. If the second register is the PC, this is an
4890    // alternate form of ADR, which uses encoding T4, so check for that too.
4891    if (static_cast<ARMOperand*>(Operands[4])->getReg() != ARM::PC &&
4892        static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
4893      return false;
4894
4895    // Otherwise, we use encoding T4, which does not have a cc_out
4896    // operand.
4897    return true;
4898  }
4899
4900  // The thumb2 multiply instruction doesn't have a CCOut register, so
4901  // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
4902  // use the 16-bit encoding or not.
4903  if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
4904      static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4905      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4906      static_cast<ARMOperand*>(Operands[4])->isReg() &&
4907      static_cast<ARMOperand*>(Operands[5])->isReg() &&
4908      // If the registers aren't low regs, the destination reg isn't the
4909      // same as one of the source regs, or the cc_out operand is zero
4910      // outside of an IT block, we have to use the 32-bit encoding, so
4911      // remove the cc_out operand.
4912      (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4913       !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4914       !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) ||
4915       !inITBlock() ||
4916       (static_cast<ARMOperand*>(Operands[3])->getReg() !=
4917        static_cast<ARMOperand*>(Operands[5])->getReg() &&
4918        static_cast<ARMOperand*>(Operands[3])->getReg() !=
4919        static_cast<ARMOperand*>(Operands[4])->getReg())))
4920    return true;
4921
4922  // Also check the 'mul' syntax variant that doesn't specify an explicit
4923  // destination register.
4924  if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
4925      static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4926      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4927      static_cast<ARMOperand*>(Operands[4])->isReg() &&
4928      // If the registers aren't low regs  or the cc_out operand is zero
4929      // outside of an IT block, we have to use the 32-bit encoding, so
4930      // remove the cc_out operand.
4931      (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4932       !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4933       !inITBlock()))
4934    return true;
4935
4936
4937
4938  // Register-register 'add/sub' for thumb does not have a cc_out operand
4939  // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
4940  // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
4941  // right, this will result in better diagnostics (which operand is off)
4942  // anyway.
4943  if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
4944      (Operands.size() == 5 || Operands.size() == 6) &&
4945      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4946      static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
4947      static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4948      (static_cast<ARMOperand*>(Operands[4])->isImm() ||
4949       (Operands.size() == 6 &&
4950        static_cast<ARMOperand*>(Operands[5])->isImm())))
4951    return true;
4952
4953  return false;
4954}
4955
4956bool ARMAsmParser::shouldOmitPredicateOperand(
4957    StringRef Mnemonic, SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
4958  // VRINT{Z, R, X} have a predicate operand in VFP, but not in NEON
4959  unsigned RegIdx = 3;
4960  if ((Mnemonic == "vrintz" || Mnemonic == "vrintx" || Mnemonic == "vrintr") &&
4961      static_cast<ARMOperand *>(Operands[2])->getToken() == ".f32") {
4962    if (static_cast<ARMOperand *>(Operands[3])->isToken() &&
4963        static_cast<ARMOperand *>(Operands[3])->getToken() == ".f32")
4964      RegIdx = 4;
4965
4966    if (static_cast<ARMOperand *>(Operands[RegIdx])->isReg() &&
4967        (ARMMCRegisterClasses[ARM::DPRRegClassID]
4968             .contains(static_cast<ARMOperand *>(Operands[RegIdx])->getReg()) ||
4969         ARMMCRegisterClasses[ARM::QPRRegClassID]
4970             .contains(static_cast<ARMOperand *>(Operands[RegIdx])->getReg())))
4971      return true;
4972  }
4973  return false;
4974}
4975
4976static bool isDataTypeToken(StringRef Tok) {
4977  return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
4978    Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
4979    Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
4980    Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
4981    Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
4982    Tok == ".f" || Tok == ".d";
4983}
4984
4985// FIXME: This bit should probably be handled via an explicit match class
4986// in the .td files that matches the suffix instead of having it be
4987// a literal string token the way it is now.
4988static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
4989  return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
4990}
4991static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features,
4992                                 unsigned VariantID);
4993/// Parse an arm instruction mnemonic followed by its operands.
4994bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
4995                                    SMLoc NameLoc,
4996                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4997  // Apply mnemonic aliases before doing anything else, as the destination
4998  // mnemnonic may include suffices and we want to handle them normally.
4999  // The generic tblgen'erated code does this later, at the start of
5000  // MatchInstructionImpl(), but that's too late for aliases that include
5001  // any sort of suffix.
5002  unsigned AvailableFeatures = getAvailableFeatures();
5003  unsigned AssemblerDialect = getParser().getAssemblerDialect();
5004  applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect);
5005
5006  // First check for the ARM-specific .req directive.
5007  if (Parser.getTok().is(AsmToken::Identifier) &&
5008      Parser.getTok().getIdentifier() == ".req") {
5009    parseDirectiveReq(Name, NameLoc);
5010    // We always return 'error' for this, as we're done with this
5011    // statement and don't need to match the 'instruction."
5012    return true;
5013  }
5014
5015  // Create the leading tokens for the mnemonic, split by '.' characters.
5016  size_t Start = 0, Next = Name.find('.');
5017  StringRef Mnemonic = Name.slice(Start, Next);
5018
5019  // Split out the predication code and carry setting flag from the mnemonic.
5020  unsigned PredicationCode;
5021  unsigned ProcessorIMod;
5022  bool CarrySetting;
5023  StringRef ITMask;
5024  Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
5025                           ProcessorIMod, ITMask);
5026
5027  // In Thumb1, only the branch (B) instruction can be predicated.
5028  if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
5029    Parser.eatToEndOfStatement();
5030    return Error(NameLoc, "conditional execution not supported in Thumb1");
5031  }
5032
5033  Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
5034
5035  // Handle the IT instruction ITMask. Convert it to a bitmask. This
5036  // is the mask as it will be for the IT encoding if the conditional
5037  // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
5038  // where the conditional bit0 is zero, the instruction post-processing
5039  // will adjust the mask accordingly.
5040  if (Mnemonic == "it") {
5041    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
5042    if (ITMask.size() > 3) {
5043      Parser.eatToEndOfStatement();
5044      return Error(Loc, "too many conditions on IT instruction");
5045    }
5046    unsigned Mask = 8;
5047    for (unsigned i = ITMask.size(); i != 0; --i) {
5048      char pos = ITMask[i - 1];
5049      if (pos != 't' && pos != 'e') {
5050        Parser.eatToEndOfStatement();
5051        return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
5052      }
5053      Mask >>= 1;
5054      if (ITMask[i - 1] == 't')
5055        Mask |= 8;
5056    }
5057    Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
5058  }
5059
5060  // FIXME: This is all a pretty gross hack. We should automatically handle
5061  // optional operands like this via tblgen.
5062
5063  // Next, add the CCOut and ConditionCode operands, if needed.
5064  //
5065  // For mnemonics which can ever incorporate a carry setting bit or predication
5066  // code, our matching model involves us always generating CCOut and
5067  // ConditionCode operands to match the mnemonic "as written" and then we let
5068  // the matcher deal with finding the right instruction or generating an
5069  // appropriate error.
5070  bool CanAcceptCarrySet, CanAcceptPredicationCode;
5071  getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
5072
5073  // If we had a carry-set on an instruction that can't do that, issue an
5074  // error.
5075  if (!CanAcceptCarrySet && CarrySetting) {
5076    Parser.eatToEndOfStatement();
5077    return Error(NameLoc, "instruction '" + Mnemonic +
5078                 "' can not set flags, but 's' suffix specified");
5079  }
5080  // If we had a predication code on an instruction that can't do that, issue an
5081  // error.
5082  if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
5083    Parser.eatToEndOfStatement();
5084    return Error(NameLoc, "instruction '" + Mnemonic +
5085                 "' is not predicable, but condition code specified");
5086  }
5087
5088  // Add the carry setting operand, if necessary.
5089  if (CanAcceptCarrySet) {
5090    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
5091    Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
5092                                               Loc));
5093  }
5094
5095  // Add the predication code operand, if necessary.
5096  if (CanAcceptPredicationCode) {
5097    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
5098                                      CarrySetting);
5099    Operands.push_back(ARMOperand::CreateCondCode(
5100                         ARMCC::CondCodes(PredicationCode), Loc));
5101  }
5102
5103  // Add the processor imod operand, if necessary.
5104  if (ProcessorIMod) {
5105    Operands.push_back(ARMOperand::CreateImm(
5106          MCConstantExpr::Create(ProcessorIMod, getContext()),
5107                                 NameLoc, NameLoc));
5108  }
5109
5110  // Add the remaining tokens in the mnemonic.
5111  while (Next != StringRef::npos) {
5112    Start = Next;
5113    Next = Name.find('.', Start + 1);
5114    StringRef ExtraToken = Name.slice(Start, Next);
5115
5116    // Some NEON instructions have an optional datatype suffix that is
5117    // completely ignored. Check for that.
5118    if (isDataTypeToken(ExtraToken) &&
5119        doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
5120      continue;
5121
5122    // For for ARM mode generate an error if the .n qualifier is used.
5123    if (ExtraToken == ".n" && !isThumb()) {
5124      SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5125      return Error(Loc, "instruction with .n (narrow) qualifier not allowed in "
5126                   "arm mode");
5127    }
5128
5129    // The .n qualifier is always discarded as that is what the tables
5130    // and matcher expect.  In ARM mode the .w qualifier has no effect,
5131    // so discard it to avoid errors that can be caused by the matcher.
5132    if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) {
5133      SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5134      Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
5135    }
5136  }
5137
5138  // Read the remaining operands.
5139  if (getLexer().isNot(AsmToken::EndOfStatement)) {
5140    // Read the first operand.
5141    if (parseOperand(Operands, Mnemonic)) {
5142      Parser.eatToEndOfStatement();
5143      return true;
5144    }
5145
5146    while (getLexer().is(AsmToken::Comma)) {
5147      Parser.Lex();  // Eat the comma.
5148
5149      // Parse and remember the operand.
5150      if (parseOperand(Operands, Mnemonic)) {
5151        Parser.eatToEndOfStatement();
5152        return true;
5153      }
5154    }
5155  }
5156
5157  if (getLexer().isNot(AsmToken::EndOfStatement)) {
5158    SMLoc Loc = getLexer().getLoc();
5159    Parser.eatToEndOfStatement();
5160    return Error(Loc, "unexpected token in argument list");
5161  }
5162
5163  Parser.Lex(); // Consume the EndOfStatement
5164
5165  // Some instructions, mostly Thumb, have forms for the same mnemonic that
5166  // do and don't have a cc_out optional-def operand. With some spot-checks
5167  // of the operand list, we can figure out which variant we're trying to
5168  // parse and adjust accordingly before actually matching. We shouldn't ever
5169  // try to remove a cc_out operand that was explicitly set on the the
5170  // mnemonic, of course (CarrySetting == true). Reason number #317 the
5171  // table driven matcher doesn't fit well with the ARM instruction set.
5172  if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
5173    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5174    Operands.erase(Operands.begin() + 1);
5175    delete Op;
5176  }
5177
5178  // Some instructions have the same mnemonic, but don't always
5179  // have a predicate. Distinguish them here and delete the
5180  // predicate if needed.
5181  if (shouldOmitPredicateOperand(Mnemonic, Operands)) {
5182    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5183    Operands.erase(Operands.begin() + 1);
5184    delete Op;
5185  }
5186
5187  // ARM mode 'blx' need special handling, as the register operand version
5188  // is predicable, but the label operand version is not. So, we can't rely
5189  // on the Mnemonic based checking to correctly figure out when to put
5190  // a k_CondCode operand in the list. If we're trying to match the label
5191  // version, remove the k_CondCode operand here.
5192  if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
5193      static_cast<ARMOperand*>(Operands[2])->isImm()) {
5194    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5195    Operands.erase(Operands.begin() + 1);
5196    delete Op;
5197  }
5198
5199  // Adjust operands of ldrexd/strexd to MCK_GPRPair.
5200  // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
5201  // a single GPRPair reg operand is used in the .td file to replace the two
5202  // GPRs. However, when parsing from asm, the two GRPs cannot be automatically
5203  // expressed as a GPRPair, so we have to manually merge them.
5204  // FIXME: We would really like to be able to tablegen'erate this.
5205  if (!isThumb() && Operands.size() > 4 &&
5206      (Mnemonic == "ldrexd" || Mnemonic == "strexd" || Mnemonic == "ldaexd" ||
5207       Mnemonic == "stlexd")) {
5208    bool isLoad = (Mnemonic == "ldrexd" || Mnemonic == "ldaexd");
5209    unsigned Idx = isLoad ? 2 : 3;
5210    ARMOperand* Op1 = static_cast<ARMOperand*>(Operands[Idx]);
5211    ARMOperand* Op2 = static_cast<ARMOperand*>(Operands[Idx+1]);
5212
5213    const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID);
5214    // Adjust only if Op1 and Op2 are GPRs.
5215    if (Op1->isReg() && Op2->isReg() && MRC.contains(Op1->getReg()) &&
5216        MRC.contains(Op2->getReg())) {
5217      unsigned Reg1 = Op1->getReg();
5218      unsigned Reg2 = Op2->getReg();
5219      unsigned Rt = MRI->getEncodingValue(Reg1);
5220      unsigned Rt2 = MRI->getEncodingValue(Reg2);
5221
5222      // Rt2 must be Rt + 1 and Rt must be even.
5223      if (Rt + 1 != Rt2 || (Rt & 1)) {
5224        Error(Op2->getStartLoc(), isLoad ?
5225            "destination operands must be sequential" :
5226            "source operands must be sequential");
5227        return true;
5228      }
5229      unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0,
5230          &(MRI->getRegClass(ARM::GPRPairRegClassID)));
5231      Operands.erase(Operands.begin() + Idx, Operands.begin() + Idx + 2);
5232      Operands.insert(Operands.begin() + Idx, ARMOperand::CreateReg(
5233            NewReg, Op1->getStartLoc(), Op2->getEndLoc()));
5234      delete Op1;
5235      delete Op2;
5236    }
5237  }
5238
5239  // FIXME: As said above, this is all a pretty gross hack.  This instruction
5240  // does not fit with other "subs" and tblgen.
5241  // Adjust operands of B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction
5242  // so the Mnemonic is the original name "subs" and delete the predicate
5243  // operand so it will match the table entry.
5244  if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 &&
5245      static_cast<ARMOperand*>(Operands[3])->isReg() &&
5246      static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::PC &&
5247      static_cast<ARMOperand*>(Operands[4])->isReg() &&
5248      static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::LR &&
5249      static_cast<ARMOperand*>(Operands[5])->isImm()) {
5250    ARMOperand *Op0 = static_cast<ARMOperand*>(Operands[0]);
5251    Operands.erase(Operands.begin());
5252    delete Op0;
5253    Operands.insert(Operands.begin(), ARMOperand::CreateToken(Name, NameLoc));
5254
5255    ARMOperand *Op1 = static_cast<ARMOperand*>(Operands[1]);
5256    Operands.erase(Operands.begin() + 1);
5257    delete Op1;
5258  }
5259  return false;
5260}
5261
5262// Validate context-sensitive operand constraints.
5263
5264// return 'true' if register list contains non-low GPR registers,
5265// 'false' otherwise. If Reg is in the register list or is HiReg, set
5266// 'containsReg' to true.
5267static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
5268                                 unsigned HiReg, bool &containsReg) {
5269  containsReg = false;
5270  for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5271    unsigned OpReg = Inst.getOperand(i).getReg();
5272    if (OpReg == Reg)
5273      containsReg = true;
5274    // Anything other than a low register isn't legal here.
5275    if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
5276      return true;
5277  }
5278  return false;
5279}
5280
5281// Check if the specified regisgter is in the register list of the inst,
5282// starting at the indicated operand number.
5283static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
5284  for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5285    unsigned OpReg = Inst.getOperand(i).getReg();
5286    if (OpReg == Reg)
5287      return true;
5288  }
5289  return false;
5290}
5291
5292// Return true if instruction has the interesting property of being
5293// allowed in IT blocks, but not being predicable.
5294static bool instIsBreakpoint(const MCInst &Inst) {
5295    return Inst.getOpcode() == ARM::tBKPT ||
5296           Inst.getOpcode() == ARM::BKPT ||
5297           Inst.getOpcode() == ARM::tHLT ||
5298           Inst.getOpcode() == ARM::HLT;
5299
5300}
5301
5302// FIXME: We would really like to be able to tablegen'erate this.
5303bool ARMAsmParser::
5304validateInstruction(MCInst &Inst,
5305                    const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5306  const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
5307  SMLoc Loc = Operands[0]->getStartLoc();
5308
5309  // Check the IT block state first.
5310  // NOTE: BKPT and HLT instructions have the interesting property of being
5311  // allowed in IT blocks, but not being predicable.  They just always
5312  // execute.
5313  if (inITBlock() && !instIsBreakpoint(Inst)) {
5314    unsigned bit = 1;
5315    if (ITState.FirstCond)
5316      ITState.FirstCond = false;
5317    else
5318      bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
5319    // The instruction must be predicable.
5320    if (!MCID.isPredicable())
5321      return Error(Loc, "instructions in IT block must be predicable");
5322    unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
5323    unsigned ITCond = bit ? ITState.Cond :
5324      ARMCC::getOppositeCondition(ITState.Cond);
5325    if (Cond != ITCond) {
5326      // Find the condition code Operand to get its SMLoc information.
5327      SMLoc CondLoc;
5328      for (unsigned i = 1; i < Operands.size(); ++i)
5329        if (static_cast<ARMOperand*>(Operands[i])->isCondCode())
5330          CondLoc = Operands[i]->getStartLoc();
5331      return Error(CondLoc, "incorrect condition in IT block; got '" +
5332                   StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
5333                   "', but expected '" +
5334                   ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
5335    }
5336  // Check for non-'al' condition codes outside of the IT block.
5337  } else if (isThumbTwo() && MCID.isPredicable() &&
5338             Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
5339             ARMCC::AL && Inst.getOpcode() != ARM::tBcc &&
5340             Inst.getOpcode() != ARM::t2Bcc)
5341    return Error(Loc, "predicated instructions must be in IT block");
5342
5343  switch (Inst.getOpcode()) {
5344  case ARM::LDRD:
5345  case ARM::LDRD_PRE:
5346  case ARM::LDRD_POST: {
5347    // Rt2 must be Rt + 1.
5348    unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5349    unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5350    if (Rt2 != Rt + 1)
5351      return Error(Operands[3]->getStartLoc(),
5352                   "destination operands must be sequential");
5353    return false;
5354  }
5355  case ARM::STRD: {
5356    // Rt2 must be Rt + 1.
5357    unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5358    unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5359    if (Rt2 != Rt + 1)
5360      return Error(Operands[3]->getStartLoc(),
5361                   "source operands must be sequential");
5362    return false;
5363  }
5364  case ARM::STRD_PRE:
5365  case ARM::STRD_POST: {
5366    // Rt2 must be Rt + 1.
5367    unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5368    unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
5369    if (Rt2 != Rt + 1)
5370      return Error(Operands[3]->getStartLoc(),
5371                   "source operands must be sequential");
5372    return false;
5373  }
5374  case ARM::SBFX:
5375  case ARM::UBFX: {
5376    // width must be in range [1, 32-lsb]
5377    unsigned lsb = Inst.getOperand(2).getImm();
5378    unsigned widthm1 = Inst.getOperand(3).getImm();
5379    if (widthm1 >= 32 - lsb)
5380      return Error(Operands[5]->getStartLoc(),
5381                   "bitfield width must be in range [1,32-lsb]");
5382    return false;
5383  }
5384  case ARM::tLDMIA: {
5385    // If we're parsing Thumb2, the .w variant is available and handles
5386    // most cases that are normally illegal for a Thumb1 LDM
5387    // instruction. We'll make the transformation in processInstruction()
5388    // if necessary.
5389    //
5390    // Thumb LDM instructions are writeback iff the base register is not
5391    // in the register list.
5392    unsigned Rn = Inst.getOperand(0).getReg();
5393    bool hasWritebackToken =
5394      (static_cast<ARMOperand*>(Operands[3])->isToken() &&
5395       static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
5396    bool listContainsBase;
5397    if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo())
5398      return Error(Operands[3 + hasWritebackToken]->getStartLoc(),
5399                   "registers must be in range r0-r7");
5400    // If we should have writeback, then there should be a '!' token.
5401    if (!listContainsBase && !hasWritebackToken && !isThumbTwo())
5402      return Error(Operands[2]->getStartLoc(),
5403                   "writeback operator '!' expected");
5404    // If we should not have writeback, there must not be a '!'. This is
5405    // true even for the 32-bit wide encodings.
5406    if (listContainsBase && hasWritebackToken)
5407      return Error(Operands[3]->getStartLoc(),
5408                   "writeback operator '!' not allowed when base register "
5409                   "in register list");
5410
5411    break;
5412  }
5413  case ARM::t2LDMIA_UPD: {
5414    if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
5415      return Error(Operands[4]->getStartLoc(),
5416                   "writeback operator '!' not allowed when base register "
5417                   "in register list");
5418    break;
5419  }
5420  case ARM::tMUL: {
5421    // The second source operand must be the same register as the destination
5422    // operand.
5423    //
5424    // In this case, we must directly check the parsed operands because the
5425    // cvtThumbMultiply() function is written in such a way that it guarantees
5426    // this first statement is always true for the new Inst.  Essentially, the
5427    // destination is unconditionally copied into the second source operand
5428    // without checking to see if it matches what we actually parsed.
5429    if (Operands.size() == 6 &&
5430        (((ARMOperand*)Operands[3])->getReg() !=
5431         ((ARMOperand*)Operands[5])->getReg()) &&
5432        (((ARMOperand*)Operands[3])->getReg() !=
5433         ((ARMOperand*)Operands[4])->getReg())) {
5434      return Error(Operands[3]->getStartLoc(),
5435                   "destination register must match source register");
5436    }
5437    break;
5438  }
5439  // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
5440  // so only issue a diagnostic for thumb1. The instructions will be
5441  // switched to the t2 encodings in processInstruction() if necessary.
5442  case ARM::tPOP: {
5443    bool listContainsBase;
5444    if (checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase) &&
5445        !isThumbTwo())
5446      return Error(Operands[2]->getStartLoc(),
5447                   "registers must be in range r0-r7 or pc");
5448    break;
5449  }
5450  case ARM::tPUSH: {
5451    bool listContainsBase;
5452    if (checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase) &&
5453        !isThumbTwo())
5454      return Error(Operands[2]->getStartLoc(),
5455                   "registers must be in range r0-r7 or lr");
5456    break;
5457  }
5458  case ARM::tSTMIA_UPD: {
5459    bool listContainsBase;
5460    if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase) && !isThumbTwo())
5461      return Error(Operands[4]->getStartLoc(),
5462                   "registers must be in range r0-r7");
5463    break;
5464  }
5465  case ARM::tADDrSP: {
5466    // If the non-SP source operand and the destination operand are not the
5467    // same, we need thumb2 (for the wide encoding), or we have an error.
5468    if (!isThumbTwo() &&
5469        Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
5470      return Error(Operands[4]->getStartLoc(),
5471                   "source register must be the same as destination");
5472    }
5473    break;
5474  }
5475  // final range checking for Thumb unconditional branch instructions
5476  case ARM::tB:
5477    if(!(static_cast<ARMOperand*>(Operands[2]))->isSignedOffset<11, 1>())
5478      return Error(Operands[2]->getStartLoc(), "Branch target out of range");
5479    break;
5480  case ARM::t2B: {
5481    int op = (Operands[2]->isImm()) ? 2 : 3;
5482    if(!(static_cast<ARMOperand*>(Operands[op]))->isSignedOffset<24, 1>())
5483      return Error(Operands[op]->getStartLoc(), "Branch target out of range");
5484    break;
5485  }
5486  // final range checking for Thumb conditional branch instructions
5487  case ARM::tBcc:
5488    if(!(static_cast<ARMOperand*>(Operands[2]))->isSignedOffset<8, 1>())
5489      return Error(Operands[2]->getStartLoc(), "Branch target out of range");
5490    break;
5491  case ARM::t2Bcc: {
5492    int op = (Operands[2]->isImm()) ? 2 : 3;
5493    if(!(static_cast<ARMOperand*>(Operands[op]))->isSignedOffset<20, 1>())
5494      return Error(Operands[op]->getStartLoc(), "Branch target out of range");
5495    break;
5496  }
5497  }
5498
5499  return false;
5500}
5501
5502static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
5503  switch(Opc) {
5504  default: llvm_unreachable("unexpected opcode!");
5505  // VST1LN
5506  case ARM::VST1LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST1LNd8_UPD;
5507  case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5508  case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5509  case ARM::VST1LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST1LNd8_UPD;
5510  case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5511  case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5512  case ARM::VST1LNdAsm_8:  Spacing = 1; return ARM::VST1LNd8;
5513  case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
5514  case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
5515
5516  // VST2LN
5517  case ARM::VST2LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST2LNd8_UPD;
5518  case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5519  case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5520  case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5521  case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5522
5523  case ARM::VST2LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST2LNd8_UPD;
5524  case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5525  case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5526  case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5527  case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5528
5529  case ARM::VST2LNdAsm_8:  Spacing = 1; return ARM::VST2LNd8;
5530  case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
5531  case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
5532  case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
5533  case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
5534
5535  // VST3LN
5536  case ARM::VST3LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST3LNd8_UPD;
5537  case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5538  case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5539  case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
5540  case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5541  case ARM::VST3LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST3LNd8_UPD;
5542  case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5543  case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5544  case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
5545  case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5546  case ARM::VST3LNdAsm_8:  Spacing = 1; return ARM::VST3LNd8;
5547  case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
5548  case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
5549  case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
5550  case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
5551
5552  // VST3
5553  case ARM::VST3dWB_fixed_Asm_8:  Spacing = 1; return ARM::VST3d8_UPD;
5554  case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5555  case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5556  case ARM::VST3qWB_fixed_Asm_8:  Spacing = 2; return ARM::VST3q8_UPD;
5557  case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5558  case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5559  case ARM::VST3dWB_register_Asm_8:  Spacing = 1; return ARM::VST3d8_UPD;
5560  case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5561  case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5562  case ARM::VST3qWB_register_Asm_8:  Spacing = 2; return ARM::VST3q8_UPD;
5563  case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5564  case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5565  case ARM::VST3dAsm_8:  Spacing = 1; return ARM::VST3d8;
5566  case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
5567  case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
5568  case ARM::VST3qAsm_8:  Spacing = 2; return ARM::VST3q8;
5569  case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
5570  case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
5571
5572  // VST4LN
5573  case ARM::VST4LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST4LNd8_UPD;
5574  case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5575  case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5576  case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
5577  case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5578  case ARM::VST4LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST4LNd8_UPD;
5579  case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5580  case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5581  case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
5582  case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5583  case ARM::VST4LNdAsm_8:  Spacing = 1; return ARM::VST4LNd8;
5584  case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
5585  case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
5586  case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
5587  case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
5588
5589  // VST4
5590  case ARM::VST4dWB_fixed_Asm_8:  Spacing = 1; return ARM::VST4d8_UPD;
5591  case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5592  case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5593  case ARM::VST4qWB_fixed_Asm_8:  Spacing = 2; return ARM::VST4q8_UPD;
5594  case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5595  case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5596  case ARM::VST4dWB_register_Asm_8:  Spacing = 1; return ARM::VST4d8_UPD;
5597  case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5598  case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5599  case ARM::VST4qWB_register_Asm_8:  Spacing = 2; return ARM::VST4q8_UPD;
5600  case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5601  case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5602  case ARM::VST4dAsm_8:  Spacing = 1; return ARM::VST4d8;
5603  case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
5604  case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
5605  case ARM::VST4qAsm_8:  Spacing = 2; return ARM::VST4q8;
5606  case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
5607  case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
5608  }
5609}
5610
5611static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
5612  switch(Opc) {
5613  default: llvm_unreachable("unexpected opcode!");
5614  // VLD1LN
5615  case ARM::VLD1LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD1LNd8_UPD;
5616  case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5617  case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5618  case ARM::VLD1LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD1LNd8_UPD;
5619  case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5620  case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5621  case ARM::VLD1LNdAsm_8:  Spacing = 1; return ARM::VLD1LNd8;
5622  case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
5623  case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
5624
5625  // VLD2LN
5626  case ARM::VLD2LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD2LNd8_UPD;
5627  case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5628  case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5629  case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
5630  case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5631  case ARM::VLD2LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD2LNd8_UPD;
5632  case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5633  case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5634  case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
5635  case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5636  case ARM::VLD2LNdAsm_8:  Spacing = 1; return ARM::VLD2LNd8;
5637  case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
5638  case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
5639  case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
5640  case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
5641
5642  // VLD3DUP
5643  case ARM::VLD3DUPdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3DUPd8_UPD;
5644  case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5645  case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5646  case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
5647  case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPq16_UPD;
5648  case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5649  case ARM::VLD3DUPdWB_register_Asm_8:  Spacing = 1; return ARM::VLD3DUPd8_UPD;
5650  case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5651  case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5652  case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
5653  case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
5654  case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5655  case ARM::VLD3DUPdAsm_8:  Spacing = 1; return ARM::VLD3DUPd8;
5656  case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
5657  case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
5658  case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
5659  case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
5660  case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
5661
5662  // VLD3LN
5663  case ARM::VLD3LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3LNd8_UPD;
5664  case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5665  case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5666  case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
5667  case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5668  case ARM::VLD3LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD3LNd8_UPD;
5669  case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5670  case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5671  case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
5672  case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5673  case ARM::VLD3LNdAsm_8:  Spacing = 1; return ARM::VLD3LNd8;
5674  case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
5675  case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
5676  case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
5677  case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
5678
5679  // VLD3
5680  case ARM::VLD3dWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3d8_UPD;
5681  case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5682  case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5683  case ARM::VLD3qWB_fixed_Asm_8:  Spacing = 2; return ARM::VLD3q8_UPD;
5684  case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5685  case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5686  case ARM::VLD3dWB_register_Asm_8:  Spacing = 1; return ARM::VLD3d8_UPD;
5687  case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5688  case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5689  case ARM::VLD3qWB_register_Asm_8:  Spacing = 2; return ARM::VLD3q8_UPD;
5690  case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5691  case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5692  case ARM::VLD3dAsm_8:  Spacing = 1; return ARM::VLD3d8;
5693  case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
5694  case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
5695  case ARM::VLD3qAsm_8:  Spacing = 2; return ARM::VLD3q8;
5696  case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
5697  case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
5698
5699  // VLD4LN
5700  case ARM::VLD4LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4LNd8_UPD;
5701  case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5702  case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5703  case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNq16_UPD;
5704  case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5705  case ARM::VLD4LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD4LNd8_UPD;
5706  case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5707  case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5708  case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
5709  case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5710  case ARM::VLD4LNdAsm_8:  Spacing = 1; return ARM::VLD4LNd8;
5711  case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
5712  case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
5713  case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
5714  case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
5715
5716  // VLD4DUP
5717  case ARM::VLD4DUPdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4DUPd8_UPD;
5718  case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5719  case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5720  case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
5721  case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
5722  case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5723  case ARM::VLD4DUPdWB_register_Asm_8:  Spacing = 1; return ARM::VLD4DUPd8_UPD;
5724  case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5725  case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5726  case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
5727  case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
5728  case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5729  case ARM::VLD4DUPdAsm_8:  Spacing = 1; return ARM::VLD4DUPd8;
5730  case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
5731  case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
5732  case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
5733  case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
5734  case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
5735
5736  // VLD4
5737  case ARM::VLD4dWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4d8_UPD;
5738  case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5739  case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5740  case ARM::VLD4qWB_fixed_Asm_8:  Spacing = 2; return ARM::VLD4q8_UPD;
5741  case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5742  case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5743  case ARM::VLD4dWB_register_Asm_8:  Spacing = 1; return ARM::VLD4d8_UPD;
5744  case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5745  case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5746  case ARM::VLD4qWB_register_Asm_8:  Spacing = 2; return ARM::VLD4q8_UPD;
5747  case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5748  case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5749  case ARM::VLD4dAsm_8:  Spacing = 1; return ARM::VLD4d8;
5750  case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
5751  case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
5752  case ARM::VLD4qAsm_8:  Spacing = 2; return ARM::VLD4q8;
5753  case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
5754  case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
5755  }
5756}
5757
5758bool ARMAsmParser::
5759processInstruction(MCInst &Inst,
5760                   const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5761  switch (Inst.getOpcode()) {
5762  // Alias for alternate form of 'ADR Rd, #imm' instruction.
5763  case ARM::ADDri: {
5764    if (Inst.getOperand(1).getReg() != ARM::PC ||
5765        Inst.getOperand(5).getReg() != 0)
5766      return false;
5767    MCInst TmpInst;
5768    TmpInst.setOpcode(ARM::ADR);
5769    TmpInst.addOperand(Inst.getOperand(0));
5770    TmpInst.addOperand(Inst.getOperand(2));
5771    TmpInst.addOperand(Inst.getOperand(3));
5772    TmpInst.addOperand(Inst.getOperand(4));
5773    Inst = TmpInst;
5774    return true;
5775  }
5776  // Aliases for alternate PC+imm syntax of LDR instructions.
5777  case ARM::t2LDRpcrel:
5778    // Select the narrow version if the immediate will fit.
5779    if (Inst.getOperand(1).getImm() > 0 &&
5780        Inst.getOperand(1).getImm() <= 0xff &&
5781        !(static_cast<ARMOperand*>(Operands[2])->isToken() &&
5782         static_cast<ARMOperand*>(Operands[2])->getToken() == ".w"))
5783      Inst.setOpcode(ARM::tLDRpci);
5784    else
5785      Inst.setOpcode(ARM::t2LDRpci);
5786    return true;
5787  case ARM::t2LDRBpcrel:
5788    Inst.setOpcode(ARM::t2LDRBpci);
5789    return true;
5790  case ARM::t2LDRHpcrel:
5791    Inst.setOpcode(ARM::t2LDRHpci);
5792    return true;
5793  case ARM::t2LDRSBpcrel:
5794    Inst.setOpcode(ARM::t2LDRSBpci);
5795    return true;
5796  case ARM::t2LDRSHpcrel:
5797    Inst.setOpcode(ARM::t2LDRSHpci);
5798    return true;
5799  // Handle NEON VST complex aliases.
5800  case ARM::VST1LNdWB_register_Asm_8:
5801  case ARM::VST1LNdWB_register_Asm_16:
5802  case ARM::VST1LNdWB_register_Asm_32: {
5803    MCInst TmpInst;
5804    // Shuffle the operands around so the lane index operand is in the
5805    // right place.
5806    unsigned Spacing;
5807    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5808    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5809    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5810    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5811    TmpInst.addOperand(Inst.getOperand(4)); // Rm
5812    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5813    TmpInst.addOperand(Inst.getOperand(1)); // lane
5814    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5815    TmpInst.addOperand(Inst.getOperand(6));
5816    Inst = TmpInst;
5817    return true;
5818  }
5819
5820  case ARM::VST2LNdWB_register_Asm_8:
5821  case ARM::VST2LNdWB_register_Asm_16:
5822  case ARM::VST2LNdWB_register_Asm_32:
5823  case ARM::VST2LNqWB_register_Asm_16:
5824  case ARM::VST2LNqWB_register_Asm_32: {
5825    MCInst TmpInst;
5826    // Shuffle the operands around so the lane index operand is in the
5827    // right place.
5828    unsigned Spacing;
5829    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5830    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5831    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5832    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5833    TmpInst.addOperand(Inst.getOperand(4)); // Rm
5834    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5835    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5836                                            Spacing));
5837    TmpInst.addOperand(Inst.getOperand(1)); // lane
5838    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5839    TmpInst.addOperand(Inst.getOperand(6));
5840    Inst = TmpInst;
5841    return true;
5842  }
5843
5844  case ARM::VST3LNdWB_register_Asm_8:
5845  case ARM::VST3LNdWB_register_Asm_16:
5846  case ARM::VST3LNdWB_register_Asm_32:
5847  case ARM::VST3LNqWB_register_Asm_16:
5848  case ARM::VST3LNqWB_register_Asm_32: {
5849    MCInst TmpInst;
5850    // Shuffle the operands around so the lane index operand is in the
5851    // right place.
5852    unsigned Spacing;
5853    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5854    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5855    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5856    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5857    TmpInst.addOperand(Inst.getOperand(4)); // Rm
5858    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5859    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5860                                            Spacing));
5861    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5862                                            Spacing * 2));
5863    TmpInst.addOperand(Inst.getOperand(1)); // lane
5864    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5865    TmpInst.addOperand(Inst.getOperand(6));
5866    Inst = TmpInst;
5867    return true;
5868  }
5869
5870  case ARM::VST4LNdWB_register_Asm_8:
5871  case ARM::VST4LNdWB_register_Asm_16:
5872  case ARM::VST4LNdWB_register_Asm_32:
5873  case ARM::VST4LNqWB_register_Asm_16:
5874  case ARM::VST4LNqWB_register_Asm_32: {
5875    MCInst TmpInst;
5876    // Shuffle the operands around so the lane index operand is in the
5877    // right place.
5878    unsigned Spacing;
5879    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5880    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5881    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5882    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5883    TmpInst.addOperand(Inst.getOperand(4)); // Rm
5884    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5885    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5886                                            Spacing));
5887    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5888                                            Spacing * 2));
5889    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5890                                            Spacing * 3));
5891    TmpInst.addOperand(Inst.getOperand(1)); // lane
5892    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5893    TmpInst.addOperand(Inst.getOperand(6));
5894    Inst = TmpInst;
5895    return true;
5896  }
5897
5898  case ARM::VST1LNdWB_fixed_Asm_8:
5899  case ARM::VST1LNdWB_fixed_Asm_16:
5900  case ARM::VST1LNdWB_fixed_Asm_32: {
5901    MCInst TmpInst;
5902    // Shuffle the operands around so the lane index operand is in the
5903    // right place.
5904    unsigned Spacing;
5905    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5906    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5907    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5908    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5909    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5910    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5911    TmpInst.addOperand(Inst.getOperand(1)); // lane
5912    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5913    TmpInst.addOperand(Inst.getOperand(5));
5914    Inst = TmpInst;
5915    return true;
5916  }
5917
5918  case ARM::VST2LNdWB_fixed_Asm_8:
5919  case ARM::VST2LNdWB_fixed_Asm_16:
5920  case ARM::VST2LNdWB_fixed_Asm_32:
5921  case ARM::VST2LNqWB_fixed_Asm_16:
5922  case ARM::VST2LNqWB_fixed_Asm_32: {
5923    MCInst TmpInst;
5924    // Shuffle the operands around so the lane index operand is in the
5925    // right place.
5926    unsigned Spacing;
5927    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5928    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5929    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5930    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5931    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5932    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5933    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5934                                            Spacing));
5935    TmpInst.addOperand(Inst.getOperand(1)); // lane
5936    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5937    TmpInst.addOperand(Inst.getOperand(5));
5938    Inst = TmpInst;
5939    return true;
5940  }
5941
5942  case ARM::VST3LNdWB_fixed_Asm_8:
5943  case ARM::VST3LNdWB_fixed_Asm_16:
5944  case ARM::VST3LNdWB_fixed_Asm_32:
5945  case ARM::VST3LNqWB_fixed_Asm_16:
5946  case ARM::VST3LNqWB_fixed_Asm_32: {
5947    MCInst TmpInst;
5948    // Shuffle the operands around so the lane index operand is in the
5949    // right place.
5950    unsigned Spacing;
5951    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5952    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5953    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5954    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5955    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5956    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5957    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5958                                            Spacing));
5959    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5960                                            Spacing * 2));
5961    TmpInst.addOperand(Inst.getOperand(1)); // lane
5962    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5963    TmpInst.addOperand(Inst.getOperand(5));
5964    Inst = TmpInst;
5965    return true;
5966  }
5967
5968  case ARM::VST4LNdWB_fixed_Asm_8:
5969  case ARM::VST4LNdWB_fixed_Asm_16:
5970  case ARM::VST4LNdWB_fixed_Asm_32:
5971  case ARM::VST4LNqWB_fixed_Asm_16:
5972  case ARM::VST4LNqWB_fixed_Asm_32: {
5973    MCInst TmpInst;
5974    // Shuffle the operands around so the lane index operand is in the
5975    // right place.
5976    unsigned Spacing;
5977    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5978    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5979    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5980    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5981    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5982    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5983    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5984                                            Spacing));
5985    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5986                                            Spacing * 2));
5987    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5988                                            Spacing * 3));
5989    TmpInst.addOperand(Inst.getOperand(1)); // lane
5990    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5991    TmpInst.addOperand(Inst.getOperand(5));
5992    Inst = TmpInst;
5993    return true;
5994  }
5995
5996  case ARM::VST1LNdAsm_8:
5997  case ARM::VST1LNdAsm_16:
5998  case ARM::VST1LNdAsm_32: {
5999    MCInst TmpInst;
6000    // Shuffle the operands around so the lane index operand is in the
6001    // right place.
6002    unsigned Spacing;
6003    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6004    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6005    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6006    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6007    TmpInst.addOperand(Inst.getOperand(1)); // lane
6008    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6009    TmpInst.addOperand(Inst.getOperand(5));
6010    Inst = TmpInst;
6011    return true;
6012  }
6013
6014  case ARM::VST2LNdAsm_8:
6015  case ARM::VST2LNdAsm_16:
6016  case ARM::VST2LNdAsm_32:
6017  case ARM::VST2LNqAsm_16:
6018  case ARM::VST2LNqAsm_32: {
6019    MCInst TmpInst;
6020    // Shuffle the operands around so the lane index operand is in the
6021    // right place.
6022    unsigned Spacing;
6023    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6024    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6025    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6026    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6027    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6028                                            Spacing));
6029    TmpInst.addOperand(Inst.getOperand(1)); // lane
6030    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6031    TmpInst.addOperand(Inst.getOperand(5));
6032    Inst = TmpInst;
6033    return true;
6034  }
6035
6036  case ARM::VST3LNdAsm_8:
6037  case ARM::VST3LNdAsm_16:
6038  case ARM::VST3LNdAsm_32:
6039  case ARM::VST3LNqAsm_16:
6040  case ARM::VST3LNqAsm_32: {
6041    MCInst TmpInst;
6042    // Shuffle the operands around so the lane index operand is in the
6043    // right place.
6044    unsigned Spacing;
6045    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6046    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6047    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6048    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6049    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6050                                            Spacing));
6051    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6052                                            Spacing * 2));
6053    TmpInst.addOperand(Inst.getOperand(1)); // lane
6054    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6055    TmpInst.addOperand(Inst.getOperand(5));
6056    Inst = TmpInst;
6057    return true;
6058  }
6059
6060  case ARM::VST4LNdAsm_8:
6061  case ARM::VST4LNdAsm_16:
6062  case ARM::VST4LNdAsm_32:
6063  case ARM::VST4LNqAsm_16:
6064  case ARM::VST4LNqAsm_32: {
6065    MCInst TmpInst;
6066    // Shuffle the operands around so the lane index operand is in the
6067    // right place.
6068    unsigned Spacing;
6069    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6070    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6071    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6072    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6073    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6074                                            Spacing));
6075    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6076                                            Spacing * 2));
6077    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6078                                            Spacing * 3));
6079    TmpInst.addOperand(Inst.getOperand(1)); // lane
6080    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6081    TmpInst.addOperand(Inst.getOperand(5));
6082    Inst = TmpInst;
6083    return true;
6084  }
6085
6086  // Handle NEON VLD complex aliases.
6087  case ARM::VLD1LNdWB_register_Asm_8:
6088  case ARM::VLD1LNdWB_register_Asm_16:
6089  case ARM::VLD1LNdWB_register_Asm_32: {
6090    MCInst TmpInst;
6091    // Shuffle the operands around so the lane index operand is in the
6092    // right place.
6093    unsigned Spacing;
6094    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6095    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6096    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6097    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6098    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6099    TmpInst.addOperand(Inst.getOperand(4)); // Rm
6100    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6101    TmpInst.addOperand(Inst.getOperand(1)); // lane
6102    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6103    TmpInst.addOperand(Inst.getOperand(6));
6104    Inst = TmpInst;
6105    return true;
6106  }
6107
6108  case ARM::VLD2LNdWB_register_Asm_8:
6109  case ARM::VLD2LNdWB_register_Asm_16:
6110  case ARM::VLD2LNdWB_register_Asm_32:
6111  case ARM::VLD2LNqWB_register_Asm_16:
6112  case ARM::VLD2LNqWB_register_Asm_32: {
6113    MCInst TmpInst;
6114    // Shuffle the operands around so the lane index operand is in the
6115    // right place.
6116    unsigned Spacing;
6117    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6118    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6119    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6120                                            Spacing));
6121    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6122    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6123    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6124    TmpInst.addOperand(Inst.getOperand(4)); // Rm
6125    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6126    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6127                                            Spacing));
6128    TmpInst.addOperand(Inst.getOperand(1)); // lane
6129    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6130    TmpInst.addOperand(Inst.getOperand(6));
6131    Inst = TmpInst;
6132    return true;
6133  }
6134
6135  case ARM::VLD3LNdWB_register_Asm_8:
6136  case ARM::VLD3LNdWB_register_Asm_16:
6137  case ARM::VLD3LNdWB_register_Asm_32:
6138  case ARM::VLD3LNqWB_register_Asm_16:
6139  case ARM::VLD3LNqWB_register_Asm_32: {
6140    MCInst TmpInst;
6141    // Shuffle the operands around so the lane index operand is in the
6142    // right place.
6143    unsigned Spacing;
6144    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6145    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6146    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6147                                            Spacing));
6148    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6149                                            Spacing * 2));
6150    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6151    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6152    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6153    TmpInst.addOperand(Inst.getOperand(4)); // Rm
6154    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6155    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6156                                            Spacing));
6157    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6158                                            Spacing * 2));
6159    TmpInst.addOperand(Inst.getOperand(1)); // lane
6160    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6161    TmpInst.addOperand(Inst.getOperand(6));
6162    Inst = TmpInst;
6163    return true;
6164  }
6165
6166  case ARM::VLD4LNdWB_register_Asm_8:
6167  case ARM::VLD4LNdWB_register_Asm_16:
6168  case ARM::VLD4LNdWB_register_Asm_32:
6169  case ARM::VLD4LNqWB_register_Asm_16:
6170  case ARM::VLD4LNqWB_register_Asm_32: {
6171    MCInst TmpInst;
6172    // Shuffle the operands around so the lane index operand is in the
6173    // right place.
6174    unsigned Spacing;
6175    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6176    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6177    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6178                                            Spacing));
6179    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6180                                            Spacing * 2));
6181    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6182                                            Spacing * 3));
6183    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6184    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6185    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6186    TmpInst.addOperand(Inst.getOperand(4)); // Rm
6187    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6188    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6189                                            Spacing));
6190    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6191                                            Spacing * 2));
6192    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6193                                            Spacing * 3));
6194    TmpInst.addOperand(Inst.getOperand(1)); // lane
6195    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6196    TmpInst.addOperand(Inst.getOperand(6));
6197    Inst = TmpInst;
6198    return true;
6199  }
6200
6201  case ARM::VLD1LNdWB_fixed_Asm_8:
6202  case ARM::VLD1LNdWB_fixed_Asm_16:
6203  case ARM::VLD1LNdWB_fixed_Asm_32: {
6204    MCInst TmpInst;
6205    // Shuffle the operands around so the lane index operand is in the
6206    // right place.
6207    unsigned Spacing;
6208    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6209    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6210    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6211    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6212    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6213    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6214    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6215    TmpInst.addOperand(Inst.getOperand(1)); // lane
6216    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6217    TmpInst.addOperand(Inst.getOperand(5));
6218    Inst = TmpInst;
6219    return true;
6220  }
6221
6222  case ARM::VLD2LNdWB_fixed_Asm_8:
6223  case ARM::VLD2LNdWB_fixed_Asm_16:
6224  case ARM::VLD2LNdWB_fixed_Asm_32:
6225  case ARM::VLD2LNqWB_fixed_Asm_16:
6226  case ARM::VLD2LNqWB_fixed_Asm_32: {
6227    MCInst TmpInst;
6228    // Shuffle the operands around so the lane index operand is in the
6229    // right place.
6230    unsigned Spacing;
6231    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6232    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6233    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6234                                            Spacing));
6235    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6236    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6237    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6238    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6239    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6240    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6241                                            Spacing));
6242    TmpInst.addOperand(Inst.getOperand(1)); // lane
6243    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6244    TmpInst.addOperand(Inst.getOperand(5));
6245    Inst = TmpInst;
6246    return true;
6247  }
6248
6249  case ARM::VLD3LNdWB_fixed_Asm_8:
6250  case ARM::VLD3LNdWB_fixed_Asm_16:
6251  case ARM::VLD3LNdWB_fixed_Asm_32:
6252  case ARM::VLD3LNqWB_fixed_Asm_16:
6253  case ARM::VLD3LNqWB_fixed_Asm_32: {
6254    MCInst TmpInst;
6255    // Shuffle the operands around so the lane index operand is in the
6256    // right place.
6257    unsigned Spacing;
6258    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6259    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6260    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6261                                            Spacing));
6262    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6263                                            Spacing * 2));
6264    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6265    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6266    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6267    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6268    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6269    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6270                                            Spacing));
6271    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6272                                            Spacing * 2));
6273    TmpInst.addOperand(Inst.getOperand(1)); // lane
6274    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6275    TmpInst.addOperand(Inst.getOperand(5));
6276    Inst = TmpInst;
6277    return true;
6278  }
6279
6280  case ARM::VLD4LNdWB_fixed_Asm_8:
6281  case ARM::VLD4LNdWB_fixed_Asm_16:
6282  case ARM::VLD4LNdWB_fixed_Asm_32:
6283  case ARM::VLD4LNqWB_fixed_Asm_16:
6284  case ARM::VLD4LNqWB_fixed_Asm_32: {
6285    MCInst TmpInst;
6286    // Shuffle the operands around so the lane index operand is in the
6287    // right place.
6288    unsigned Spacing;
6289    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6290    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6291    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6292                                            Spacing));
6293    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6294                                            Spacing * 2));
6295    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6296                                            Spacing * 3));
6297    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6298    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6299    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6300    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6301    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6302    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6303                                            Spacing));
6304    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6305                                            Spacing * 2));
6306    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6307                                            Spacing * 3));
6308    TmpInst.addOperand(Inst.getOperand(1)); // lane
6309    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6310    TmpInst.addOperand(Inst.getOperand(5));
6311    Inst = TmpInst;
6312    return true;
6313  }
6314
6315  case ARM::VLD1LNdAsm_8:
6316  case ARM::VLD1LNdAsm_16:
6317  case ARM::VLD1LNdAsm_32: {
6318    MCInst TmpInst;
6319    // Shuffle the operands around so the lane index operand is in the
6320    // right place.
6321    unsigned Spacing;
6322    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6323    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6324    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6325    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6326    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6327    TmpInst.addOperand(Inst.getOperand(1)); // lane
6328    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6329    TmpInst.addOperand(Inst.getOperand(5));
6330    Inst = TmpInst;
6331    return true;
6332  }
6333
6334  case ARM::VLD2LNdAsm_8:
6335  case ARM::VLD2LNdAsm_16:
6336  case ARM::VLD2LNdAsm_32:
6337  case ARM::VLD2LNqAsm_16:
6338  case ARM::VLD2LNqAsm_32: {
6339    MCInst TmpInst;
6340    // Shuffle the operands around so the lane index operand is in the
6341    // right place.
6342    unsigned Spacing;
6343    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6344    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6345    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6346                                            Spacing));
6347    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6348    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6349    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6350    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6351                                            Spacing));
6352    TmpInst.addOperand(Inst.getOperand(1)); // lane
6353    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6354    TmpInst.addOperand(Inst.getOperand(5));
6355    Inst = TmpInst;
6356    return true;
6357  }
6358
6359  case ARM::VLD3LNdAsm_8:
6360  case ARM::VLD3LNdAsm_16:
6361  case ARM::VLD3LNdAsm_32:
6362  case ARM::VLD3LNqAsm_16:
6363  case ARM::VLD3LNqAsm_32: {
6364    MCInst TmpInst;
6365    // Shuffle the operands around so the lane index operand is in the
6366    // right place.
6367    unsigned Spacing;
6368    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6369    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6370    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6371                                            Spacing));
6372    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6373                                            Spacing * 2));
6374    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6375    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6376    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6377    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6378                                            Spacing));
6379    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6380                                            Spacing * 2));
6381    TmpInst.addOperand(Inst.getOperand(1)); // lane
6382    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6383    TmpInst.addOperand(Inst.getOperand(5));
6384    Inst = TmpInst;
6385    return true;
6386  }
6387
6388  case ARM::VLD4LNdAsm_8:
6389  case ARM::VLD4LNdAsm_16:
6390  case ARM::VLD4LNdAsm_32:
6391  case ARM::VLD4LNqAsm_16:
6392  case ARM::VLD4LNqAsm_32: {
6393    MCInst TmpInst;
6394    // Shuffle the operands around so the lane index operand is in the
6395    // right place.
6396    unsigned Spacing;
6397    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6398    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6399    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6400                                            Spacing));
6401    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6402                                            Spacing * 2));
6403    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6404                                            Spacing * 3));
6405    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6406    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6407    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6408    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6409                                            Spacing));
6410    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6411                                            Spacing * 2));
6412    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6413                                            Spacing * 3));
6414    TmpInst.addOperand(Inst.getOperand(1)); // lane
6415    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6416    TmpInst.addOperand(Inst.getOperand(5));
6417    Inst = TmpInst;
6418    return true;
6419  }
6420
6421  // VLD3DUP single 3-element structure to all lanes instructions.
6422  case ARM::VLD3DUPdAsm_8:
6423  case ARM::VLD3DUPdAsm_16:
6424  case ARM::VLD3DUPdAsm_32:
6425  case ARM::VLD3DUPqAsm_8:
6426  case ARM::VLD3DUPqAsm_16:
6427  case ARM::VLD3DUPqAsm_32: {
6428    MCInst TmpInst;
6429    unsigned Spacing;
6430    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6431    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6432    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6433                                            Spacing));
6434    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6435                                            Spacing * 2));
6436    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6437    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6438    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6439    TmpInst.addOperand(Inst.getOperand(4));
6440    Inst = TmpInst;
6441    return true;
6442  }
6443
6444  case ARM::VLD3DUPdWB_fixed_Asm_8:
6445  case ARM::VLD3DUPdWB_fixed_Asm_16:
6446  case ARM::VLD3DUPdWB_fixed_Asm_32:
6447  case ARM::VLD3DUPqWB_fixed_Asm_8:
6448  case ARM::VLD3DUPqWB_fixed_Asm_16:
6449  case ARM::VLD3DUPqWB_fixed_Asm_32: {
6450    MCInst TmpInst;
6451    unsigned Spacing;
6452    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6453    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6454    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6455                                            Spacing));
6456    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6457                                            Spacing * 2));
6458    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6459    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6460    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6461    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6462    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6463    TmpInst.addOperand(Inst.getOperand(4));
6464    Inst = TmpInst;
6465    return true;
6466  }
6467
6468  case ARM::VLD3DUPdWB_register_Asm_8:
6469  case ARM::VLD3DUPdWB_register_Asm_16:
6470  case ARM::VLD3DUPdWB_register_Asm_32:
6471  case ARM::VLD3DUPqWB_register_Asm_8:
6472  case ARM::VLD3DUPqWB_register_Asm_16:
6473  case ARM::VLD3DUPqWB_register_Asm_32: {
6474    MCInst TmpInst;
6475    unsigned Spacing;
6476    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6477    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6478    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6479                                            Spacing));
6480    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6481                                            Spacing * 2));
6482    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6483    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6484    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6485    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6486    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6487    TmpInst.addOperand(Inst.getOperand(5));
6488    Inst = TmpInst;
6489    return true;
6490  }
6491
6492  // VLD3 multiple 3-element structure instructions.
6493  case ARM::VLD3dAsm_8:
6494  case ARM::VLD3dAsm_16:
6495  case ARM::VLD3dAsm_32:
6496  case ARM::VLD3qAsm_8:
6497  case ARM::VLD3qAsm_16:
6498  case ARM::VLD3qAsm_32: {
6499    MCInst TmpInst;
6500    unsigned Spacing;
6501    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6502    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6503    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6504                                            Spacing));
6505    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6506                                            Spacing * 2));
6507    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6508    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6509    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6510    TmpInst.addOperand(Inst.getOperand(4));
6511    Inst = TmpInst;
6512    return true;
6513  }
6514
6515  case ARM::VLD3dWB_fixed_Asm_8:
6516  case ARM::VLD3dWB_fixed_Asm_16:
6517  case ARM::VLD3dWB_fixed_Asm_32:
6518  case ARM::VLD3qWB_fixed_Asm_8:
6519  case ARM::VLD3qWB_fixed_Asm_16:
6520  case ARM::VLD3qWB_fixed_Asm_32: {
6521    MCInst TmpInst;
6522    unsigned Spacing;
6523    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6524    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6525    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6526                                            Spacing));
6527    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6528                                            Spacing * 2));
6529    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6530    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6531    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6532    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6533    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6534    TmpInst.addOperand(Inst.getOperand(4));
6535    Inst = TmpInst;
6536    return true;
6537  }
6538
6539  case ARM::VLD3dWB_register_Asm_8:
6540  case ARM::VLD3dWB_register_Asm_16:
6541  case ARM::VLD3dWB_register_Asm_32:
6542  case ARM::VLD3qWB_register_Asm_8:
6543  case ARM::VLD3qWB_register_Asm_16:
6544  case ARM::VLD3qWB_register_Asm_32: {
6545    MCInst TmpInst;
6546    unsigned Spacing;
6547    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6548    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6549    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6550                                            Spacing));
6551    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6552                                            Spacing * 2));
6553    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6554    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6555    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6556    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6557    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6558    TmpInst.addOperand(Inst.getOperand(5));
6559    Inst = TmpInst;
6560    return true;
6561  }
6562
6563  // VLD4DUP single 3-element structure to all lanes instructions.
6564  case ARM::VLD4DUPdAsm_8:
6565  case ARM::VLD4DUPdAsm_16:
6566  case ARM::VLD4DUPdAsm_32:
6567  case ARM::VLD4DUPqAsm_8:
6568  case ARM::VLD4DUPqAsm_16:
6569  case ARM::VLD4DUPqAsm_32: {
6570    MCInst TmpInst;
6571    unsigned Spacing;
6572    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6573    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6574    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6575                                            Spacing));
6576    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6577                                            Spacing * 2));
6578    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6579                                            Spacing * 3));
6580    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6581    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6582    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6583    TmpInst.addOperand(Inst.getOperand(4));
6584    Inst = TmpInst;
6585    return true;
6586  }
6587
6588  case ARM::VLD4DUPdWB_fixed_Asm_8:
6589  case ARM::VLD4DUPdWB_fixed_Asm_16:
6590  case ARM::VLD4DUPdWB_fixed_Asm_32:
6591  case ARM::VLD4DUPqWB_fixed_Asm_8:
6592  case ARM::VLD4DUPqWB_fixed_Asm_16:
6593  case ARM::VLD4DUPqWB_fixed_Asm_32: {
6594    MCInst TmpInst;
6595    unsigned Spacing;
6596    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6597    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6598    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6599                                            Spacing));
6600    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6601                                            Spacing * 2));
6602    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6603                                            Spacing * 3));
6604    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6605    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6606    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6607    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6608    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6609    TmpInst.addOperand(Inst.getOperand(4));
6610    Inst = TmpInst;
6611    return true;
6612  }
6613
6614  case ARM::VLD4DUPdWB_register_Asm_8:
6615  case ARM::VLD4DUPdWB_register_Asm_16:
6616  case ARM::VLD4DUPdWB_register_Asm_32:
6617  case ARM::VLD4DUPqWB_register_Asm_8:
6618  case ARM::VLD4DUPqWB_register_Asm_16:
6619  case ARM::VLD4DUPqWB_register_Asm_32: {
6620    MCInst TmpInst;
6621    unsigned Spacing;
6622    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6623    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6624    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6625                                            Spacing));
6626    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6627                                            Spacing * 2));
6628    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6629                                            Spacing * 3));
6630    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6631    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6632    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6633    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6634    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6635    TmpInst.addOperand(Inst.getOperand(5));
6636    Inst = TmpInst;
6637    return true;
6638  }
6639
6640  // VLD4 multiple 4-element structure instructions.
6641  case ARM::VLD4dAsm_8:
6642  case ARM::VLD4dAsm_16:
6643  case ARM::VLD4dAsm_32:
6644  case ARM::VLD4qAsm_8:
6645  case ARM::VLD4qAsm_16:
6646  case ARM::VLD4qAsm_32: {
6647    MCInst TmpInst;
6648    unsigned Spacing;
6649    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6650    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6651    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6652                                            Spacing));
6653    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6654                                            Spacing * 2));
6655    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6656                                            Spacing * 3));
6657    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6658    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6659    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6660    TmpInst.addOperand(Inst.getOperand(4));
6661    Inst = TmpInst;
6662    return true;
6663  }
6664
6665  case ARM::VLD4dWB_fixed_Asm_8:
6666  case ARM::VLD4dWB_fixed_Asm_16:
6667  case ARM::VLD4dWB_fixed_Asm_32:
6668  case ARM::VLD4qWB_fixed_Asm_8:
6669  case ARM::VLD4qWB_fixed_Asm_16:
6670  case ARM::VLD4qWB_fixed_Asm_32: {
6671    MCInst TmpInst;
6672    unsigned Spacing;
6673    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6674    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6675    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6676                                            Spacing));
6677    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6678                                            Spacing * 2));
6679    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6680                                            Spacing * 3));
6681    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6682    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6683    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6684    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6685    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6686    TmpInst.addOperand(Inst.getOperand(4));
6687    Inst = TmpInst;
6688    return true;
6689  }
6690
6691  case ARM::VLD4dWB_register_Asm_8:
6692  case ARM::VLD4dWB_register_Asm_16:
6693  case ARM::VLD4dWB_register_Asm_32:
6694  case ARM::VLD4qWB_register_Asm_8:
6695  case ARM::VLD4qWB_register_Asm_16:
6696  case ARM::VLD4qWB_register_Asm_32: {
6697    MCInst TmpInst;
6698    unsigned Spacing;
6699    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6700    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6701    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6702                                            Spacing));
6703    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6704                                            Spacing * 2));
6705    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6706                                            Spacing * 3));
6707    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6708    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6709    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6710    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6711    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6712    TmpInst.addOperand(Inst.getOperand(5));
6713    Inst = TmpInst;
6714    return true;
6715  }
6716
6717  // VST3 multiple 3-element structure instructions.
6718  case ARM::VST3dAsm_8:
6719  case ARM::VST3dAsm_16:
6720  case ARM::VST3dAsm_32:
6721  case ARM::VST3qAsm_8:
6722  case ARM::VST3qAsm_16:
6723  case ARM::VST3qAsm_32: {
6724    MCInst TmpInst;
6725    unsigned Spacing;
6726    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6727    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6728    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6729    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6730    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6731                                            Spacing));
6732    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6733                                            Spacing * 2));
6734    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6735    TmpInst.addOperand(Inst.getOperand(4));
6736    Inst = TmpInst;
6737    return true;
6738  }
6739
6740  case ARM::VST3dWB_fixed_Asm_8:
6741  case ARM::VST3dWB_fixed_Asm_16:
6742  case ARM::VST3dWB_fixed_Asm_32:
6743  case ARM::VST3qWB_fixed_Asm_8:
6744  case ARM::VST3qWB_fixed_Asm_16:
6745  case ARM::VST3qWB_fixed_Asm_32: {
6746    MCInst TmpInst;
6747    unsigned Spacing;
6748    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6749    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6750    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6751    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6752    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6753    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6754    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6755                                            Spacing));
6756    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6757                                            Spacing * 2));
6758    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6759    TmpInst.addOperand(Inst.getOperand(4));
6760    Inst = TmpInst;
6761    return true;
6762  }
6763
6764  case ARM::VST3dWB_register_Asm_8:
6765  case ARM::VST3dWB_register_Asm_16:
6766  case ARM::VST3dWB_register_Asm_32:
6767  case ARM::VST3qWB_register_Asm_8:
6768  case ARM::VST3qWB_register_Asm_16:
6769  case ARM::VST3qWB_register_Asm_32: {
6770    MCInst TmpInst;
6771    unsigned Spacing;
6772    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6773    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6774    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6775    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6776    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6777    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6778    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6779                                            Spacing));
6780    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6781                                            Spacing * 2));
6782    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6783    TmpInst.addOperand(Inst.getOperand(5));
6784    Inst = TmpInst;
6785    return true;
6786  }
6787
6788  // VST4 multiple 3-element structure instructions.
6789  case ARM::VST4dAsm_8:
6790  case ARM::VST4dAsm_16:
6791  case ARM::VST4dAsm_32:
6792  case ARM::VST4qAsm_8:
6793  case ARM::VST4qAsm_16:
6794  case ARM::VST4qAsm_32: {
6795    MCInst TmpInst;
6796    unsigned Spacing;
6797    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6798    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6799    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6800    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6801    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6802                                            Spacing));
6803    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6804                                            Spacing * 2));
6805    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6806                                            Spacing * 3));
6807    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6808    TmpInst.addOperand(Inst.getOperand(4));
6809    Inst = TmpInst;
6810    return true;
6811  }
6812
6813  case ARM::VST4dWB_fixed_Asm_8:
6814  case ARM::VST4dWB_fixed_Asm_16:
6815  case ARM::VST4dWB_fixed_Asm_32:
6816  case ARM::VST4qWB_fixed_Asm_8:
6817  case ARM::VST4qWB_fixed_Asm_16:
6818  case ARM::VST4qWB_fixed_Asm_32: {
6819    MCInst TmpInst;
6820    unsigned Spacing;
6821    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6822    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6823    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6824    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6825    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6826    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6827    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6828                                            Spacing));
6829    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6830                                            Spacing * 2));
6831    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6832                                            Spacing * 3));
6833    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6834    TmpInst.addOperand(Inst.getOperand(4));
6835    Inst = TmpInst;
6836    return true;
6837  }
6838
6839  case ARM::VST4dWB_register_Asm_8:
6840  case ARM::VST4dWB_register_Asm_16:
6841  case ARM::VST4dWB_register_Asm_32:
6842  case ARM::VST4qWB_register_Asm_8:
6843  case ARM::VST4qWB_register_Asm_16:
6844  case ARM::VST4qWB_register_Asm_32: {
6845    MCInst TmpInst;
6846    unsigned Spacing;
6847    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6848    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6849    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6850    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6851    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6852    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6853    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6854                                            Spacing));
6855    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6856                                            Spacing * 2));
6857    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6858                                            Spacing * 3));
6859    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6860    TmpInst.addOperand(Inst.getOperand(5));
6861    Inst = TmpInst;
6862    return true;
6863  }
6864
6865  // Handle encoding choice for the shift-immediate instructions.
6866  case ARM::t2LSLri:
6867  case ARM::t2LSRri:
6868  case ARM::t2ASRri: {
6869    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6870        Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
6871        Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
6872        !(static_cast<ARMOperand*>(Operands[3])->isToken() &&
6873         static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) {
6874      unsigned NewOpc;
6875      switch (Inst.getOpcode()) {
6876      default: llvm_unreachable("unexpected opcode");
6877      case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
6878      case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
6879      case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
6880      }
6881      // The Thumb1 operands aren't in the same order. Awesome, eh?
6882      MCInst TmpInst;
6883      TmpInst.setOpcode(NewOpc);
6884      TmpInst.addOperand(Inst.getOperand(0));
6885      TmpInst.addOperand(Inst.getOperand(5));
6886      TmpInst.addOperand(Inst.getOperand(1));
6887      TmpInst.addOperand(Inst.getOperand(2));
6888      TmpInst.addOperand(Inst.getOperand(3));
6889      TmpInst.addOperand(Inst.getOperand(4));
6890      Inst = TmpInst;
6891      return true;
6892    }
6893    return false;
6894  }
6895
6896  // Handle the Thumb2 mode MOV complex aliases.
6897  case ARM::t2MOVsr:
6898  case ARM::t2MOVSsr: {
6899    // Which instruction to expand to depends on the CCOut operand and
6900    // whether we're in an IT block if the register operands are low
6901    // registers.
6902    bool isNarrow = false;
6903    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6904        isARMLowRegister(Inst.getOperand(1).getReg()) &&
6905        isARMLowRegister(Inst.getOperand(2).getReg()) &&
6906        Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
6907        inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
6908      isNarrow = true;
6909    MCInst TmpInst;
6910    unsigned newOpc;
6911    switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
6912    default: llvm_unreachable("unexpected opcode!");
6913    case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
6914    case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
6915    case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
6916    case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR   : ARM::t2RORrr; break;
6917    }
6918    TmpInst.setOpcode(newOpc);
6919    TmpInst.addOperand(Inst.getOperand(0)); // Rd
6920    if (isNarrow)
6921      TmpInst.addOperand(MCOperand::CreateReg(
6922          Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
6923    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6924    TmpInst.addOperand(Inst.getOperand(2)); // Rm
6925    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6926    TmpInst.addOperand(Inst.getOperand(5));
6927    if (!isNarrow)
6928      TmpInst.addOperand(MCOperand::CreateReg(
6929          Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
6930    Inst = TmpInst;
6931    return true;
6932  }
6933  case ARM::t2MOVsi:
6934  case ARM::t2MOVSsi: {
6935    // Which instruction to expand to depends on the CCOut operand and
6936    // whether we're in an IT block if the register operands are low
6937    // registers.
6938    bool isNarrow = false;
6939    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6940        isARMLowRegister(Inst.getOperand(1).getReg()) &&
6941        inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
6942      isNarrow = true;
6943    MCInst TmpInst;
6944    unsigned newOpc;
6945    switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
6946    default: llvm_unreachable("unexpected opcode!");
6947    case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
6948    case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
6949    case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
6950    case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
6951    case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
6952    }
6953    unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
6954    if (Amount == 32) Amount = 0;
6955    TmpInst.setOpcode(newOpc);
6956    TmpInst.addOperand(Inst.getOperand(0)); // Rd
6957    if (isNarrow)
6958      TmpInst.addOperand(MCOperand::CreateReg(
6959          Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
6960    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6961    if (newOpc != ARM::t2RRX)
6962      TmpInst.addOperand(MCOperand::CreateImm(Amount));
6963    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6964    TmpInst.addOperand(Inst.getOperand(4));
6965    if (!isNarrow)
6966      TmpInst.addOperand(MCOperand::CreateReg(
6967          Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
6968    Inst = TmpInst;
6969    return true;
6970  }
6971  // Handle the ARM mode MOV complex aliases.
6972  case ARM::ASRr:
6973  case ARM::LSRr:
6974  case ARM::LSLr:
6975  case ARM::RORr: {
6976    ARM_AM::ShiftOpc ShiftTy;
6977    switch(Inst.getOpcode()) {
6978    default: llvm_unreachable("unexpected opcode!");
6979    case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
6980    case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
6981    case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
6982    case ARM::RORr: ShiftTy = ARM_AM::ror; break;
6983    }
6984    unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
6985    MCInst TmpInst;
6986    TmpInst.setOpcode(ARM::MOVsr);
6987    TmpInst.addOperand(Inst.getOperand(0)); // Rd
6988    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6989    TmpInst.addOperand(Inst.getOperand(2)); // Rm
6990    TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
6991    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6992    TmpInst.addOperand(Inst.getOperand(4));
6993    TmpInst.addOperand(Inst.getOperand(5)); // cc_out
6994    Inst = TmpInst;
6995    return true;
6996  }
6997  case ARM::ASRi:
6998  case ARM::LSRi:
6999  case ARM::LSLi:
7000  case ARM::RORi: {
7001    ARM_AM::ShiftOpc ShiftTy;
7002    switch(Inst.getOpcode()) {
7003    default: llvm_unreachable("unexpected opcode!");
7004    case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
7005    case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
7006    case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
7007    case ARM::RORi: ShiftTy = ARM_AM::ror; break;
7008    }
7009    // A shift by zero is a plain MOVr, not a MOVsi.
7010    unsigned Amt = Inst.getOperand(2).getImm();
7011    unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
7012    // A shift by 32 should be encoded as 0 when permitted
7013    if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
7014      Amt = 0;
7015    unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
7016    MCInst TmpInst;
7017    TmpInst.setOpcode(Opc);
7018    TmpInst.addOperand(Inst.getOperand(0)); // Rd
7019    TmpInst.addOperand(Inst.getOperand(1)); // Rn
7020    if (Opc == ARM::MOVsi)
7021      TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7022    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7023    TmpInst.addOperand(Inst.getOperand(4));
7024    TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7025    Inst = TmpInst;
7026    return true;
7027  }
7028  case ARM::RRXi: {
7029    unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
7030    MCInst TmpInst;
7031    TmpInst.setOpcode(ARM::MOVsi);
7032    TmpInst.addOperand(Inst.getOperand(0)); // Rd
7033    TmpInst.addOperand(Inst.getOperand(1)); // Rn
7034    TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7035    TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7036    TmpInst.addOperand(Inst.getOperand(3));
7037    TmpInst.addOperand(Inst.getOperand(4)); // cc_out
7038    Inst = TmpInst;
7039    return true;
7040  }
7041  case ARM::t2LDMIA_UPD: {
7042    // If this is a load of a single register, then we should use
7043    // a post-indexed LDR instruction instead, per the ARM ARM.
7044    if (Inst.getNumOperands() != 5)
7045      return false;
7046    MCInst TmpInst;
7047    TmpInst.setOpcode(ARM::t2LDR_POST);
7048    TmpInst.addOperand(Inst.getOperand(4)); // Rt
7049    TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7050    TmpInst.addOperand(Inst.getOperand(1)); // Rn
7051    TmpInst.addOperand(MCOperand::CreateImm(4));
7052    TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7053    TmpInst.addOperand(Inst.getOperand(3));
7054    Inst = TmpInst;
7055    return true;
7056  }
7057  case ARM::t2STMDB_UPD: {
7058    // If this is a store of a single register, then we should use
7059    // a pre-indexed STR instruction instead, per the ARM ARM.
7060    if (Inst.getNumOperands() != 5)
7061      return false;
7062    MCInst TmpInst;
7063    TmpInst.setOpcode(ARM::t2STR_PRE);
7064    TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7065    TmpInst.addOperand(Inst.getOperand(4)); // Rt
7066    TmpInst.addOperand(Inst.getOperand(1)); // Rn
7067    TmpInst.addOperand(MCOperand::CreateImm(-4));
7068    TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7069    TmpInst.addOperand(Inst.getOperand(3));
7070    Inst = TmpInst;
7071    return true;
7072  }
7073  case ARM::LDMIA_UPD:
7074    // If this is a load of a single register via a 'pop', then we should use
7075    // a post-indexed LDR instruction instead, per the ARM ARM.
7076    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
7077        Inst.getNumOperands() == 5) {
7078      MCInst TmpInst;
7079      TmpInst.setOpcode(ARM::LDR_POST_IMM);
7080      TmpInst.addOperand(Inst.getOperand(4)); // Rt
7081      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7082      TmpInst.addOperand(Inst.getOperand(1)); // Rn
7083      TmpInst.addOperand(MCOperand::CreateReg(0));  // am2offset
7084      TmpInst.addOperand(MCOperand::CreateImm(4));
7085      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7086      TmpInst.addOperand(Inst.getOperand(3));
7087      Inst = TmpInst;
7088      return true;
7089    }
7090    break;
7091  case ARM::STMDB_UPD:
7092    // If this is a store of a single register via a 'push', then we should use
7093    // a pre-indexed STR instruction instead, per the ARM ARM.
7094    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
7095        Inst.getNumOperands() == 5) {
7096      MCInst TmpInst;
7097      TmpInst.setOpcode(ARM::STR_PRE_IMM);
7098      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7099      TmpInst.addOperand(Inst.getOperand(4)); // Rt
7100      TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
7101      TmpInst.addOperand(MCOperand::CreateImm(-4));
7102      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7103      TmpInst.addOperand(Inst.getOperand(3));
7104      Inst = TmpInst;
7105    }
7106    break;
7107  case ARM::t2ADDri12:
7108    // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
7109    // mnemonic was used (not "addw"), encoding T3 is preferred.
7110    if (static_cast<ARMOperand*>(Operands[0])->getToken() != "add" ||
7111        ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7112      break;
7113    Inst.setOpcode(ARM::t2ADDri);
7114    Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7115    break;
7116  case ARM::t2SUBri12:
7117    // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
7118    // mnemonic was used (not "subw"), encoding T3 is preferred.
7119    if (static_cast<ARMOperand*>(Operands[0])->getToken() != "sub" ||
7120        ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7121      break;
7122    Inst.setOpcode(ARM::t2SUBri);
7123    Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7124    break;
7125  case ARM::tADDi8:
7126    // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7127    // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7128    // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7129    // to encoding T1 if <Rd> is omitted."
7130    if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7131      Inst.setOpcode(ARM::tADDi3);
7132      return true;
7133    }
7134    break;
7135  case ARM::tSUBi8:
7136    // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7137    // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7138    // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7139    // to encoding T1 if <Rd> is omitted."
7140    if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7141      Inst.setOpcode(ARM::tSUBi3);
7142      return true;
7143    }
7144    break;
7145  case ARM::t2ADDri:
7146  case ARM::t2SUBri: {
7147    // If the destination and first source operand are the same, and
7148    // the flags are compatible with the current IT status, use encoding T2
7149    // instead of T3. For compatibility with the system 'as'. Make sure the
7150    // wide encoding wasn't explicit.
7151    if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7152        !isARMLowRegister(Inst.getOperand(0).getReg()) ||
7153        (unsigned)Inst.getOperand(2).getImm() > 255 ||
7154        ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
7155        (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
7156        (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7157         static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7158      break;
7159    MCInst TmpInst;
7160    TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
7161                      ARM::tADDi8 : ARM::tSUBi8);
7162    TmpInst.addOperand(Inst.getOperand(0));
7163    TmpInst.addOperand(Inst.getOperand(5));
7164    TmpInst.addOperand(Inst.getOperand(0));
7165    TmpInst.addOperand(Inst.getOperand(2));
7166    TmpInst.addOperand(Inst.getOperand(3));
7167    TmpInst.addOperand(Inst.getOperand(4));
7168    Inst = TmpInst;
7169    return true;
7170  }
7171  case ARM::t2ADDrr: {
7172    // If the destination and first source operand are the same, and
7173    // there's no setting of the flags, use encoding T2 instead of T3.
7174    // Note that this is only for ADD, not SUB. This mirrors the system
7175    // 'as' behaviour. Make sure the wide encoding wasn't explicit.
7176    if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7177        Inst.getOperand(5).getReg() != 0 ||
7178        (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7179         static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7180      break;
7181    MCInst TmpInst;
7182    TmpInst.setOpcode(ARM::tADDhirr);
7183    TmpInst.addOperand(Inst.getOperand(0));
7184    TmpInst.addOperand(Inst.getOperand(0));
7185    TmpInst.addOperand(Inst.getOperand(2));
7186    TmpInst.addOperand(Inst.getOperand(3));
7187    TmpInst.addOperand(Inst.getOperand(4));
7188    Inst = TmpInst;
7189    return true;
7190  }
7191  case ARM::tADDrSP: {
7192    // If the non-SP source operand and the destination operand are not the
7193    // same, we need to use the 32-bit encoding if it's available.
7194    if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
7195      Inst.setOpcode(ARM::t2ADDrr);
7196      Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7197      return true;
7198    }
7199    break;
7200  }
7201  case ARM::tB:
7202    // A Thumb conditional branch outside of an IT block is a tBcc.
7203    if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
7204      Inst.setOpcode(ARM::tBcc);
7205      return true;
7206    }
7207    break;
7208  case ARM::t2B:
7209    // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
7210    if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
7211      Inst.setOpcode(ARM::t2Bcc);
7212      return true;
7213    }
7214    break;
7215  case ARM::t2Bcc:
7216    // If the conditional is AL or we're in an IT block, we really want t2B.
7217    if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
7218      Inst.setOpcode(ARM::t2B);
7219      return true;
7220    }
7221    break;
7222  case ARM::tBcc:
7223    // If the conditional is AL, we really want tB.
7224    if (Inst.getOperand(1).getImm() == ARMCC::AL) {
7225      Inst.setOpcode(ARM::tB);
7226      return true;
7227    }
7228    break;
7229  case ARM::tLDMIA: {
7230    // If the register list contains any high registers, or if the writeback
7231    // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
7232    // instead if we're in Thumb2. Otherwise, this should have generated
7233    // an error in validateInstruction().
7234    unsigned Rn = Inst.getOperand(0).getReg();
7235    bool hasWritebackToken =
7236      (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7237       static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
7238    bool listContainsBase;
7239    if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
7240        (!listContainsBase && !hasWritebackToken) ||
7241        (listContainsBase && hasWritebackToken)) {
7242      // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7243      assert (isThumbTwo());
7244      Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
7245      // If we're switching to the updating version, we need to insert
7246      // the writeback tied operand.
7247      if (hasWritebackToken)
7248        Inst.insert(Inst.begin(),
7249                    MCOperand::CreateReg(Inst.getOperand(0).getReg()));
7250      return true;
7251    }
7252    break;
7253  }
7254  case ARM::tSTMIA_UPD: {
7255    // If the register list contains any high registers, we need to use
7256    // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7257    // should have generated an error in validateInstruction().
7258    unsigned Rn = Inst.getOperand(0).getReg();
7259    bool listContainsBase;
7260    if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
7261      // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7262      assert (isThumbTwo());
7263      Inst.setOpcode(ARM::t2STMIA_UPD);
7264      return true;
7265    }
7266    break;
7267  }
7268  case ARM::tPOP: {
7269    bool listContainsBase;
7270    // If the register list contains any high registers, we need to use
7271    // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7272    // should have generated an error in validateInstruction().
7273    if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
7274      return false;
7275    assert (isThumbTwo());
7276    Inst.setOpcode(ARM::t2LDMIA_UPD);
7277    // Add the base register and writeback operands.
7278    Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7279    Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7280    return true;
7281  }
7282  case ARM::tPUSH: {
7283    bool listContainsBase;
7284    if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
7285      return false;
7286    assert (isThumbTwo());
7287    Inst.setOpcode(ARM::t2STMDB_UPD);
7288    // Add the base register and writeback operands.
7289    Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7290    Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7291    return true;
7292  }
7293  case ARM::t2MOVi: {
7294    // If we can use the 16-bit encoding and the user didn't explicitly
7295    // request the 32-bit variant, transform it here.
7296    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7297        (unsigned)Inst.getOperand(1).getImm() <= 255 &&
7298        ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
7299         Inst.getOperand(4).getReg() == ARM::CPSR) ||
7300        (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
7301        (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7302         static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7303      // The operands aren't in the same order for tMOVi8...
7304      MCInst TmpInst;
7305      TmpInst.setOpcode(ARM::tMOVi8);
7306      TmpInst.addOperand(Inst.getOperand(0));
7307      TmpInst.addOperand(Inst.getOperand(4));
7308      TmpInst.addOperand(Inst.getOperand(1));
7309      TmpInst.addOperand(Inst.getOperand(2));
7310      TmpInst.addOperand(Inst.getOperand(3));
7311      Inst = TmpInst;
7312      return true;
7313    }
7314    break;
7315  }
7316  case ARM::t2MOVr: {
7317    // If we can use the 16-bit encoding and the user didn't explicitly
7318    // request the 32-bit variant, transform it here.
7319    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7320        isARMLowRegister(Inst.getOperand(1).getReg()) &&
7321        Inst.getOperand(2).getImm() == ARMCC::AL &&
7322        Inst.getOperand(4).getReg() == ARM::CPSR &&
7323        (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7324         static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7325      // The operands aren't the same for tMOV[S]r... (no cc_out)
7326      MCInst TmpInst;
7327      TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
7328      TmpInst.addOperand(Inst.getOperand(0));
7329      TmpInst.addOperand(Inst.getOperand(1));
7330      TmpInst.addOperand(Inst.getOperand(2));
7331      TmpInst.addOperand(Inst.getOperand(3));
7332      Inst = TmpInst;
7333      return true;
7334    }
7335    break;
7336  }
7337  case ARM::t2SXTH:
7338  case ARM::t2SXTB:
7339  case ARM::t2UXTH:
7340  case ARM::t2UXTB: {
7341    // If we can use the 16-bit encoding and the user didn't explicitly
7342    // request the 32-bit variant, transform it here.
7343    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7344        isARMLowRegister(Inst.getOperand(1).getReg()) &&
7345        Inst.getOperand(2).getImm() == 0 &&
7346        (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7347         static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7348      unsigned NewOpc;
7349      switch (Inst.getOpcode()) {
7350      default: llvm_unreachable("Illegal opcode!");
7351      case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
7352      case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
7353      case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
7354      case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
7355      }
7356      // The operands aren't the same for thumb1 (no rotate operand).
7357      MCInst TmpInst;
7358      TmpInst.setOpcode(NewOpc);
7359      TmpInst.addOperand(Inst.getOperand(0));
7360      TmpInst.addOperand(Inst.getOperand(1));
7361      TmpInst.addOperand(Inst.getOperand(3));
7362      TmpInst.addOperand(Inst.getOperand(4));
7363      Inst = TmpInst;
7364      return true;
7365    }
7366    break;
7367  }
7368  case ARM::MOVsi: {
7369    ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
7370    // rrx shifts and asr/lsr of #32 is encoded as 0
7371    if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
7372      return false;
7373    if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
7374      // Shifting by zero is accepted as a vanilla 'MOVr'
7375      MCInst TmpInst;
7376      TmpInst.setOpcode(ARM::MOVr);
7377      TmpInst.addOperand(Inst.getOperand(0));
7378      TmpInst.addOperand(Inst.getOperand(1));
7379      TmpInst.addOperand(Inst.getOperand(3));
7380      TmpInst.addOperand(Inst.getOperand(4));
7381      TmpInst.addOperand(Inst.getOperand(5));
7382      Inst = TmpInst;
7383      return true;
7384    }
7385    return false;
7386  }
7387  case ARM::ANDrsi:
7388  case ARM::ORRrsi:
7389  case ARM::EORrsi:
7390  case ARM::BICrsi:
7391  case ARM::SUBrsi:
7392  case ARM::ADDrsi: {
7393    unsigned newOpc;
7394    ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
7395    if (SOpc == ARM_AM::rrx) return false;
7396    switch (Inst.getOpcode()) {
7397    default: llvm_unreachable("unexpected opcode!");
7398    case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
7399    case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
7400    case ARM::EORrsi: newOpc = ARM::EORrr; break;
7401    case ARM::BICrsi: newOpc = ARM::BICrr; break;
7402    case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
7403    case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
7404    }
7405    // If the shift is by zero, use the non-shifted instruction definition.
7406    // The exception is for right shifts, where 0 == 32
7407    if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
7408        !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
7409      MCInst TmpInst;
7410      TmpInst.setOpcode(newOpc);
7411      TmpInst.addOperand(Inst.getOperand(0));
7412      TmpInst.addOperand(Inst.getOperand(1));
7413      TmpInst.addOperand(Inst.getOperand(2));
7414      TmpInst.addOperand(Inst.getOperand(4));
7415      TmpInst.addOperand(Inst.getOperand(5));
7416      TmpInst.addOperand(Inst.getOperand(6));
7417      Inst = TmpInst;
7418      return true;
7419    }
7420    return false;
7421  }
7422  case ARM::ITasm:
7423  case ARM::t2IT: {
7424    // The mask bits for all but the first condition are represented as
7425    // the low bit of the condition code value implies 't'. We currently
7426    // always have 1 implies 't', so XOR toggle the bits if the low bit
7427    // of the condition code is zero.
7428    MCOperand &MO = Inst.getOperand(1);
7429    unsigned Mask = MO.getImm();
7430    unsigned OrigMask = Mask;
7431    unsigned TZ = countTrailingZeros(Mask);
7432    if ((Inst.getOperand(0).getImm() & 1) == 0) {
7433      assert(Mask && TZ <= 3 && "illegal IT mask value!");
7434      Mask ^= (0xE << TZ) & 0xF;
7435    }
7436    MO.setImm(Mask);
7437
7438    // Set up the IT block state according to the IT instruction we just
7439    // matched.
7440    assert(!inITBlock() && "nested IT blocks?!");
7441    ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
7442    ITState.Mask = OrigMask; // Use the original mask, not the updated one.
7443    ITState.CurPosition = 0;
7444    ITState.FirstCond = true;
7445    break;
7446  }
7447  case ARM::t2LSLrr:
7448  case ARM::t2LSRrr:
7449  case ARM::t2ASRrr:
7450  case ARM::t2SBCrr:
7451  case ARM::t2RORrr:
7452  case ARM::t2BICrr:
7453  {
7454    // Assemblers should use the narrow encodings of these instructions when permissible.
7455    if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7456         isARMLowRegister(Inst.getOperand(2).getReg())) &&
7457        Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7458        ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7459         (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7460        (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7461         !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7462      unsigned NewOpc;
7463      switch (Inst.getOpcode()) {
7464        default: llvm_unreachable("unexpected opcode");
7465        case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
7466        case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
7467        case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
7468        case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
7469        case ARM::t2RORrr: NewOpc = ARM::tROR; break;
7470        case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
7471      }
7472      MCInst TmpInst;
7473      TmpInst.setOpcode(NewOpc);
7474      TmpInst.addOperand(Inst.getOperand(0));
7475      TmpInst.addOperand(Inst.getOperand(5));
7476      TmpInst.addOperand(Inst.getOperand(1));
7477      TmpInst.addOperand(Inst.getOperand(2));
7478      TmpInst.addOperand(Inst.getOperand(3));
7479      TmpInst.addOperand(Inst.getOperand(4));
7480      Inst = TmpInst;
7481      return true;
7482    }
7483    return false;
7484  }
7485  case ARM::t2ANDrr:
7486  case ARM::t2EORrr:
7487  case ARM::t2ADCrr:
7488  case ARM::t2ORRrr:
7489  {
7490    // Assemblers should use the narrow encodings of these instructions when permissible.
7491    // These instructions are special in that they are commutable, so shorter encodings
7492    // are available more often.
7493    if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7494         isARMLowRegister(Inst.getOperand(2).getReg())) &&
7495        (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
7496         Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
7497        ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7498         (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7499        (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7500         !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7501      unsigned NewOpc;
7502      switch (Inst.getOpcode()) {
7503        default: llvm_unreachable("unexpected opcode");
7504        case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
7505        case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
7506        case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
7507        case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
7508      }
7509      MCInst TmpInst;
7510      TmpInst.setOpcode(NewOpc);
7511      TmpInst.addOperand(Inst.getOperand(0));
7512      TmpInst.addOperand(Inst.getOperand(5));
7513      if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
7514        TmpInst.addOperand(Inst.getOperand(1));
7515        TmpInst.addOperand(Inst.getOperand(2));
7516      } else {
7517        TmpInst.addOperand(Inst.getOperand(2));
7518        TmpInst.addOperand(Inst.getOperand(1));
7519      }
7520      TmpInst.addOperand(Inst.getOperand(3));
7521      TmpInst.addOperand(Inst.getOperand(4));
7522      Inst = TmpInst;
7523      return true;
7524    }
7525    return false;
7526  }
7527  }
7528  return false;
7529}
7530
7531unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
7532  // 16-bit thumb arithmetic instructions either require or preclude the 'S'
7533  // suffix depending on whether they're in an IT block or not.
7534  unsigned Opc = Inst.getOpcode();
7535  const MCInstrDesc &MCID = MII.get(Opc);
7536  if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
7537    assert(MCID.hasOptionalDef() &&
7538           "optionally flag setting instruction missing optional def operand");
7539    assert(MCID.NumOperands == Inst.getNumOperands() &&
7540           "operand count mismatch!");
7541    // Find the optional-def operand (cc_out).
7542    unsigned OpNo;
7543    for (OpNo = 0;
7544         !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
7545         ++OpNo)
7546      ;
7547    // If we're parsing Thumb1, reject it completely.
7548    if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
7549      return Match_MnemonicFail;
7550    // If we're parsing Thumb2, which form is legal depends on whether we're
7551    // in an IT block.
7552    if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
7553        !inITBlock())
7554      return Match_RequiresITBlock;
7555    if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
7556        inITBlock())
7557      return Match_RequiresNotITBlock;
7558  }
7559  // Some high-register supporting Thumb1 encodings only allow both registers
7560  // to be from r0-r7 when in Thumb2.
7561  else if (Opc == ARM::tADDhirr && isThumbOne() &&
7562           isARMLowRegister(Inst.getOperand(1).getReg()) &&
7563           isARMLowRegister(Inst.getOperand(2).getReg()))
7564    return Match_RequiresThumb2;
7565  // Others only require ARMv6 or later.
7566  else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
7567           isARMLowRegister(Inst.getOperand(0).getReg()) &&
7568           isARMLowRegister(Inst.getOperand(1).getReg()))
7569    return Match_RequiresV6;
7570  return Match_Success;
7571}
7572
7573static const char *getSubtargetFeatureName(unsigned Val);
7574bool ARMAsmParser::
7575MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
7576                        SmallVectorImpl<MCParsedAsmOperand*> &Operands,
7577                        MCStreamer &Out, unsigned &ErrorInfo,
7578                        bool MatchingInlineAsm) {
7579  MCInst Inst;
7580  unsigned MatchResult;
7581
7582  MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
7583                                     MatchingInlineAsm);
7584  switch (MatchResult) {
7585  default: break;
7586  case Match_Success:
7587    // Context sensitive operand constraints aren't handled by the matcher,
7588    // so check them here.
7589    if (validateInstruction(Inst, Operands)) {
7590      // Still progress the IT block, otherwise one wrong condition causes
7591      // nasty cascading errors.
7592      forwardITPosition();
7593      return true;
7594    }
7595
7596    // Some instructions need post-processing to, for example, tweak which
7597    // encoding is selected. Loop on it while changes happen so the
7598    // individual transformations can chain off each other. E.g.,
7599    // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
7600    while (processInstruction(Inst, Operands))
7601      ;
7602
7603    // Only move forward at the very end so that everything in validate
7604    // and process gets a consistent answer about whether we're in an IT
7605    // block.
7606    forwardITPosition();
7607
7608    // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
7609    // doesn't actually encode.
7610    if (Inst.getOpcode() == ARM::ITasm)
7611      return false;
7612
7613    Inst.setLoc(IDLoc);
7614    Out.EmitInstruction(Inst);
7615    return false;
7616  case Match_MissingFeature: {
7617    assert(ErrorInfo && "Unknown missing feature!");
7618    // Special case the error message for the very common case where only
7619    // a single subtarget feature is missing (Thumb vs. ARM, e.g.).
7620    std::string Msg = "instruction requires:";
7621    unsigned Mask = 1;
7622    for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
7623      if (ErrorInfo & Mask) {
7624        Msg += " ";
7625        Msg += getSubtargetFeatureName(ErrorInfo & Mask);
7626      }
7627      Mask <<= 1;
7628    }
7629    return Error(IDLoc, Msg);
7630  }
7631  case Match_InvalidOperand: {
7632    SMLoc ErrorLoc = IDLoc;
7633    if (ErrorInfo != ~0U) {
7634      if (ErrorInfo >= Operands.size())
7635        return Error(IDLoc, "too few operands for instruction");
7636
7637      ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7638      if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7639    }
7640
7641    return Error(ErrorLoc, "invalid operand for instruction");
7642  }
7643  case Match_MnemonicFail:
7644    return Error(IDLoc, "invalid instruction",
7645                 ((ARMOperand*)Operands[0])->getLocRange());
7646  case Match_RequiresNotITBlock:
7647    return Error(IDLoc, "flag setting instruction only valid outside IT block");
7648  case Match_RequiresITBlock:
7649    return Error(IDLoc, "instruction only valid inside IT block");
7650  case Match_RequiresV6:
7651    return Error(IDLoc, "instruction variant requires ARMv6 or later");
7652  case Match_RequiresThumb2:
7653    return Error(IDLoc, "instruction variant requires Thumb2");
7654  case Match_ImmRange0_4: {
7655    SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7656    if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7657    return Error(ErrorLoc, "immediate operand must be in the range [0,4]");
7658  }
7659  case Match_ImmRange0_15: {
7660    SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7661    if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7662    return Error(ErrorLoc, "immediate operand must be in the range [0,15]");
7663  }
7664  }
7665
7666  llvm_unreachable("Implement any new match types added!");
7667}
7668
7669/// parseDirective parses the arm specific directives
7670bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
7671  StringRef IDVal = DirectiveID.getIdentifier();
7672  if (IDVal == ".word")
7673    return parseDirectiveWord(4, DirectiveID.getLoc());
7674  else if (IDVal == ".thumb")
7675    return parseDirectiveThumb(DirectiveID.getLoc());
7676  else if (IDVal == ".arm")
7677    return parseDirectiveARM(DirectiveID.getLoc());
7678  else if (IDVal == ".thumb_func")
7679    return parseDirectiveThumbFunc(DirectiveID.getLoc());
7680  else if (IDVal == ".code")
7681    return parseDirectiveCode(DirectiveID.getLoc());
7682  else if (IDVal == ".syntax")
7683    return parseDirectiveSyntax(DirectiveID.getLoc());
7684  else if (IDVal == ".unreq")
7685    return parseDirectiveUnreq(DirectiveID.getLoc());
7686  else if (IDVal == ".arch")
7687    return parseDirectiveArch(DirectiveID.getLoc());
7688  else if (IDVal == ".eabi_attribute")
7689    return parseDirectiveEabiAttr(DirectiveID.getLoc());
7690  else if (IDVal == ".fnstart")
7691    return parseDirectiveFnStart(DirectiveID.getLoc());
7692  else if (IDVal == ".fnend")
7693    return parseDirectiveFnEnd(DirectiveID.getLoc());
7694  else if (IDVal == ".cantunwind")
7695    return parseDirectiveCantUnwind(DirectiveID.getLoc());
7696  else if (IDVal == ".personality")
7697    return parseDirectivePersonality(DirectiveID.getLoc());
7698  else if (IDVal == ".handlerdata")
7699    return parseDirectiveHandlerData(DirectiveID.getLoc());
7700  else if (IDVal == ".setfp")
7701    return parseDirectiveSetFP(DirectiveID.getLoc());
7702  else if (IDVal == ".pad")
7703    return parseDirectivePad(DirectiveID.getLoc());
7704  else if (IDVal == ".save")
7705    return parseDirectiveRegSave(DirectiveID.getLoc(), false);
7706  else if (IDVal == ".vsave")
7707    return parseDirectiveRegSave(DirectiveID.getLoc(), true);
7708  return true;
7709}
7710
7711/// parseDirectiveWord
7712///  ::= .word [ expression (, expression)* ]
7713bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
7714  if (getLexer().isNot(AsmToken::EndOfStatement)) {
7715    for (;;) {
7716      const MCExpr *Value;
7717      if (getParser().parseExpression(Value))
7718        return true;
7719
7720      getParser().getStreamer().EmitValue(Value, Size);
7721
7722      if (getLexer().is(AsmToken::EndOfStatement))
7723        break;
7724
7725      // FIXME: Improve diagnostic.
7726      if (getLexer().isNot(AsmToken::Comma))
7727        return Error(L, "unexpected token in directive");
7728      Parser.Lex();
7729    }
7730  }
7731
7732  Parser.Lex();
7733  return false;
7734}
7735
7736/// parseDirectiveThumb
7737///  ::= .thumb
7738bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
7739  if (getLexer().isNot(AsmToken::EndOfStatement))
7740    return Error(L, "unexpected token in directive");
7741  Parser.Lex();
7742
7743  if (!hasThumb())
7744    return Error(L, "target does not support Thumb mode");
7745
7746  if (!isThumb())
7747    SwitchMode();
7748  getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
7749  return false;
7750}
7751
7752/// parseDirectiveARM
7753///  ::= .arm
7754bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
7755  if (getLexer().isNot(AsmToken::EndOfStatement))
7756    return Error(L, "unexpected token in directive");
7757  Parser.Lex();
7758
7759  if (!hasARM())
7760    return Error(L, "target does not support ARM mode");
7761
7762  if (isThumb())
7763    SwitchMode();
7764  getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
7765  return false;
7766}
7767
7768/// parseDirectiveThumbFunc
7769///  ::= .thumbfunc symbol_name
7770bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
7771  const MCAsmInfo *MAI = getParser().getStreamer().getContext().getAsmInfo();
7772  bool isMachO = MAI->hasSubsectionsViaSymbols();
7773  StringRef Name;
7774  bool needFuncName = true;
7775
7776  // Darwin asm has (optionally) function name after .thumb_func direction
7777  // ELF doesn't
7778  if (isMachO) {
7779    const AsmToken &Tok = Parser.getTok();
7780    if (Tok.isNot(AsmToken::EndOfStatement)) {
7781      if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
7782        return Error(L, "unexpected token in .thumb_func directive");
7783      Name = Tok.getIdentifier();
7784      Parser.Lex(); // Consume the identifier token.
7785      needFuncName = false;
7786    }
7787  }
7788
7789  if (getLexer().isNot(AsmToken::EndOfStatement))
7790    return Error(L, "unexpected token in directive");
7791
7792  // Eat the end of statement and any blank lines that follow.
7793  while (getLexer().is(AsmToken::EndOfStatement))
7794    Parser.Lex();
7795
7796  // FIXME: assuming function name will be the line following .thumb_func
7797  // We really should be checking the next symbol definition even if there's
7798  // stuff in between.
7799  if (needFuncName) {
7800    Name = Parser.getTok().getIdentifier();
7801  }
7802
7803  // Mark symbol as a thumb symbol.
7804  MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
7805  getParser().getStreamer().EmitThumbFunc(Func);
7806  return false;
7807}
7808
7809/// parseDirectiveSyntax
7810///  ::= .syntax unified | divided
7811bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
7812  const AsmToken &Tok = Parser.getTok();
7813  if (Tok.isNot(AsmToken::Identifier))
7814    return Error(L, "unexpected token in .syntax directive");
7815  StringRef Mode = Tok.getString();
7816  if (Mode == "unified" || Mode == "UNIFIED")
7817    Parser.Lex();
7818  else if (Mode == "divided" || Mode == "DIVIDED")
7819    return Error(L, "'.syntax divided' arm asssembly not supported");
7820  else
7821    return Error(L, "unrecognized syntax mode in .syntax directive");
7822
7823  if (getLexer().isNot(AsmToken::EndOfStatement))
7824    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
7825  Parser.Lex();
7826
7827  // TODO tell the MC streamer the mode
7828  // getParser().getStreamer().Emit???();
7829  return false;
7830}
7831
7832/// parseDirectiveCode
7833///  ::= .code 16 | 32
7834bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
7835  const AsmToken &Tok = Parser.getTok();
7836  if (Tok.isNot(AsmToken::Integer))
7837    return Error(L, "unexpected token in .code directive");
7838  int64_t Val = Parser.getTok().getIntVal();
7839  if (Val == 16)
7840    Parser.Lex();
7841  else if (Val == 32)
7842    Parser.Lex();
7843  else
7844    return Error(L, "invalid operand to .code directive");
7845
7846  if (getLexer().isNot(AsmToken::EndOfStatement))
7847    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
7848  Parser.Lex();
7849
7850  if (Val == 16) {
7851    if (!hasThumb())
7852      return Error(L, "target does not support Thumb mode");
7853
7854    if (!isThumb())
7855      SwitchMode();
7856    getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
7857  } else {
7858    if (!hasARM())
7859      return Error(L, "target does not support ARM mode");
7860
7861    if (isThumb())
7862      SwitchMode();
7863    getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
7864  }
7865
7866  return false;
7867}
7868
7869/// parseDirectiveReq
7870///  ::= name .req registername
7871bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
7872  Parser.Lex(); // Eat the '.req' token.
7873  unsigned Reg;
7874  SMLoc SRegLoc, ERegLoc;
7875  if (ParseRegister(Reg, SRegLoc, ERegLoc)) {
7876    Parser.eatToEndOfStatement();
7877    return Error(SRegLoc, "register name expected");
7878  }
7879
7880  // Shouldn't be anything else.
7881  if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
7882    Parser.eatToEndOfStatement();
7883    return Error(Parser.getTok().getLoc(),
7884                 "unexpected input in .req directive.");
7885  }
7886
7887  Parser.Lex(); // Consume the EndOfStatement
7888
7889  if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg)
7890    return Error(SRegLoc, "redefinition of '" + Name +
7891                          "' does not match original.");
7892
7893  return false;
7894}
7895
7896/// parseDirectiveUneq
7897///  ::= .unreq registername
7898bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
7899  if (Parser.getTok().isNot(AsmToken::Identifier)) {
7900    Parser.eatToEndOfStatement();
7901    return Error(L, "unexpected input in .unreq directive.");
7902  }
7903  RegisterReqs.erase(Parser.getTok().getIdentifier());
7904  Parser.Lex(); // Eat the identifier.
7905  return false;
7906}
7907
7908/// parseDirectiveArch
7909///  ::= .arch token
7910bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
7911  return true;
7912}
7913
7914/// parseDirectiveEabiAttr
7915///  ::= .eabi_attribute int, int
7916bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
7917  return true;
7918}
7919
7920/// parseDirectiveFnStart
7921///  ::= .fnstart
7922bool ARMAsmParser::parseDirectiveFnStart(SMLoc L) {
7923  if (FnStartLoc.isValid()) {
7924    Error(L, ".fnstart starts before the end of previous one");
7925    Error(FnStartLoc, "previous .fnstart starts here");
7926    return true;
7927  }
7928
7929  FnStartLoc = L;
7930  getParser().getStreamer().EmitFnStart();
7931  return false;
7932}
7933
7934/// parseDirectiveFnEnd
7935///  ::= .fnend
7936bool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) {
7937  // Check the ordering of unwind directives
7938  if (!FnStartLoc.isValid())
7939    return Error(L, ".fnstart must precede .fnend directive");
7940
7941  // Reset the unwind directives parser state
7942  resetUnwindDirectiveParserState();
7943
7944  getParser().getStreamer().EmitFnEnd();
7945  return false;
7946}
7947
7948/// parseDirectiveCantUnwind
7949///  ::= .cantunwind
7950bool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) {
7951  // Check the ordering of unwind directives
7952  CantUnwindLoc = L;
7953  if (!FnStartLoc.isValid())
7954    return Error(L, ".fnstart must precede .cantunwind directive");
7955  if (HandlerDataLoc.isValid()) {
7956    Error(L, ".cantunwind can't be used with .handlerdata directive");
7957    Error(HandlerDataLoc, ".handlerdata was specified here");
7958    return true;
7959  }
7960  if (PersonalityLoc.isValid()) {
7961    Error(L, ".cantunwind can't be used with .personality directive");
7962    Error(PersonalityLoc, ".personality was specified here");
7963    return true;
7964  }
7965
7966  getParser().getStreamer().EmitCantUnwind();
7967  return false;
7968}
7969
7970/// parseDirectivePersonality
7971///  ::= .personality name
7972bool ARMAsmParser::parseDirectivePersonality(SMLoc L) {
7973  // Check the ordering of unwind directives
7974  PersonalityLoc = L;
7975  if (!FnStartLoc.isValid())
7976    return Error(L, ".fnstart must precede .personality directive");
7977  if (CantUnwindLoc.isValid()) {
7978    Error(L, ".personality can't be used with .cantunwind directive");
7979    Error(CantUnwindLoc, ".cantunwind was specified here");
7980    return true;
7981  }
7982  if (HandlerDataLoc.isValid()) {
7983    Error(L, ".personality must precede .handlerdata directive");
7984    Error(HandlerDataLoc, ".handlerdata was specified here");
7985    return true;
7986  }
7987
7988  // Parse the name of the personality routine
7989  if (Parser.getTok().isNot(AsmToken::Identifier)) {
7990    Parser.eatToEndOfStatement();
7991    return Error(L, "unexpected input in .personality directive.");
7992  }
7993  StringRef Name(Parser.getTok().getIdentifier());
7994  Parser.Lex();
7995
7996  MCSymbol *PR = getParser().getContext().GetOrCreateSymbol(Name);
7997  getParser().getStreamer().EmitPersonality(PR);
7998  return false;
7999}
8000
8001/// parseDirectiveHandlerData
8002///  ::= .handlerdata
8003bool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) {
8004  // Check the ordering of unwind directives
8005  HandlerDataLoc = L;
8006  if (!FnStartLoc.isValid())
8007    return Error(L, ".fnstart must precede .personality directive");
8008  if (CantUnwindLoc.isValid()) {
8009    Error(L, ".handlerdata can't be used with .cantunwind directive");
8010    Error(CantUnwindLoc, ".cantunwind was specified here");
8011    return true;
8012  }
8013
8014  getParser().getStreamer().EmitHandlerData();
8015  return false;
8016}
8017
8018/// parseDirectiveSetFP
8019///  ::= .setfp fpreg, spreg [, offset]
8020bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) {
8021  // Check the ordering of unwind directives
8022  if (!FnStartLoc.isValid())
8023    return Error(L, ".fnstart must precede .setfp directive");
8024  if (HandlerDataLoc.isValid())
8025    return Error(L, ".setfp must precede .handlerdata directive");
8026
8027  // Parse fpreg
8028  SMLoc NewFPRegLoc = Parser.getTok().getLoc();
8029  int NewFPReg = tryParseRegister();
8030  if (NewFPReg == -1)
8031    return Error(NewFPRegLoc, "frame pointer register expected");
8032
8033  // Consume comma
8034  if (!Parser.getTok().is(AsmToken::Comma))
8035    return Error(Parser.getTok().getLoc(), "comma expected");
8036  Parser.Lex(); // skip comma
8037
8038  // Parse spreg
8039  SMLoc NewSPRegLoc = Parser.getTok().getLoc();
8040  int NewSPReg = tryParseRegister();
8041  if (NewSPReg == -1)
8042    return Error(NewSPRegLoc, "stack pointer register expected");
8043
8044  if (NewSPReg != ARM::SP && NewSPReg != FPReg)
8045    return Error(NewSPRegLoc,
8046                 "register should be either $sp or the latest fp register");
8047
8048  // Update the frame pointer register
8049  FPReg = NewFPReg;
8050
8051  // Parse offset
8052  int64_t Offset = 0;
8053  if (Parser.getTok().is(AsmToken::Comma)) {
8054    Parser.Lex(); // skip comma
8055
8056    if (Parser.getTok().isNot(AsmToken::Hash) &&
8057        Parser.getTok().isNot(AsmToken::Dollar)) {
8058      return Error(Parser.getTok().getLoc(), "'#' expected");
8059    }
8060    Parser.Lex(); // skip hash token.
8061
8062    const MCExpr *OffsetExpr;
8063    SMLoc ExLoc = Parser.getTok().getLoc();
8064    SMLoc EndLoc;
8065    if (getParser().parseExpression(OffsetExpr, EndLoc))
8066      return Error(ExLoc, "malformed setfp offset");
8067    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
8068    if (!CE)
8069      return Error(ExLoc, "setfp offset must be an immediate");
8070
8071    Offset = CE->getValue();
8072  }
8073
8074  getParser().getStreamer().EmitSetFP(static_cast<unsigned>(NewFPReg),
8075                                      static_cast<unsigned>(NewSPReg),
8076                                      Offset);
8077  return false;
8078}
8079
8080/// parseDirective
8081///  ::= .pad offset
8082bool ARMAsmParser::parseDirectivePad(SMLoc L) {
8083  // Check the ordering of unwind directives
8084  if (!FnStartLoc.isValid())
8085    return Error(L, ".fnstart must precede .pad directive");
8086  if (HandlerDataLoc.isValid())
8087    return Error(L, ".pad must precede .handlerdata directive");
8088
8089  // Parse the offset
8090  if (Parser.getTok().isNot(AsmToken::Hash) &&
8091      Parser.getTok().isNot(AsmToken::Dollar)) {
8092    return Error(Parser.getTok().getLoc(), "'#' expected");
8093  }
8094  Parser.Lex(); // skip hash token.
8095
8096  const MCExpr *OffsetExpr;
8097  SMLoc ExLoc = Parser.getTok().getLoc();
8098  SMLoc EndLoc;
8099  if (getParser().parseExpression(OffsetExpr, EndLoc))
8100    return Error(ExLoc, "malformed pad offset");
8101  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
8102  if (!CE)
8103    return Error(ExLoc, "pad offset must be an immediate");
8104
8105  getParser().getStreamer().EmitPad(CE->getValue());
8106  return false;
8107}
8108
8109/// parseDirectiveRegSave
8110///  ::= .save  { registers }
8111///  ::= .vsave { registers }
8112bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) {
8113  // Check the ordering of unwind directives
8114  if (!FnStartLoc.isValid())
8115    return Error(L, ".fnstart must precede .save or .vsave directives");
8116  if (HandlerDataLoc.isValid())
8117    return Error(L, ".save or .vsave must precede .handlerdata directive");
8118
8119  // RAII object to make sure parsed operands are deleted.
8120  struct CleanupObject {
8121    SmallVector<MCParsedAsmOperand *, 1> Operands;
8122    ~CleanupObject() {
8123      for (unsigned I = 0, E = Operands.size(); I != E; ++I)
8124        delete Operands[I];
8125    }
8126  } CO;
8127
8128  // Parse the register list
8129  if (parseRegisterList(CO.Operands))
8130    return true;
8131  ARMOperand *Op = (ARMOperand*)CO.Operands[0];
8132  if (!IsVector && !Op->isRegList())
8133    return Error(L, ".save expects GPR registers");
8134  if (IsVector && !Op->isDPRRegList())
8135    return Error(L, ".vsave expects DPR registers");
8136
8137  getParser().getStreamer().EmitRegSave(Op->getRegList(), IsVector);
8138  return false;
8139}
8140
8141/// Force static initialization.
8142extern "C" void LLVMInitializeARMAsmParser() {
8143  RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
8144  RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
8145}
8146
8147#define GET_REGISTER_MATCHER
8148#define GET_SUBTARGET_FEATURE_NAME
8149#define GET_MATCHER_IMPLEMENTATION
8150#include "ARMGenAsmMatcher.inc"
8151
8152// Define this matcher function after the auto-generated include so we
8153// have the match class enum definitions.
8154unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand *AsmOp,
8155                                                  unsigned Kind) {
8156  ARMOperand *Op = static_cast<ARMOperand*>(AsmOp);
8157  // If the kind is a token for a literal immediate, check if our asm
8158  // operand matches. This is for InstAliases which have a fixed-value
8159  // immediate in the syntax.
8160  if (Kind == MCK__35_0 && Op->isImm()) {
8161    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
8162    if (!CE)
8163      return Match_InvalidOperand;
8164    if (CE->getValue() == 0)
8165      return Match_Success;
8166  }
8167  return Match_InvalidOperand;
8168}
8169