ARMAsmParser.cpp revision 756d2cc2f7f6745603fdc0ec1ed4476d06385845
1//===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10#include "MCTargetDesc/ARMBaseInfo.h" 11#include "MCTargetDesc/ARMAddressingModes.h" 12#include "MCTargetDesc/ARMMCExpr.h" 13#include "llvm/MC/MCParser/MCAsmLexer.h" 14#include "llvm/MC/MCParser/MCAsmParser.h" 15#include "llvm/MC/MCParser/MCParsedAsmOperand.h" 16#include "llvm/MC/MCAsmInfo.h" 17#include "llvm/MC/MCContext.h" 18#include "llvm/MC/MCStreamer.h" 19#include "llvm/MC/MCExpr.h" 20#include "llvm/MC/MCInst.h" 21#include "llvm/MC/MCInstrDesc.h" 22#include "llvm/MC/MCRegisterInfo.h" 23#include "llvm/MC/MCSubtargetInfo.h" 24#include "llvm/MC/MCTargetAsmParser.h" 25#include "llvm/Support/MathExtras.h" 26#include "llvm/Support/SourceMgr.h" 27#include "llvm/Support/TargetRegistry.h" 28#include "llvm/Support/raw_ostream.h" 29#include "llvm/ADT/BitVector.h" 30#include "llvm/ADT/OwningPtr.h" 31#include "llvm/ADT/STLExtras.h" 32#include "llvm/ADT/SmallVector.h" 33#include "llvm/ADT/StringSwitch.h" 34#include "llvm/ADT/Twine.h" 35 36using namespace llvm; 37 38namespace { 39 40class ARMOperand; 41 42enum VectorLaneTy { NoLanes, AllLanes, IndexedLane }; 43 44class ARMAsmParser : public MCTargetAsmParser { 45 MCSubtargetInfo &STI; 46 MCAsmParser &Parser; 47 const MCRegisterInfo *MRI; 48 49 // Map of register aliases registers via the .req directive. 50 StringMap<unsigned> RegisterReqs; 51 52 struct { 53 ARMCC::CondCodes Cond; // Condition for IT block. 54 unsigned Mask:4; // Condition mask for instructions. 55 // Starting at first 1 (from lsb). 56 // '1' condition as indicated in IT. 57 // '0' inverse of condition (else). 58 // Count of instructions in IT block is 59 // 4 - trailingzeroes(mask) 60 61 bool FirstCond; // Explicit flag for when we're parsing the 62 // First instruction in the IT block. It's 63 // implied in the mask, so needs special 64 // handling. 65 66 unsigned CurPosition; // Current position in parsing of IT 67 // block. In range [0,3]. Initialized 68 // according to count of instructions in block. 69 // ~0U if no active IT block. 70 } ITState; 71 bool inITBlock() { return ITState.CurPosition != ~0U;} 72 void forwardITPosition() { 73 if (!inITBlock()) return; 74 // Move to the next instruction in the IT block, if there is one. If not, 75 // mark the block as done. 76 unsigned TZ = CountTrailingZeros_32(ITState.Mask); 77 if (++ITState.CurPosition == 5 - TZ) 78 ITState.CurPosition = ~0U; // Done with the IT block after this. 79 } 80 81 82 MCAsmParser &getParser() const { return Parser; } 83 MCAsmLexer &getLexer() const { return Parser.getLexer(); } 84 85 bool Warning(SMLoc L, const Twine &Msg, 86 ArrayRef<SMRange> Ranges = ArrayRef<SMRange>()) { 87 return Parser.Warning(L, Msg, Ranges); 88 } 89 bool Error(SMLoc L, const Twine &Msg, 90 ArrayRef<SMRange> Ranges = ArrayRef<SMRange>()) { 91 return Parser.Error(L, Msg, Ranges); 92 } 93 94 int tryParseRegister(); 95 bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &); 96 int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &); 97 bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &); 98 bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &); 99 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic); 100 bool parsePrefix(ARMMCExpr::VariantKind &RefKind); 101 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType, 102 unsigned &ShiftAmount); 103 bool parseDirectiveWord(unsigned Size, SMLoc L); 104 bool parseDirectiveThumb(SMLoc L); 105 bool parseDirectiveARM(SMLoc L); 106 bool parseDirectiveThumbFunc(SMLoc L); 107 bool parseDirectiveCode(SMLoc L); 108 bool parseDirectiveSyntax(SMLoc L); 109 bool parseDirectiveReq(StringRef Name, SMLoc L); 110 bool parseDirectiveUnreq(SMLoc L); 111 bool parseDirectiveArch(SMLoc L); 112 bool parseDirectiveEabiAttr(SMLoc L); 113 114 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode, 115 bool &CarrySetting, unsigned &ProcessorIMod, 116 StringRef &ITMask); 117 void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet, 118 bool &CanAcceptPredicationCode); 119 120 bool isThumb() const { 121 // FIXME: Can tablegen auto-generate this? 122 return (STI.getFeatureBits() & ARM::ModeThumb) != 0; 123 } 124 bool isThumbOne() const { 125 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0; 126 } 127 bool isThumbTwo() const { 128 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2); 129 } 130 bool hasV6Ops() const { 131 return STI.getFeatureBits() & ARM::HasV6Ops; 132 } 133 bool hasV7Ops() const { 134 return STI.getFeatureBits() & ARM::HasV7Ops; 135 } 136 void SwitchMode() { 137 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb)); 138 setAvailableFeatures(FB); 139 } 140 bool isMClass() const { 141 return STI.getFeatureBits() & ARM::FeatureMClass; 142 } 143 144 /// @name Auto-generated Match Functions 145 /// { 146 147#define GET_ASSEMBLER_HEADER 148#include "ARMGenAsmMatcher.inc" 149 150 /// } 151 152 OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&); 153 OperandMatchResultTy parseCoprocNumOperand( 154 SmallVectorImpl<MCParsedAsmOperand*>&); 155 OperandMatchResultTy parseCoprocRegOperand( 156 SmallVectorImpl<MCParsedAsmOperand*>&); 157 OperandMatchResultTy parseCoprocOptionOperand( 158 SmallVectorImpl<MCParsedAsmOperand*>&); 159 OperandMatchResultTy parseMemBarrierOptOperand( 160 SmallVectorImpl<MCParsedAsmOperand*>&); 161 OperandMatchResultTy parseProcIFlagsOperand( 162 SmallVectorImpl<MCParsedAsmOperand*>&); 163 OperandMatchResultTy parseMSRMaskOperand( 164 SmallVectorImpl<MCParsedAsmOperand*>&); 165 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O, 166 StringRef Op, int Low, int High); 167 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) { 168 return parsePKHImm(O, "lsl", 0, 31); 169 } 170 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) { 171 return parsePKHImm(O, "asr", 1, 32); 172 } 173 OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&); 174 OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&); 175 OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&); 176 OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&); 177 OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&); 178 OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&); 179 OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&); 180 OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&); 181 OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index); 182 183 // Asm Match Converter Methods 184 void cvtT2LdrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &); 185 void cvtT2StrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &); 186 void cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, 187 const SmallVectorImpl<MCParsedAsmOperand*> &); 188 void cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, 189 const SmallVectorImpl<MCParsedAsmOperand*> &); 190 void cvtLdWriteBackRegAddrMode2(MCInst &Inst, 191 const SmallVectorImpl<MCParsedAsmOperand*> &); 192 void cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, 193 const SmallVectorImpl<MCParsedAsmOperand*> &); 194 void cvtStWriteBackRegAddrModeImm12(MCInst &Inst, 195 const SmallVectorImpl<MCParsedAsmOperand*> &); 196 void cvtStWriteBackRegAddrMode2(MCInst &Inst, 197 const SmallVectorImpl<MCParsedAsmOperand*> &); 198 void cvtStWriteBackRegAddrMode3(MCInst &Inst, 199 const SmallVectorImpl<MCParsedAsmOperand*> &); 200 void cvtLdExtTWriteBackImm(MCInst &Inst, 201 const SmallVectorImpl<MCParsedAsmOperand*> &); 202 void cvtLdExtTWriteBackReg(MCInst &Inst, 203 const SmallVectorImpl<MCParsedAsmOperand*> &); 204 void cvtStExtTWriteBackImm(MCInst &Inst, 205 const SmallVectorImpl<MCParsedAsmOperand*> &); 206 void cvtStExtTWriteBackReg(MCInst &Inst, 207 const SmallVectorImpl<MCParsedAsmOperand*> &); 208 void cvtLdrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &); 209 void cvtStrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &); 210 void cvtLdWriteBackRegAddrMode3(MCInst &Inst, 211 const SmallVectorImpl<MCParsedAsmOperand*> &); 212 void cvtThumbMultiply(MCInst &Inst, 213 const SmallVectorImpl<MCParsedAsmOperand*> &); 214 void cvtVLDwbFixed(MCInst &Inst, 215 const SmallVectorImpl<MCParsedAsmOperand*> &); 216 void cvtVLDwbRegister(MCInst &Inst, 217 const SmallVectorImpl<MCParsedAsmOperand*> &); 218 void cvtVSTwbFixed(MCInst &Inst, 219 const SmallVectorImpl<MCParsedAsmOperand*> &); 220 void cvtVSTwbRegister(MCInst &Inst, 221 const SmallVectorImpl<MCParsedAsmOperand*> &); 222 bool validateInstruction(MCInst &Inst, 223 const SmallVectorImpl<MCParsedAsmOperand*> &Ops); 224 bool processInstruction(MCInst &Inst, 225 const SmallVectorImpl<MCParsedAsmOperand*> &Ops); 226 bool shouldOmitCCOutOperand(StringRef Mnemonic, 227 SmallVectorImpl<MCParsedAsmOperand*> &Operands); 228 229public: 230 enum ARMMatchResultTy { 231 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY, 232 Match_RequiresNotITBlock, 233 Match_RequiresV6, 234 Match_RequiresThumb2, 235#define GET_OPERAND_DIAGNOSTIC_TYPES 236#include "ARMGenAsmMatcher.inc" 237 238 }; 239 240 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser) 241 : MCTargetAsmParser(), STI(_STI), Parser(_Parser) { 242 MCAsmParserExtension::Initialize(_Parser); 243 244 // Cache the MCRegisterInfo. 245 MRI = &getContext().getRegisterInfo(); 246 247 // Initialize the set of available features. 248 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); 249 250 // Not in an ITBlock to start with. 251 ITState.CurPosition = ~0U; 252 } 253 254 // Implementation of the MCTargetAsmParser interface: 255 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc); 256 bool ParseInstruction(StringRef Name, SMLoc NameLoc, 257 SmallVectorImpl<MCParsedAsmOperand*> &Operands); 258 bool ParseDirective(AsmToken DirectiveID); 259 260 unsigned checkTargetMatchPredicate(MCInst &Inst); 261 262 bool MatchAndEmitInstruction(SMLoc IDLoc, 263 SmallVectorImpl<MCParsedAsmOperand*> &Operands, 264 MCStreamer &Out); 265}; 266} // end anonymous namespace 267 268namespace { 269 270/// ARMOperand - Instances of this class represent a parsed ARM machine 271/// instruction. 272class ARMOperand : public MCParsedAsmOperand { 273 enum KindTy { 274 k_CondCode, 275 k_CCOut, 276 k_ITCondMask, 277 k_CoprocNum, 278 k_CoprocReg, 279 k_CoprocOption, 280 k_Immediate, 281 k_MemBarrierOpt, 282 k_Memory, 283 k_PostIndexRegister, 284 k_MSRMask, 285 k_ProcIFlags, 286 k_VectorIndex, 287 k_Register, 288 k_RegisterList, 289 k_DPRRegisterList, 290 k_SPRRegisterList, 291 k_VectorList, 292 k_VectorListAllLanes, 293 k_VectorListIndexed, 294 k_ShiftedRegister, 295 k_ShiftedImmediate, 296 k_ShifterImmediate, 297 k_RotateImmediate, 298 k_BitfieldDescriptor, 299 k_Token 300 } Kind; 301 302 SMLoc StartLoc, EndLoc; 303 SmallVector<unsigned, 8> Registers; 304 305 union { 306 struct { 307 ARMCC::CondCodes Val; 308 } CC; 309 310 struct { 311 unsigned Val; 312 } Cop; 313 314 struct { 315 unsigned Val; 316 } CoprocOption; 317 318 struct { 319 unsigned Mask:4; 320 } ITMask; 321 322 struct { 323 ARM_MB::MemBOpt Val; 324 } MBOpt; 325 326 struct { 327 ARM_PROC::IFlags Val; 328 } IFlags; 329 330 struct { 331 unsigned Val; 332 } MMask; 333 334 struct { 335 const char *Data; 336 unsigned Length; 337 } Tok; 338 339 struct { 340 unsigned RegNum; 341 } Reg; 342 343 // A vector register list is a sequential list of 1 to 4 registers. 344 struct { 345 unsigned RegNum; 346 unsigned Count; 347 unsigned LaneIndex; 348 bool isDoubleSpaced; 349 } VectorList; 350 351 struct { 352 unsigned Val; 353 } VectorIndex; 354 355 struct { 356 const MCExpr *Val; 357 } Imm; 358 359 /// Combined record for all forms of ARM address expressions. 360 struct { 361 unsigned BaseRegNum; 362 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset 363 // was specified. 364 const MCConstantExpr *OffsetImm; // Offset immediate value 365 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL 366 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg 367 unsigned ShiftImm; // shift for OffsetReg. 368 unsigned Alignment; // 0 = no alignment specified 369 // n = alignment in bytes (2, 4, 8, 16, or 32) 370 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit) 371 } Memory; 372 373 struct { 374 unsigned RegNum; 375 bool isAdd; 376 ARM_AM::ShiftOpc ShiftTy; 377 unsigned ShiftImm; 378 } PostIdxReg; 379 380 struct { 381 bool isASR; 382 unsigned Imm; 383 } ShifterImm; 384 struct { 385 ARM_AM::ShiftOpc ShiftTy; 386 unsigned SrcReg; 387 unsigned ShiftReg; 388 unsigned ShiftImm; 389 } RegShiftedReg; 390 struct { 391 ARM_AM::ShiftOpc ShiftTy; 392 unsigned SrcReg; 393 unsigned ShiftImm; 394 } RegShiftedImm; 395 struct { 396 unsigned Imm; 397 } RotImm; 398 struct { 399 unsigned LSB; 400 unsigned Width; 401 } Bitfield; 402 }; 403 404 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {} 405public: 406 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() { 407 Kind = o.Kind; 408 StartLoc = o.StartLoc; 409 EndLoc = o.EndLoc; 410 switch (Kind) { 411 case k_CondCode: 412 CC = o.CC; 413 break; 414 case k_ITCondMask: 415 ITMask = o.ITMask; 416 break; 417 case k_Token: 418 Tok = o.Tok; 419 break; 420 case k_CCOut: 421 case k_Register: 422 Reg = o.Reg; 423 break; 424 case k_RegisterList: 425 case k_DPRRegisterList: 426 case k_SPRRegisterList: 427 Registers = o.Registers; 428 break; 429 case k_VectorList: 430 case k_VectorListAllLanes: 431 case k_VectorListIndexed: 432 VectorList = o.VectorList; 433 break; 434 case k_CoprocNum: 435 case k_CoprocReg: 436 Cop = o.Cop; 437 break; 438 case k_CoprocOption: 439 CoprocOption = o.CoprocOption; 440 break; 441 case k_Immediate: 442 Imm = o.Imm; 443 break; 444 case k_MemBarrierOpt: 445 MBOpt = o.MBOpt; 446 break; 447 case k_Memory: 448 Memory = o.Memory; 449 break; 450 case k_PostIndexRegister: 451 PostIdxReg = o.PostIdxReg; 452 break; 453 case k_MSRMask: 454 MMask = o.MMask; 455 break; 456 case k_ProcIFlags: 457 IFlags = o.IFlags; 458 break; 459 case k_ShifterImmediate: 460 ShifterImm = o.ShifterImm; 461 break; 462 case k_ShiftedRegister: 463 RegShiftedReg = o.RegShiftedReg; 464 break; 465 case k_ShiftedImmediate: 466 RegShiftedImm = o.RegShiftedImm; 467 break; 468 case k_RotateImmediate: 469 RotImm = o.RotImm; 470 break; 471 case k_BitfieldDescriptor: 472 Bitfield = o.Bitfield; 473 break; 474 case k_VectorIndex: 475 VectorIndex = o.VectorIndex; 476 break; 477 } 478 } 479 480 /// getStartLoc - Get the location of the first token of this operand. 481 SMLoc getStartLoc() const { return StartLoc; } 482 /// getEndLoc - Get the location of the last token of this operand. 483 SMLoc getEndLoc() const { return EndLoc; } 484 485 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); } 486 487 ARMCC::CondCodes getCondCode() const { 488 assert(Kind == k_CondCode && "Invalid access!"); 489 return CC.Val; 490 } 491 492 unsigned getCoproc() const { 493 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!"); 494 return Cop.Val; 495 } 496 497 StringRef getToken() const { 498 assert(Kind == k_Token && "Invalid access!"); 499 return StringRef(Tok.Data, Tok.Length); 500 } 501 502 unsigned getReg() const { 503 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!"); 504 return Reg.RegNum; 505 } 506 507 const SmallVectorImpl<unsigned> &getRegList() const { 508 assert((Kind == k_RegisterList || Kind == k_DPRRegisterList || 509 Kind == k_SPRRegisterList) && "Invalid access!"); 510 return Registers; 511 } 512 513 const MCExpr *getImm() const { 514 assert(isImm() && "Invalid access!"); 515 return Imm.Val; 516 } 517 518 unsigned getVectorIndex() const { 519 assert(Kind == k_VectorIndex && "Invalid access!"); 520 return VectorIndex.Val; 521 } 522 523 ARM_MB::MemBOpt getMemBarrierOpt() const { 524 assert(Kind == k_MemBarrierOpt && "Invalid access!"); 525 return MBOpt.Val; 526 } 527 528 ARM_PROC::IFlags getProcIFlags() const { 529 assert(Kind == k_ProcIFlags && "Invalid access!"); 530 return IFlags.Val; 531 } 532 533 unsigned getMSRMask() const { 534 assert(Kind == k_MSRMask && "Invalid access!"); 535 return MMask.Val; 536 } 537 538 bool isCoprocNum() const { return Kind == k_CoprocNum; } 539 bool isCoprocReg() const { return Kind == k_CoprocReg; } 540 bool isCoprocOption() const { return Kind == k_CoprocOption; } 541 bool isCondCode() const { return Kind == k_CondCode; } 542 bool isCCOut() const { return Kind == k_CCOut; } 543 bool isITMask() const { return Kind == k_ITCondMask; } 544 bool isITCondCode() const { return Kind == k_CondCode; } 545 bool isImm() const { return Kind == k_Immediate; } 546 bool isFPImm() const { 547 if (!isImm()) return false; 548 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 549 if (!CE) return false; 550 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue())); 551 return Val != -1; 552 } 553 bool isFBits16() const { 554 if (!isImm()) return false; 555 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 556 if (!CE) return false; 557 int64_t Value = CE->getValue(); 558 return Value >= 0 && Value <= 16; 559 } 560 bool isFBits32() const { 561 if (!isImm()) return false; 562 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 563 if (!CE) return false; 564 int64_t Value = CE->getValue(); 565 return Value >= 1 && Value <= 32; 566 } 567 bool isImm8s4() const { 568 if (!isImm()) return false; 569 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 570 if (!CE) return false; 571 int64_t Value = CE->getValue(); 572 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020; 573 } 574 bool isImm0_1020s4() const { 575 if (!isImm()) return false; 576 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 577 if (!CE) return false; 578 int64_t Value = CE->getValue(); 579 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020; 580 } 581 bool isImm0_508s4() const { 582 if (!isImm()) return false; 583 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 584 if (!CE) return false; 585 int64_t Value = CE->getValue(); 586 return ((Value & 3) == 0) && Value >= 0 && Value <= 508; 587 } 588 bool isImm0_508s4Neg() const { 589 if (!isImm()) return false; 590 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 591 if (!CE) return false; 592 int64_t Value = -CE->getValue(); 593 // explicitly exclude zero. we want that to use the normal 0_508 version. 594 return ((Value & 3) == 0) && Value > 0 && Value <= 508; 595 } 596 bool isImm0_255() const { 597 if (!isImm()) return false; 598 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 599 if (!CE) return false; 600 int64_t Value = CE->getValue(); 601 return Value >= 0 && Value < 256; 602 } 603 bool isImm0_4095() const { 604 if (!isImm()) return false; 605 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 606 if (!CE) return false; 607 int64_t Value = CE->getValue(); 608 return Value >= 0 && Value < 4096; 609 } 610 bool isImm0_4095Neg() const { 611 if (!isImm()) return false; 612 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 613 if (!CE) return false; 614 int64_t Value = -CE->getValue(); 615 return Value > 0 && Value < 4096; 616 } 617 bool isImm0_1() const { 618 if (!isImm()) return false; 619 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 620 if (!CE) return false; 621 int64_t Value = CE->getValue(); 622 return Value >= 0 && Value < 2; 623 } 624 bool isImm0_3() const { 625 if (!isImm()) return false; 626 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 627 if (!CE) return false; 628 int64_t Value = CE->getValue(); 629 return Value >= 0 && Value < 4; 630 } 631 bool isImm0_7() const { 632 if (!isImm()) return false; 633 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 634 if (!CE) return false; 635 int64_t Value = CE->getValue(); 636 return Value >= 0 && Value < 8; 637 } 638 bool isImm0_15() const { 639 if (!isImm()) return false; 640 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 641 if (!CE) return false; 642 int64_t Value = CE->getValue(); 643 return Value >= 0 && Value < 16; 644 } 645 bool isImm0_31() const { 646 if (!isImm()) return false; 647 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 648 if (!CE) return false; 649 int64_t Value = CE->getValue(); 650 return Value >= 0 && Value < 32; 651 } 652 bool isImm0_63() const { 653 if (!isImm()) return false; 654 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 655 if (!CE) return false; 656 int64_t Value = CE->getValue(); 657 return Value >= 0 && Value < 64; 658 } 659 bool isImm8() const { 660 if (!isImm()) return false; 661 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 662 if (!CE) return false; 663 int64_t Value = CE->getValue(); 664 return Value == 8; 665 } 666 bool isImm16() const { 667 if (!isImm()) return false; 668 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 669 if (!CE) return false; 670 int64_t Value = CE->getValue(); 671 return Value == 16; 672 } 673 bool isImm32() const { 674 if (!isImm()) return false; 675 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 676 if (!CE) return false; 677 int64_t Value = CE->getValue(); 678 return Value == 32; 679 } 680 bool isShrImm8() const { 681 if (!isImm()) return false; 682 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 683 if (!CE) return false; 684 int64_t Value = CE->getValue(); 685 return Value > 0 && Value <= 8; 686 } 687 bool isShrImm16() const { 688 if (!isImm()) return false; 689 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 690 if (!CE) return false; 691 int64_t Value = CE->getValue(); 692 return Value > 0 && Value <= 16; 693 } 694 bool isShrImm32() const { 695 if (!isImm()) return false; 696 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 697 if (!CE) return false; 698 int64_t Value = CE->getValue(); 699 return Value > 0 && Value <= 32; 700 } 701 bool isShrImm64() const { 702 if (!isImm()) return false; 703 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 704 if (!CE) return false; 705 int64_t Value = CE->getValue(); 706 return Value > 0 && Value <= 64; 707 } 708 bool isImm1_7() const { 709 if (!isImm()) return false; 710 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 711 if (!CE) return false; 712 int64_t Value = CE->getValue(); 713 return Value > 0 && Value < 8; 714 } 715 bool isImm1_15() const { 716 if (!isImm()) return false; 717 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 718 if (!CE) return false; 719 int64_t Value = CE->getValue(); 720 return Value > 0 && Value < 16; 721 } 722 bool isImm1_31() const { 723 if (!isImm()) return false; 724 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 725 if (!CE) return false; 726 int64_t Value = CE->getValue(); 727 return Value > 0 && Value < 32; 728 } 729 bool isImm1_16() const { 730 if (!isImm()) return false; 731 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 732 if (!CE) return false; 733 int64_t Value = CE->getValue(); 734 return Value > 0 && Value < 17; 735 } 736 bool isImm1_32() const { 737 if (!isImm()) return false; 738 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 739 if (!CE) return false; 740 int64_t Value = CE->getValue(); 741 return Value > 0 && Value < 33; 742 } 743 bool isImm0_32() const { 744 if (!isImm()) return false; 745 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 746 if (!CE) return false; 747 int64_t Value = CE->getValue(); 748 return Value >= 0 && Value < 33; 749 } 750 bool isImm0_65535() const { 751 if (!isImm()) return false; 752 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 753 if (!CE) return false; 754 int64_t Value = CE->getValue(); 755 return Value >= 0 && Value < 65536; 756 } 757 bool isImm0_65535Expr() const { 758 if (!isImm()) return false; 759 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 760 // If it's not a constant expression, it'll generate a fixup and be 761 // handled later. 762 if (!CE) return true; 763 int64_t Value = CE->getValue(); 764 return Value >= 0 && Value < 65536; 765 } 766 bool isImm24bit() const { 767 if (!isImm()) return false; 768 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 769 if (!CE) return false; 770 int64_t Value = CE->getValue(); 771 return Value >= 0 && Value <= 0xffffff; 772 } 773 bool isImmThumbSR() const { 774 if (!isImm()) return false; 775 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 776 if (!CE) return false; 777 int64_t Value = CE->getValue(); 778 return Value > 0 && Value < 33; 779 } 780 bool isPKHLSLImm() const { 781 if (!isImm()) return false; 782 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 783 if (!CE) return false; 784 int64_t Value = CE->getValue(); 785 return Value >= 0 && Value < 32; 786 } 787 bool isPKHASRImm() const { 788 if (!isImm()) return false; 789 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 790 if (!CE) return false; 791 int64_t Value = CE->getValue(); 792 return Value > 0 && Value <= 32; 793 } 794 bool isAdrLabel() const { 795 // If we have an immediate that's not a constant, treat it as a label 796 // reference needing a fixup. If it is a constant, but it can't fit 797 // into shift immediate encoding, we reject it. 798 if (isImm() && !isa<MCConstantExpr>(getImm())) return true; 799 else return (isARMSOImm() || isARMSOImmNeg()); 800 } 801 bool isARMSOImm() const { 802 if (!isImm()) return false; 803 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 804 if (!CE) return false; 805 int64_t Value = CE->getValue(); 806 return ARM_AM::getSOImmVal(Value) != -1; 807 } 808 bool isARMSOImmNot() const { 809 if (!isImm()) return false; 810 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 811 if (!CE) return false; 812 int64_t Value = CE->getValue(); 813 return ARM_AM::getSOImmVal(~Value) != -1; 814 } 815 bool isARMSOImmNeg() const { 816 if (!isImm()) return false; 817 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 818 if (!CE) return false; 819 int64_t Value = CE->getValue(); 820 // Only use this when not representable as a plain so_imm. 821 return ARM_AM::getSOImmVal(Value) == -1 && 822 ARM_AM::getSOImmVal(-Value) != -1; 823 } 824 bool isT2SOImm() const { 825 if (!isImm()) return false; 826 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 827 if (!CE) return false; 828 int64_t Value = CE->getValue(); 829 return ARM_AM::getT2SOImmVal(Value) != -1; 830 } 831 bool isT2SOImmNot() const { 832 if (!isImm()) return false; 833 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 834 if (!CE) return false; 835 int64_t Value = CE->getValue(); 836 return ARM_AM::getT2SOImmVal(~Value) != -1; 837 } 838 bool isT2SOImmNeg() const { 839 if (!isImm()) return false; 840 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 841 if (!CE) return false; 842 int64_t Value = CE->getValue(); 843 // Only use this when not representable as a plain so_imm. 844 return ARM_AM::getT2SOImmVal(Value) == -1 && 845 ARM_AM::getT2SOImmVal(-Value) != -1; 846 } 847 bool isSetEndImm() const { 848 if (!isImm()) return false; 849 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 850 if (!CE) return false; 851 int64_t Value = CE->getValue(); 852 return Value == 1 || Value == 0; 853 } 854 bool isReg() const { return Kind == k_Register; } 855 bool isRegList() const { return Kind == k_RegisterList; } 856 bool isDPRRegList() const { return Kind == k_DPRRegisterList; } 857 bool isSPRRegList() const { return Kind == k_SPRRegisterList; } 858 bool isToken() const { return Kind == k_Token; } 859 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; } 860 bool isMemory() const { return Kind == k_Memory; } 861 bool isShifterImm() const { return Kind == k_ShifterImmediate; } 862 bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; } 863 bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; } 864 bool isRotImm() const { return Kind == k_RotateImmediate; } 865 bool isBitfield() const { return Kind == k_BitfieldDescriptor; } 866 bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; } 867 bool isPostIdxReg() const { 868 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift; 869 } 870 bool isMemNoOffset(bool alignOK = false) const { 871 if (!isMemory()) 872 return false; 873 // No offset of any kind. 874 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 && 875 (alignOK || Memory.Alignment == 0); 876 } 877 bool isMemPCRelImm12() const { 878 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 879 return false; 880 // Base register must be PC. 881 if (Memory.BaseRegNum != ARM::PC) 882 return false; 883 // Immediate offset in range [-4095, 4095]. 884 if (!Memory.OffsetImm) return true; 885 int64_t Val = Memory.OffsetImm->getValue(); 886 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN); 887 } 888 bool isAlignedMemory() const { 889 return isMemNoOffset(true); 890 } 891 bool isAddrMode2() const { 892 if (!isMemory() || Memory.Alignment != 0) return false; 893 // Check for register offset. 894 if (Memory.OffsetRegNum) return true; 895 // Immediate offset in range [-4095, 4095]. 896 if (!Memory.OffsetImm) return true; 897 int64_t Val = Memory.OffsetImm->getValue(); 898 return Val > -4096 && Val < 4096; 899 } 900 bool isAM2OffsetImm() const { 901 if (!isImm()) return false; 902 // Immediate offset in range [-4095, 4095]. 903 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 904 if (!CE) return false; 905 int64_t Val = CE->getValue(); 906 return Val > -4096 && Val < 4096; 907 } 908 bool isAddrMode3() const { 909 // If we have an immediate that's not a constant, treat it as a label 910 // reference needing a fixup. If it is a constant, it's something else 911 // and we reject it. 912 if (isImm() && !isa<MCConstantExpr>(getImm())) 913 return true; 914 if (!isMemory() || Memory.Alignment != 0) return false; 915 // No shifts are legal for AM3. 916 if (Memory.ShiftType != ARM_AM::no_shift) return false; 917 // Check for register offset. 918 if (Memory.OffsetRegNum) return true; 919 // Immediate offset in range [-255, 255]. 920 if (!Memory.OffsetImm) return true; 921 int64_t Val = Memory.OffsetImm->getValue(); 922 // The #-0 offset is encoded as INT32_MIN, and we have to check 923 // for this too. 924 return (Val > -256 && Val < 256) || Val == INT32_MIN; 925 } 926 bool isAM3Offset() const { 927 if (Kind != k_Immediate && Kind != k_PostIndexRegister) 928 return false; 929 if (Kind == k_PostIndexRegister) 930 return PostIdxReg.ShiftTy == ARM_AM::no_shift; 931 // Immediate offset in range [-255, 255]. 932 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 933 if (!CE) return false; 934 int64_t Val = CE->getValue(); 935 // Special case, #-0 is INT32_MIN. 936 return (Val > -256 && Val < 256) || Val == INT32_MIN; 937 } 938 bool isAddrMode5() const { 939 // If we have an immediate that's not a constant, treat it as a label 940 // reference needing a fixup. If it is a constant, it's something else 941 // and we reject it. 942 if (isImm() && !isa<MCConstantExpr>(getImm())) 943 return true; 944 if (!isMemory() || Memory.Alignment != 0) return false; 945 // Check for register offset. 946 if (Memory.OffsetRegNum) return false; 947 // Immediate offset in range [-1020, 1020] and a multiple of 4. 948 if (!Memory.OffsetImm) return true; 949 int64_t Val = Memory.OffsetImm->getValue(); 950 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) || 951 Val == INT32_MIN; 952 } 953 bool isMemTBB() const { 954 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative || 955 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) 956 return false; 957 return true; 958 } 959 bool isMemTBH() const { 960 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative || 961 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 || 962 Memory.Alignment != 0 ) 963 return false; 964 return true; 965 } 966 bool isMemRegOffset() const { 967 if (!isMemory() || !Memory.OffsetRegNum || Memory.Alignment != 0) 968 return false; 969 return true; 970 } 971 bool isT2MemRegOffset() const { 972 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative || 973 Memory.Alignment != 0) 974 return false; 975 // Only lsl #{0, 1, 2, 3} allowed. 976 if (Memory.ShiftType == ARM_AM::no_shift) 977 return true; 978 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3) 979 return false; 980 return true; 981 } 982 bool isMemThumbRR() const { 983 // Thumb reg+reg addressing is simple. Just two registers, a base and 984 // an offset. No shifts, negations or any other complicating factors. 985 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative || 986 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) 987 return false; 988 return isARMLowRegister(Memory.BaseRegNum) && 989 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum)); 990 } 991 bool isMemThumbRIs4() const { 992 if (!isMemory() || Memory.OffsetRegNum != 0 || 993 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 994 return false; 995 // Immediate offset, multiple of 4 in range [0, 124]. 996 if (!Memory.OffsetImm) return true; 997 int64_t Val = Memory.OffsetImm->getValue(); 998 return Val >= 0 && Val <= 124 && (Val % 4) == 0; 999 } 1000 bool isMemThumbRIs2() const { 1001 if (!isMemory() || Memory.OffsetRegNum != 0 || 1002 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 1003 return false; 1004 // Immediate offset, multiple of 4 in range [0, 62]. 1005 if (!Memory.OffsetImm) return true; 1006 int64_t Val = Memory.OffsetImm->getValue(); 1007 return Val >= 0 && Val <= 62 && (Val % 2) == 0; 1008 } 1009 bool isMemThumbRIs1() const { 1010 if (!isMemory() || Memory.OffsetRegNum != 0 || 1011 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 1012 return false; 1013 // Immediate offset in range [0, 31]. 1014 if (!Memory.OffsetImm) return true; 1015 int64_t Val = Memory.OffsetImm->getValue(); 1016 return Val >= 0 && Val <= 31; 1017 } 1018 bool isMemThumbSPI() const { 1019 if (!isMemory() || Memory.OffsetRegNum != 0 || 1020 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0) 1021 return false; 1022 // Immediate offset, multiple of 4 in range [0, 1020]. 1023 if (!Memory.OffsetImm) return true; 1024 int64_t Val = Memory.OffsetImm->getValue(); 1025 return Val >= 0 && Val <= 1020 && (Val % 4) == 0; 1026 } 1027 bool isMemImm8s4Offset() const { 1028 // If we have an immediate that's not a constant, treat it as a label 1029 // reference needing a fixup. If it is a constant, it's something else 1030 // and we reject it. 1031 if (isImm() && !isa<MCConstantExpr>(getImm())) 1032 return true; 1033 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1034 return false; 1035 // Immediate offset a multiple of 4 in range [-1020, 1020]. 1036 if (!Memory.OffsetImm) return true; 1037 int64_t Val = Memory.OffsetImm->getValue(); 1038 // Special case, #-0 is INT32_MIN. 1039 return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN; 1040 } 1041 bool isMemImm0_1020s4Offset() const { 1042 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1043 return false; 1044 // Immediate offset a multiple of 4 in range [0, 1020]. 1045 if (!Memory.OffsetImm) return true; 1046 int64_t Val = Memory.OffsetImm->getValue(); 1047 return Val >= 0 && Val <= 1020 && (Val & 3) == 0; 1048 } 1049 bool isMemImm8Offset() const { 1050 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1051 return false; 1052 // Base reg of PC isn't allowed for these encodings. 1053 if (Memory.BaseRegNum == ARM::PC) return false; 1054 // Immediate offset in range [-255, 255]. 1055 if (!Memory.OffsetImm) return true; 1056 int64_t Val = Memory.OffsetImm->getValue(); 1057 return (Val == INT32_MIN) || (Val > -256 && Val < 256); 1058 } 1059 bool isMemPosImm8Offset() const { 1060 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1061 return false; 1062 // Immediate offset in range [0, 255]. 1063 if (!Memory.OffsetImm) return true; 1064 int64_t Val = Memory.OffsetImm->getValue(); 1065 return Val >= 0 && Val < 256; 1066 } 1067 bool isMemNegImm8Offset() const { 1068 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1069 return false; 1070 // Base reg of PC isn't allowed for these encodings. 1071 if (Memory.BaseRegNum == ARM::PC) return false; 1072 // Immediate offset in range [-255, -1]. 1073 if (!Memory.OffsetImm) return false; 1074 int64_t Val = Memory.OffsetImm->getValue(); 1075 return (Val == INT32_MIN) || (Val > -256 && Val < 0); 1076 } 1077 bool isMemUImm12Offset() const { 1078 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1079 return false; 1080 // Immediate offset in range [0, 4095]. 1081 if (!Memory.OffsetImm) return true; 1082 int64_t Val = Memory.OffsetImm->getValue(); 1083 return (Val >= 0 && Val < 4096); 1084 } 1085 bool isMemImm12Offset() const { 1086 // If we have an immediate that's not a constant, treat it as a label 1087 // reference needing a fixup. If it is a constant, it's something else 1088 // and we reject it. 1089 if (isImm() && !isa<MCConstantExpr>(getImm())) 1090 return true; 1091 1092 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1093 return false; 1094 // Immediate offset in range [-4095, 4095]. 1095 if (!Memory.OffsetImm) return true; 1096 int64_t Val = Memory.OffsetImm->getValue(); 1097 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN); 1098 } 1099 bool isPostIdxImm8() const { 1100 if (!isImm()) return false; 1101 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1102 if (!CE) return false; 1103 int64_t Val = CE->getValue(); 1104 return (Val > -256 && Val < 256) || (Val == INT32_MIN); 1105 } 1106 bool isPostIdxImm8s4() const { 1107 if (!isImm()) return false; 1108 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1109 if (!CE) return false; 1110 int64_t Val = CE->getValue(); 1111 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) || 1112 (Val == INT32_MIN); 1113 } 1114 1115 bool isMSRMask() const { return Kind == k_MSRMask; } 1116 bool isProcIFlags() const { return Kind == k_ProcIFlags; } 1117 1118 // NEON operands. 1119 bool isSingleSpacedVectorList() const { 1120 return Kind == k_VectorList && !VectorList.isDoubleSpaced; 1121 } 1122 bool isDoubleSpacedVectorList() const { 1123 return Kind == k_VectorList && VectorList.isDoubleSpaced; 1124 } 1125 bool isVecListOneD() const { 1126 if (!isSingleSpacedVectorList()) return false; 1127 return VectorList.Count == 1; 1128 } 1129 1130 bool isVecListDPair() const { 1131 if (!isSingleSpacedVectorList()) return false; 1132 return (ARMMCRegisterClasses[ARM::DPairRegClassID] 1133 .contains(VectorList.RegNum)); 1134 } 1135 1136 bool isVecListThreeD() const { 1137 if (!isSingleSpacedVectorList()) return false; 1138 return VectorList.Count == 3; 1139 } 1140 1141 bool isVecListFourD() const { 1142 if (!isSingleSpacedVectorList()) return false; 1143 return VectorList.Count == 4; 1144 } 1145 1146 bool isVecListDPairSpaced() const { 1147 if (isSingleSpacedVectorList()) return false; 1148 return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID] 1149 .contains(VectorList.RegNum)); 1150 } 1151 1152 bool isVecListThreeQ() const { 1153 if (!isDoubleSpacedVectorList()) return false; 1154 return VectorList.Count == 3; 1155 } 1156 1157 bool isVecListFourQ() const { 1158 if (!isDoubleSpacedVectorList()) return false; 1159 return VectorList.Count == 4; 1160 } 1161 1162 bool isSingleSpacedVectorAllLanes() const { 1163 return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced; 1164 } 1165 bool isDoubleSpacedVectorAllLanes() const { 1166 return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced; 1167 } 1168 bool isVecListOneDAllLanes() const { 1169 if (!isSingleSpacedVectorAllLanes()) return false; 1170 return VectorList.Count == 1; 1171 } 1172 1173 bool isVecListDPairAllLanes() const { 1174 if (!isSingleSpacedVectorAllLanes()) return false; 1175 return (ARMMCRegisterClasses[ARM::DPairRegClassID] 1176 .contains(VectorList.RegNum)); 1177 } 1178 1179 bool isVecListDPairSpacedAllLanes() const { 1180 if (!isDoubleSpacedVectorAllLanes()) return false; 1181 return VectorList.Count == 2; 1182 } 1183 1184 bool isVecListThreeDAllLanes() const { 1185 if (!isSingleSpacedVectorAllLanes()) return false; 1186 return VectorList.Count == 3; 1187 } 1188 1189 bool isVecListThreeQAllLanes() const { 1190 if (!isDoubleSpacedVectorAllLanes()) return false; 1191 return VectorList.Count == 3; 1192 } 1193 1194 bool isVecListFourDAllLanes() const { 1195 if (!isSingleSpacedVectorAllLanes()) return false; 1196 return VectorList.Count == 4; 1197 } 1198 1199 bool isVecListFourQAllLanes() const { 1200 if (!isDoubleSpacedVectorAllLanes()) return false; 1201 return VectorList.Count == 4; 1202 } 1203 1204 bool isSingleSpacedVectorIndexed() const { 1205 return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced; 1206 } 1207 bool isDoubleSpacedVectorIndexed() const { 1208 return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced; 1209 } 1210 bool isVecListOneDByteIndexed() const { 1211 if (!isSingleSpacedVectorIndexed()) return false; 1212 return VectorList.Count == 1 && VectorList.LaneIndex <= 7; 1213 } 1214 1215 bool isVecListOneDHWordIndexed() const { 1216 if (!isSingleSpacedVectorIndexed()) return false; 1217 return VectorList.Count == 1 && VectorList.LaneIndex <= 3; 1218 } 1219 1220 bool isVecListOneDWordIndexed() const { 1221 if (!isSingleSpacedVectorIndexed()) return false; 1222 return VectorList.Count == 1 && VectorList.LaneIndex <= 1; 1223 } 1224 1225 bool isVecListTwoDByteIndexed() const { 1226 if (!isSingleSpacedVectorIndexed()) return false; 1227 return VectorList.Count == 2 && VectorList.LaneIndex <= 7; 1228 } 1229 1230 bool isVecListTwoDHWordIndexed() const { 1231 if (!isSingleSpacedVectorIndexed()) return false; 1232 return VectorList.Count == 2 && VectorList.LaneIndex <= 3; 1233 } 1234 1235 bool isVecListTwoQWordIndexed() const { 1236 if (!isDoubleSpacedVectorIndexed()) return false; 1237 return VectorList.Count == 2 && VectorList.LaneIndex <= 1; 1238 } 1239 1240 bool isVecListTwoQHWordIndexed() const { 1241 if (!isDoubleSpacedVectorIndexed()) return false; 1242 return VectorList.Count == 2 && VectorList.LaneIndex <= 3; 1243 } 1244 1245 bool isVecListTwoDWordIndexed() const { 1246 if (!isSingleSpacedVectorIndexed()) return false; 1247 return VectorList.Count == 2 && VectorList.LaneIndex <= 1; 1248 } 1249 1250 bool isVecListThreeDByteIndexed() const { 1251 if (!isSingleSpacedVectorIndexed()) return false; 1252 return VectorList.Count == 3 && VectorList.LaneIndex <= 7; 1253 } 1254 1255 bool isVecListThreeDHWordIndexed() const { 1256 if (!isSingleSpacedVectorIndexed()) return false; 1257 return VectorList.Count == 3 && VectorList.LaneIndex <= 3; 1258 } 1259 1260 bool isVecListThreeQWordIndexed() const { 1261 if (!isDoubleSpacedVectorIndexed()) return false; 1262 return VectorList.Count == 3 && VectorList.LaneIndex <= 1; 1263 } 1264 1265 bool isVecListThreeQHWordIndexed() const { 1266 if (!isDoubleSpacedVectorIndexed()) return false; 1267 return VectorList.Count == 3 && VectorList.LaneIndex <= 3; 1268 } 1269 1270 bool isVecListThreeDWordIndexed() const { 1271 if (!isSingleSpacedVectorIndexed()) return false; 1272 return VectorList.Count == 3 && VectorList.LaneIndex <= 1; 1273 } 1274 1275 bool isVecListFourDByteIndexed() const { 1276 if (!isSingleSpacedVectorIndexed()) return false; 1277 return VectorList.Count == 4 && VectorList.LaneIndex <= 7; 1278 } 1279 1280 bool isVecListFourDHWordIndexed() const { 1281 if (!isSingleSpacedVectorIndexed()) return false; 1282 return VectorList.Count == 4 && VectorList.LaneIndex <= 3; 1283 } 1284 1285 bool isVecListFourQWordIndexed() const { 1286 if (!isDoubleSpacedVectorIndexed()) return false; 1287 return VectorList.Count == 4 && VectorList.LaneIndex <= 1; 1288 } 1289 1290 bool isVecListFourQHWordIndexed() const { 1291 if (!isDoubleSpacedVectorIndexed()) return false; 1292 return VectorList.Count == 4 && VectorList.LaneIndex <= 3; 1293 } 1294 1295 bool isVecListFourDWordIndexed() const { 1296 if (!isSingleSpacedVectorIndexed()) return false; 1297 return VectorList.Count == 4 && VectorList.LaneIndex <= 1; 1298 } 1299 1300 bool isVectorIndex8() const { 1301 if (Kind != k_VectorIndex) return false; 1302 return VectorIndex.Val < 8; 1303 } 1304 bool isVectorIndex16() const { 1305 if (Kind != k_VectorIndex) return false; 1306 return VectorIndex.Val < 4; 1307 } 1308 bool isVectorIndex32() const { 1309 if (Kind != k_VectorIndex) return false; 1310 return VectorIndex.Val < 2; 1311 } 1312 1313 bool isNEONi8splat() const { 1314 if (!isImm()) return false; 1315 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1316 // Must be a constant. 1317 if (!CE) return false; 1318 int64_t Value = CE->getValue(); 1319 // i8 value splatted across 8 bytes. The immediate is just the 8 byte 1320 // value. 1321 return Value >= 0 && Value < 256; 1322 } 1323 1324 bool isNEONi16splat() const { 1325 if (!isImm()) return false; 1326 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1327 // Must be a constant. 1328 if (!CE) return false; 1329 int64_t Value = CE->getValue(); 1330 // i16 value in the range [0,255] or [0x0100, 0xff00] 1331 return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00); 1332 } 1333 1334 bool isNEONi32splat() const { 1335 if (!isImm()) return false; 1336 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1337 // Must be a constant. 1338 if (!CE) return false; 1339 int64_t Value = CE->getValue(); 1340 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X. 1341 return (Value >= 0 && Value < 256) || 1342 (Value >= 0x0100 && Value <= 0xff00) || 1343 (Value >= 0x010000 && Value <= 0xff0000) || 1344 (Value >= 0x01000000 && Value <= 0xff000000); 1345 } 1346 1347 bool isNEONi32vmov() const { 1348 if (!isImm()) return false; 1349 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1350 // Must be a constant. 1351 if (!CE) return false; 1352 int64_t Value = CE->getValue(); 1353 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X, 1354 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted. 1355 return (Value >= 0 && Value < 256) || 1356 (Value >= 0x0100 && Value <= 0xff00) || 1357 (Value >= 0x010000 && Value <= 0xff0000) || 1358 (Value >= 0x01000000 && Value <= 0xff000000) || 1359 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) || 1360 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff); 1361 } 1362 bool isNEONi32vmovNeg() const { 1363 if (!isImm()) return false; 1364 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1365 // Must be a constant. 1366 if (!CE) return false; 1367 int64_t Value = ~CE->getValue(); 1368 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X, 1369 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted. 1370 return (Value >= 0 && Value < 256) || 1371 (Value >= 0x0100 && Value <= 0xff00) || 1372 (Value >= 0x010000 && Value <= 0xff0000) || 1373 (Value >= 0x01000000 && Value <= 0xff000000) || 1374 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) || 1375 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff); 1376 } 1377 1378 bool isNEONi64splat() const { 1379 if (!isImm()) return false; 1380 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1381 // Must be a constant. 1382 if (!CE) return false; 1383 uint64_t Value = CE->getValue(); 1384 // i64 value with each byte being either 0 or 0xff. 1385 for (unsigned i = 0; i < 8; ++i) 1386 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false; 1387 return true; 1388 } 1389 1390 void addExpr(MCInst &Inst, const MCExpr *Expr) const { 1391 // Add as immediates when possible. Null MCExpr = 0. 1392 if (Expr == 0) 1393 Inst.addOperand(MCOperand::CreateImm(0)); 1394 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr)) 1395 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 1396 else 1397 Inst.addOperand(MCOperand::CreateExpr(Expr)); 1398 } 1399 1400 void addCondCodeOperands(MCInst &Inst, unsigned N) const { 1401 assert(N == 2 && "Invalid number of operands!"); 1402 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); 1403 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; 1404 Inst.addOperand(MCOperand::CreateReg(RegNum)); 1405 } 1406 1407 void addCoprocNumOperands(MCInst &Inst, unsigned N) const { 1408 assert(N == 1 && "Invalid number of operands!"); 1409 Inst.addOperand(MCOperand::CreateImm(getCoproc())); 1410 } 1411 1412 void addCoprocRegOperands(MCInst &Inst, unsigned N) const { 1413 assert(N == 1 && "Invalid number of operands!"); 1414 Inst.addOperand(MCOperand::CreateImm(getCoproc())); 1415 } 1416 1417 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const { 1418 assert(N == 1 && "Invalid number of operands!"); 1419 Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val)); 1420 } 1421 1422 void addITMaskOperands(MCInst &Inst, unsigned N) const { 1423 assert(N == 1 && "Invalid number of operands!"); 1424 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask)); 1425 } 1426 1427 void addITCondCodeOperands(MCInst &Inst, unsigned N) const { 1428 assert(N == 1 && "Invalid number of operands!"); 1429 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); 1430 } 1431 1432 void addCCOutOperands(MCInst &Inst, unsigned N) const { 1433 assert(N == 1 && "Invalid number of operands!"); 1434 Inst.addOperand(MCOperand::CreateReg(getReg())); 1435 } 1436 1437 void addRegOperands(MCInst &Inst, unsigned N) const { 1438 assert(N == 1 && "Invalid number of operands!"); 1439 Inst.addOperand(MCOperand::CreateReg(getReg())); 1440 } 1441 1442 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const { 1443 assert(N == 3 && "Invalid number of operands!"); 1444 assert(isRegShiftedReg() && 1445 "addRegShiftedRegOperands() on non RegShiftedReg!"); 1446 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg)); 1447 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg)); 1448 Inst.addOperand(MCOperand::CreateImm( 1449 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm))); 1450 } 1451 1452 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const { 1453 assert(N == 2 && "Invalid number of operands!"); 1454 assert(isRegShiftedImm() && 1455 "addRegShiftedImmOperands() on non RegShiftedImm!"); 1456 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg)); 1457 // Shift of #32 is encoded as 0 where permitted 1458 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm); 1459 Inst.addOperand(MCOperand::CreateImm( 1460 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm))); 1461 } 1462 1463 void addShifterImmOperands(MCInst &Inst, unsigned N) const { 1464 assert(N == 1 && "Invalid number of operands!"); 1465 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) | 1466 ShifterImm.Imm)); 1467 } 1468 1469 void addRegListOperands(MCInst &Inst, unsigned N) const { 1470 assert(N == 1 && "Invalid number of operands!"); 1471 const SmallVectorImpl<unsigned> &RegList = getRegList(); 1472 for (SmallVectorImpl<unsigned>::const_iterator 1473 I = RegList.begin(), E = RegList.end(); I != E; ++I) 1474 Inst.addOperand(MCOperand::CreateReg(*I)); 1475 } 1476 1477 void addDPRRegListOperands(MCInst &Inst, unsigned N) const { 1478 addRegListOperands(Inst, N); 1479 } 1480 1481 void addSPRRegListOperands(MCInst &Inst, unsigned N) const { 1482 addRegListOperands(Inst, N); 1483 } 1484 1485 void addRotImmOperands(MCInst &Inst, unsigned N) const { 1486 assert(N == 1 && "Invalid number of operands!"); 1487 // Encoded as val>>3. The printer handles display as 8, 16, 24. 1488 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3)); 1489 } 1490 1491 void addBitfieldOperands(MCInst &Inst, unsigned N) const { 1492 assert(N == 1 && "Invalid number of operands!"); 1493 // Munge the lsb/width into a bitfield mask. 1494 unsigned lsb = Bitfield.LSB; 1495 unsigned width = Bitfield.Width; 1496 // Make a 32-bit mask w/ the referenced bits clear and all other bits set. 1497 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >> 1498 (32 - (lsb + width))); 1499 Inst.addOperand(MCOperand::CreateImm(Mask)); 1500 } 1501 1502 void addImmOperands(MCInst &Inst, unsigned N) const { 1503 assert(N == 1 && "Invalid number of operands!"); 1504 addExpr(Inst, getImm()); 1505 } 1506 1507 void addFBits16Operands(MCInst &Inst, unsigned N) const { 1508 assert(N == 1 && "Invalid number of operands!"); 1509 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1510 Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue())); 1511 } 1512 1513 void addFBits32Operands(MCInst &Inst, unsigned N) const { 1514 assert(N == 1 && "Invalid number of operands!"); 1515 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1516 Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue())); 1517 } 1518 1519 void addFPImmOperands(MCInst &Inst, unsigned N) const { 1520 assert(N == 1 && "Invalid number of operands!"); 1521 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1522 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue())); 1523 Inst.addOperand(MCOperand::CreateImm(Val)); 1524 } 1525 1526 void addImm8s4Operands(MCInst &Inst, unsigned N) const { 1527 assert(N == 1 && "Invalid number of operands!"); 1528 // FIXME: We really want to scale the value here, but the LDRD/STRD 1529 // instruction don't encode operands that way yet. 1530 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1531 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 1532 } 1533 1534 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const { 1535 assert(N == 1 && "Invalid number of operands!"); 1536 // The immediate is scaled by four in the encoding and is stored 1537 // in the MCInst as such. Lop off the low two bits here. 1538 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1539 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4)); 1540 } 1541 1542 void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const { 1543 assert(N == 1 && "Invalid number of operands!"); 1544 // The immediate is scaled by four in the encoding and is stored 1545 // in the MCInst as such. Lop off the low two bits here. 1546 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1547 Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4))); 1548 } 1549 1550 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const { 1551 assert(N == 1 && "Invalid number of operands!"); 1552 // The immediate is scaled by four in the encoding and is stored 1553 // in the MCInst as such. Lop off the low two bits here. 1554 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1555 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4)); 1556 } 1557 1558 void addImm1_16Operands(MCInst &Inst, unsigned N) const { 1559 assert(N == 1 && "Invalid number of operands!"); 1560 // The constant encodes as the immediate-1, and we store in the instruction 1561 // the bits as encoded, so subtract off one here. 1562 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1563 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1)); 1564 } 1565 1566 void addImm1_32Operands(MCInst &Inst, unsigned N) const { 1567 assert(N == 1 && "Invalid number of operands!"); 1568 // The constant encodes as the immediate-1, and we store in the instruction 1569 // the bits as encoded, so subtract off one here. 1570 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1571 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1)); 1572 } 1573 1574 void addImmThumbSROperands(MCInst &Inst, unsigned N) const { 1575 assert(N == 1 && "Invalid number of operands!"); 1576 // The constant encodes as the immediate, except for 32, which encodes as 1577 // zero. 1578 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1579 unsigned Imm = CE->getValue(); 1580 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm))); 1581 } 1582 1583 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const { 1584 assert(N == 1 && "Invalid number of operands!"); 1585 // An ASR value of 32 encodes as 0, so that's how we want to add it to 1586 // the instruction as well. 1587 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1588 int Val = CE->getValue(); 1589 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val)); 1590 } 1591 1592 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const { 1593 assert(N == 1 && "Invalid number of operands!"); 1594 // The operand is actually a t2_so_imm, but we have its bitwise 1595 // negation in the assembly source, so twiddle it here. 1596 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1597 Inst.addOperand(MCOperand::CreateImm(~CE->getValue())); 1598 } 1599 1600 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const { 1601 assert(N == 1 && "Invalid number of operands!"); 1602 // The operand is actually a t2_so_imm, but we have its 1603 // negation in the assembly source, so twiddle it here. 1604 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1605 Inst.addOperand(MCOperand::CreateImm(-CE->getValue())); 1606 } 1607 1608 void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const { 1609 assert(N == 1 && "Invalid number of operands!"); 1610 // The operand is actually an imm0_4095, but we have its 1611 // negation in the assembly source, so twiddle it here. 1612 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1613 Inst.addOperand(MCOperand::CreateImm(-CE->getValue())); 1614 } 1615 1616 void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const { 1617 assert(N == 1 && "Invalid number of operands!"); 1618 // The operand is actually a so_imm, but we have its bitwise 1619 // negation in the assembly source, so twiddle it here. 1620 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1621 Inst.addOperand(MCOperand::CreateImm(~CE->getValue())); 1622 } 1623 1624 void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const { 1625 assert(N == 1 && "Invalid number of operands!"); 1626 // The operand is actually a so_imm, but we have its 1627 // negation in the assembly source, so twiddle it here. 1628 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1629 Inst.addOperand(MCOperand::CreateImm(-CE->getValue())); 1630 } 1631 1632 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const { 1633 assert(N == 1 && "Invalid number of operands!"); 1634 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt()))); 1635 } 1636 1637 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const { 1638 assert(N == 1 && "Invalid number of operands!"); 1639 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1640 } 1641 1642 void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const { 1643 assert(N == 1 && "Invalid number of operands!"); 1644 int32_t Imm = Memory.OffsetImm->getValue(); 1645 // FIXME: Handle #-0 1646 if (Imm == INT32_MIN) Imm = 0; 1647 Inst.addOperand(MCOperand::CreateImm(Imm)); 1648 } 1649 1650 void addAdrLabelOperands(MCInst &Inst, unsigned N) const { 1651 assert(N == 1 && "Invalid number of operands!"); 1652 assert(isImm() && "Not an immediate!"); 1653 1654 // If we have an immediate that's not a constant, treat it as a label 1655 // reference needing a fixup. 1656 if (!isa<MCConstantExpr>(getImm())) { 1657 Inst.addOperand(MCOperand::CreateExpr(getImm())); 1658 return; 1659 } 1660 1661 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1662 int Val = CE->getValue(); 1663 Inst.addOperand(MCOperand::CreateImm(Val)); 1664 } 1665 1666 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const { 1667 assert(N == 2 && "Invalid number of operands!"); 1668 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1669 Inst.addOperand(MCOperand::CreateImm(Memory.Alignment)); 1670 } 1671 1672 void addAddrMode2Operands(MCInst &Inst, unsigned N) const { 1673 assert(N == 3 && "Invalid number of operands!"); 1674 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1675 if (!Memory.OffsetRegNum) { 1676 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1677 // Special case for #-0 1678 if (Val == INT32_MIN) Val = 0; 1679 if (Val < 0) Val = -Val; 1680 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); 1681 } else { 1682 // For register offset, we encode the shift type and negation flag 1683 // here. 1684 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 1685 Memory.ShiftImm, Memory.ShiftType); 1686 } 1687 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1688 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1689 Inst.addOperand(MCOperand::CreateImm(Val)); 1690 } 1691 1692 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const { 1693 assert(N == 2 && "Invalid number of operands!"); 1694 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1695 assert(CE && "non-constant AM2OffsetImm operand!"); 1696 int32_t Val = CE->getValue(); 1697 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1698 // Special case for #-0 1699 if (Val == INT32_MIN) Val = 0; 1700 if (Val < 0) Val = -Val; 1701 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); 1702 Inst.addOperand(MCOperand::CreateReg(0)); 1703 Inst.addOperand(MCOperand::CreateImm(Val)); 1704 } 1705 1706 void addAddrMode3Operands(MCInst &Inst, unsigned N) const { 1707 assert(N == 3 && "Invalid number of operands!"); 1708 // If we have an immediate that's not a constant, treat it as a label 1709 // reference needing a fixup. If it is a constant, it's something else 1710 // and we reject it. 1711 if (isImm()) { 1712 Inst.addOperand(MCOperand::CreateExpr(getImm())); 1713 Inst.addOperand(MCOperand::CreateReg(0)); 1714 Inst.addOperand(MCOperand::CreateImm(0)); 1715 return; 1716 } 1717 1718 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1719 if (!Memory.OffsetRegNum) { 1720 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1721 // Special case for #-0 1722 if (Val == INT32_MIN) Val = 0; 1723 if (Val < 0) Val = -Val; 1724 Val = ARM_AM::getAM3Opc(AddSub, Val); 1725 } else { 1726 // For register offset, we encode the shift type and negation flag 1727 // here. 1728 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0); 1729 } 1730 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1731 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1732 Inst.addOperand(MCOperand::CreateImm(Val)); 1733 } 1734 1735 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const { 1736 assert(N == 2 && "Invalid number of operands!"); 1737 if (Kind == k_PostIndexRegister) { 1738 int32_t Val = 1739 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0); 1740 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 1741 Inst.addOperand(MCOperand::CreateImm(Val)); 1742 return; 1743 } 1744 1745 // Constant offset. 1746 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm()); 1747 int32_t Val = CE->getValue(); 1748 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1749 // Special case for #-0 1750 if (Val == INT32_MIN) Val = 0; 1751 if (Val < 0) Val = -Val; 1752 Val = ARM_AM::getAM3Opc(AddSub, Val); 1753 Inst.addOperand(MCOperand::CreateReg(0)); 1754 Inst.addOperand(MCOperand::CreateImm(Val)); 1755 } 1756 1757 void addAddrMode5Operands(MCInst &Inst, unsigned N) const { 1758 assert(N == 2 && "Invalid number of operands!"); 1759 // If we have an immediate that's not a constant, treat it as a label 1760 // reference needing a fixup. If it is a constant, it's something else 1761 // and we reject it. 1762 if (isImm()) { 1763 Inst.addOperand(MCOperand::CreateExpr(getImm())); 1764 Inst.addOperand(MCOperand::CreateImm(0)); 1765 return; 1766 } 1767 1768 // The lower two bits are always zero and as such are not encoded. 1769 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0; 1770 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1771 // Special case for #-0 1772 if (Val == INT32_MIN) Val = 0; 1773 if (Val < 0) Val = -Val; 1774 Val = ARM_AM::getAM5Opc(AddSub, Val); 1775 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1776 Inst.addOperand(MCOperand::CreateImm(Val)); 1777 } 1778 1779 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const { 1780 assert(N == 2 && "Invalid number of operands!"); 1781 // If we have an immediate that's not a constant, treat it as a label 1782 // reference needing a fixup. If it is a constant, it's something else 1783 // and we reject it. 1784 if (isImm()) { 1785 Inst.addOperand(MCOperand::CreateExpr(getImm())); 1786 Inst.addOperand(MCOperand::CreateImm(0)); 1787 return; 1788 } 1789 1790 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1791 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1792 Inst.addOperand(MCOperand::CreateImm(Val)); 1793 } 1794 1795 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const { 1796 assert(N == 2 && "Invalid number of operands!"); 1797 // The lower two bits are always zero and as such are not encoded. 1798 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0; 1799 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1800 Inst.addOperand(MCOperand::CreateImm(Val)); 1801 } 1802 1803 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const { 1804 assert(N == 2 && "Invalid number of operands!"); 1805 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1806 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1807 Inst.addOperand(MCOperand::CreateImm(Val)); 1808 } 1809 1810 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const { 1811 addMemImm8OffsetOperands(Inst, N); 1812 } 1813 1814 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const { 1815 addMemImm8OffsetOperands(Inst, N); 1816 } 1817 1818 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const { 1819 assert(N == 2 && "Invalid number of operands!"); 1820 // If this is an immediate, it's a label reference. 1821 if (isImm()) { 1822 addExpr(Inst, getImm()); 1823 Inst.addOperand(MCOperand::CreateImm(0)); 1824 return; 1825 } 1826 1827 // Otherwise, it's a normal memory reg+offset. 1828 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1829 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1830 Inst.addOperand(MCOperand::CreateImm(Val)); 1831 } 1832 1833 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const { 1834 assert(N == 2 && "Invalid number of operands!"); 1835 // If this is an immediate, it's a label reference. 1836 if (isImm()) { 1837 addExpr(Inst, getImm()); 1838 Inst.addOperand(MCOperand::CreateImm(0)); 1839 return; 1840 } 1841 1842 // Otherwise, it's a normal memory reg+offset. 1843 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1844 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1845 Inst.addOperand(MCOperand::CreateImm(Val)); 1846 } 1847 1848 void addMemTBBOperands(MCInst &Inst, unsigned N) const { 1849 assert(N == 2 && "Invalid number of operands!"); 1850 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1851 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1852 } 1853 1854 void addMemTBHOperands(MCInst &Inst, unsigned N) const { 1855 assert(N == 2 && "Invalid number of operands!"); 1856 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1857 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1858 } 1859 1860 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const { 1861 assert(N == 3 && "Invalid number of operands!"); 1862 unsigned Val = 1863 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 1864 Memory.ShiftImm, Memory.ShiftType); 1865 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1866 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1867 Inst.addOperand(MCOperand::CreateImm(Val)); 1868 } 1869 1870 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const { 1871 assert(N == 3 && "Invalid number of operands!"); 1872 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1873 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1874 Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm)); 1875 } 1876 1877 void addMemThumbRROperands(MCInst &Inst, unsigned N) const { 1878 assert(N == 2 && "Invalid number of operands!"); 1879 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1880 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1881 } 1882 1883 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const { 1884 assert(N == 2 && "Invalid number of operands!"); 1885 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0; 1886 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1887 Inst.addOperand(MCOperand::CreateImm(Val)); 1888 } 1889 1890 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const { 1891 assert(N == 2 && "Invalid number of operands!"); 1892 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0; 1893 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1894 Inst.addOperand(MCOperand::CreateImm(Val)); 1895 } 1896 1897 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const { 1898 assert(N == 2 && "Invalid number of operands!"); 1899 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0; 1900 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1901 Inst.addOperand(MCOperand::CreateImm(Val)); 1902 } 1903 1904 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const { 1905 assert(N == 2 && "Invalid number of operands!"); 1906 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0; 1907 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1908 Inst.addOperand(MCOperand::CreateImm(Val)); 1909 } 1910 1911 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const { 1912 assert(N == 1 && "Invalid number of operands!"); 1913 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1914 assert(CE && "non-constant post-idx-imm8 operand!"); 1915 int Imm = CE->getValue(); 1916 bool isAdd = Imm >= 0; 1917 if (Imm == INT32_MIN) Imm = 0; 1918 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8; 1919 Inst.addOperand(MCOperand::CreateImm(Imm)); 1920 } 1921 1922 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const { 1923 assert(N == 1 && "Invalid number of operands!"); 1924 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1925 assert(CE && "non-constant post-idx-imm8s4 operand!"); 1926 int Imm = CE->getValue(); 1927 bool isAdd = Imm >= 0; 1928 if (Imm == INT32_MIN) Imm = 0; 1929 // Immediate is scaled by 4. 1930 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8; 1931 Inst.addOperand(MCOperand::CreateImm(Imm)); 1932 } 1933 1934 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const { 1935 assert(N == 2 && "Invalid number of operands!"); 1936 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 1937 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd)); 1938 } 1939 1940 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const { 1941 assert(N == 2 && "Invalid number of operands!"); 1942 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 1943 // The sign, shift type, and shift amount are encoded in a single operand 1944 // using the AM2 encoding helpers. 1945 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub; 1946 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm, 1947 PostIdxReg.ShiftTy); 1948 Inst.addOperand(MCOperand::CreateImm(Imm)); 1949 } 1950 1951 void addMSRMaskOperands(MCInst &Inst, unsigned N) const { 1952 assert(N == 1 && "Invalid number of operands!"); 1953 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask()))); 1954 } 1955 1956 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const { 1957 assert(N == 1 && "Invalid number of operands!"); 1958 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags()))); 1959 } 1960 1961 void addVecListOperands(MCInst &Inst, unsigned N) const { 1962 assert(N == 1 && "Invalid number of operands!"); 1963 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum)); 1964 } 1965 1966 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const { 1967 assert(N == 2 && "Invalid number of operands!"); 1968 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum)); 1969 Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex)); 1970 } 1971 1972 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const { 1973 assert(N == 1 && "Invalid number of operands!"); 1974 Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); 1975 } 1976 1977 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const { 1978 assert(N == 1 && "Invalid number of operands!"); 1979 Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); 1980 } 1981 1982 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const { 1983 assert(N == 1 && "Invalid number of operands!"); 1984 Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); 1985 } 1986 1987 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const { 1988 assert(N == 1 && "Invalid number of operands!"); 1989 // The immediate encodes the type of constant as well as the value. 1990 // Mask in that this is an i8 splat. 1991 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1992 Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00)); 1993 } 1994 1995 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const { 1996 assert(N == 1 && "Invalid number of operands!"); 1997 // The immediate encodes the type of constant as well as the value. 1998 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1999 unsigned Value = CE->getValue(); 2000 if (Value >= 256) 2001 Value = (Value >> 8) | 0xa00; 2002 else 2003 Value |= 0x800; 2004 Inst.addOperand(MCOperand::CreateImm(Value)); 2005 } 2006 2007 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const { 2008 assert(N == 1 && "Invalid number of operands!"); 2009 // The immediate encodes the type of constant as well as the value. 2010 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2011 unsigned Value = CE->getValue(); 2012 if (Value >= 256 && Value <= 0xff00) 2013 Value = (Value >> 8) | 0x200; 2014 else if (Value > 0xffff && Value <= 0xff0000) 2015 Value = (Value >> 16) | 0x400; 2016 else if (Value > 0xffffff) 2017 Value = (Value >> 24) | 0x600; 2018 Inst.addOperand(MCOperand::CreateImm(Value)); 2019 } 2020 2021 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const { 2022 assert(N == 1 && "Invalid number of operands!"); 2023 // The immediate encodes the type of constant as well as the value. 2024 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2025 unsigned Value = CE->getValue(); 2026 if (Value >= 256 && Value <= 0xffff) 2027 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200); 2028 else if (Value > 0xffff && Value <= 0xffffff) 2029 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400); 2030 else if (Value > 0xffffff) 2031 Value = (Value >> 24) | 0x600; 2032 Inst.addOperand(MCOperand::CreateImm(Value)); 2033 } 2034 2035 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const { 2036 assert(N == 1 && "Invalid number of operands!"); 2037 // The immediate encodes the type of constant as well as the value. 2038 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2039 unsigned Value = ~CE->getValue(); 2040 if (Value >= 256 && Value <= 0xffff) 2041 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200); 2042 else if (Value > 0xffff && Value <= 0xffffff) 2043 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400); 2044 else if (Value > 0xffffff) 2045 Value = (Value >> 24) | 0x600; 2046 Inst.addOperand(MCOperand::CreateImm(Value)); 2047 } 2048 2049 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const { 2050 assert(N == 1 && "Invalid number of operands!"); 2051 // The immediate encodes the type of constant as well as the value. 2052 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2053 uint64_t Value = CE->getValue(); 2054 unsigned Imm = 0; 2055 for (unsigned i = 0; i < 8; ++i, Value >>= 8) { 2056 Imm |= (Value & 1) << i; 2057 } 2058 Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00)); 2059 } 2060 2061 virtual void print(raw_ostream &OS) const; 2062 2063 static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) { 2064 ARMOperand *Op = new ARMOperand(k_ITCondMask); 2065 Op->ITMask.Mask = Mask; 2066 Op->StartLoc = S; 2067 Op->EndLoc = S; 2068 return Op; 2069 } 2070 2071 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) { 2072 ARMOperand *Op = new ARMOperand(k_CondCode); 2073 Op->CC.Val = CC; 2074 Op->StartLoc = S; 2075 Op->EndLoc = S; 2076 return Op; 2077 } 2078 2079 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) { 2080 ARMOperand *Op = new ARMOperand(k_CoprocNum); 2081 Op->Cop.Val = CopVal; 2082 Op->StartLoc = S; 2083 Op->EndLoc = S; 2084 return Op; 2085 } 2086 2087 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) { 2088 ARMOperand *Op = new ARMOperand(k_CoprocReg); 2089 Op->Cop.Val = CopVal; 2090 Op->StartLoc = S; 2091 Op->EndLoc = S; 2092 return Op; 2093 } 2094 2095 static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) { 2096 ARMOperand *Op = new ARMOperand(k_CoprocOption); 2097 Op->Cop.Val = Val; 2098 Op->StartLoc = S; 2099 Op->EndLoc = E; 2100 return Op; 2101 } 2102 2103 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) { 2104 ARMOperand *Op = new ARMOperand(k_CCOut); 2105 Op->Reg.RegNum = RegNum; 2106 Op->StartLoc = S; 2107 Op->EndLoc = S; 2108 return Op; 2109 } 2110 2111 static ARMOperand *CreateToken(StringRef Str, SMLoc S) { 2112 ARMOperand *Op = new ARMOperand(k_Token); 2113 Op->Tok.Data = Str.data(); 2114 Op->Tok.Length = Str.size(); 2115 Op->StartLoc = S; 2116 Op->EndLoc = S; 2117 return Op; 2118 } 2119 2120 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) { 2121 ARMOperand *Op = new ARMOperand(k_Register); 2122 Op->Reg.RegNum = RegNum; 2123 Op->StartLoc = S; 2124 Op->EndLoc = E; 2125 return Op; 2126 } 2127 2128 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, 2129 unsigned SrcReg, 2130 unsigned ShiftReg, 2131 unsigned ShiftImm, 2132 SMLoc S, SMLoc E) { 2133 ARMOperand *Op = new ARMOperand(k_ShiftedRegister); 2134 Op->RegShiftedReg.ShiftTy = ShTy; 2135 Op->RegShiftedReg.SrcReg = SrcReg; 2136 Op->RegShiftedReg.ShiftReg = ShiftReg; 2137 Op->RegShiftedReg.ShiftImm = ShiftImm; 2138 Op->StartLoc = S; 2139 Op->EndLoc = E; 2140 return Op; 2141 } 2142 2143 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, 2144 unsigned SrcReg, 2145 unsigned ShiftImm, 2146 SMLoc S, SMLoc E) { 2147 ARMOperand *Op = new ARMOperand(k_ShiftedImmediate); 2148 Op->RegShiftedImm.ShiftTy = ShTy; 2149 Op->RegShiftedImm.SrcReg = SrcReg; 2150 Op->RegShiftedImm.ShiftImm = ShiftImm; 2151 Op->StartLoc = S; 2152 Op->EndLoc = E; 2153 return Op; 2154 } 2155 2156 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm, 2157 SMLoc S, SMLoc E) { 2158 ARMOperand *Op = new ARMOperand(k_ShifterImmediate); 2159 Op->ShifterImm.isASR = isASR; 2160 Op->ShifterImm.Imm = Imm; 2161 Op->StartLoc = S; 2162 Op->EndLoc = E; 2163 return Op; 2164 } 2165 2166 static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) { 2167 ARMOperand *Op = new ARMOperand(k_RotateImmediate); 2168 Op->RotImm.Imm = Imm; 2169 Op->StartLoc = S; 2170 Op->EndLoc = E; 2171 return Op; 2172 } 2173 2174 static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width, 2175 SMLoc S, SMLoc E) { 2176 ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor); 2177 Op->Bitfield.LSB = LSB; 2178 Op->Bitfield.Width = Width; 2179 Op->StartLoc = S; 2180 Op->EndLoc = E; 2181 return Op; 2182 } 2183 2184 static ARMOperand * 2185 CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs, 2186 SMLoc StartLoc, SMLoc EndLoc) { 2187 KindTy Kind = k_RegisterList; 2188 2189 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().first)) 2190 Kind = k_DPRRegisterList; 2191 else if (ARMMCRegisterClasses[ARM::SPRRegClassID]. 2192 contains(Regs.front().first)) 2193 Kind = k_SPRRegisterList; 2194 2195 ARMOperand *Op = new ARMOperand(Kind); 2196 for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator 2197 I = Regs.begin(), E = Regs.end(); I != E; ++I) 2198 Op->Registers.push_back(I->first); 2199 array_pod_sort(Op->Registers.begin(), Op->Registers.end()); 2200 Op->StartLoc = StartLoc; 2201 Op->EndLoc = EndLoc; 2202 return Op; 2203 } 2204 2205 static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count, 2206 bool isDoubleSpaced, SMLoc S, SMLoc E) { 2207 ARMOperand *Op = new ARMOperand(k_VectorList); 2208 Op->VectorList.RegNum = RegNum; 2209 Op->VectorList.Count = Count; 2210 Op->VectorList.isDoubleSpaced = isDoubleSpaced; 2211 Op->StartLoc = S; 2212 Op->EndLoc = E; 2213 return Op; 2214 } 2215 2216 static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count, 2217 bool isDoubleSpaced, 2218 SMLoc S, SMLoc E) { 2219 ARMOperand *Op = new ARMOperand(k_VectorListAllLanes); 2220 Op->VectorList.RegNum = RegNum; 2221 Op->VectorList.Count = Count; 2222 Op->VectorList.isDoubleSpaced = isDoubleSpaced; 2223 Op->StartLoc = S; 2224 Op->EndLoc = E; 2225 return Op; 2226 } 2227 2228 static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count, 2229 unsigned Index, 2230 bool isDoubleSpaced, 2231 SMLoc S, SMLoc E) { 2232 ARMOperand *Op = new ARMOperand(k_VectorListIndexed); 2233 Op->VectorList.RegNum = RegNum; 2234 Op->VectorList.Count = Count; 2235 Op->VectorList.LaneIndex = Index; 2236 Op->VectorList.isDoubleSpaced = isDoubleSpaced; 2237 Op->StartLoc = S; 2238 Op->EndLoc = E; 2239 return Op; 2240 } 2241 2242 static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E, 2243 MCContext &Ctx) { 2244 ARMOperand *Op = new ARMOperand(k_VectorIndex); 2245 Op->VectorIndex.Val = Idx; 2246 Op->StartLoc = S; 2247 Op->EndLoc = E; 2248 return Op; 2249 } 2250 2251 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) { 2252 ARMOperand *Op = new ARMOperand(k_Immediate); 2253 Op->Imm.Val = Val; 2254 Op->StartLoc = S; 2255 Op->EndLoc = E; 2256 return Op; 2257 } 2258 2259 static ARMOperand *CreateMem(unsigned BaseRegNum, 2260 const MCConstantExpr *OffsetImm, 2261 unsigned OffsetRegNum, 2262 ARM_AM::ShiftOpc ShiftType, 2263 unsigned ShiftImm, 2264 unsigned Alignment, 2265 bool isNegative, 2266 SMLoc S, SMLoc E) { 2267 ARMOperand *Op = new ARMOperand(k_Memory); 2268 Op->Memory.BaseRegNum = BaseRegNum; 2269 Op->Memory.OffsetImm = OffsetImm; 2270 Op->Memory.OffsetRegNum = OffsetRegNum; 2271 Op->Memory.ShiftType = ShiftType; 2272 Op->Memory.ShiftImm = ShiftImm; 2273 Op->Memory.Alignment = Alignment; 2274 Op->Memory.isNegative = isNegative; 2275 Op->StartLoc = S; 2276 Op->EndLoc = E; 2277 return Op; 2278 } 2279 2280 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd, 2281 ARM_AM::ShiftOpc ShiftTy, 2282 unsigned ShiftImm, 2283 SMLoc S, SMLoc E) { 2284 ARMOperand *Op = new ARMOperand(k_PostIndexRegister); 2285 Op->PostIdxReg.RegNum = RegNum; 2286 Op->PostIdxReg.isAdd = isAdd; 2287 Op->PostIdxReg.ShiftTy = ShiftTy; 2288 Op->PostIdxReg.ShiftImm = ShiftImm; 2289 Op->StartLoc = S; 2290 Op->EndLoc = E; 2291 return Op; 2292 } 2293 2294 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) { 2295 ARMOperand *Op = new ARMOperand(k_MemBarrierOpt); 2296 Op->MBOpt.Val = Opt; 2297 Op->StartLoc = S; 2298 Op->EndLoc = S; 2299 return Op; 2300 } 2301 2302 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) { 2303 ARMOperand *Op = new ARMOperand(k_ProcIFlags); 2304 Op->IFlags.Val = IFlags; 2305 Op->StartLoc = S; 2306 Op->EndLoc = S; 2307 return Op; 2308 } 2309 2310 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) { 2311 ARMOperand *Op = new ARMOperand(k_MSRMask); 2312 Op->MMask.Val = MMask; 2313 Op->StartLoc = S; 2314 Op->EndLoc = S; 2315 return Op; 2316 } 2317}; 2318 2319} // end anonymous namespace. 2320 2321void ARMOperand::print(raw_ostream &OS) const { 2322 switch (Kind) { 2323 case k_CondCode: 2324 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">"; 2325 break; 2326 case k_CCOut: 2327 OS << "<ccout " << getReg() << ">"; 2328 break; 2329 case k_ITCondMask: { 2330 static const char *const MaskStr[] = { 2331 "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)", 2332 "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)" 2333 }; 2334 assert((ITMask.Mask & 0xf) == ITMask.Mask); 2335 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">"; 2336 break; 2337 } 2338 case k_CoprocNum: 2339 OS << "<coprocessor number: " << getCoproc() << ">"; 2340 break; 2341 case k_CoprocReg: 2342 OS << "<coprocessor register: " << getCoproc() << ">"; 2343 break; 2344 case k_CoprocOption: 2345 OS << "<coprocessor option: " << CoprocOption.Val << ">"; 2346 break; 2347 case k_MSRMask: 2348 OS << "<mask: " << getMSRMask() << ">"; 2349 break; 2350 case k_Immediate: 2351 getImm()->print(OS); 2352 break; 2353 case k_MemBarrierOpt: 2354 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">"; 2355 break; 2356 case k_Memory: 2357 OS << "<memory " 2358 << " base:" << Memory.BaseRegNum; 2359 OS << ">"; 2360 break; 2361 case k_PostIndexRegister: 2362 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-") 2363 << PostIdxReg.RegNum; 2364 if (PostIdxReg.ShiftTy != ARM_AM::no_shift) 2365 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " " 2366 << PostIdxReg.ShiftImm; 2367 OS << ">"; 2368 break; 2369 case k_ProcIFlags: { 2370 OS << "<ARM_PROC::"; 2371 unsigned IFlags = getProcIFlags(); 2372 for (int i=2; i >= 0; --i) 2373 if (IFlags & (1 << i)) 2374 OS << ARM_PROC::IFlagsToString(1 << i); 2375 OS << ">"; 2376 break; 2377 } 2378 case k_Register: 2379 OS << "<register " << getReg() << ">"; 2380 break; 2381 case k_ShifterImmediate: 2382 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl") 2383 << " #" << ShifterImm.Imm << ">"; 2384 break; 2385 case k_ShiftedRegister: 2386 OS << "<so_reg_reg " 2387 << RegShiftedReg.SrcReg << " " 2388 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy) 2389 << " " << RegShiftedReg.ShiftReg << ">"; 2390 break; 2391 case k_ShiftedImmediate: 2392 OS << "<so_reg_imm " 2393 << RegShiftedImm.SrcReg << " " 2394 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy) 2395 << " #" << RegShiftedImm.ShiftImm << ">"; 2396 break; 2397 case k_RotateImmediate: 2398 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">"; 2399 break; 2400 case k_BitfieldDescriptor: 2401 OS << "<bitfield " << "lsb: " << Bitfield.LSB 2402 << ", width: " << Bitfield.Width << ">"; 2403 break; 2404 case k_RegisterList: 2405 case k_DPRRegisterList: 2406 case k_SPRRegisterList: { 2407 OS << "<register_list "; 2408 2409 const SmallVectorImpl<unsigned> &RegList = getRegList(); 2410 for (SmallVectorImpl<unsigned>::const_iterator 2411 I = RegList.begin(), E = RegList.end(); I != E; ) { 2412 OS << *I; 2413 if (++I < E) OS << ", "; 2414 } 2415 2416 OS << ">"; 2417 break; 2418 } 2419 case k_VectorList: 2420 OS << "<vector_list " << VectorList.Count << " * " 2421 << VectorList.RegNum << ">"; 2422 break; 2423 case k_VectorListAllLanes: 2424 OS << "<vector_list(all lanes) " << VectorList.Count << " * " 2425 << VectorList.RegNum << ">"; 2426 break; 2427 case k_VectorListIndexed: 2428 OS << "<vector_list(lane " << VectorList.LaneIndex << ") " 2429 << VectorList.Count << " * " << VectorList.RegNum << ">"; 2430 break; 2431 case k_Token: 2432 OS << "'" << getToken() << "'"; 2433 break; 2434 case k_VectorIndex: 2435 OS << "<vectorindex " << getVectorIndex() << ">"; 2436 break; 2437 } 2438} 2439 2440/// @name Auto-generated Match Functions 2441/// { 2442 2443static unsigned MatchRegisterName(StringRef Name); 2444 2445/// } 2446 2447bool ARMAsmParser::ParseRegister(unsigned &RegNo, 2448 SMLoc &StartLoc, SMLoc &EndLoc) { 2449 StartLoc = Parser.getTok().getLoc(); 2450 RegNo = tryParseRegister(); 2451 EndLoc = Parser.getTok().getLoc(); 2452 2453 return (RegNo == (unsigned)-1); 2454} 2455 2456/// Try to parse a register name. The token must be an Identifier when called, 2457/// and if it is a register name the token is eaten and the register number is 2458/// returned. Otherwise return -1. 2459/// 2460int ARMAsmParser::tryParseRegister() { 2461 const AsmToken &Tok = Parser.getTok(); 2462 if (Tok.isNot(AsmToken::Identifier)) return -1; 2463 2464 std::string lowerCase = Tok.getString().lower(); 2465 unsigned RegNum = MatchRegisterName(lowerCase); 2466 if (!RegNum) { 2467 RegNum = StringSwitch<unsigned>(lowerCase) 2468 .Case("r13", ARM::SP) 2469 .Case("r14", ARM::LR) 2470 .Case("r15", ARM::PC) 2471 .Case("ip", ARM::R12) 2472 // Additional register name aliases for 'gas' compatibility. 2473 .Case("a1", ARM::R0) 2474 .Case("a2", ARM::R1) 2475 .Case("a3", ARM::R2) 2476 .Case("a4", ARM::R3) 2477 .Case("v1", ARM::R4) 2478 .Case("v2", ARM::R5) 2479 .Case("v3", ARM::R6) 2480 .Case("v4", ARM::R7) 2481 .Case("v5", ARM::R8) 2482 .Case("v6", ARM::R9) 2483 .Case("v7", ARM::R10) 2484 .Case("v8", ARM::R11) 2485 .Case("sb", ARM::R9) 2486 .Case("sl", ARM::R10) 2487 .Case("fp", ARM::R11) 2488 .Default(0); 2489 } 2490 if (!RegNum) { 2491 // Check for aliases registered via .req. Canonicalize to lower case. 2492 // That's more consistent since register names are case insensitive, and 2493 // it's how the original entry was passed in from MC/MCParser/AsmParser. 2494 StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase); 2495 // If no match, return failure. 2496 if (Entry == RegisterReqs.end()) 2497 return -1; 2498 Parser.Lex(); // Eat identifier token. 2499 return Entry->getValue(); 2500 } 2501 2502 Parser.Lex(); // Eat identifier token. 2503 2504 return RegNum; 2505} 2506 2507// Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0. 2508// If a recoverable error occurs, return 1. If an irrecoverable error 2509// occurs, return -1. An irrecoverable error is one where tokens have been 2510// consumed in the process of trying to parse the shifter (i.e., when it is 2511// indeed a shifter operand, but malformed). 2512int ARMAsmParser::tryParseShiftRegister( 2513 SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2514 SMLoc S = Parser.getTok().getLoc(); 2515 const AsmToken &Tok = Parser.getTok(); 2516 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 2517 2518 std::string lowerCase = Tok.getString().lower(); 2519 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase) 2520 .Case("asl", ARM_AM::lsl) 2521 .Case("lsl", ARM_AM::lsl) 2522 .Case("lsr", ARM_AM::lsr) 2523 .Case("asr", ARM_AM::asr) 2524 .Case("ror", ARM_AM::ror) 2525 .Case("rrx", ARM_AM::rrx) 2526 .Default(ARM_AM::no_shift); 2527 2528 if (ShiftTy == ARM_AM::no_shift) 2529 return 1; 2530 2531 Parser.Lex(); // Eat the operator. 2532 2533 // The source register for the shift has already been added to the 2534 // operand list, so we need to pop it off and combine it into the shifted 2535 // register operand instead. 2536 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val()); 2537 if (!PrevOp->isReg()) 2538 return Error(PrevOp->getStartLoc(), "shift must be of a register"); 2539 int SrcReg = PrevOp->getReg(); 2540 int64_t Imm = 0; 2541 int ShiftReg = 0; 2542 if (ShiftTy == ARM_AM::rrx) { 2543 // RRX Doesn't have an explicit shift amount. The encoder expects 2544 // the shift register to be the same as the source register. Seems odd, 2545 // but OK. 2546 ShiftReg = SrcReg; 2547 } else { 2548 // Figure out if this is shifted by a constant or a register (for non-RRX). 2549 if (Parser.getTok().is(AsmToken::Hash) || 2550 Parser.getTok().is(AsmToken::Dollar)) { 2551 Parser.Lex(); // Eat hash. 2552 SMLoc ImmLoc = Parser.getTok().getLoc(); 2553 const MCExpr *ShiftExpr = 0; 2554 if (getParser().ParseExpression(ShiftExpr)) { 2555 Error(ImmLoc, "invalid immediate shift value"); 2556 return -1; 2557 } 2558 // The expression must be evaluatable as an immediate. 2559 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr); 2560 if (!CE) { 2561 Error(ImmLoc, "invalid immediate shift value"); 2562 return -1; 2563 } 2564 // Range check the immediate. 2565 // lsl, ror: 0 <= imm <= 31 2566 // lsr, asr: 0 <= imm <= 32 2567 Imm = CE->getValue(); 2568 if (Imm < 0 || 2569 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) || 2570 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) { 2571 Error(ImmLoc, "immediate shift value out of range"); 2572 return -1; 2573 } 2574 // shift by zero is a nop. Always send it through as lsl. 2575 // ('as' compatibility) 2576 if (Imm == 0) 2577 ShiftTy = ARM_AM::lsl; 2578 } else if (Parser.getTok().is(AsmToken::Identifier)) { 2579 ShiftReg = tryParseRegister(); 2580 SMLoc L = Parser.getTok().getLoc(); 2581 if (ShiftReg == -1) { 2582 Error (L, "expected immediate or register in shift operand"); 2583 return -1; 2584 } 2585 } else { 2586 Error (Parser.getTok().getLoc(), 2587 "expected immediate or register in shift operand"); 2588 return -1; 2589 } 2590 } 2591 2592 if (ShiftReg && ShiftTy != ARM_AM::rrx) 2593 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg, 2594 ShiftReg, Imm, 2595 S, Parser.getTok().getLoc())); 2596 else 2597 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm, 2598 S, Parser.getTok().getLoc())); 2599 2600 return 0; 2601} 2602 2603 2604/// Try to parse a register name. The token must be an Identifier when called. 2605/// If it's a register, an AsmOperand is created. Another AsmOperand is created 2606/// if there is a "writeback". 'true' if it's not a register. 2607/// 2608/// TODO this is likely to change to allow different register types and or to 2609/// parse for a specific register type. 2610bool ARMAsmParser:: 2611tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2612 SMLoc S = Parser.getTok().getLoc(); 2613 int RegNo = tryParseRegister(); 2614 if (RegNo == -1) 2615 return true; 2616 2617 Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc())); 2618 2619 const AsmToken &ExclaimTok = Parser.getTok(); 2620 if (ExclaimTok.is(AsmToken::Exclaim)) { 2621 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(), 2622 ExclaimTok.getLoc())); 2623 Parser.Lex(); // Eat exclaim token 2624 return false; 2625 } 2626 2627 // Also check for an index operand. This is only legal for vector registers, 2628 // but that'll get caught OK in operand matching, so we don't need to 2629 // explicitly filter everything else out here. 2630 if (Parser.getTok().is(AsmToken::LBrac)) { 2631 SMLoc SIdx = Parser.getTok().getLoc(); 2632 Parser.Lex(); // Eat left bracket token. 2633 2634 const MCExpr *ImmVal; 2635 if (getParser().ParseExpression(ImmVal)) 2636 return true; 2637 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal); 2638 if (!MCE) 2639 return TokError("immediate value expected for vector index"); 2640 2641 SMLoc E = Parser.getTok().getLoc(); 2642 if (Parser.getTok().isNot(AsmToken::RBrac)) 2643 return Error(E, "']' expected"); 2644 2645 Parser.Lex(); // Eat right bracket token. 2646 2647 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(), 2648 SIdx, E, 2649 getContext())); 2650 } 2651 2652 return false; 2653} 2654 2655/// MatchCoprocessorOperandName - Try to parse an coprocessor related 2656/// instruction with a symbolic operand name. Example: "p1", "p7", "c3", 2657/// "c5", ... 2658static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) { 2659 // Use the same layout as the tablegen'erated register name matcher. Ugly, 2660 // but efficient. 2661 switch (Name.size()) { 2662 default: return -1; 2663 case 2: 2664 if (Name[0] != CoprocOp) 2665 return -1; 2666 switch (Name[1]) { 2667 default: return -1; 2668 case '0': return 0; 2669 case '1': return 1; 2670 case '2': return 2; 2671 case '3': return 3; 2672 case '4': return 4; 2673 case '5': return 5; 2674 case '6': return 6; 2675 case '7': return 7; 2676 case '8': return 8; 2677 case '9': return 9; 2678 } 2679 case 3: 2680 if (Name[0] != CoprocOp || Name[1] != '1') 2681 return -1; 2682 switch (Name[2]) { 2683 default: return -1; 2684 case '0': return 10; 2685 case '1': return 11; 2686 case '2': return 12; 2687 case '3': return 13; 2688 case '4': return 14; 2689 case '5': return 15; 2690 } 2691 } 2692} 2693 2694/// parseITCondCode - Try to parse a condition code for an IT instruction. 2695ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2696parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2697 SMLoc S = Parser.getTok().getLoc(); 2698 const AsmToken &Tok = Parser.getTok(); 2699 if (!Tok.is(AsmToken::Identifier)) 2700 return MatchOperand_NoMatch; 2701 unsigned CC = StringSwitch<unsigned>(Tok.getString().lower()) 2702 .Case("eq", ARMCC::EQ) 2703 .Case("ne", ARMCC::NE) 2704 .Case("hs", ARMCC::HS) 2705 .Case("cs", ARMCC::HS) 2706 .Case("lo", ARMCC::LO) 2707 .Case("cc", ARMCC::LO) 2708 .Case("mi", ARMCC::MI) 2709 .Case("pl", ARMCC::PL) 2710 .Case("vs", ARMCC::VS) 2711 .Case("vc", ARMCC::VC) 2712 .Case("hi", ARMCC::HI) 2713 .Case("ls", ARMCC::LS) 2714 .Case("ge", ARMCC::GE) 2715 .Case("lt", ARMCC::LT) 2716 .Case("gt", ARMCC::GT) 2717 .Case("le", ARMCC::LE) 2718 .Case("al", ARMCC::AL) 2719 .Default(~0U); 2720 if (CC == ~0U) 2721 return MatchOperand_NoMatch; 2722 Parser.Lex(); // Eat the token. 2723 2724 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S)); 2725 2726 return MatchOperand_Success; 2727} 2728 2729/// parseCoprocNumOperand - Try to parse an coprocessor number operand. The 2730/// token must be an Identifier when called, and if it is a coprocessor 2731/// number, the token is eaten and the operand is added to the operand list. 2732ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2733parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2734 SMLoc S = Parser.getTok().getLoc(); 2735 const AsmToken &Tok = Parser.getTok(); 2736 if (Tok.isNot(AsmToken::Identifier)) 2737 return MatchOperand_NoMatch; 2738 2739 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p'); 2740 if (Num == -1) 2741 return MatchOperand_NoMatch; 2742 2743 Parser.Lex(); // Eat identifier token. 2744 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S)); 2745 return MatchOperand_Success; 2746} 2747 2748/// parseCoprocRegOperand - Try to parse an coprocessor register operand. The 2749/// token must be an Identifier when called, and if it is a coprocessor 2750/// number, the token is eaten and the operand is added to the operand list. 2751ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2752parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2753 SMLoc S = Parser.getTok().getLoc(); 2754 const AsmToken &Tok = Parser.getTok(); 2755 if (Tok.isNot(AsmToken::Identifier)) 2756 return MatchOperand_NoMatch; 2757 2758 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c'); 2759 if (Reg == -1) 2760 return MatchOperand_NoMatch; 2761 2762 Parser.Lex(); // Eat identifier token. 2763 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S)); 2764 return MatchOperand_Success; 2765} 2766 2767/// parseCoprocOptionOperand - Try to parse an coprocessor option operand. 2768/// coproc_option : '{' imm0_255 '}' 2769ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2770parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2771 SMLoc S = Parser.getTok().getLoc(); 2772 2773 // If this isn't a '{', this isn't a coprocessor immediate operand. 2774 if (Parser.getTok().isNot(AsmToken::LCurly)) 2775 return MatchOperand_NoMatch; 2776 Parser.Lex(); // Eat the '{' 2777 2778 const MCExpr *Expr; 2779 SMLoc Loc = Parser.getTok().getLoc(); 2780 if (getParser().ParseExpression(Expr)) { 2781 Error(Loc, "illegal expression"); 2782 return MatchOperand_ParseFail; 2783 } 2784 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 2785 if (!CE || CE->getValue() < 0 || CE->getValue() > 255) { 2786 Error(Loc, "coprocessor option must be an immediate in range [0, 255]"); 2787 return MatchOperand_ParseFail; 2788 } 2789 int Val = CE->getValue(); 2790 2791 // Check for and consume the closing '}' 2792 if (Parser.getTok().isNot(AsmToken::RCurly)) 2793 return MatchOperand_ParseFail; 2794 SMLoc E = Parser.getTok().getLoc(); 2795 Parser.Lex(); // Eat the '}' 2796 2797 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E)); 2798 return MatchOperand_Success; 2799} 2800 2801// For register list parsing, we need to map from raw GPR register numbering 2802// to the enumeration values. The enumeration values aren't sorted by 2803// register number due to our using "sp", "lr" and "pc" as canonical names. 2804static unsigned getNextRegister(unsigned Reg) { 2805 // If this is a GPR, we need to do it manually, otherwise we can rely 2806 // on the sort ordering of the enumeration since the other reg-classes 2807 // are sane. 2808 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 2809 return Reg + 1; 2810 switch(Reg) { 2811 default: llvm_unreachable("Invalid GPR number!"); 2812 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2; 2813 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4; 2814 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6; 2815 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8; 2816 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10; 2817 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12; 2818 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR; 2819 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0; 2820 } 2821} 2822 2823// Return the low-subreg of a given Q register. 2824static unsigned getDRegFromQReg(unsigned QReg) { 2825 switch (QReg) { 2826 default: llvm_unreachable("expected a Q register!"); 2827 case ARM::Q0: return ARM::D0; 2828 case ARM::Q1: return ARM::D2; 2829 case ARM::Q2: return ARM::D4; 2830 case ARM::Q3: return ARM::D6; 2831 case ARM::Q4: return ARM::D8; 2832 case ARM::Q5: return ARM::D10; 2833 case ARM::Q6: return ARM::D12; 2834 case ARM::Q7: return ARM::D14; 2835 case ARM::Q8: return ARM::D16; 2836 case ARM::Q9: return ARM::D18; 2837 case ARM::Q10: return ARM::D20; 2838 case ARM::Q11: return ARM::D22; 2839 case ARM::Q12: return ARM::D24; 2840 case ARM::Q13: return ARM::D26; 2841 case ARM::Q14: return ARM::D28; 2842 case ARM::Q15: return ARM::D30; 2843 } 2844} 2845 2846/// Parse a register list. 2847bool ARMAsmParser:: 2848parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2849 assert(Parser.getTok().is(AsmToken::LCurly) && 2850 "Token is not a Left Curly Brace"); 2851 SMLoc S = Parser.getTok().getLoc(); 2852 Parser.Lex(); // Eat '{' token. 2853 SMLoc RegLoc = Parser.getTok().getLoc(); 2854 2855 // Check the first register in the list to see what register class 2856 // this is a list of. 2857 int Reg = tryParseRegister(); 2858 if (Reg == -1) 2859 return Error(RegLoc, "register expected"); 2860 2861 // The reglist instructions have at most 16 registers, so reserve 2862 // space for that many. 2863 SmallVector<std::pair<unsigned, SMLoc>, 16> Registers; 2864 2865 // Allow Q regs and just interpret them as the two D sub-registers. 2866 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 2867 Reg = getDRegFromQReg(Reg); 2868 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc)); 2869 ++Reg; 2870 } 2871 const MCRegisterClass *RC; 2872 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 2873 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID]; 2874 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) 2875 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID]; 2876 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg)) 2877 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID]; 2878 else 2879 return Error(RegLoc, "invalid register in register list"); 2880 2881 // Store the register. 2882 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc)); 2883 2884 // This starts immediately after the first register token in the list, 2885 // so we can see either a comma or a minus (range separator) as a legal 2886 // next token. 2887 while (Parser.getTok().is(AsmToken::Comma) || 2888 Parser.getTok().is(AsmToken::Minus)) { 2889 if (Parser.getTok().is(AsmToken::Minus)) { 2890 Parser.Lex(); // Eat the minus. 2891 SMLoc EndLoc = Parser.getTok().getLoc(); 2892 int EndReg = tryParseRegister(); 2893 if (EndReg == -1) 2894 return Error(EndLoc, "register expected"); 2895 // Allow Q regs and just interpret them as the two D sub-registers. 2896 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) 2897 EndReg = getDRegFromQReg(EndReg) + 1; 2898 // If the register is the same as the start reg, there's nothing 2899 // more to do. 2900 if (Reg == EndReg) 2901 continue; 2902 // The register must be in the same register class as the first. 2903 if (!RC->contains(EndReg)) 2904 return Error(EndLoc, "invalid register in register list"); 2905 // Ranges must go from low to high. 2906 if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg)) 2907 return Error(EndLoc, "bad range in register list"); 2908 2909 // Add all the registers in the range to the register list. 2910 while (Reg != EndReg) { 2911 Reg = getNextRegister(Reg); 2912 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc)); 2913 } 2914 continue; 2915 } 2916 Parser.Lex(); // Eat the comma. 2917 RegLoc = Parser.getTok().getLoc(); 2918 int OldReg = Reg; 2919 const AsmToken RegTok = Parser.getTok(); 2920 Reg = tryParseRegister(); 2921 if (Reg == -1) 2922 return Error(RegLoc, "register expected"); 2923 // Allow Q regs and just interpret them as the two D sub-registers. 2924 bool isQReg = false; 2925 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 2926 Reg = getDRegFromQReg(Reg); 2927 isQReg = true; 2928 } 2929 // The register must be in the same register class as the first. 2930 if (!RC->contains(Reg)) 2931 return Error(RegLoc, "invalid register in register list"); 2932 // List must be monotonically increasing. 2933 if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) { 2934 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 2935 Warning(RegLoc, "register list not in ascending order"); 2936 else 2937 return Error(RegLoc, "register list not in ascending order"); 2938 } 2939 if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) { 2940 Warning(RegLoc, "duplicated register (" + RegTok.getString() + 2941 ") in register list"); 2942 continue; 2943 } 2944 // VFP register lists must also be contiguous. 2945 // It's OK to use the enumeration values directly here rather, as the 2946 // VFP register classes have the enum sorted properly. 2947 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] && 2948 Reg != OldReg + 1) 2949 return Error(RegLoc, "non-contiguous register range"); 2950 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc)); 2951 if (isQReg) 2952 Registers.push_back(std::pair<unsigned, SMLoc>(++Reg, RegLoc)); 2953 } 2954 2955 SMLoc E = Parser.getTok().getLoc(); 2956 if (Parser.getTok().isNot(AsmToken::RCurly)) 2957 return Error(E, "'}' expected"); 2958 Parser.Lex(); // Eat '}' token. 2959 2960 // Push the register list operand. 2961 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E)); 2962 2963 // The ARM system instruction variants for LDM/STM have a '^' token here. 2964 if (Parser.getTok().is(AsmToken::Caret)) { 2965 Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc())); 2966 Parser.Lex(); // Eat '^' token. 2967 } 2968 2969 return false; 2970} 2971 2972// Helper function to parse the lane index for vector lists. 2973ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2974parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index) { 2975 Index = 0; // Always return a defined index value. 2976 if (Parser.getTok().is(AsmToken::LBrac)) { 2977 Parser.Lex(); // Eat the '['. 2978 if (Parser.getTok().is(AsmToken::RBrac)) { 2979 // "Dn[]" is the 'all lanes' syntax. 2980 LaneKind = AllLanes; 2981 Parser.Lex(); // Eat the ']'. 2982 return MatchOperand_Success; 2983 } 2984 2985 // There's an optional '#' token here. Normally there wouldn't be, but 2986 // inline assemble puts one in, and it's friendly to accept that. 2987 if (Parser.getTok().is(AsmToken::Hash)) 2988 Parser.Lex(); // Eat the '#' 2989 2990 const MCExpr *LaneIndex; 2991 SMLoc Loc = Parser.getTok().getLoc(); 2992 if (getParser().ParseExpression(LaneIndex)) { 2993 Error(Loc, "illegal expression"); 2994 return MatchOperand_ParseFail; 2995 } 2996 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex); 2997 if (!CE) { 2998 Error(Loc, "lane index must be empty or an integer"); 2999 return MatchOperand_ParseFail; 3000 } 3001 if (Parser.getTok().isNot(AsmToken::RBrac)) { 3002 Error(Parser.getTok().getLoc(), "']' expected"); 3003 return MatchOperand_ParseFail; 3004 } 3005 Parser.Lex(); // Eat the ']'. 3006 int64_t Val = CE->getValue(); 3007 3008 // FIXME: Make this range check context sensitive for .8, .16, .32. 3009 if (Val < 0 || Val > 7) { 3010 Error(Parser.getTok().getLoc(), "lane index out of range"); 3011 return MatchOperand_ParseFail; 3012 } 3013 Index = Val; 3014 LaneKind = IndexedLane; 3015 return MatchOperand_Success; 3016 } 3017 LaneKind = NoLanes; 3018 return MatchOperand_Success; 3019} 3020 3021// parse a vector register list 3022ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3023parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3024 VectorLaneTy LaneKind; 3025 unsigned LaneIndex; 3026 SMLoc S = Parser.getTok().getLoc(); 3027 // As an extension (to match gas), support a plain D register or Q register 3028 // (without encosing curly braces) as a single or double entry list, 3029 // respectively. 3030 if (Parser.getTok().is(AsmToken::Identifier)) { 3031 int Reg = tryParseRegister(); 3032 if (Reg == -1) 3033 return MatchOperand_NoMatch; 3034 SMLoc E = Parser.getTok().getLoc(); 3035 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) { 3036 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex); 3037 if (Res != MatchOperand_Success) 3038 return Res; 3039 switch (LaneKind) { 3040 case NoLanes: 3041 E = Parser.getTok().getLoc(); 3042 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E)); 3043 break; 3044 case AllLanes: 3045 E = Parser.getTok().getLoc(); 3046 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false, 3047 S, E)); 3048 break; 3049 case IndexedLane: 3050 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1, 3051 LaneIndex, 3052 false, S, E)); 3053 break; 3054 } 3055 return MatchOperand_Success; 3056 } 3057 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3058 Reg = getDRegFromQReg(Reg); 3059 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex); 3060 if (Res != MatchOperand_Success) 3061 return Res; 3062 switch (LaneKind) { 3063 case NoLanes: 3064 E = Parser.getTok().getLoc(); 3065 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0, 3066 &ARMMCRegisterClasses[ARM::DPairRegClassID]); 3067 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E)); 3068 break; 3069 case AllLanes: 3070 E = Parser.getTok().getLoc(); 3071 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0, 3072 &ARMMCRegisterClasses[ARM::DPairRegClassID]); 3073 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false, 3074 S, E)); 3075 break; 3076 case IndexedLane: 3077 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2, 3078 LaneIndex, 3079 false, S, E)); 3080 break; 3081 } 3082 return MatchOperand_Success; 3083 } 3084 Error(S, "vector register expected"); 3085 return MatchOperand_ParseFail; 3086 } 3087 3088 if (Parser.getTok().isNot(AsmToken::LCurly)) 3089 return MatchOperand_NoMatch; 3090 3091 Parser.Lex(); // Eat '{' token. 3092 SMLoc RegLoc = Parser.getTok().getLoc(); 3093 3094 int Reg = tryParseRegister(); 3095 if (Reg == -1) { 3096 Error(RegLoc, "register expected"); 3097 return MatchOperand_ParseFail; 3098 } 3099 unsigned Count = 1; 3100 int Spacing = 0; 3101 unsigned FirstReg = Reg; 3102 // The list is of D registers, but we also allow Q regs and just interpret 3103 // them as the two D sub-registers. 3104 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3105 FirstReg = Reg = getDRegFromQReg(Reg); 3106 Spacing = 1; // double-spacing requires explicit D registers, otherwise 3107 // it's ambiguous with four-register single spaced. 3108 ++Reg; 3109 ++Count; 3110 } 3111 if (parseVectorLane(LaneKind, LaneIndex) != MatchOperand_Success) 3112 return MatchOperand_ParseFail; 3113 3114 while (Parser.getTok().is(AsmToken::Comma) || 3115 Parser.getTok().is(AsmToken::Minus)) { 3116 if (Parser.getTok().is(AsmToken::Minus)) { 3117 if (!Spacing) 3118 Spacing = 1; // Register range implies a single spaced list. 3119 else if (Spacing == 2) { 3120 Error(Parser.getTok().getLoc(), 3121 "sequential registers in double spaced list"); 3122 return MatchOperand_ParseFail; 3123 } 3124 Parser.Lex(); // Eat the minus. 3125 SMLoc EndLoc = Parser.getTok().getLoc(); 3126 int EndReg = tryParseRegister(); 3127 if (EndReg == -1) { 3128 Error(EndLoc, "register expected"); 3129 return MatchOperand_ParseFail; 3130 } 3131 // Allow Q regs and just interpret them as the two D sub-registers. 3132 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) 3133 EndReg = getDRegFromQReg(EndReg) + 1; 3134 // If the register is the same as the start reg, there's nothing 3135 // more to do. 3136 if (Reg == EndReg) 3137 continue; 3138 // The register must be in the same register class as the first. 3139 if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) { 3140 Error(EndLoc, "invalid register in register list"); 3141 return MatchOperand_ParseFail; 3142 } 3143 // Ranges must go from low to high. 3144 if (Reg > EndReg) { 3145 Error(EndLoc, "bad range in register list"); 3146 return MatchOperand_ParseFail; 3147 } 3148 // Parse the lane specifier if present. 3149 VectorLaneTy NextLaneKind; 3150 unsigned NextLaneIndex; 3151 if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success) 3152 return MatchOperand_ParseFail; 3153 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { 3154 Error(EndLoc, "mismatched lane index in register list"); 3155 return MatchOperand_ParseFail; 3156 } 3157 EndLoc = Parser.getTok().getLoc(); 3158 3159 // Add all the registers in the range to the register list. 3160 Count += EndReg - Reg; 3161 Reg = EndReg; 3162 continue; 3163 } 3164 Parser.Lex(); // Eat the comma. 3165 RegLoc = Parser.getTok().getLoc(); 3166 int OldReg = Reg; 3167 Reg = tryParseRegister(); 3168 if (Reg == -1) { 3169 Error(RegLoc, "register expected"); 3170 return MatchOperand_ParseFail; 3171 } 3172 // vector register lists must be contiguous. 3173 // It's OK to use the enumeration values directly here rather, as the 3174 // VFP register classes have the enum sorted properly. 3175 // 3176 // The list is of D registers, but we also allow Q regs and just interpret 3177 // them as the two D sub-registers. 3178 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3179 if (!Spacing) 3180 Spacing = 1; // Register range implies a single spaced list. 3181 else if (Spacing == 2) { 3182 Error(RegLoc, 3183 "invalid register in double-spaced list (must be 'D' register')"); 3184 return MatchOperand_ParseFail; 3185 } 3186 Reg = getDRegFromQReg(Reg); 3187 if (Reg != OldReg + 1) { 3188 Error(RegLoc, "non-contiguous register range"); 3189 return MatchOperand_ParseFail; 3190 } 3191 ++Reg; 3192 Count += 2; 3193 // Parse the lane specifier if present. 3194 VectorLaneTy NextLaneKind; 3195 unsigned NextLaneIndex; 3196 SMLoc EndLoc = Parser.getTok().getLoc(); 3197 if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success) 3198 return MatchOperand_ParseFail; 3199 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { 3200 Error(EndLoc, "mismatched lane index in register list"); 3201 return MatchOperand_ParseFail; 3202 } 3203 continue; 3204 } 3205 // Normal D register. 3206 // Figure out the register spacing (single or double) of the list if 3207 // we don't know it already. 3208 if (!Spacing) 3209 Spacing = 1 + (Reg == OldReg + 2); 3210 3211 // Just check that it's contiguous and keep going. 3212 if (Reg != OldReg + Spacing) { 3213 Error(RegLoc, "non-contiguous register range"); 3214 return MatchOperand_ParseFail; 3215 } 3216 ++Count; 3217 // Parse the lane specifier if present. 3218 VectorLaneTy NextLaneKind; 3219 unsigned NextLaneIndex; 3220 SMLoc EndLoc = Parser.getTok().getLoc(); 3221 if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success) 3222 return MatchOperand_ParseFail; 3223 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { 3224 Error(EndLoc, "mismatched lane index in register list"); 3225 return MatchOperand_ParseFail; 3226 } 3227 } 3228 3229 SMLoc E = Parser.getTok().getLoc(); 3230 if (Parser.getTok().isNot(AsmToken::RCurly)) { 3231 Error(E, "'}' expected"); 3232 return MatchOperand_ParseFail; 3233 } 3234 Parser.Lex(); // Eat '}' token. 3235 3236 switch (LaneKind) { 3237 case NoLanes: 3238 // Two-register operands have been converted to the 3239 // composite register classes. 3240 if (Count == 2) { 3241 const MCRegisterClass *RC = (Spacing == 1) ? 3242 &ARMMCRegisterClasses[ARM::DPairRegClassID] : 3243 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID]; 3244 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); 3245 } 3246 3247 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count, 3248 (Spacing == 2), S, E)); 3249 break; 3250 case AllLanes: 3251 // Two-register operands have been converted to the 3252 // composite register classes. 3253 if (Count == 2) { 3254 const MCRegisterClass *RC = (Spacing == 1) ? 3255 &ARMMCRegisterClasses[ARM::DPairRegClassID] : 3256 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID]; 3257 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); 3258 } 3259 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count, 3260 (Spacing == 2), 3261 S, E)); 3262 break; 3263 case IndexedLane: 3264 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count, 3265 LaneIndex, 3266 (Spacing == 2), 3267 S, E)); 3268 break; 3269 } 3270 return MatchOperand_Success; 3271} 3272 3273/// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options. 3274ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3275parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3276 SMLoc S = Parser.getTok().getLoc(); 3277 const AsmToken &Tok = Parser.getTok(); 3278 unsigned Opt; 3279 3280 if (Tok.is(AsmToken::Identifier)) { 3281 StringRef OptStr = Tok.getString(); 3282 3283 Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower()) 3284 .Case("sy", ARM_MB::SY) 3285 .Case("st", ARM_MB::ST) 3286 .Case("sh", ARM_MB::ISH) 3287 .Case("ish", ARM_MB::ISH) 3288 .Case("shst", ARM_MB::ISHST) 3289 .Case("ishst", ARM_MB::ISHST) 3290 .Case("nsh", ARM_MB::NSH) 3291 .Case("un", ARM_MB::NSH) 3292 .Case("nshst", ARM_MB::NSHST) 3293 .Case("unst", ARM_MB::NSHST) 3294 .Case("osh", ARM_MB::OSH) 3295 .Case("oshst", ARM_MB::OSHST) 3296 .Default(~0U); 3297 3298 if (Opt == ~0U) 3299 return MatchOperand_NoMatch; 3300 3301 Parser.Lex(); // Eat identifier token. 3302 } else if (Tok.is(AsmToken::Hash) || 3303 Tok.is(AsmToken::Dollar) || 3304 Tok.is(AsmToken::Integer)) { 3305 if (Parser.getTok().isNot(AsmToken::Integer)) 3306 Parser.Lex(); // Eat the '#'. 3307 SMLoc Loc = Parser.getTok().getLoc(); 3308 3309 const MCExpr *MemBarrierID; 3310 if (getParser().ParseExpression(MemBarrierID)) { 3311 Error(Loc, "illegal expression"); 3312 return MatchOperand_ParseFail; 3313 } 3314 3315 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID); 3316 if (!CE) { 3317 Error(Loc, "constant expression expected"); 3318 return MatchOperand_ParseFail; 3319 } 3320 3321 int Val = CE->getValue(); 3322 if (Val & ~0xf) { 3323 Error(Loc, "immediate value out of range"); 3324 return MatchOperand_ParseFail; 3325 } 3326 3327 Opt = ARM_MB::RESERVED_0 + Val; 3328 } else 3329 return MatchOperand_ParseFail; 3330 3331 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S)); 3332 return MatchOperand_Success; 3333} 3334 3335/// parseProcIFlagsOperand - Try to parse iflags from CPS instruction. 3336ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3337parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3338 SMLoc S = Parser.getTok().getLoc(); 3339 const AsmToken &Tok = Parser.getTok(); 3340 if (!Tok.is(AsmToken::Identifier)) 3341 return MatchOperand_NoMatch; 3342 StringRef IFlagsStr = Tok.getString(); 3343 3344 // An iflags string of "none" is interpreted to mean that none of the AIF 3345 // bits are set. Not a terribly useful instruction, but a valid encoding. 3346 unsigned IFlags = 0; 3347 if (IFlagsStr != "none") { 3348 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) { 3349 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1)) 3350 .Case("a", ARM_PROC::A) 3351 .Case("i", ARM_PROC::I) 3352 .Case("f", ARM_PROC::F) 3353 .Default(~0U); 3354 3355 // If some specific iflag is already set, it means that some letter is 3356 // present more than once, this is not acceptable. 3357 if (Flag == ~0U || (IFlags & Flag)) 3358 return MatchOperand_NoMatch; 3359 3360 IFlags |= Flag; 3361 } 3362 } 3363 3364 Parser.Lex(); // Eat identifier token. 3365 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S)); 3366 return MatchOperand_Success; 3367} 3368 3369/// parseMSRMaskOperand - Try to parse mask flags from MSR instruction. 3370ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3371parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3372 SMLoc S = Parser.getTok().getLoc(); 3373 const AsmToken &Tok = Parser.getTok(); 3374 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 3375 StringRef Mask = Tok.getString(); 3376 3377 if (isMClass()) { 3378 // See ARMv6-M 10.1.1 3379 std::string Name = Mask.lower(); 3380 unsigned FlagsVal = StringSwitch<unsigned>(Name) 3381 // Note: in the documentation: 3382 // ARM deprecates using MSR APSR without a _<bits> qualifier as an alias 3383 // for MSR APSR_nzcvq. 3384 // but we do make it an alias here. This is so to get the "mask encoding" 3385 // bits correct on MSR APSR writes. 3386 // 3387 // FIXME: Note the 0xc00 "mask encoding" bits version of the registers 3388 // should really only be allowed when writing a special register. Note 3389 // they get dropped in the MRS instruction reading a special register as 3390 // the SYSm field is only 8 bits. 3391 // 3392 // FIXME: the _g and _nzcvqg versions are only allowed if the processor 3393 // includes the DSP extension but that is not checked. 3394 .Case("apsr", 0x800) 3395 .Case("apsr_nzcvq", 0x800) 3396 .Case("apsr_g", 0x400) 3397 .Case("apsr_nzcvqg", 0xc00) 3398 .Case("iapsr", 0x801) 3399 .Case("iapsr_nzcvq", 0x801) 3400 .Case("iapsr_g", 0x401) 3401 .Case("iapsr_nzcvqg", 0xc01) 3402 .Case("eapsr", 0x802) 3403 .Case("eapsr_nzcvq", 0x802) 3404 .Case("eapsr_g", 0x402) 3405 .Case("eapsr_nzcvqg", 0xc02) 3406 .Case("xpsr", 0x803) 3407 .Case("xpsr_nzcvq", 0x803) 3408 .Case("xpsr_g", 0x403) 3409 .Case("xpsr_nzcvqg", 0xc03) 3410 .Case("ipsr", 0x805) 3411 .Case("epsr", 0x806) 3412 .Case("iepsr", 0x807) 3413 .Case("msp", 0x808) 3414 .Case("psp", 0x809) 3415 .Case("primask", 0x810) 3416 .Case("basepri", 0x811) 3417 .Case("basepri_max", 0x812) 3418 .Case("faultmask", 0x813) 3419 .Case("control", 0x814) 3420 .Default(~0U); 3421 3422 if (FlagsVal == ~0U) 3423 return MatchOperand_NoMatch; 3424 3425 if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813) 3426 // basepri, basepri_max and faultmask only valid for V7m. 3427 return MatchOperand_NoMatch; 3428 3429 Parser.Lex(); // Eat identifier token. 3430 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); 3431 return MatchOperand_Success; 3432 } 3433 3434 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf" 3435 size_t Start = 0, Next = Mask.find('_'); 3436 StringRef Flags = ""; 3437 std::string SpecReg = Mask.slice(Start, Next).lower(); 3438 if (Next != StringRef::npos) 3439 Flags = Mask.slice(Next+1, Mask.size()); 3440 3441 // FlagsVal contains the complete mask: 3442 // 3-0: Mask 3443 // 4: Special Reg (cpsr, apsr => 0; spsr => 1) 3444 unsigned FlagsVal = 0; 3445 3446 if (SpecReg == "apsr") { 3447 FlagsVal = StringSwitch<unsigned>(Flags) 3448 .Case("nzcvq", 0x8) // same as CPSR_f 3449 .Case("g", 0x4) // same as CPSR_s 3450 .Case("nzcvqg", 0xc) // same as CPSR_fs 3451 .Default(~0U); 3452 3453 if (FlagsVal == ~0U) { 3454 if (!Flags.empty()) 3455 return MatchOperand_NoMatch; 3456 else 3457 FlagsVal = 8; // No flag 3458 } 3459 } else if (SpecReg == "cpsr" || SpecReg == "spsr") { 3460 // cpsr_all is an alias for cpsr_fc, as is plain cpsr. 3461 if (Flags == "all" || Flags == "") 3462 Flags = "fc"; 3463 for (int i = 0, e = Flags.size(); i != e; ++i) { 3464 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1)) 3465 .Case("c", 1) 3466 .Case("x", 2) 3467 .Case("s", 4) 3468 .Case("f", 8) 3469 .Default(~0U); 3470 3471 // If some specific flag is already set, it means that some letter is 3472 // present more than once, this is not acceptable. 3473 if (FlagsVal == ~0U || (FlagsVal & Flag)) 3474 return MatchOperand_NoMatch; 3475 FlagsVal |= Flag; 3476 } 3477 } else // No match for special register. 3478 return MatchOperand_NoMatch; 3479 3480 // Special register without flags is NOT equivalent to "fc" flags. 3481 // NOTE: This is a divergence from gas' behavior. Uncommenting the following 3482 // two lines would enable gas compatibility at the expense of breaking 3483 // round-tripping. 3484 // 3485 // if (!FlagsVal) 3486 // FlagsVal = 0x9; 3487 3488 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1) 3489 if (SpecReg == "spsr") 3490 FlagsVal |= 16; 3491 3492 Parser.Lex(); // Eat identifier token. 3493 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); 3494 return MatchOperand_Success; 3495} 3496 3497ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3498parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op, 3499 int Low, int High) { 3500 const AsmToken &Tok = Parser.getTok(); 3501 if (Tok.isNot(AsmToken::Identifier)) { 3502 Error(Parser.getTok().getLoc(), Op + " operand expected."); 3503 return MatchOperand_ParseFail; 3504 } 3505 StringRef ShiftName = Tok.getString(); 3506 std::string LowerOp = Op.lower(); 3507 std::string UpperOp = Op.upper(); 3508 if (ShiftName != LowerOp && ShiftName != UpperOp) { 3509 Error(Parser.getTok().getLoc(), Op + " operand expected."); 3510 return MatchOperand_ParseFail; 3511 } 3512 Parser.Lex(); // Eat shift type token. 3513 3514 // There must be a '#' and a shift amount. 3515 if (Parser.getTok().isNot(AsmToken::Hash) && 3516 Parser.getTok().isNot(AsmToken::Dollar)) { 3517 Error(Parser.getTok().getLoc(), "'#' expected"); 3518 return MatchOperand_ParseFail; 3519 } 3520 Parser.Lex(); // Eat hash token. 3521 3522 const MCExpr *ShiftAmount; 3523 SMLoc Loc = Parser.getTok().getLoc(); 3524 if (getParser().ParseExpression(ShiftAmount)) { 3525 Error(Loc, "illegal expression"); 3526 return MatchOperand_ParseFail; 3527 } 3528 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 3529 if (!CE) { 3530 Error(Loc, "constant expression expected"); 3531 return MatchOperand_ParseFail; 3532 } 3533 int Val = CE->getValue(); 3534 if (Val < Low || Val > High) { 3535 Error(Loc, "immediate value out of range"); 3536 return MatchOperand_ParseFail; 3537 } 3538 3539 Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc())); 3540 3541 return MatchOperand_Success; 3542} 3543 3544ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3545parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3546 const AsmToken &Tok = Parser.getTok(); 3547 SMLoc S = Tok.getLoc(); 3548 if (Tok.isNot(AsmToken::Identifier)) { 3549 Error(Tok.getLoc(), "'be' or 'le' operand expected"); 3550 return MatchOperand_ParseFail; 3551 } 3552 int Val = StringSwitch<int>(Tok.getString()) 3553 .Case("be", 1) 3554 .Case("le", 0) 3555 .Default(-1); 3556 Parser.Lex(); // Eat the token. 3557 3558 if (Val == -1) { 3559 Error(Tok.getLoc(), "'be' or 'le' operand expected"); 3560 return MatchOperand_ParseFail; 3561 } 3562 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val, 3563 getContext()), 3564 S, Parser.getTok().getLoc())); 3565 return MatchOperand_Success; 3566} 3567 3568/// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT 3569/// instructions. Legal values are: 3570/// lsl #n 'n' in [0,31] 3571/// asr #n 'n' in [1,32] 3572/// n == 32 encoded as n == 0. 3573ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3574parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3575 const AsmToken &Tok = Parser.getTok(); 3576 SMLoc S = Tok.getLoc(); 3577 if (Tok.isNot(AsmToken::Identifier)) { 3578 Error(S, "shift operator 'asr' or 'lsl' expected"); 3579 return MatchOperand_ParseFail; 3580 } 3581 StringRef ShiftName = Tok.getString(); 3582 bool isASR; 3583 if (ShiftName == "lsl" || ShiftName == "LSL") 3584 isASR = false; 3585 else if (ShiftName == "asr" || ShiftName == "ASR") 3586 isASR = true; 3587 else { 3588 Error(S, "shift operator 'asr' or 'lsl' expected"); 3589 return MatchOperand_ParseFail; 3590 } 3591 Parser.Lex(); // Eat the operator. 3592 3593 // A '#' and a shift amount. 3594 if (Parser.getTok().isNot(AsmToken::Hash) && 3595 Parser.getTok().isNot(AsmToken::Dollar)) { 3596 Error(Parser.getTok().getLoc(), "'#' expected"); 3597 return MatchOperand_ParseFail; 3598 } 3599 Parser.Lex(); // Eat hash token. 3600 3601 const MCExpr *ShiftAmount; 3602 SMLoc E = Parser.getTok().getLoc(); 3603 if (getParser().ParseExpression(ShiftAmount)) { 3604 Error(E, "malformed shift expression"); 3605 return MatchOperand_ParseFail; 3606 } 3607 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 3608 if (!CE) { 3609 Error(E, "shift amount must be an immediate"); 3610 return MatchOperand_ParseFail; 3611 } 3612 3613 int64_t Val = CE->getValue(); 3614 if (isASR) { 3615 // Shift amount must be in [1,32] 3616 if (Val < 1 || Val > 32) { 3617 Error(E, "'asr' shift amount must be in range [1,32]"); 3618 return MatchOperand_ParseFail; 3619 } 3620 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode. 3621 if (isThumb() && Val == 32) { 3622 Error(E, "'asr #32' shift amount not allowed in Thumb mode"); 3623 return MatchOperand_ParseFail; 3624 } 3625 if (Val == 32) Val = 0; 3626 } else { 3627 // Shift amount must be in [1,32] 3628 if (Val < 0 || Val > 31) { 3629 Error(E, "'lsr' shift amount must be in range [0,31]"); 3630 return MatchOperand_ParseFail; 3631 } 3632 } 3633 3634 E = Parser.getTok().getLoc(); 3635 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E)); 3636 3637 return MatchOperand_Success; 3638} 3639 3640/// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family 3641/// of instructions. Legal values are: 3642/// ror #n 'n' in {0, 8, 16, 24} 3643ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3644parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3645 const AsmToken &Tok = Parser.getTok(); 3646 SMLoc S = Tok.getLoc(); 3647 if (Tok.isNot(AsmToken::Identifier)) 3648 return MatchOperand_NoMatch; 3649 StringRef ShiftName = Tok.getString(); 3650 if (ShiftName != "ror" && ShiftName != "ROR") 3651 return MatchOperand_NoMatch; 3652 Parser.Lex(); // Eat the operator. 3653 3654 // A '#' and a rotate amount. 3655 if (Parser.getTok().isNot(AsmToken::Hash) && 3656 Parser.getTok().isNot(AsmToken::Dollar)) { 3657 Error(Parser.getTok().getLoc(), "'#' expected"); 3658 return MatchOperand_ParseFail; 3659 } 3660 Parser.Lex(); // Eat hash token. 3661 3662 const MCExpr *ShiftAmount; 3663 SMLoc E = Parser.getTok().getLoc(); 3664 if (getParser().ParseExpression(ShiftAmount)) { 3665 Error(E, "malformed rotate expression"); 3666 return MatchOperand_ParseFail; 3667 } 3668 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 3669 if (!CE) { 3670 Error(E, "rotate amount must be an immediate"); 3671 return MatchOperand_ParseFail; 3672 } 3673 3674 int64_t Val = CE->getValue(); 3675 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension) 3676 // normally, zero is represented in asm by omitting the rotate operand 3677 // entirely. 3678 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) { 3679 Error(E, "'ror' rotate amount must be 8, 16, or 24"); 3680 return MatchOperand_ParseFail; 3681 } 3682 3683 E = Parser.getTok().getLoc(); 3684 Operands.push_back(ARMOperand::CreateRotImm(Val, S, E)); 3685 3686 return MatchOperand_Success; 3687} 3688 3689ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3690parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3691 SMLoc S = Parser.getTok().getLoc(); 3692 // The bitfield descriptor is really two operands, the LSB and the width. 3693 if (Parser.getTok().isNot(AsmToken::Hash) && 3694 Parser.getTok().isNot(AsmToken::Dollar)) { 3695 Error(Parser.getTok().getLoc(), "'#' expected"); 3696 return MatchOperand_ParseFail; 3697 } 3698 Parser.Lex(); // Eat hash token. 3699 3700 const MCExpr *LSBExpr; 3701 SMLoc E = Parser.getTok().getLoc(); 3702 if (getParser().ParseExpression(LSBExpr)) { 3703 Error(E, "malformed immediate expression"); 3704 return MatchOperand_ParseFail; 3705 } 3706 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr); 3707 if (!CE) { 3708 Error(E, "'lsb' operand must be an immediate"); 3709 return MatchOperand_ParseFail; 3710 } 3711 3712 int64_t LSB = CE->getValue(); 3713 // The LSB must be in the range [0,31] 3714 if (LSB < 0 || LSB > 31) { 3715 Error(E, "'lsb' operand must be in the range [0,31]"); 3716 return MatchOperand_ParseFail; 3717 } 3718 E = Parser.getTok().getLoc(); 3719 3720 // Expect another immediate operand. 3721 if (Parser.getTok().isNot(AsmToken::Comma)) { 3722 Error(Parser.getTok().getLoc(), "too few operands"); 3723 return MatchOperand_ParseFail; 3724 } 3725 Parser.Lex(); // Eat hash token. 3726 if (Parser.getTok().isNot(AsmToken::Hash) && 3727 Parser.getTok().isNot(AsmToken::Dollar)) { 3728 Error(Parser.getTok().getLoc(), "'#' expected"); 3729 return MatchOperand_ParseFail; 3730 } 3731 Parser.Lex(); // Eat hash token. 3732 3733 const MCExpr *WidthExpr; 3734 if (getParser().ParseExpression(WidthExpr)) { 3735 Error(E, "malformed immediate expression"); 3736 return MatchOperand_ParseFail; 3737 } 3738 CE = dyn_cast<MCConstantExpr>(WidthExpr); 3739 if (!CE) { 3740 Error(E, "'width' operand must be an immediate"); 3741 return MatchOperand_ParseFail; 3742 } 3743 3744 int64_t Width = CE->getValue(); 3745 // The LSB must be in the range [1,32-lsb] 3746 if (Width < 1 || Width > 32 - LSB) { 3747 Error(E, "'width' operand must be in the range [1,32-lsb]"); 3748 return MatchOperand_ParseFail; 3749 } 3750 E = Parser.getTok().getLoc(); 3751 3752 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E)); 3753 3754 return MatchOperand_Success; 3755} 3756 3757ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3758parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3759 // Check for a post-index addressing register operand. Specifically: 3760 // postidx_reg := '+' register {, shift} 3761 // | '-' register {, shift} 3762 // | register {, shift} 3763 3764 // This method must return MatchOperand_NoMatch without consuming any tokens 3765 // in the case where there is no match, as other alternatives take other 3766 // parse methods. 3767 AsmToken Tok = Parser.getTok(); 3768 SMLoc S = Tok.getLoc(); 3769 bool haveEaten = false; 3770 bool isAdd = true; 3771 int Reg = -1; 3772 if (Tok.is(AsmToken::Plus)) { 3773 Parser.Lex(); // Eat the '+' token. 3774 haveEaten = true; 3775 } else if (Tok.is(AsmToken::Minus)) { 3776 Parser.Lex(); // Eat the '-' token. 3777 isAdd = false; 3778 haveEaten = true; 3779 } 3780 if (Parser.getTok().is(AsmToken::Identifier)) 3781 Reg = tryParseRegister(); 3782 if (Reg == -1) { 3783 if (!haveEaten) 3784 return MatchOperand_NoMatch; 3785 Error(Parser.getTok().getLoc(), "register expected"); 3786 return MatchOperand_ParseFail; 3787 } 3788 SMLoc E = Parser.getTok().getLoc(); 3789 3790 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift; 3791 unsigned ShiftImm = 0; 3792 if (Parser.getTok().is(AsmToken::Comma)) { 3793 Parser.Lex(); // Eat the ','. 3794 if (parseMemRegOffsetShift(ShiftTy, ShiftImm)) 3795 return MatchOperand_ParseFail; 3796 } 3797 3798 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy, 3799 ShiftImm, S, E)); 3800 3801 return MatchOperand_Success; 3802} 3803 3804ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3805parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3806 // Check for a post-index addressing register operand. Specifically: 3807 // am3offset := '+' register 3808 // | '-' register 3809 // | register 3810 // | # imm 3811 // | # + imm 3812 // | # - imm 3813 3814 // This method must return MatchOperand_NoMatch without consuming any tokens 3815 // in the case where there is no match, as other alternatives take other 3816 // parse methods. 3817 AsmToken Tok = Parser.getTok(); 3818 SMLoc S = Tok.getLoc(); 3819 3820 // Do immediates first, as we always parse those if we have a '#'. 3821 if (Parser.getTok().is(AsmToken::Hash) || 3822 Parser.getTok().is(AsmToken::Dollar)) { 3823 Parser.Lex(); // Eat the '#'. 3824 // Explicitly look for a '-', as we need to encode negative zero 3825 // differently. 3826 bool isNegative = Parser.getTok().is(AsmToken::Minus); 3827 const MCExpr *Offset; 3828 if (getParser().ParseExpression(Offset)) 3829 return MatchOperand_ParseFail; 3830 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset); 3831 if (!CE) { 3832 Error(S, "constant expression expected"); 3833 return MatchOperand_ParseFail; 3834 } 3835 SMLoc E = Tok.getLoc(); 3836 // Negative zero is encoded as the flag value INT32_MIN. 3837 int32_t Val = CE->getValue(); 3838 if (isNegative && Val == 0) 3839 Val = INT32_MIN; 3840 3841 Operands.push_back( 3842 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E)); 3843 3844 return MatchOperand_Success; 3845 } 3846 3847 3848 bool haveEaten = false; 3849 bool isAdd = true; 3850 int Reg = -1; 3851 if (Tok.is(AsmToken::Plus)) { 3852 Parser.Lex(); // Eat the '+' token. 3853 haveEaten = true; 3854 } else if (Tok.is(AsmToken::Minus)) { 3855 Parser.Lex(); // Eat the '-' token. 3856 isAdd = false; 3857 haveEaten = true; 3858 } 3859 if (Parser.getTok().is(AsmToken::Identifier)) 3860 Reg = tryParseRegister(); 3861 if (Reg == -1) { 3862 if (!haveEaten) 3863 return MatchOperand_NoMatch; 3864 Error(Parser.getTok().getLoc(), "register expected"); 3865 return MatchOperand_ParseFail; 3866 } 3867 SMLoc E = Parser.getTok().getLoc(); 3868 3869 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift, 3870 0, S, E)); 3871 3872 return MatchOperand_Success; 3873} 3874 3875/// cvtT2LdrdPre - Convert parsed operands to MCInst. 3876/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3877/// when they refer multiple MIOperands inside a single one. 3878void ARMAsmParser:: 3879cvtT2LdrdPre(MCInst &Inst, 3880 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3881 // Rt, Rt2 3882 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3883 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 3884 // Create a writeback register dummy placeholder. 3885 Inst.addOperand(MCOperand::CreateReg(0)); 3886 // addr 3887 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2); 3888 // pred 3889 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3890} 3891 3892/// cvtT2StrdPre - Convert parsed operands to MCInst. 3893/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3894/// when they refer multiple MIOperands inside a single one. 3895void ARMAsmParser:: 3896cvtT2StrdPre(MCInst &Inst, 3897 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3898 // Create a writeback register dummy placeholder. 3899 Inst.addOperand(MCOperand::CreateReg(0)); 3900 // Rt, Rt2 3901 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3902 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 3903 // addr 3904 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2); 3905 // pred 3906 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3907} 3908 3909/// cvtLdWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst. 3910/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3911/// when they refer multiple MIOperands inside a single one. 3912void ARMAsmParser:: 3913cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, 3914 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3915 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3916 3917 // Create a writeback register dummy placeholder. 3918 Inst.addOperand(MCOperand::CreateImm(0)); 3919 3920 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2); 3921 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3922} 3923 3924/// cvtStWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst. 3925/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3926/// when they refer multiple MIOperands inside a single one. 3927void ARMAsmParser:: 3928cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, 3929 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3930 // Create a writeback register dummy placeholder. 3931 Inst.addOperand(MCOperand::CreateImm(0)); 3932 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3933 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2); 3934 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3935} 3936 3937/// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst. 3938/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3939/// when they refer multiple MIOperands inside a single one. 3940void ARMAsmParser:: 3941cvtLdWriteBackRegAddrMode2(MCInst &Inst, 3942 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3943 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3944 3945 // Create a writeback register dummy placeholder. 3946 Inst.addOperand(MCOperand::CreateImm(0)); 3947 3948 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3); 3949 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3950} 3951 3952/// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst. 3953/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3954/// when they refer multiple MIOperands inside a single one. 3955void ARMAsmParser:: 3956cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, 3957 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3958 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3959 3960 // Create a writeback register dummy placeholder. 3961 Inst.addOperand(MCOperand::CreateImm(0)); 3962 3963 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2); 3964 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3965} 3966 3967 3968/// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst. 3969/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3970/// when they refer multiple MIOperands inside a single one. 3971void ARMAsmParser:: 3972cvtStWriteBackRegAddrModeImm12(MCInst &Inst, 3973 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3974 // Create a writeback register dummy placeholder. 3975 Inst.addOperand(MCOperand::CreateImm(0)); 3976 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3977 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2); 3978 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3979} 3980 3981/// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst. 3982/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3983/// when they refer multiple MIOperands inside a single one. 3984void ARMAsmParser:: 3985cvtStWriteBackRegAddrMode2(MCInst &Inst, 3986 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3987 // Create a writeback register dummy placeholder. 3988 Inst.addOperand(MCOperand::CreateImm(0)); 3989 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3990 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3); 3991 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3992} 3993 3994/// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst. 3995/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3996/// when they refer multiple MIOperands inside a single one. 3997void ARMAsmParser:: 3998cvtStWriteBackRegAddrMode3(MCInst &Inst, 3999 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4000 // Create a writeback register dummy placeholder. 4001 Inst.addOperand(MCOperand::CreateImm(0)); 4002 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4003 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3); 4004 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4005} 4006 4007/// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst. 4008/// Needed here because the Asm Gen Matcher can't handle properly tied operands 4009/// when they refer multiple MIOperands inside a single one. 4010void ARMAsmParser:: 4011cvtLdExtTWriteBackImm(MCInst &Inst, 4012 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4013 // Rt 4014 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4015 // Create a writeback register dummy placeholder. 4016 Inst.addOperand(MCOperand::CreateImm(0)); 4017 // addr 4018 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 4019 // offset 4020 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1); 4021 // pred 4022 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4023} 4024 4025/// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst. 4026/// Needed here because the Asm Gen Matcher can't handle properly tied operands 4027/// when they refer multiple MIOperands inside a single one. 4028void ARMAsmParser:: 4029cvtLdExtTWriteBackReg(MCInst &Inst, 4030 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4031 // Rt 4032 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4033 // Create a writeback register dummy placeholder. 4034 Inst.addOperand(MCOperand::CreateImm(0)); 4035 // addr 4036 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 4037 // offset 4038 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2); 4039 // pred 4040 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4041} 4042 4043/// cvtStExtTWriteBackImm - Convert parsed operands to MCInst. 4044/// Needed here because the Asm Gen Matcher can't handle properly tied operands 4045/// when they refer multiple MIOperands inside a single one. 4046void ARMAsmParser:: 4047cvtStExtTWriteBackImm(MCInst &Inst, 4048 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4049 // Create a writeback register dummy placeholder. 4050 Inst.addOperand(MCOperand::CreateImm(0)); 4051 // Rt 4052 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4053 // addr 4054 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 4055 // offset 4056 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1); 4057 // pred 4058 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4059} 4060 4061/// cvtStExtTWriteBackReg - Convert parsed operands to MCInst. 4062/// Needed here because the Asm Gen Matcher can't handle properly tied operands 4063/// when they refer multiple MIOperands inside a single one. 4064void ARMAsmParser:: 4065cvtStExtTWriteBackReg(MCInst &Inst, 4066 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4067 // Create a writeback register dummy placeholder. 4068 Inst.addOperand(MCOperand::CreateImm(0)); 4069 // Rt 4070 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4071 // addr 4072 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 4073 // offset 4074 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2); 4075 // pred 4076 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4077} 4078 4079/// cvtLdrdPre - Convert parsed operands to MCInst. 4080/// Needed here because the Asm Gen Matcher can't handle properly tied operands 4081/// when they refer multiple MIOperands inside a single one. 4082void ARMAsmParser:: 4083cvtLdrdPre(MCInst &Inst, 4084 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4085 // Rt, Rt2 4086 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4087 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 4088 // Create a writeback register dummy placeholder. 4089 Inst.addOperand(MCOperand::CreateImm(0)); 4090 // addr 4091 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3); 4092 // pred 4093 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4094} 4095 4096/// cvtStrdPre - Convert parsed operands to MCInst. 4097/// Needed here because the Asm Gen Matcher can't handle properly tied operands 4098/// when they refer multiple MIOperands inside a single one. 4099void ARMAsmParser:: 4100cvtStrdPre(MCInst &Inst, 4101 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4102 // Create a writeback register dummy placeholder. 4103 Inst.addOperand(MCOperand::CreateImm(0)); 4104 // Rt, Rt2 4105 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4106 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 4107 // addr 4108 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3); 4109 // pred 4110 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4111} 4112 4113/// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst. 4114/// Needed here because the Asm Gen Matcher can't handle properly tied operands 4115/// when they refer multiple MIOperands inside a single one. 4116void ARMAsmParser:: 4117cvtLdWriteBackRegAddrMode3(MCInst &Inst, 4118 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4119 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4120 // Create a writeback register dummy placeholder. 4121 Inst.addOperand(MCOperand::CreateImm(0)); 4122 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3); 4123 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4124} 4125 4126/// cvtThumbMultiply - Convert parsed operands to MCInst. 4127/// Needed here because the Asm Gen Matcher can't handle properly tied operands 4128/// when they refer multiple MIOperands inside a single one. 4129void ARMAsmParser:: 4130cvtThumbMultiply(MCInst &Inst, 4131 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4132 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 4133 ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1); 4134 // If we have a three-operand form, make sure to set Rn to be the operand 4135 // that isn't the same as Rd. 4136 unsigned RegOp = 4; 4137 if (Operands.size() == 6 && 4138 ((ARMOperand*)Operands[4])->getReg() == 4139 ((ARMOperand*)Operands[3])->getReg()) 4140 RegOp = 5; 4141 ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1); 4142 Inst.addOperand(Inst.getOperand(0)); 4143 ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2); 4144} 4145 4146void ARMAsmParser:: 4147cvtVLDwbFixed(MCInst &Inst, 4148 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4149 // Vd 4150 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1); 4151 // Create a writeback register dummy placeholder. 4152 Inst.addOperand(MCOperand::CreateImm(0)); 4153 // Vn 4154 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2); 4155 // pred 4156 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4157} 4158 4159void ARMAsmParser:: 4160cvtVLDwbRegister(MCInst &Inst, 4161 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4162 // Vd 4163 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1); 4164 // Create a writeback register dummy placeholder. 4165 Inst.addOperand(MCOperand::CreateImm(0)); 4166 // Vn 4167 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2); 4168 // Vm 4169 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1); 4170 // pred 4171 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4172} 4173 4174void ARMAsmParser:: 4175cvtVSTwbFixed(MCInst &Inst, 4176 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4177 // Create a writeback register dummy placeholder. 4178 Inst.addOperand(MCOperand::CreateImm(0)); 4179 // Vn 4180 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2); 4181 // Vt 4182 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1); 4183 // pred 4184 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4185} 4186 4187void ARMAsmParser:: 4188cvtVSTwbRegister(MCInst &Inst, 4189 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4190 // Create a writeback register dummy placeholder. 4191 Inst.addOperand(MCOperand::CreateImm(0)); 4192 // Vn 4193 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2); 4194 // Vm 4195 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1); 4196 // Vt 4197 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1); 4198 // pred 4199 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4200} 4201 4202/// Parse an ARM memory expression, return false if successful else return true 4203/// or an error. The first token must be a '[' when called. 4204bool ARMAsmParser:: 4205parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4206 SMLoc S, E; 4207 assert(Parser.getTok().is(AsmToken::LBrac) && 4208 "Token is not a Left Bracket"); 4209 S = Parser.getTok().getLoc(); 4210 Parser.Lex(); // Eat left bracket token. 4211 4212 const AsmToken &BaseRegTok = Parser.getTok(); 4213 int BaseRegNum = tryParseRegister(); 4214 if (BaseRegNum == -1) 4215 return Error(BaseRegTok.getLoc(), "register expected"); 4216 4217 // The next token must either be a comma or a closing bracket. 4218 const AsmToken &Tok = Parser.getTok(); 4219 if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac)) 4220 return Error(Tok.getLoc(), "malformed memory operand"); 4221 4222 if (Tok.is(AsmToken::RBrac)) { 4223 E = Tok.getLoc(); 4224 Parser.Lex(); // Eat right bracket token. 4225 4226 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift, 4227 0, 0, false, S, E)); 4228 4229 // If there's a pre-indexing writeback marker, '!', just add it as a token 4230 // operand. It's rather odd, but syntactically valid. 4231 if (Parser.getTok().is(AsmToken::Exclaim)) { 4232 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4233 Parser.Lex(); // Eat the '!'. 4234 } 4235 4236 return false; 4237 } 4238 4239 assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!"); 4240 Parser.Lex(); // Eat the comma. 4241 4242 // If we have a ':', it's an alignment specifier. 4243 if (Parser.getTok().is(AsmToken::Colon)) { 4244 Parser.Lex(); // Eat the ':'. 4245 E = Parser.getTok().getLoc(); 4246 4247 const MCExpr *Expr; 4248 if (getParser().ParseExpression(Expr)) 4249 return true; 4250 4251 // The expression has to be a constant. Memory references with relocations 4252 // don't come through here, as they use the <label> forms of the relevant 4253 // instructions. 4254 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 4255 if (!CE) 4256 return Error (E, "constant expression expected"); 4257 4258 unsigned Align = 0; 4259 switch (CE->getValue()) { 4260 default: 4261 return Error(E, 4262 "alignment specifier must be 16, 32, 64, 128, or 256 bits"); 4263 case 16: Align = 2; break; 4264 case 32: Align = 4; break; 4265 case 64: Align = 8; break; 4266 case 128: Align = 16; break; 4267 case 256: Align = 32; break; 4268 } 4269 4270 // Now we should have the closing ']' 4271 E = Parser.getTok().getLoc(); 4272 if (Parser.getTok().isNot(AsmToken::RBrac)) 4273 return Error(E, "']' expected"); 4274 Parser.Lex(); // Eat right bracket token. 4275 4276 // Don't worry about range checking the value here. That's handled by 4277 // the is*() predicates. 4278 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, 4279 ARM_AM::no_shift, 0, Align, 4280 false, S, E)); 4281 4282 // If there's a pre-indexing writeback marker, '!', just add it as a token 4283 // operand. 4284 if (Parser.getTok().is(AsmToken::Exclaim)) { 4285 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4286 Parser.Lex(); // Eat the '!'. 4287 } 4288 4289 return false; 4290 } 4291 4292 // If we have a '#', it's an immediate offset, else assume it's a register 4293 // offset. Be friendly and also accept a plain integer (without a leading 4294 // hash) for gas compatibility. 4295 if (Parser.getTok().is(AsmToken::Hash) || 4296 Parser.getTok().is(AsmToken::Dollar) || 4297 Parser.getTok().is(AsmToken::Integer)) { 4298 if (Parser.getTok().isNot(AsmToken::Integer)) 4299 Parser.Lex(); // Eat the '#'. 4300 E = Parser.getTok().getLoc(); 4301 4302 bool isNegative = getParser().getTok().is(AsmToken::Minus); 4303 const MCExpr *Offset; 4304 if (getParser().ParseExpression(Offset)) 4305 return true; 4306 4307 // The expression has to be a constant. Memory references with relocations 4308 // don't come through here, as they use the <label> forms of the relevant 4309 // instructions. 4310 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset); 4311 if (!CE) 4312 return Error (E, "constant expression expected"); 4313 4314 // If the constant was #-0, represent it as INT32_MIN. 4315 int32_t Val = CE->getValue(); 4316 if (isNegative && Val == 0) 4317 CE = MCConstantExpr::Create(INT32_MIN, getContext()); 4318 4319 // Now we should have the closing ']' 4320 E = Parser.getTok().getLoc(); 4321 if (Parser.getTok().isNot(AsmToken::RBrac)) 4322 return Error(E, "']' expected"); 4323 Parser.Lex(); // Eat right bracket token. 4324 4325 // Don't worry about range checking the value here. That's handled by 4326 // the is*() predicates. 4327 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0, 4328 ARM_AM::no_shift, 0, 0, 4329 false, S, E)); 4330 4331 // If there's a pre-indexing writeback marker, '!', just add it as a token 4332 // operand. 4333 if (Parser.getTok().is(AsmToken::Exclaim)) { 4334 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4335 Parser.Lex(); // Eat the '!'. 4336 } 4337 4338 return false; 4339 } 4340 4341 // The register offset is optionally preceded by a '+' or '-' 4342 bool isNegative = false; 4343 if (Parser.getTok().is(AsmToken::Minus)) { 4344 isNegative = true; 4345 Parser.Lex(); // Eat the '-'. 4346 } else if (Parser.getTok().is(AsmToken::Plus)) { 4347 // Nothing to do. 4348 Parser.Lex(); // Eat the '+'. 4349 } 4350 4351 E = Parser.getTok().getLoc(); 4352 int OffsetRegNum = tryParseRegister(); 4353 if (OffsetRegNum == -1) 4354 return Error(E, "register expected"); 4355 4356 // If there's a shift operator, handle it. 4357 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift; 4358 unsigned ShiftImm = 0; 4359 if (Parser.getTok().is(AsmToken::Comma)) { 4360 Parser.Lex(); // Eat the ','. 4361 if (parseMemRegOffsetShift(ShiftType, ShiftImm)) 4362 return true; 4363 } 4364 4365 // Now we should have the closing ']' 4366 E = Parser.getTok().getLoc(); 4367 if (Parser.getTok().isNot(AsmToken::RBrac)) 4368 return Error(E, "']' expected"); 4369 Parser.Lex(); // Eat right bracket token. 4370 4371 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum, 4372 ShiftType, ShiftImm, 0, isNegative, 4373 S, E)); 4374 4375 // If there's a pre-indexing writeback marker, '!', just add it as a token 4376 // operand. 4377 if (Parser.getTok().is(AsmToken::Exclaim)) { 4378 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4379 Parser.Lex(); // Eat the '!'. 4380 } 4381 4382 return false; 4383} 4384 4385/// parseMemRegOffsetShift - one of these two: 4386/// ( lsl | lsr | asr | ror ) , # shift_amount 4387/// rrx 4388/// return true if it parses a shift otherwise it returns false. 4389bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St, 4390 unsigned &Amount) { 4391 SMLoc Loc = Parser.getTok().getLoc(); 4392 const AsmToken &Tok = Parser.getTok(); 4393 if (Tok.isNot(AsmToken::Identifier)) 4394 return true; 4395 StringRef ShiftName = Tok.getString(); 4396 if (ShiftName == "lsl" || ShiftName == "LSL" || 4397 ShiftName == "asl" || ShiftName == "ASL") 4398 St = ARM_AM::lsl; 4399 else if (ShiftName == "lsr" || ShiftName == "LSR") 4400 St = ARM_AM::lsr; 4401 else if (ShiftName == "asr" || ShiftName == "ASR") 4402 St = ARM_AM::asr; 4403 else if (ShiftName == "ror" || ShiftName == "ROR") 4404 St = ARM_AM::ror; 4405 else if (ShiftName == "rrx" || ShiftName == "RRX") 4406 St = ARM_AM::rrx; 4407 else 4408 return Error(Loc, "illegal shift operator"); 4409 Parser.Lex(); // Eat shift type token. 4410 4411 // rrx stands alone. 4412 Amount = 0; 4413 if (St != ARM_AM::rrx) { 4414 Loc = Parser.getTok().getLoc(); 4415 // A '#' and a shift amount. 4416 const AsmToken &HashTok = Parser.getTok(); 4417 if (HashTok.isNot(AsmToken::Hash) && 4418 HashTok.isNot(AsmToken::Dollar)) 4419 return Error(HashTok.getLoc(), "'#' expected"); 4420 Parser.Lex(); // Eat hash token. 4421 4422 const MCExpr *Expr; 4423 if (getParser().ParseExpression(Expr)) 4424 return true; 4425 // Range check the immediate. 4426 // lsl, ror: 0 <= imm <= 31 4427 // lsr, asr: 0 <= imm <= 32 4428 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 4429 if (!CE) 4430 return Error(Loc, "shift amount must be an immediate"); 4431 int64_t Imm = CE->getValue(); 4432 if (Imm < 0 || 4433 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) || 4434 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32)) 4435 return Error(Loc, "immediate shift value out of range"); 4436 Amount = Imm; 4437 } 4438 4439 return false; 4440} 4441 4442/// parseFPImm - A floating point immediate expression operand. 4443ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 4444parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4445 // Anything that can accept a floating point constant as an operand 4446 // needs to go through here, as the regular ParseExpression is 4447 // integer only. 4448 // 4449 // This routine still creates a generic Immediate operand, containing 4450 // a bitcast of the 64-bit floating point value. The various operands 4451 // that accept floats can check whether the value is valid for them 4452 // via the standard is*() predicates. 4453 4454 SMLoc S = Parser.getTok().getLoc(); 4455 4456 if (Parser.getTok().isNot(AsmToken::Hash) && 4457 Parser.getTok().isNot(AsmToken::Dollar)) 4458 return MatchOperand_NoMatch; 4459 4460 // Disambiguate the VMOV forms that can accept an FP immediate. 4461 // vmov.f32 <sreg>, #imm 4462 // vmov.f64 <dreg>, #imm 4463 // vmov.f32 <dreg>, #imm @ vector f32x2 4464 // vmov.f32 <qreg>, #imm @ vector f32x4 4465 // 4466 // There are also the NEON VMOV instructions which expect an 4467 // integer constant. Make sure we don't try to parse an FPImm 4468 // for these: 4469 // vmov.i{8|16|32|64} <dreg|qreg>, #imm 4470 ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]); 4471 if (!TyOp->isToken() || (TyOp->getToken() != ".f32" && 4472 TyOp->getToken() != ".f64")) 4473 return MatchOperand_NoMatch; 4474 4475 Parser.Lex(); // Eat the '#'. 4476 4477 // Handle negation, as that still comes through as a separate token. 4478 bool isNegative = false; 4479 if (Parser.getTok().is(AsmToken::Minus)) { 4480 isNegative = true; 4481 Parser.Lex(); 4482 } 4483 const AsmToken &Tok = Parser.getTok(); 4484 SMLoc Loc = Tok.getLoc(); 4485 if (Tok.is(AsmToken::Real)) { 4486 APFloat RealVal(APFloat::IEEEsingle, Tok.getString()); 4487 uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue(); 4488 // If we had a '-' in front, toggle the sign bit. 4489 IntVal ^= (uint64_t)isNegative << 31; 4490 Parser.Lex(); // Eat the token. 4491 Operands.push_back(ARMOperand::CreateImm( 4492 MCConstantExpr::Create(IntVal, getContext()), 4493 S, Parser.getTok().getLoc())); 4494 return MatchOperand_Success; 4495 } 4496 // Also handle plain integers. Instructions which allow floating point 4497 // immediates also allow a raw encoded 8-bit value. 4498 if (Tok.is(AsmToken::Integer)) { 4499 int64_t Val = Tok.getIntVal(); 4500 Parser.Lex(); // Eat the token. 4501 if (Val > 255 || Val < 0) { 4502 Error(Loc, "encoded floating point value out of range"); 4503 return MatchOperand_ParseFail; 4504 } 4505 double RealVal = ARM_AM::getFPImmFloat(Val); 4506 Val = APFloat(APFloat::IEEEdouble, RealVal).bitcastToAPInt().getZExtValue(); 4507 Operands.push_back(ARMOperand::CreateImm( 4508 MCConstantExpr::Create(Val, getContext()), S, 4509 Parser.getTok().getLoc())); 4510 return MatchOperand_Success; 4511 } 4512 4513 Error(Loc, "invalid floating point immediate"); 4514 return MatchOperand_ParseFail; 4515} 4516 4517/// Parse a arm instruction operand. For now this parses the operand regardless 4518/// of the mnemonic. 4519bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands, 4520 StringRef Mnemonic) { 4521 SMLoc S, E; 4522 4523 // Check if the current operand has a custom associated parser, if so, try to 4524 // custom parse the operand, or fallback to the general approach. 4525 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic); 4526 if (ResTy == MatchOperand_Success) 4527 return false; 4528 // If there wasn't a custom match, try the generic matcher below. Otherwise, 4529 // there was a match, but an error occurred, in which case, just return that 4530 // the operand parsing failed. 4531 if (ResTy == MatchOperand_ParseFail) 4532 return true; 4533 4534 switch (getLexer().getKind()) { 4535 default: 4536 Error(Parser.getTok().getLoc(), "unexpected token in operand"); 4537 return true; 4538 case AsmToken::Identifier: { 4539 if (!tryParseRegisterWithWriteBack(Operands)) 4540 return false; 4541 int Res = tryParseShiftRegister(Operands); 4542 if (Res == 0) // success 4543 return false; 4544 else if (Res == -1) // irrecoverable error 4545 return true; 4546 // If this is VMRS, check for the apsr_nzcv operand. 4547 if (Mnemonic == "vmrs" && 4548 Parser.getTok().getString().equals_lower("apsr_nzcv")) { 4549 S = Parser.getTok().getLoc(); 4550 Parser.Lex(); 4551 Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S)); 4552 return false; 4553 } 4554 4555 // Fall though for the Identifier case that is not a register or a 4556 // special name. 4557 } 4558 case AsmToken::LParen: // parenthesized expressions like (_strcmp-4) 4559 case AsmToken::Integer: // things like 1f and 2b as a branch targets 4560 case AsmToken::String: // quoted label names. 4561 case AsmToken::Dot: { // . as a branch target 4562 // This was not a register so parse other operands that start with an 4563 // identifier (like labels) as expressions and create them as immediates. 4564 const MCExpr *IdVal; 4565 S = Parser.getTok().getLoc(); 4566 if (getParser().ParseExpression(IdVal)) 4567 return true; 4568 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 4569 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E)); 4570 return false; 4571 } 4572 case AsmToken::LBrac: 4573 return parseMemory(Operands); 4574 case AsmToken::LCurly: 4575 return parseRegisterList(Operands); 4576 case AsmToken::Dollar: 4577 case AsmToken::Hash: { 4578 // #42 -> immediate. 4579 S = Parser.getTok().getLoc(); 4580 Parser.Lex(); 4581 4582 if (Parser.getTok().isNot(AsmToken::Colon)) { 4583 bool isNegative = Parser.getTok().is(AsmToken::Minus); 4584 const MCExpr *ImmVal; 4585 if (getParser().ParseExpression(ImmVal)) 4586 return true; 4587 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal); 4588 if (CE) { 4589 int32_t Val = CE->getValue(); 4590 if (isNegative && Val == 0) 4591 ImmVal = MCConstantExpr::Create(INT32_MIN, getContext()); 4592 } 4593 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 4594 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E)); 4595 return false; 4596 } 4597 // w/ a ':' after the '#', it's just like a plain ':'. 4598 // FALLTHROUGH 4599 } 4600 case AsmToken::Colon: { 4601 // ":lower16:" and ":upper16:" expression prefixes 4602 // FIXME: Check it's an expression prefix, 4603 // e.g. (FOO - :lower16:BAR) isn't legal. 4604 ARMMCExpr::VariantKind RefKind; 4605 if (parsePrefix(RefKind)) 4606 return true; 4607 4608 const MCExpr *SubExprVal; 4609 if (getParser().ParseExpression(SubExprVal)) 4610 return true; 4611 4612 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal, 4613 getContext()); 4614 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 4615 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E)); 4616 return false; 4617 } 4618 } 4619} 4620 4621// parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e. 4622// :lower16: and :upper16:. 4623bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) { 4624 RefKind = ARMMCExpr::VK_ARM_None; 4625 4626 // :lower16: and :upper16: modifiers 4627 assert(getLexer().is(AsmToken::Colon) && "expected a :"); 4628 Parser.Lex(); // Eat ':' 4629 4630 if (getLexer().isNot(AsmToken::Identifier)) { 4631 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand"); 4632 return true; 4633 } 4634 4635 StringRef IDVal = Parser.getTok().getIdentifier(); 4636 if (IDVal == "lower16") { 4637 RefKind = ARMMCExpr::VK_ARM_LO16; 4638 } else if (IDVal == "upper16") { 4639 RefKind = ARMMCExpr::VK_ARM_HI16; 4640 } else { 4641 Error(Parser.getTok().getLoc(), "unexpected prefix in operand"); 4642 return true; 4643 } 4644 Parser.Lex(); 4645 4646 if (getLexer().isNot(AsmToken::Colon)) { 4647 Error(Parser.getTok().getLoc(), "unexpected token after prefix"); 4648 return true; 4649 } 4650 Parser.Lex(); // Eat the last ':' 4651 return false; 4652} 4653 4654/// \brief Given a mnemonic, split out possible predication code and carry 4655/// setting letters to form a canonical mnemonic and flags. 4656// 4657// FIXME: Would be nice to autogen this. 4658// FIXME: This is a bit of a maze of special cases. 4659StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic, 4660 unsigned &PredicationCode, 4661 bool &CarrySetting, 4662 unsigned &ProcessorIMod, 4663 StringRef &ITMask) { 4664 PredicationCode = ARMCC::AL; 4665 CarrySetting = false; 4666 ProcessorIMod = 0; 4667 4668 // Ignore some mnemonics we know aren't predicated forms. 4669 // 4670 // FIXME: Would be nice to autogen this. 4671 if ((Mnemonic == "movs" && isThumb()) || 4672 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" || 4673 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" || 4674 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" || 4675 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" || 4676 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" || 4677 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" || 4678 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" || 4679 Mnemonic == "fmuls") 4680 return Mnemonic; 4681 4682 // First, split out any predication code. Ignore mnemonics we know aren't 4683 // predicated but do have a carry-set and so weren't caught above. 4684 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" && 4685 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" && 4686 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" && 4687 Mnemonic != "sbcs" && Mnemonic != "rscs") { 4688 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2)) 4689 .Case("eq", ARMCC::EQ) 4690 .Case("ne", ARMCC::NE) 4691 .Case("hs", ARMCC::HS) 4692 .Case("cs", ARMCC::HS) 4693 .Case("lo", ARMCC::LO) 4694 .Case("cc", ARMCC::LO) 4695 .Case("mi", ARMCC::MI) 4696 .Case("pl", ARMCC::PL) 4697 .Case("vs", ARMCC::VS) 4698 .Case("vc", ARMCC::VC) 4699 .Case("hi", ARMCC::HI) 4700 .Case("ls", ARMCC::LS) 4701 .Case("ge", ARMCC::GE) 4702 .Case("lt", ARMCC::LT) 4703 .Case("gt", ARMCC::GT) 4704 .Case("le", ARMCC::LE) 4705 .Case("al", ARMCC::AL) 4706 .Default(~0U); 4707 if (CC != ~0U) { 4708 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2); 4709 PredicationCode = CC; 4710 } 4711 } 4712 4713 // Next, determine if we have a carry setting bit. We explicitly ignore all 4714 // the instructions we know end in 's'. 4715 if (Mnemonic.endswith("s") && 4716 !(Mnemonic == "cps" || Mnemonic == "mls" || 4717 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" || 4718 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" || 4719 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" || 4720 Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" || 4721 Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" || 4722 Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" || 4723 Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" || 4724 Mnemonic == "vfms" || Mnemonic == "vfnms" || 4725 (Mnemonic == "movs" && isThumb()))) { 4726 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1); 4727 CarrySetting = true; 4728 } 4729 4730 // The "cps" instruction can have a interrupt mode operand which is glued into 4731 // the mnemonic. Check if this is the case, split it and parse the imod op 4732 if (Mnemonic.startswith("cps")) { 4733 // Split out any imod code. 4734 unsigned IMod = 4735 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2)) 4736 .Case("ie", ARM_PROC::IE) 4737 .Case("id", ARM_PROC::ID) 4738 .Default(~0U); 4739 if (IMod != ~0U) { 4740 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2); 4741 ProcessorIMod = IMod; 4742 } 4743 } 4744 4745 // The "it" instruction has the condition mask on the end of the mnemonic. 4746 if (Mnemonic.startswith("it")) { 4747 ITMask = Mnemonic.slice(2, Mnemonic.size()); 4748 Mnemonic = Mnemonic.slice(0, 2); 4749 } 4750 4751 return Mnemonic; 4752} 4753 4754/// \brief Given a canonical mnemonic, determine if the instruction ever allows 4755/// inclusion of carry set or predication code operands. 4756// 4757// FIXME: It would be nice to autogen this. 4758void ARMAsmParser:: 4759getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet, 4760 bool &CanAcceptPredicationCode) { 4761 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" || 4762 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" || 4763 Mnemonic == "add" || Mnemonic == "adc" || 4764 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" || 4765 Mnemonic == "orr" || Mnemonic == "mvn" || 4766 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" || 4767 Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" || 4768 Mnemonic == "vfm" || Mnemonic == "vfnm" || 4769 (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" || 4770 Mnemonic == "mla" || Mnemonic == "smlal" || 4771 Mnemonic == "umlal" || Mnemonic == "umull"))) { 4772 CanAcceptCarrySet = true; 4773 } else 4774 CanAcceptCarrySet = false; 4775 4776 if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" || 4777 Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" || 4778 Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" || 4779 Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" || 4780 Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "setend" || 4781 (Mnemonic == "clrex" && !isThumb()) || 4782 (Mnemonic == "nop" && isThumbOne()) || 4783 ((Mnemonic == "pld" || Mnemonic == "pli" || Mnemonic == "pldw" || 4784 Mnemonic == "ldc2" || Mnemonic == "ldc2l" || 4785 Mnemonic == "stc2" || Mnemonic == "stc2l") && !isThumb()) || 4786 ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs")) && 4787 !isThumb()) || 4788 Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumbOne())) { 4789 CanAcceptPredicationCode = false; 4790 } else 4791 CanAcceptPredicationCode = true; 4792 4793 if (isThumb()) { 4794 if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" || 4795 Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp") 4796 CanAcceptPredicationCode = false; 4797 } 4798} 4799 4800bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic, 4801 SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4802 // FIXME: This is all horribly hacky. We really need a better way to deal 4803 // with optional operands like this in the matcher table. 4804 4805 // The 'mov' mnemonic is special. One variant has a cc_out operand, while 4806 // another does not. Specifically, the MOVW instruction does not. So we 4807 // special case it here and remove the defaulted (non-setting) cc_out 4808 // operand if that's the instruction we're trying to match. 4809 // 4810 // We do this as post-processing of the explicit operands rather than just 4811 // conditionally adding the cc_out in the first place because we need 4812 // to check the type of the parsed immediate operand. 4813 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() && 4814 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() && 4815 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() && 4816 static_cast<ARMOperand*>(Operands[1])->getReg() == 0) 4817 return true; 4818 4819 // Register-register 'add' for thumb does not have a cc_out operand 4820 // when there are only two register operands. 4821 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 && 4822 static_cast<ARMOperand*>(Operands[3])->isReg() && 4823 static_cast<ARMOperand*>(Operands[4])->isReg() && 4824 static_cast<ARMOperand*>(Operands[1])->getReg() == 0) 4825 return true; 4826 // Register-register 'add' for thumb does not have a cc_out operand 4827 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do 4828 // have to check the immediate range here since Thumb2 has a variant 4829 // that can handle a different range and has a cc_out operand. 4830 if (((isThumb() && Mnemonic == "add") || 4831 (isThumbTwo() && Mnemonic == "sub")) && 4832 Operands.size() == 6 && 4833 static_cast<ARMOperand*>(Operands[3])->isReg() && 4834 static_cast<ARMOperand*>(Operands[4])->isReg() && 4835 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP && 4836 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 4837 ((Mnemonic == "add" &&static_cast<ARMOperand*>(Operands[5])->isReg()) || 4838 static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4())) 4839 return true; 4840 // For Thumb2, add/sub immediate does not have a cc_out operand for the 4841 // imm0_4095 variant. That's the least-preferred variant when 4842 // selecting via the generic "add" mnemonic, so to know that we 4843 // should remove the cc_out operand, we have to explicitly check that 4844 // it's not one of the other variants. Ugh. 4845 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") && 4846 Operands.size() == 6 && 4847 static_cast<ARMOperand*>(Operands[3])->isReg() && 4848 static_cast<ARMOperand*>(Operands[4])->isReg() && 4849 static_cast<ARMOperand*>(Operands[5])->isImm()) { 4850 // Nest conditions rather than one big 'if' statement for readability. 4851 // 4852 // If either register is a high reg, it's either one of the SP 4853 // variants (handled above) or a 32-bit encoding, so we just 4854 // check against T3. If the second register is the PC, this is an 4855 // alternate form of ADR, which uses encoding T4, so check for that too. 4856 if ((!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) || 4857 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg())) && 4858 static_cast<ARMOperand*>(Operands[4])->getReg() != ARM::PC && 4859 static_cast<ARMOperand*>(Operands[5])->isT2SOImm()) 4860 return false; 4861 // If both registers are low, we're in an IT block, and the immediate is 4862 // in range, we should use encoding T1 instead, which has a cc_out. 4863 if (inITBlock() && 4864 isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) && 4865 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) && 4866 static_cast<ARMOperand*>(Operands[5])->isImm0_7()) 4867 return false; 4868 4869 // Otherwise, we use encoding T4, which does not have a cc_out 4870 // operand. 4871 return true; 4872 } 4873 4874 // The thumb2 multiply instruction doesn't have a CCOut register, so 4875 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to 4876 // use the 16-bit encoding or not. 4877 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 && 4878 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 4879 static_cast<ARMOperand*>(Operands[3])->isReg() && 4880 static_cast<ARMOperand*>(Operands[4])->isReg() && 4881 static_cast<ARMOperand*>(Operands[5])->isReg() && 4882 // If the registers aren't low regs, the destination reg isn't the 4883 // same as one of the source regs, or the cc_out operand is zero 4884 // outside of an IT block, we have to use the 32-bit encoding, so 4885 // remove the cc_out operand. 4886 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) || 4887 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) || 4888 !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) || 4889 !inITBlock() || 4890 (static_cast<ARMOperand*>(Operands[3])->getReg() != 4891 static_cast<ARMOperand*>(Operands[5])->getReg() && 4892 static_cast<ARMOperand*>(Operands[3])->getReg() != 4893 static_cast<ARMOperand*>(Operands[4])->getReg()))) 4894 return true; 4895 4896 // Also check the 'mul' syntax variant that doesn't specify an explicit 4897 // destination register. 4898 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 && 4899 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 4900 static_cast<ARMOperand*>(Operands[3])->isReg() && 4901 static_cast<ARMOperand*>(Operands[4])->isReg() && 4902 // If the registers aren't low regs or the cc_out operand is zero 4903 // outside of an IT block, we have to use the 32-bit encoding, so 4904 // remove the cc_out operand. 4905 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) || 4906 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) || 4907 !inITBlock())) 4908 return true; 4909 4910 4911 4912 // Register-register 'add/sub' for thumb does not have a cc_out operand 4913 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also 4914 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't 4915 // right, this will result in better diagnostics (which operand is off) 4916 // anyway. 4917 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") && 4918 (Operands.size() == 5 || Operands.size() == 6) && 4919 static_cast<ARMOperand*>(Operands[3])->isReg() && 4920 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP && 4921 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 4922 (static_cast<ARMOperand*>(Operands[4])->isImm() || 4923 (Operands.size() == 6 && 4924 static_cast<ARMOperand*>(Operands[5])->isImm()))) 4925 return true; 4926 4927 return false; 4928} 4929 4930static bool isDataTypeToken(StringRef Tok) { 4931 return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" || 4932 Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" || 4933 Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" || 4934 Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" || 4935 Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" || 4936 Tok == ".f" || Tok == ".d"; 4937} 4938 4939// FIXME: This bit should probably be handled via an explicit match class 4940// in the .td files that matches the suffix instead of having it be 4941// a literal string token the way it is now. 4942static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) { 4943 return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm"); 4944} 4945 4946static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features); 4947/// Parse an arm instruction mnemonic followed by its operands. 4948bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc, 4949 SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4950 // Apply mnemonic aliases before doing anything else, as the destination 4951 // mnemnonic may include suffices and we want to handle them normally. 4952 // The generic tblgen'erated code does this later, at the start of 4953 // MatchInstructionImpl(), but that's too late for aliases that include 4954 // any sort of suffix. 4955 unsigned AvailableFeatures = getAvailableFeatures(); 4956 applyMnemonicAliases(Name, AvailableFeatures); 4957 4958 // First check for the ARM-specific .req directive. 4959 if (Parser.getTok().is(AsmToken::Identifier) && 4960 Parser.getTok().getIdentifier() == ".req") { 4961 parseDirectiveReq(Name, NameLoc); 4962 // We always return 'error' for this, as we're done with this 4963 // statement and don't need to match the 'instruction." 4964 return true; 4965 } 4966 4967 // Create the leading tokens for the mnemonic, split by '.' characters. 4968 size_t Start = 0, Next = Name.find('.'); 4969 StringRef Mnemonic = Name.slice(Start, Next); 4970 4971 // Split out the predication code and carry setting flag from the mnemonic. 4972 unsigned PredicationCode; 4973 unsigned ProcessorIMod; 4974 bool CarrySetting; 4975 StringRef ITMask; 4976 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting, 4977 ProcessorIMod, ITMask); 4978 4979 // In Thumb1, only the branch (B) instruction can be predicated. 4980 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") { 4981 Parser.EatToEndOfStatement(); 4982 return Error(NameLoc, "conditional execution not supported in Thumb1"); 4983 } 4984 4985 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc)); 4986 4987 // Handle the IT instruction ITMask. Convert it to a bitmask. This 4988 // is the mask as it will be for the IT encoding if the conditional 4989 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case 4990 // where the conditional bit0 is zero, the instruction post-processing 4991 // will adjust the mask accordingly. 4992 if (Mnemonic == "it") { 4993 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2); 4994 if (ITMask.size() > 3) { 4995 Parser.EatToEndOfStatement(); 4996 return Error(Loc, "too many conditions on IT instruction"); 4997 } 4998 unsigned Mask = 8; 4999 for (unsigned i = ITMask.size(); i != 0; --i) { 5000 char pos = ITMask[i - 1]; 5001 if (pos != 't' && pos != 'e') { 5002 Parser.EatToEndOfStatement(); 5003 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'"); 5004 } 5005 Mask >>= 1; 5006 if (ITMask[i - 1] == 't') 5007 Mask |= 8; 5008 } 5009 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc)); 5010 } 5011 5012 // FIXME: This is all a pretty gross hack. We should automatically handle 5013 // optional operands like this via tblgen. 5014 5015 // Next, add the CCOut and ConditionCode operands, if needed. 5016 // 5017 // For mnemonics which can ever incorporate a carry setting bit or predication 5018 // code, our matching model involves us always generating CCOut and 5019 // ConditionCode operands to match the mnemonic "as written" and then we let 5020 // the matcher deal with finding the right instruction or generating an 5021 // appropriate error. 5022 bool CanAcceptCarrySet, CanAcceptPredicationCode; 5023 getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode); 5024 5025 // If we had a carry-set on an instruction that can't do that, issue an 5026 // error. 5027 if (!CanAcceptCarrySet && CarrySetting) { 5028 Parser.EatToEndOfStatement(); 5029 return Error(NameLoc, "instruction '" + Mnemonic + 5030 "' can not set flags, but 's' suffix specified"); 5031 } 5032 // If we had a predication code on an instruction that can't do that, issue an 5033 // error. 5034 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) { 5035 Parser.EatToEndOfStatement(); 5036 return Error(NameLoc, "instruction '" + Mnemonic + 5037 "' is not predicable, but condition code specified"); 5038 } 5039 5040 // Add the carry setting operand, if necessary. 5041 if (CanAcceptCarrySet) { 5042 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size()); 5043 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0, 5044 Loc)); 5045 } 5046 5047 // Add the predication code operand, if necessary. 5048 if (CanAcceptPredicationCode) { 5049 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() + 5050 CarrySetting); 5051 Operands.push_back(ARMOperand::CreateCondCode( 5052 ARMCC::CondCodes(PredicationCode), Loc)); 5053 } 5054 5055 // Add the processor imod operand, if necessary. 5056 if (ProcessorIMod) { 5057 Operands.push_back(ARMOperand::CreateImm( 5058 MCConstantExpr::Create(ProcessorIMod, getContext()), 5059 NameLoc, NameLoc)); 5060 } 5061 5062 // Add the remaining tokens in the mnemonic. 5063 while (Next != StringRef::npos) { 5064 Start = Next; 5065 Next = Name.find('.', Start + 1); 5066 StringRef ExtraToken = Name.slice(Start, Next); 5067 5068 // Some NEON instructions have an optional datatype suffix that is 5069 // completely ignored. Check for that. 5070 if (isDataTypeToken(ExtraToken) && 5071 doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken)) 5072 continue; 5073 5074 if (ExtraToken != ".n") { 5075 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start); 5076 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc)); 5077 } 5078 } 5079 5080 // Read the remaining operands. 5081 if (getLexer().isNot(AsmToken::EndOfStatement)) { 5082 // Read the first operand. 5083 if (parseOperand(Operands, Mnemonic)) { 5084 Parser.EatToEndOfStatement(); 5085 return true; 5086 } 5087 5088 while (getLexer().is(AsmToken::Comma)) { 5089 Parser.Lex(); // Eat the comma. 5090 5091 // Parse and remember the operand. 5092 if (parseOperand(Operands, Mnemonic)) { 5093 Parser.EatToEndOfStatement(); 5094 return true; 5095 } 5096 } 5097 } 5098 5099 if (getLexer().isNot(AsmToken::EndOfStatement)) { 5100 SMLoc Loc = getLexer().getLoc(); 5101 Parser.EatToEndOfStatement(); 5102 return Error(Loc, "unexpected token in argument list"); 5103 } 5104 5105 Parser.Lex(); // Consume the EndOfStatement 5106 5107 // Some instructions, mostly Thumb, have forms for the same mnemonic that 5108 // do and don't have a cc_out optional-def operand. With some spot-checks 5109 // of the operand list, we can figure out which variant we're trying to 5110 // parse and adjust accordingly before actually matching. We shouldn't ever 5111 // try to remove a cc_out operand that was explicitly set on the the 5112 // mnemonic, of course (CarrySetting == true). Reason number #317 the 5113 // table driven matcher doesn't fit well with the ARM instruction set. 5114 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) { 5115 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]); 5116 Operands.erase(Operands.begin() + 1); 5117 delete Op; 5118 } 5119 5120 // ARM mode 'blx' need special handling, as the register operand version 5121 // is predicable, but the label operand version is not. So, we can't rely 5122 // on the Mnemonic based checking to correctly figure out when to put 5123 // a k_CondCode operand in the list. If we're trying to match the label 5124 // version, remove the k_CondCode operand here. 5125 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 && 5126 static_cast<ARMOperand*>(Operands[2])->isImm()) { 5127 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]); 5128 Operands.erase(Operands.begin() + 1); 5129 delete Op; 5130 } 5131 5132 // The vector-compare-to-zero instructions have a literal token "#0" at 5133 // the end that comes to here as an immediate operand. Convert it to a 5134 // token to play nicely with the matcher. 5135 if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" || 5136 Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 && 5137 static_cast<ARMOperand*>(Operands[5])->isImm()) { 5138 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]); 5139 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm()); 5140 if (CE && CE->getValue() == 0) { 5141 Operands.erase(Operands.begin() + 5); 5142 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc())); 5143 delete Op; 5144 } 5145 } 5146 // VCMP{E} does the same thing, but with a different operand count. 5147 if ((Mnemonic == "vcmp" || Mnemonic == "vcmpe") && Operands.size() == 5 && 5148 static_cast<ARMOperand*>(Operands[4])->isImm()) { 5149 ARMOperand *Op = static_cast<ARMOperand*>(Operands[4]); 5150 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm()); 5151 if (CE && CE->getValue() == 0) { 5152 Operands.erase(Operands.begin() + 4); 5153 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc())); 5154 delete Op; 5155 } 5156 } 5157 // Similarly, the Thumb1 "RSB" instruction has a literal "#0" on the 5158 // end. Convert it to a token here. Take care not to convert those 5159 // that should hit the Thumb2 encoding. 5160 if (Mnemonic == "rsb" && isThumb() && Operands.size() == 6 && 5161 static_cast<ARMOperand*>(Operands[3])->isReg() && 5162 static_cast<ARMOperand*>(Operands[4])->isReg() && 5163 static_cast<ARMOperand*>(Operands[5])->isImm()) { 5164 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]); 5165 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm()); 5166 if (CE && CE->getValue() == 0 && 5167 (isThumbOne() || 5168 // The cc_out operand matches the IT block. 5169 ((inITBlock() != CarrySetting) && 5170 // Neither register operand is a high register. 5171 (isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) && 5172 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()))))){ 5173 Operands.erase(Operands.begin() + 5); 5174 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc())); 5175 delete Op; 5176 } 5177 } 5178 5179 return false; 5180} 5181 5182// Validate context-sensitive operand constraints. 5183 5184// return 'true' if register list contains non-low GPR registers, 5185// 'false' otherwise. If Reg is in the register list or is HiReg, set 5186// 'containsReg' to true. 5187static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg, 5188 unsigned HiReg, bool &containsReg) { 5189 containsReg = false; 5190 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) { 5191 unsigned OpReg = Inst.getOperand(i).getReg(); 5192 if (OpReg == Reg) 5193 containsReg = true; 5194 // Anything other than a low register isn't legal here. 5195 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg)) 5196 return true; 5197 } 5198 return false; 5199} 5200 5201// Check if the specified regisgter is in the register list of the inst, 5202// starting at the indicated operand number. 5203static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) { 5204 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) { 5205 unsigned OpReg = Inst.getOperand(i).getReg(); 5206 if (OpReg == Reg) 5207 return true; 5208 } 5209 return false; 5210} 5211 5212// FIXME: We would really prefer to have MCInstrInfo (the wrapper around 5213// the ARMInsts array) instead. Getting that here requires awkward 5214// API changes, though. Better way? 5215namespace llvm { 5216extern const MCInstrDesc ARMInsts[]; 5217} 5218static const MCInstrDesc &getInstDesc(unsigned Opcode) { 5219 return ARMInsts[Opcode]; 5220} 5221 5222// FIXME: We would really like to be able to tablegen'erate this. 5223bool ARMAsmParser:: 5224validateInstruction(MCInst &Inst, 5225 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 5226 const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode()); 5227 SMLoc Loc = Operands[0]->getStartLoc(); 5228 // Check the IT block state first. 5229 // NOTE: BKPT instruction has the interesting property of being 5230 // allowed in IT blocks, but not being predicable. It just always 5231 // executes. 5232 if (inITBlock() && Inst.getOpcode() != ARM::tBKPT && 5233 Inst.getOpcode() != ARM::BKPT) { 5234 unsigned bit = 1; 5235 if (ITState.FirstCond) 5236 ITState.FirstCond = false; 5237 else 5238 bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1; 5239 // The instruction must be predicable. 5240 if (!MCID.isPredicable()) 5241 return Error(Loc, "instructions in IT block must be predicable"); 5242 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm(); 5243 unsigned ITCond = bit ? ITState.Cond : 5244 ARMCC::getOppositeCondition(ITState.Cond); 5245 if (Cond != ITCond) { 5246 // Find the condition code Operand to get its SMLoc information. 5247 SMLoc CondLoc; 5248 for (unsigned i = 1; i < Operands.size(); ++i) 5249 if (static_cast<ARMOperand*>(Operands[i])->isCondCode()) 5250 CondLoc = Operands[i]->getStartLoc(); 5251 return Error(CondLoc, "incorrect condition in IT block; got '" + 5252 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) + 5253 "', but expected '" + 5254 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'"); 5255 } 5256 // Check for non-'al' condition codes outside of the IT block. 5257 } else if (isThumbTwo() && MCID.isPredicable() && 5258 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() != 5259 ARMCC::AL && Inst.getOpcode() != ARM::tB && 5260 Inst.getOpcode() != ARM::t2B) 5261 return Error(Loc, "predicated instructions must be in IT block"); 5262 5263 switch (Inst.getOpcode()) { 5264 case ARM::LDRD: 5265 case ARM::LDRD_PRE: 5266 case ARM::LDRD_POST: 5267 case ARM::LDREXD: { 5268 // Rt2 must be Rt + 1. 5269 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); 5270 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg()); 5271 if (Rt2 != Rt + 1) 5272 return Error(Operands[3]->getStartLoc(), 5273 "destination operands must be sequential"); 5274 return false; 5275 } 5276 case ARM::STRD: { 5277 // Rt2 must be Rt + 1. 5278 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); 5279 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg()); 5280 if (Rt2 != Rt + 1) 5281 return Error(Operands[3]->getStartLoc(), 5282 "source operands must be sequential"); 5283 return false; 5284 } 5285 case ARM::STRD_PRE: 5286 case ARM::STRD_POST: 5287 case ARM::STREXD: { 5288 // Rt2 must be Rt + 1. 5289 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg()); 5290 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg()); 5291 if (Rt2 != Rt + 1) 5292 return Error(Operands[3]->getStartLoc(), 5293 "source operands must be sequential"); 5294 return false; 5295 } 5296 case ARM::SBFX: 5297 case ARM::UBFX: { 5298 // width must be in range [1, 32-lsb] 5299 unsigned lsb = Inst.getOperand(2).getImm(); 5300 unsigned widthm1 = Inst.getOperand(3).getImm(); 5301 if (widthm1 >= 32 - lsb) 5302 return Error(Operands[5]->getStartLoc(), 5303 "bitfield width must be in range [1,32-lsb]"); 5304 return false; 5305 } 5306 case ARM::tLDMIA: { 5307 // If we're parsing Thumb2, the .w variant is available and handles 5308 // most cases that are normally illegal for a Thumb1 LDM 5309 // instruction. We'll make the transformation in processInstruction() 5310 // if necessary. 5311 // 5312 // Thumb LDM instructions are writeback iff the base register is not 5313 // in the register list. 5314 unsigned Rn = Inst.getOperand(0).getReg(); 5315 bool hasWritebackToken = 5316 (static_cast<ARMOperand*>(Operands[3])->isToken() && 5317 static_cast<ARMOperand*>(Operands[3])->getToken() == "!"); 5318 bool listContainsBase; 5319 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo()) 5320 return Error(Operands[3 + hasWritebackToken]->getStartLoc(), 5321 "registers must be in range r0-r7"); 5322 // If we should have writeback, then there should be a '!' token. 5323 if (!listContainsBase && !hasWritebackToken && !isThumbTwo()) 5324 return Error(Operands[2]->getStartLoc(), 5325 "writeback operator '!' expected"); 5326 // If we should not have writeback, there must not be a '!'. This is 5327 // true even for the 32-bit wide encodings. 5328 if (listContainsBase && hasWritebackToken) 5329 return Error(Operands[3]->getStartLoc(), 5330 "writeback operator '!' not allowed when base register " 5331 "in register list"); 5332 5333 break; 5334 } 5335 case ARM::t2LDMIA_UPD: { 5336 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg())) 5337 return Error(Operands[4]->getStartLoc(), 5338 "writeback operator '!' not allowed when base register " 5339 "in register list"); 5340 break; 5341 } 5342 case ARM::tMUL: { 5343 // The second source operand must be the same register as the destination 5344 // operand. 5345 // 5346 // In this case, we must directly check the parsed operands because the 5347 // cvtThumbMultiply() function is written in such a way that it guarantees 5348 // this first statement is always true for the new Inst. Essentially, the 5349 // destination is unconditionally copied into the second source operand 5350 // without checking to see if it matches what we actually parsed. 5351 if (Operands.size() == 6 && 5352 (((ARMOperand*)Operands[3])->getReg() != 5353 ((ARMOperand*)Operands[5])->getReg()) && 5354 (((ARMOperand*)Operands[3])->getReg() != 5355 ((ARMOperand*)Operands[4])->getReg())) { 5356 return Error(Operands[3]->getStartLoc(), 5357 "destination register must match source register"); 5358 } 5359 break; 5360 } 5361 // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2, 5362 // so only issue a diagnostic for thumb1. The instructions will be 5363 // switched to the t2 encodings in processInstruction() if necessary. 5364 case ARM::tPOP: { 5365 bool listContainsBase; 5366 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase) && 5367 !isThumbTwo()) 5368 return Error(Operands[2]->getStartLoc(), 5369 "registers must be in range r0-r7 or pc"); 5370 break; 5371 } 5372 case ARM::tPUSH: { 5373 bool listContainsBase; 5374 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase) && 5375 !isThumbTwo()) 5376 return Error(Operands[2]->getStartLoc(), 5377 "registers must be in range r0-r7 or lr"); 5378 break; 5379 } 5380 case ARM::tSTMIA_UPD: { 5381 bool listContainsBase; 5382 if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase) && !isThumbTwo()) 5383 return Error(Operands[4]->getStartLoc(), 5384 "registers must be in range r0-r7"); 5385 break; 5386 } 5387 case ARM::tADDrSP: { 5388 // If the non-SP source operand and the destination operand are not the 5389 // same, we need thumb2 (for the wide encoding), or we have an error. 5390 if (!isThumbTwo() && 5391 Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) { 5392 return Error(Operands[4]->getStartLoc(), 5393 "source register must be the same as destination"); 5394 } 5395 break; 5396 } 5397 } 5398 5399 return false; 5400} 5401 5402static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) { 5403 switch(Opc) { 5404 default: llvm_unreachable("unexpected opcode!"); 5405 // VST1LN 5406 case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD; 5407 case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD; 5408 case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD; 5409 case ARM::VST1LNdWB_register_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD; 5410 case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD; 5411 case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD; 5412 case ARM::VST1LNdAsm_8: Spacing = 1; return ARM::VST1LNd8; 5413 case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16; 5414 case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32; 5415 5416 // VST2LN 5417 case ARM::VST2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD; 5418 case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD; 5419 case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD; 5420 case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD; 5421 case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD; 5422 5423 case ARM::VST2LNdWB_register_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD; 5424 case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD; 5425 case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD; 5426 case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD; 5427 case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD; 5428 5429 case ARM::VST2LNdAsm_8: Spacing = 1; return ARM::VST2LNd8; 5430 case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16; 5431 case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32; 5432 case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16; 5433 case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32; 5434 5435 // VST3LN 5436 case ARM::VST3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD; 5437 case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD; 5438 case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD; 5439 case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD; 5440 case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD; 5441 case ARM::VST3LNdWB_register_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD; 5442 case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD; 5443 case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD; 5444 case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD; 5445 case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD; 5446 case ARM::VST3LNdAsm_8: Spacing = 1; return ARM::VST3LNd8; 5447 case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16; 5448 case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32; 5449 case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16; 5450 case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32; 5451 5452 // VST3 5453 case ARM::VST3dWB_fixed_Asm_8: Spacing = 1; return ARM::VST3d8_UPD; 5454 case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD; 5455 case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD; 5456 case ARM::VST3qWB_fixed_Asm_8: Spacing = 2; return ARM::VST3q8_UPD; 5457 case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD; 5458 case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD; 5459 case ARM::VST3dWB_register_Asm_8: Spacing = 1; return ARM::VST3d8_UPD; 5460 case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD; 5461 case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD; 5462 case ARM::VST3qWB_register_Asm_8: Spacing = 2; return ARM::VST3q8_UPD; 5463 case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD; 5464 case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD; 5465 case ARM::VST3dAsm_8: Spacing = 1; return ARM::VST3d8; 5466 case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16; 5467 case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32; 5468 case ARM::VST3qAsm_8: Spacing = 2; return ARM::VST3q8; 5469 case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16; 5470 case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32; 5471 5472 // VST4LN 5473 case ARM::VST4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD; 5474 case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD; 5475 case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD; 5476 case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD; 5477 case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD; 5478 case ARM::VST4LNdWB_register_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD; 5479 case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD; 5480 case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD; 5481 case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD; 5482 case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD; 5483 case ARM::VST4LNdAsm_8: Spacing = 1; return ARM::VST4LNd8; 5484 case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16; 5485 case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32; 5486 case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16; 5487 case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32; 5488 5489 // VST4 5490 case ARM::VST4dWB_fixed_Asm_8: Spacing = 1; return ARM::VST4d8_UPD; 5491 case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD; 5492 case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD; 5493 case ARM::VST4qWB_fixed_Asm_8: Spacing = 2; return ARM::VST4q8_UPD; 5494 case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD; 5495 case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD; 5496 case ARM::VST4dWB_register_Asm_8: Spacing = 1; return ARM::VST4d8_UPD; 5497 case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD; 5498 case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD; 5499 case ARM::VST4qWB_register_Asm_8: Spacing = 2; return ARM::VST4q8_UPD; 5500 case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD; 5501 case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD; 5502 case ARM::VST4dAsm_8: Spacing = 1; return ARM::VST4d8; 5503 case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16; 5504 case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32; 5505 case ARM::VST4qAsm_8: Spacing = 2; return ARM::VST4q8; 5506 case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16; 5507 case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32; 5508 } 5509} 5510 5511static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) { 5512 switch(Opc) { 5513 default: llvm_unreachable("unexpected opcode!"); 5514 // VLD1LN 5515 case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD; 5516 case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD; 5517 case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD; 5518 case ARM::VLD1LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD; 5519 case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD; 5520 case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD; 5521 case ARM::VLD1LNdAsm_8: Spacing = 1; return ARM::VLD1LNd8; 5522 case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16; 5523 case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32; 5524 5525 // VLD2LN 5526 case ARM::VLD2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD; 5527 case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD; 5528 case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD; 5529 case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD; 5530 case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD; 5531 case ARM::VLD2LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD; 5532 case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD; 5533 case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD; 5534 case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD; 5535 case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD; 5536 case ARM::VLD2LNdAsm_8: Spacing = 1; return ARM::VLD2LNd8; 5537 case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16; 5538 case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32; 5539 case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16; 5540 case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32; 5541 5542 // VLD3DUP 5543 case ARM::VLD3DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD; 5544 case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD; 5545 case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD; 5546 case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD; 5547 case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPq16_UPD; 5548 case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD; 5549 case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD; 5550 case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD; 5551 case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD; 5552 case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD; 5553 case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD; 5554 case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD; 5555 case ARM::VLD3DUPdAsm_8: Spacing = 1; return ARM::VLD3DUPd8; 5556 case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16; 5557 case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32; 5558 case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8; 5559 case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16; 5560 case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32; 5561 5562 // VLD3LN 5563 case ARM::VLD3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD; 5564 case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD; 5565 case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD; 5566 case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD; 5567 case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD; 5568 case ARM::VLD3LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD; 5569 case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD; 5570 case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD; 5571 case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD; 5572 case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD; 5573 case ARM::VLD3LNdAsm_8: Spacing = 1; return ARM::VLD3LNd8; 5574 case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16; 5575 case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32; 5576 case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16; 5577 case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32; 5578 5579 // VLD3 5580 case ARM::VLD3dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD; 5581 case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD; 5582 case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD; 5583 case ARM::VLD3qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD; 5584 case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD; 5585 case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD; 5586 case ARM::VLD3dWB_register_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD; 5587 case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD; 5588 case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD; 5589 case ARM::VLD3qWB_register_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD; 5590 case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD; 5591 case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD; 5592 case ARM::VLD3dAsm_8: Spacing = 1; return ARM::VLD3d8; 5593 case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16; 5594 case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32; 5595 case ARM::VLD3qAsm_8: Spacing = 2; return ARM::VLD3q8; 5596 case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16; 5597 case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32; 5598 5599 // VLD4LN 5600 case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD; 5601 case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD; 5602 case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD; 5603 case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNq16_UPD; 5604 case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD; 5605 case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD; 5606 case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD; 5607 case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD; 5608 case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD; 5609 case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD; 5610 case ARM::VLD4LNdAsm_8: Spacing = 1; return ARM::VLD4LNd8; 5611 case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16; 5612 case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32; 5613 case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16; 5614 case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32; 5615 5616 // VLD4DUP 5617 case ARM::VLD4DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD; 5618 case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD; 5619 case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD; 5620 case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD; 5621 case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD; 5622 case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD; 5623 case ARM::VLD4DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD; 5624 case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD; 5625 case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD; 5626 case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD; 5627 case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD; 5628 case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD; 5629 case ARM::VLD4DUPdAsm_8: Spacing = 1; return ARM::VLD4DUPd8; 5630 case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16; 5631 case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32; 5632 case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8; 5633 case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16; 5634 case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32; 5635 5636 // VLD4 5637 case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD; 5638 case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD; 5639 case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD; 5640 case ARM::VLD4qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD; 5641 case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD; 5642 case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD; 5643 case ARM::VLD4dWB_register_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD; 5644 case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD; 5645 case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD; 5646 case ARM::VLD4qWB_register_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD; 5647 case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD; 5648 case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD; 5649 case ARM::VLD4dAsm_8: Spacing = 1; return ARM::VLD4d8; 5650 case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16; 5651 case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32; 5652 case ARM::VLD4qAsm_8: Spacing = 2; return ARM::VLD4q8; 5653 case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16; 5654 case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32; 5655 } 5656} 5657 5658bool ARMAsmParser:: 5659processInstruction(MCInst &Inst, 5660 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 5661 switch (Inst.getOpcode()) { 5662 // Aliases for alternate PC+imm syntax of LDR instructions. 5663 case ARM::t2LDRpcrel: 5664 Inst.setOpcode(ARM::t2LDRpci); 5665 return true; 5666 case ARM::t2LDRBpcrel: 5667 Inst.setOpcode(ARM::t2LDRBpci); 5668 return true; 5669 case ARM::t2LDRHpcrel: 5670 Inst.setOpcode(ARM::t2LDRHpci); 5671 return true; 5672 case ARM::t2LDRSBpcrel: 5673 Inst.setOpcode(ARM::t2LDRSBpci); 5674 return true; 5675 case ARM::t2LDRSHpcrel: 5676 Inst.setOpcode(ARM::t2LDRSHpci); 5677 return true; 5678 // Handle NEON VST complex aliases. 5679 case ARM::VST1LNdWB_register_Asm_8: 5680 case ARM::VST1LNdWB_register_Asm_16: 5681 case ARM::VST1LNdWB_register_Asm_32: { 5682 MCInst TmpInst; 5683 // Shuffle the operands around so the lane index operand is in the 5684 // right place. 5685 unsigned Spacing; 5686 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5687 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5688 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5689 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5690 TmpInst.addOperand(Inst.getOperand(4)); // Rm 5691 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5692 TmpInst.addOperand(Inst.getOperand(1)); // lane 5693 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 5694 TmpInst.addOperand(Inst.getOperand(6)); 5695 Inst = TmpInst; 5696 return true; 5697 } 5698 5699 case ARM::VST2LNdWB_register_Asm_8: 5700 case ARM::VST2LNdWB_register_Asm_16: 5701 case ARM::VST2LNdWB_register_Asm_32: 5702 case ARM::VST2LNqWB_register_Asm_16: 5703 case ARM::VST2LNqWB_register_Asm_32: { 5704 MCInst TmpInst; 5705 // Shuffle the operands around so the lane index operand is in the 5706 // right place. 5707 unsigned Spacing; 5708 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5709 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5710 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5711 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5712 TmpInst.addOperand(Inst.getOperand(4)); // Rm 5713 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5714 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5715 Spacing)); 5716 TmpInst.addOperand(Inst.getOperand(1)); // lane 5717 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 5718 TmpInst.addOperand(Inst.getOperand(6)); 5719 Inst = TmpInst; 5720 return true; 5721 } 5722 5723 case ARM::VST3LNdWB_register_Asm_8: 5724 case ARM::VST3LNdWB_register_Asm_16: 5725 case ARM::VST3LNdWB_register_Asm_32: 5726 case ARM::VST3LNqWB_register_Asm_16: 5727 case ARM::VST3LNqWB_register_Asm_32: { 5728 MCInst TmpInst; 5729 // Shuffle the operands around so the lane index operand is in the 5730 // right place. 5731 unsigned Spacing; 5732 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5733 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5734 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5735 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5736 TmpInst.addOperand(Inst.getOperand(4)); // Rm 5737 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5738 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5739 Spacing)); 5740 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5741 Spacing * 2)); 5742 TmpInst.addOperand(Inst.getOperand(1)); // lane 5743 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 5744 TmpInst.addOperand(Inst.getOperand(6)); 5745 Inst = TmpInst; 5746 return true; 5747 } 5748 5749 case ARM::VST4LNdWB_register_Asm_8: 5750 case ARM::VST4LNdWB_register_Asm_16: 5751 case ARM::VST4LNdWB_register_Asm_32: 5752 case ARM::VST4LNqWB_register_Asm_16: 5753 case ARM::VST4LNqWB_register_Asm_32: { 5754 MCInst TmpInst; 5755 // Shuffle the operands around so the lane index operand is in the 5756 // right place. 5757 unsigned Spacing; 5758 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5759 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5760 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5761 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5762 TmpInst.addOperand(Inst.getOperand(4)); // Rm 5763 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5764 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5765 Spacing)); 5766 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5767 Spacing * 2)); 5768 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5769 Spacing * 3)); 5770 TmpInst.addOperand(Inst.getOperand(1)); // lane 5771 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 5772 TmpInst.addOperand(Inst.getOperand(6)); 5773 Inst = TmpInst; 5774 return true; 5775 } 5776 5777 case ARM::VST1LNdWB_fixed_Asm_8: 5778 case ARM::VST1LNdWB_fixed_Asm_16: 5779 case ARM::VST1LNdWB_fixed_Asm_32: { 5780 MCInst TmpInst; 5781 // Shuffle the operands around so the lane index operand is in the 5782 // right place. 5783 unsigned Spacing; 5784 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5785 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5786 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5787 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5788 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 5789 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5790 TmpInst.addOperand(Inst.getOperand(1)); // lane 5791 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 5792 TmpInst.addOperand(Inst.getOperand(5)); 5793 Inst = TmpInst; 5794 return true; 5795 } 5796 5797 case ARM::VST2LNdWB_fixed_Asm_8: 5798 case ARM::VST2LNdWB_fixed_Asm_16: 5799 case ARM::VST2LNdWB_fixed_Asm_32: 5800 case ARM::VST2LNqWB_fixed_Asm_16: 5801 case ARM::VST2LNqWB_fixed_Asm_32: { 5802 MCInst TmpInst; 5803 // Shuffle the operands around so the lane index operand is in the 5804 // right place. 5805 unsigned Spacing; 5806 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5807 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5808 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5809 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5810 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 5811 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5812 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5813 Spacing)); 5814 TmpInst.addOperand(Inst.getOperand(1)); // lane 5815 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 5816 TmpInst.addOperand(Inst.getOperand(5)); 5817 Inst = TmpInst; 5818 return true; 5819 } 5820 5821 case ARM::VST3LNdWB_fixed_Asm_8: 5822 case ARM::VST3LNdWB_fixed_Asm_16: 5823 case ARM::VST3LNdWB_fixed_Asm_32: 5824 case ARM::VST3LNqWB_fixed_Asm_16: 5825 case ARM::VST3LNqWB_fixed_Asm_32: { 5826 MCInst TmpInst; 5827 // Shuffle the operands around so the lane index operand is in the 5828 // right place. 5829 unsigned Spacing; 5830 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5831 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5832 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5833 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5834 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 5835 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5836 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5837 Spacing)); 5838 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5839 Spacing * 2)); 5840 TmpInst.addOperand(Inst.getOperand(1)); // lane 5841 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 5842 TmpInst.addOperand(Inst.getOperand(5)); 5843 Inst = TmpInst; 5844 return true; 5845 } 5846 5847 case ARM::VST4LNdWB_fixed_Asm_8: 5848 case ARM::VST4LNdWB_fixed_Asm_16: 5849 case ARM::VST4LNdWB_fixed_Asm_32: 5850 case ARM::VST4LNqWB_fixed_Asm_16: 5851 case ARM::VST4LNqWB_fixed_Asm_32: { 5852 MCInst TmpInst; 5853 // Shuffle the operands around so the lane index operand is in the 5854 // right place. 5855 unsigned Spacing; 5856 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5857 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5858 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5859 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5860 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 5861 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5862 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5863 Spacing)); 5864 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5865 Spacing * 2)); 5866 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5867 Spacing * 3)); 5868 TmpInst.addOperand(Inst.getOperand(1)); // lane 5869 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 5870 TmpInst.addOperand(Inst.getOperand(5)); 5871 Inst = TmpInst; 5872 return true; 5873 } 5874 5875 case ARM::VST1LNdAsm_8: 5876 case ARM::VST1LNdAsm_16: 5877 case ARM::VST1LNdAsm_32: { 5878 MCInst TmpInst; 5879 // Shuffle the operands around so the lane index operand is in the 5880 // right place. 5881 unsigned Spacing; 5882 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5883 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5884 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5885 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5886 TmpInst.addOperand(Inst.getOperand(1)); // lane 5887 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 5888 TmpInst.addOperand(Inst.getOperand(5)); 5889 Inst = TmpInst; 5890 return true; 5891 } 5892 5893 case ARM::VST2LNdAsm_8: 5894 case ARM::VST2LNdAsm_16: 5895 case ARM::VST2LNdAsm_32: 5896 case ARM::VST2LNqAsm_16: 5897 case ARM::VST2LNqAsm_32: { 5898 MCInst TmpInst; 5899 // Shuffle the operands around so the lane index operand is in the 5900 // right place. 5901 unsigned Spacing; 5902 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5903 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5904 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5905 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5906 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5907 Spacing)); 5908 TmpInst.addOperand(Inst.getOperand(1)); // lane 5909 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 5910 TmpInst.addOperand(Inst.getOperand(5)); 5911 Inst = TmpInst; 5912 return true; 5913 } 5914 5915 case ARM::VST3LNdAsm_8: 5916 case ARM::VST3LNdAsm_16: 5917 case ARM::VST3LNdAsm_32: 5918 case ARM::VST3LNqAsm_16: 5919 case ARM::VST3LNqAsm_32: { 5920 MCInst TmpInst; 5921 // Shuffle the operands around so the lane index operand is in the 5922 // right place. 5923 unsigned Spacing; 5924 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5925 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5926 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5927 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5928 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5929 Spacing)); 5930 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5931 Spacing * 2)); 5932 TmpInst.addOperand(Inst.getOperand(1)); // lane 5933 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 5934 TmpInst.addOperand(Inst.getOperand(5)); 5935 Inst = TmpInst; 5936 return true; 5937 } 5938 5939 case ARM::VST4LNdAsm_8: 5940 case ARM::VST4LNdAsm_16: 5941 case ARM::VST4LNdAsm_32: 5942 case ARM::VST4LNqAsm_16: 5943 case ARM::VST4LNqAsm_32: { 5944 MCInst TmpInst; 5945 // Shuffle the operands around so the lane index operand is in the 5946 // right place. 5947 unsigned Spacing; 5948 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5949 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5950 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5951 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5952 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5953 Spacing)); 5954 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5955 Spacing * 2)); 5956 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5957 Spacing * 3)); 5958 TmpInst.addOperand(Inst.getOperand(1)); // lane 5959 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 5960 TmpInst.addOperand(Inst.getOperand(5)); 5961 Inst = TmpInst; 5962 return true; 5963 } 5964 5965 // Handle NEON VLD complex aliases. 5966 case ARM::VLD1LNdWB_register_Asm_8: 5967 case ARM::VLD1LNdWB_register_Asm_16: 5968 case ARM::VLD1LNdWB_register_Asm_32: { 5969 MCInst TmpInst; 5970 // Shuffle the operands around so the lane index operand is in the 5971 // right place. 5972 unsigned Spacing; 5973 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 5974 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5975 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5976 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5977 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5978 TmpInst.addOperand(Inst.getOperand(4)); // Rm 5979 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 5980 TmpInst.addOperand(Inst.getOperand(1)); // lane 5981 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 5982 TmpInst.addOperand(Inst.getOperand(6)); 5983 Inst = TmpInst; 5984 return true; 5985 } 5986 5987 case ARM::VLD2LNdWB_register_Asm_8: 5988 case ARM::VLD2LNdWB_register_Asm_16: 5989 case ARM::VLD2LNdWB_register_Asm_32: 5990 case ARM::VLD2LNqWB_register_Asm_16: 5991 case ARM::VLD2LNqWB_register_Asm_32: { 5992 MCInst TmpInst; 5993 // Shuffle the operands around so the lane index operand is in the 5994 // right place. 5995 unsigned Spacing; 5996 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 5997 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5998 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5999 Spacing)); 6000 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6001 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6002 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6003 TmpInst.addOperand(Inst.getOperand(4)); // Rm 6004 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6005 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6006 Spacing)); 6007 TmpInst.addOperand(Inst.getOperand(1)); // lane 6008 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 6009 TmpInst.addOperand(Inst.getOperand(6)); 6010 Inst = TmpInst; 6011 return true; 6012 } 6013 6014 case ARM::VLD3LNdWB_register_Asm_8: 6015 case ARM::VLD3LNdWB_register_Asm_16: 6016 case ARM::VLD3LNdWB_register_Asm_32: 6017 case ARM::VLD3LNqWB_register_Asm_16: 6018 case ARM::VLD3LNqWB_register_Asm_32: { 6019 MCInst TmpInst; 6020 // Shuffle the operands around so the lane index operand is in the 6021 // right place. 6022 unsigned Spacing; 6023 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6024 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6025 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6026 Spacing)); 6027 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6028 Spacing * 2)); 6029 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6030 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6031 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6032 TmpInst.addOperand(Inst.getOperand(4)); // Rm 6033 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6034 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6035 Spacing)); 6036 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6037 Spacing * 2)); 6038 TmpInst.addOperand(Inst.getOperand(1)); // lane 6039 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 6040 TmpInst.addOperand(Inst.getOperand(6)); 6041 Inst = TmpInst; 6042 return true; 6043 } 6044 6045 case ARM::VLD4LNdWB_register_Asm_8: 6046 case ARM::VLD4LNdWB_register_Asm_16: 6047 case ARM::VLD4LNdWB_register_Asm_32: 6048 case ARM::VLD4LNqWB_register_Asm_16: 6049 case ARM::VLD4LNqWB_register_Asm_32: { 6050 MCInst TmpInst; 6051 // Shuffle the operands around so the lane index operand is in the 6052 // right place. 6053 unsigned Spacing; 6054 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6055 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6056 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6057 Spacing)); 6058 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6059 Spacing * 2)); 6060 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6061 Spacing * 3)); 6062 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6063 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6064 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6065 TmpInst.addOperand(Inst.getOperand(4)); // Rm 6066 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6067 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6068 Spacing)); 6069 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6070 Spacing * 2)); 6071 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6072 Spacing * 3)); 6073 TmpInst.addOperand(Inst.getOperand(1)); // lane 6074 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 6075 TmpInst.addOperand(Inst.getOperand(6)); 6076 Inst = TmpInst; 6077 return true; 6078 } 6079 6080 case ARM::VLD1LNdWB_fixed_Asm_8: 6081 case ARM::VLD1LNdWB_fixed_Asm_16: 6082 case ARM::VLD1LNdWB_fixed_Asm_32: { 6083 MCInst TmpInst; 6084 // Shuffle the operands around so the lane index operand is in the 6085 // right place. 6086 unsigned Spacing; 6087 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6088 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6089 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6090 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6091 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6092 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6093 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6094 TmpInst.addOperand(Inst.getOperand(1)); // lane 6095 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6096 TmpInst.addOperand(Inst.getOperand(5)); 6097 Inst = TmpInst; 6098 return true; 6099 } 6100 6101 case ARM::VLD2LNdWB_fixed_Asm_8: 6102 case ARM::VLD2LNdWB_fixed_Asm_16: 6103 case ARM::VLD2LNdWB_fixed_Asm_32: 6104 case ARM::VLD2LNqWB_fixed_Asm_16: 6105 case ARM::VLD2LNqWB_fixed_Asm_32: { 6106 MCInst TmpInst; 6107 // Shuffle the operands around so the lane index operand is in the 6108 // right place. 6109 unsigned Spacing; 6110 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6111 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6112 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6113 Spacing)); 6114 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6115 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6116 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6117 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6118 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6119 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6120 Spacing)); 6121 TmpInst.addOperand(Inst.getOperand(1)); // lane 6122 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6123 TmpInst.addOperand(Inst.getOperand(5)); 6124 Inst = TmpInst; 6125 return true; 6126 } 6127 6128 case ARM::VLD3LNdWB_fixed_Asm_8: 6129 case ARM::VLD3LNdWB_fixed_Asm_16: 6130 case ARM::VLD3LNdWB_fixed_Asm_32: 6131 case ARM::VLD3LNqWB_fixed_Asm_16: 6132 case ARM::VLD3LNqWB_fixed_Asm_32: { 6133 MCInst TmpInst; 6134 // Shuffle the operands around so the lane index operand is in the 6135 // right place. 6136 unsigned Spacing; 6137 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6138 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6139 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6140 Spacing)); 6141 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6142 Spacing * 2)); 6143 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6144 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6145 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6146 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6147 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6148 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6149 Spacing)); 6150 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6151 Spacing * 2)); 6152 TmpInst.addOperand(Inst.getOperand(1)); // lane 6153 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6154 TmpInst.addOperand(Inst.getOperand(5)); 6155 Inst = TmpInst; 6156 return true; 6157 } 6158 6159 case ARM::VLD4LNdWB_fixed_Asm_8: 6160 case ARM::VLD4LNdWB_fixed_Asm_16: 6161 case ARM::VLD4LNdWB_fixed_Asm_32: 6162 case ARM::VLD4LNqWB_fixed_Asm_16: 6163 case ARM::VLD4LNqWB_fixed_Asm_32: { 6164 MCInst TmpInst; 6165 // Shuffle the operands around so the lane index operand is in the 6166 // right place. 6167 unsigned Spacing; 6168 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6169 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6170 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6171 Spacing)); 6172 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6173 Spacing * 2)); 6174 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6175 Spacing * 3)); 6176 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6177 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6178 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6179 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6180 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6181 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6182 Spacing)); 6183 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6184 Spacing * 2)); 6185 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6186 Spacing * 3)); 6187 TmpInst.addOperand(Inst.getOperand(1)); // lane 6188 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6189 TmpInst.addOperand(Inst.getOperand(5)); 6190 Inst = TmpInst; 6191 return true; 6192 } 6193 6194 case ARM::VLD1LNdAsm_8: 6195 case ARM::VLD1LNdAsm_16: 6196 case ARM::VLD1LNdAsm_32: { 6197 MCInst TmpInst; 6198 // Shuffle the operands around so the lane index operand is in the 6199 // right place. 6200 unsigned Spacing; 6201 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6202 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6203 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6204 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6205 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6206 TmpInst.addOperand(Inst.getOperand(1)); // lane 6207 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6208 TmpInst.addOperand(Inst.getOperand(5)); 6209 Inst = TmpInst; 6210 return true; 6211 } 6212 6213 case ARM::VLD2LNdAsm_8: 6214 case ARM::VLD2LNdAsm_16: 6215 case ARM::VLD2LNdAsm_32: 6216 case ARM::VLD2LNqAsm_16: 6217 case ARM::VLD2LNqAsm_32: { 6218 MCInst TmpInst; 6219 // Shuffle the operands around so the lane index operand is in the 6220 // right place. 6221 unsigned Spacing; 6222 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6223 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6224 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6225 Spacing)); 6226 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6227 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6228 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6229 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6230 Spacing)); 6231 TmpInst.addOperand(Inst.getOperand(1)); // lane 6232 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6233 TmpInst.addOperand(Inst.getOperand(5)); 6234 Inst = TmpInst; 6235 return true; 6236 } 6237 6238 case ARM::VLD3LNdAsm_8: 6239 case ARM::VLD3LNdAsm_16: 6240 case ARM::VLD3LNdAsm_32: 6241 case ARM::VLD3LNqAsm_16: 6242 case ARM::VLD3LNqAsm_32: { 6243 MCInst TmpInst; 6244 // Shuffle the operands around so the lane index operand is in the 6245 // right place. 6246 unsigned Spacing; 6247 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6248 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6249 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6250 Spacing)); 6251 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6252 Spacing * 2)); 6253 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6254 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6255 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6256 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6257 Spacing)); 6258 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6259 Spacing * 2)); 6260 TmpInst.addOperand(Inst.getOperand(1)); // lane 6261 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6262 TmpInst.addOperand(Inst.getOperand(5)); 6263 Inst = TmpInst; 6264 return true; 6265 } 6266 6267 case ARM::VLD4LNdAsm_8: 6268 case ARM::VLD4LNdAsm_16: 6269 case ARM::VLD4LNdAsm_32: 6270 case ARM::VLD4LNqAsm_16: 6271 case ARM::VLD4LNqAsm_32: { 6272 MCInst TmpInst; 6273 // Shuffle the operands around so the lane index operand is in the 6274 // right place. 6275 unsigned Spacing; 6276 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6277 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6278 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6279 Spacing)); 6280 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6281 Spacing * 2)); 6282 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6283 Spacing * 3)); 6284 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6285 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6286 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6287 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6288 Spacing)); 6289 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6290 Spacing * 2)); 6291 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6292 Spacing * 3)); 6293 TmpInst.addOperand(Inst.getOperand(1)); // lane 6294 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6295 TmpInst.addOperand(Inst.getOperand(5)); 6296 Inst = TmpInst; 6297 return true; 6298 } 6299 6300 // VLD3DUP single 3-element structure to all lanes instructions. 6301 case ARM::VLD3DUPdAsm_8: 6302 case ARM::VLD3DUPdAsm_16: 6303 case ARM::VLD3DUPdAsm_32: 6304 case ARM::VLD3DUPqAsm_8: 6305 case ARM::VLD3DUPqAsm_16: 6306 case ARM::VLD3DUPqAsm_32: { 6307 MCInst TmpInst; 6308 unsigned Spacing; 6309 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6310 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6311 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6312 Spacing)); 6313 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6314 Spacing * 2)); 6315 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6316 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6317 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6318 TmpInst.addOperand(Inst.getOperand(4)); 6319 Inst = TmpInst; 6320 return true; 6321 } 6322 6323 case ARM::VLD3DUPdWB_fixed_Asm_8: 6324 case ARM::VLD3DUPdWB_fixed_Asm_16: 6325 case ARM::VLD3DUPdWB_fixed_Asm_32: 6326 case ARM::VLD3DUPqWB_fixed_Asm_8: 6327 case ARM::VLD3DUPqWB_fixed_Asm_16: 6328 case ARM::VLD3DUPqWB_fixed_Asm_32: { 6329 MCInst TmpInst; 6330 unsigned Spacing; 6331 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6332 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6333 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6334 Spacing)); 6335 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6336 Spacing * 2)); 6337 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6338 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6339 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6340 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6341 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6342 TmpInst.addOperand(Inst.getOperand(4)); 6343 Inst = TmpInst; 6344 return true; 6345 } 6346 6347 case ARM::VLD3DUPdWB_register_Asm_8: 6348 case ARM::VLD3DUPdWB_register_Asm_16: 6349 case ARM::VLD3DUPdWB_register_Asm_32: 6350 case ARM::VLD3DUPqWB_register_Asm_8: 6351 case ARM::VLD3DUPqWB_register_Asm_16: 6352 case ARM::VLD3DUPqWB_register_Asm_32: { 6353 MCInst TmpInst; 6354 unsigned Spacing; 6355 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6356 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6357 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6358 Spacing)); 6359 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6360 Spacing * 2)); 6361 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6362 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6363 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6364 TmpInst.addOperand(Inst.getOperand(3)); // Rm 6365 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6366 TmpInst.addOperand(Inst.getOperand(5)); 6367 Inst = TmpInst; 6368 return true; 6369 } 6370 6371 // VLD3 multiple 3-element structure instructions. 6372 case ARM::VLD3dAsm_8: 6373 case ARM::VLD3dAsm_16: 6374 case ARM::VLD3dAsm_32: 6375 case ARM::VLD3qAsm_8: 6376 case ARM::VLD3qAsm_16: 6377 case ARM::VLD3qAsm_32: { 6378 MCInst TmpInst; 6379 unsigned Spacing; 6380 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6381 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6382 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6383 Spacing)); 6384 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6385 Spacing * 2)); 6386 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6387 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6388 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6389 TmpInst.addOperand(Inst.getOperand(4)); 6390 Inst = TmpInst; 6391 return true; 6392 } 6393 6394 case ARM::VLD3dWB_fixed_Asm_8: 6395 case ARM::VLD3dWB_fixed_Asm_16: 6396 case ARM::VLD3dWB_fixed_Asm_32: 6397 case ARM::VLD3qWB_fixed_Asm_8: 6398 case ARM::VLD3qWB_fixed_Asm_16: 6399 case ARM::VLD3qWB_fixed_Asm_32: { 6400 MCInst TmpInst; 6401 unsigned Spacing; 6402 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6403 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6404 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6405 Spacing)); 6406 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6407 Spacing * 2)); 6408 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6409 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6410 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6411 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6412 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6413 TmpInst.addOperand(Inst.getOperand(4)); 6414 Inst = TmpInst; 6415 return true; 6416 } 6417 6418 case ARM::VLD3dWB_register_Asm_8: 6419 case ARM::VLD3dWB_register_Asm_16: 6420 case ARM::VLD3dWB_register_Asm_32: 6421 case ARM::VLD3qWB_register_Asm_8: 6422 case ARM::VLD3qWB_register_Asm_16: 6423 case ARM::VLD3qWB_register_Asm_32: { 6424 MCInst TmpInst; 6425 unsigned Spacing; 6426 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6427 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6428 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6429 Spacing)); 6430 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6431 Spacing * 2)); 6432 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6433 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6434 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6435 TmpInst.addOperand(Inst.getOperand(3)); // Rm 6436 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6437 TmpInst.addOperand(Inst.getOperand(5)); 6438 Inst = TmpInst; 6439 return true; 6440 } 6441 6442 // VLD4DUP single 3-element structure to all lanes instructions. 6443 case ARM::VLD4DUPdAsm_8: 6444 case ARM::VLD4DUPdAsm_16: 6445 case ARM::VLD4DUPdAsm_32: 6446 case ARM::VLD4DUPqAsm_8: 6447 case ARM::VLD4DUPqAsm_16: 6448 case ARM::VLD4DUPqAsm_32: { 6449 MCInst TmpInst; 6450 unsigned Spacing; 6451 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6452 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6453 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6454 Spacing)); 6455 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6456 Spacing * 2)); 6457 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6458 Spacing * 3)); 6459 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6460 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6461 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6462 TmpInst.addOperand(Inst.getOperand(4)); 6463 Inst = TmpInst; 6464 return true; 6465 } 6466 6467 case ARM::VLD4DUPdWB_fixed_Asm_8: 6468 case ARM::VLD4DUPdWB_fixed_Asm_16: 6469 case ARM::VLD4DUPdWB_fixed_Asm_32: 6470 case ARM::VLD4DUPqWB_fixed_Asm_8: 6471 case ARM::VLD4DUPqWB_fixed_Asm_16: 6472 case ARM::VLD4DUPqWB_fixed_Asm_32: { 6473 MCInst TmpInst; 6474 unsigned Spacing; 6475 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6476 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6477 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6478 Spacing)); 6479 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6480 Spacing * 2)); 6481 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6482 Spacing * 3)); 6483 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6484 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6485 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6486 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6487 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6488 TmpInst.addOperand(Inst.getOperand(4)); 6489 Inst = TmpInst; 6490 return true; 6491 } 6492 6493 case ARM::VLD4DUPdWB_register_Asm_8: 6494 case ARM::VLD4DUPdWB_register_Asm_16: 6495 case ARM::VLD4DUPdWB_register_Asm_32: 6496 case ARM::VLD4DUPqWB_register_Asm_8: 6497 case ARM::VLD4DUPqWB_register_Asm_16: 6498 case ARM::VLD4DUPqWB_register_Asm_32: { 6499 MCInst TmpInst; 6500 unsigned Spacing; 6501 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6502 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6503 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6504 Spacing)); 6505 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6506 Spacing * 2)); 6507 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6508 Spacing * 3)); 6509 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6510 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6511 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6512 TmpInst.addOperand(Inst.getOperand(3)); // Rm 6513 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6514 TmpInst.addOperand(Inst.getOperand(5)); 6515 Inst = TmpInst; 6516 return true; 6517 } 6518 6519 // VLD4 multiple 4-element structure instructions. 6520 case ARM::VLD4dAsm_8: 6521 case ARM::VLD4dAsm_16: 6522 case ARM::VLD4dAsm_32: 6523 case ARM::VLD4qAsm_8: 6524 case ARM::VLD4qAsm_16: 6525 case ARM::VLD4qAsm_32: { 6526 MCInst TmpInst; 6527 unsigned Spacing; 6528 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6529 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6530 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6531 Spacing)); 6532 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6533 Spacing * 2)); 6534 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6535 Spacing * 3)); 6536 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6537 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6538 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6539 TmpInst.addOperand(Inst.getOperand(4)); 6540 Inst = TmpInst; 6541 return true; 6542 } 6543 6544 case ARM::VLD4dWB_fixed_Asm_8: 6545 case ARM::VLD4dWB_fixed_Asm_16: 6546 case ARM::VLD4dWB_fixed_Asm_32: 6547 case ARM::VLD4qWB_fixed_Asm_8: 6548 case ARM::VLD4qWB_fixed_Asm_16: 6549 case ARM::VLD4qWB_fixed_Asm_32: { 6550 MCInst TmpInst; 6551 unsigned Spacing; 6552 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6553 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6554 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6555 Spacing)); 6556 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6557 Spacing * 2)); 6558 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6559 Spacing * 3)); 6560 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6561 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6562 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6563 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6564 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6565 TmpInst.addOperand(Inst.getOperand(4)); 6566 Inst = TmpInst; 6567 return true; 6568 } 6569 6570 case ARM::VLD4dWB_register_Asm_8: 6571 case ARM::VLD4dWB_register_Asm_16: 6572 case ARM::VLD4dWB_register_Asm_32: 6573 case ARM::VLD4qWB_register_Asm_8: 6574 case ARM::VLD4qWB_register_Asm_16: 6575 case ARM::VLD4qWB_register_Asm_32: { 6576 MCInst TmpInst; 6577 unsigned Spacing; 6578 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6579 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6580 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6581 Spacing)); 6582 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6583 Spacing * 2)); 6584 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6585 Spacing * 3)); 6586 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6587 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6588 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6589 TmpInst.addOperand(Inst.getOperand(3)); // Rm 6590 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6591 TmpInst.addOperand(Inst.getOperand(5)); 6592 Inst = TmpInst; 6593 return true; 6594 } 6595 6596 // VST3 multiple 3-element structure instructions. 6597 case ARM::VST3dAsm_8: 6598 case ARM::VST3dAsm_16: 6599 case ARM::VST3dAsm_32: 6600 case ARM::VST3qAsm_8: 6601 case ARM::VST3qAsm_16: 6602 case ARM::VST3qAsm_32: { 6603 MCInst TmpInst; 6604 unsigned Spacing; 6605 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6606 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6607 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6608 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6609 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6610 Spacing)); 6611 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6612 Spacing * 2)); 6613 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6614 TmpInst.addOperand(Inst.getOperand(4)); 6615 Inst = TmpInst; 6616 return true; 6617 } 6618 6619 case ARM::VST3dWB_fixed_Asm_8: 6620 case ARM::VST3dWB_fixed_Asm_16: 6621 case ARM::VST3dWB_fixed_Asm_32: 6622 case ARM::VST3qWB_fixed_Asm_8: 6623 case ARM::VST3qWB_fixed_Asm_16: 6624 case ARM::VST3qWB_fixed_Asm_32: { 6625 MCInst TmpInst; 6626 unsigned Spacing; 6627 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6628 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6629 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6630 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6631 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6632 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6633 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6634 Spacing)); 6635 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6636 Spacing * 2)); 6637 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6638 TmpInst.addOperand(Inst.getOperand(4)); 6639 Inst = TmpInst; 6640 return true; 6641 } 6642 6643 case ARM::VST3dWB_register_Asm_8: 6644 case ARM::VST3dWB_register_Asm_16: 6645 case ARM::VST3dWB_register_Asm_32: 6646 case ARM::VST3qWB_register_Asm_8: 6647 case ARM::VST3qWB_register_Asm_16: 6648 case ARM::VST3qWB_register_Asm_32: { 6649 MCInst TmpInst; 6650 unsigned Spacing; 6651 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6652 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6653 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6654 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6655 TmpInst.addOperand(Inst.getOperand(3)); // Rm 6656 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6657 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6658 Spacing)); 6659 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6660 Spacing * 2)); 6661 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6662 TmpInst.addOperand(Inst.getOperand(5)); 6663 Inst = TmpInst; 6664 return true; 6665 } 6666 6667 // VST4 multiple 3-element structure instructions. 6668 case ARM::VST4dAsm_8: 6669 case ARM::VST4dAsm_16: 6670 case ARM::VST4dAsm_32: 6671 case ARM::VST4qAsm_8: 6672 case ARM::VST4qAsm_16: 6673 case ARM::VST4qAsm_32: { 6674 MCInst TmpInst; 6675 unsigned Spacing; 6676 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6677 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6678 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6679 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6680 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6681 Spacing)); 6682 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6683 Spacing * 2)); 6684 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6685 Spacing * 3)); 6686 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6687 TmpInst.addOperand(Inst.getOperand(4)); 6688 Inst = TmpInst; 6689 return true; 6690 } 6691 6692 case ARM::VST4dWB_fixed_Asm_8: 6693 case ARM::VST4dWB_fixed_Asm_16: 6694 case ARM::VST4dWB_fixed_Asm_32: 6695 case ARM::VST4qWB_fixed_Asm_8: 6696 case ARM::VST4qWB_fixed_Asm_16: 6697 case ARM::VST4qWB_fixed_Asm_32: { 6698 MCInst TmpInst; 6699 unsigned Spacing; 6700 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6701 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6702 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6703 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6704 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6705 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6706 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6707 Spacing)); 6708 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6709 Spacing * 2)); 6710 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6711 Spacing * 3)); 6712 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6713 TmpInst.addOperand(Inst.getOperand(4)); 6714 Inst = TmpInst; 6715 return true; 6716 } 6717 6718 case ARM::VST4dWB_register_Asm_8: 6719 case ARM::VST4dWB_register_Asm_16: 6720 case ARM::VST4dWB_register_Asm_32: 6721 case ARM::VST4qWB_register_Asm_8: 6722 case ARM::VST4qWB_register_Asm_16: 6723 case ARM::VST4qWB_register_Asm_32: { 6724 MCInst TmpInst; 6725 unsigned Spacing; 6726 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6727 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6728 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6729 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6730 TmpInst.addOperand(Inst.getOperand(3)); // Rm 6731 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6732 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6733 Spacing)); 6734 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6735 Spacing * 2)); 6736 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6737 Spacing * 3)); 6738 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6739 TmpInst.addOperand(Inst.getOperand(5)); 6740 Inst = TmpInst; 6741 return true; 6742 } 6743 6744 // Handle encoding choice for the shift-immediate instructions. 6745 case ARM::t2LSLri: 6746 case ARM::t2LSRri: 6747 case ARM::t2ASRri: { 6748 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 6749 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && 6750 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) && 6751 !(static_cast<ARMOperand*>(Operands[3])->isToken() && 6752 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) { 6753 unsigned NewOpc; 6754 switch (Inst.getOpcode()) { 6755 default: llvm_unreachable("unexpected opcode"); 6756 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break; 6757 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break; 6758 case ARM::t2ASRri: NewOpc = ARM::tASRri; break; 6759 } 6760 // The Thumb1 operands aren't in the same order. Awesome, eh? 6761 MCInst TmpInst; 6762 TmpInst.setOpcode(NewOpc); 6763 TmpInst.addOperand(Inst.getOperand(0)); 6764 TmpInst.addOperand(Inst.getOperand(5)); 6765 TmpInst.addOperand(Inst.getOperand(1)); 6766 TmpInst.addOperand(Inst.getOperand(2)); 6767 TmpInst.addOperand(Inst.getOperand(3)); 6768 TmpInst.addOperand(Inst.getOperand(4)); 6769 Inst = TmpInst; 6770 return true; 6771 } 6772 return false; 6773 } 6774 6775 // Handle the Thumb2 mode MOV complex aliases. 6776 case ARM::t2MOVsr: 6777 case ARM::t2MOVSsr: { 6778 // Which instruction to expand to depends on the CCOut operand and 6779 // whether we're in an IT block if the register operands are low 6780 // registers. 6781 bool isNarrow = false; 6782 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 6783 isARMLowRegister(Inst.getOperand(1).getReg()) && 6784 isARMLowRegister(Inst.getOperand(2).getReg()) && 6785 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && 6786 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr)) 6787 isNarrow = true; 6788 MCInst TmpInst; 6789 unsigned newOpc; 6790 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) { 6791 default: llvm_unreachable("unexpected opcode!"); 6792 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break; 6793 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break; 6794 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break; 6795 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break; 6796 } 6797 TmpInst.setOpcode(newOpc); 6798 TmpInst.addOperand(Inst.getOperand(0)); // Rd 6799 if (isNarrow) 6800 TmpInst.addOperand(MCOperand::CreateReg( 6801 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); 6802 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6803 TmpInst.addOperand(Inst.getOperand(2)); // Rm 6804 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6805 TmpInst.addOperand(Inst.getOperand(5)); 6806 if (!isNarrow) 6807 TmpInst.addOperand(MCOperand::CreateReg( 6808 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); 6809 Inst = TmpInst; 6810 return true; 6811 } 6812 case ARM::t2MOVsi: 6813 case ARM::t2MOVSsi: { 6814 // Which instruction to expand to depends on the CCOut operand and 6815 // whether we're in an IT block if the register operands are low 6816 // registers. 6817 bool isNarrow = false; 6818 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 6819 isARMLowRegister(Inst.getOperand(1).getReg()) && 6820 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi)) 6821 isNarrow = true; 6822 MCInst TmpInst; 6823 unsigned newOpc; 6824 switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) { 6825 default: llvm_unreachable("unexpected opcode!"); 6826 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break; 6827 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break; 6828 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break; 6829 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break; 6830 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break; 6831 } 6832 unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()); 6833 if (Amount == 32) Amount = 0; 6834 TmpInst.setOpcode(newOpc); 6835 TmpInst.addOperand(Inst.getOperand(0)); // Rd 6836 if (isNarrow) 6837 TmpInst.addOperand(MCOperand::CreateReg( 6838 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); 6839 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6840 if (newOpc != ARM::t2RRX) 6841 TmpInst.addOperand(MCOperand::CreateImm(Amount)); 6842 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6843 TmpInst.addOperand(Inst.getOperand(4)); 6844 if (!isNarrow) 6845 TmpInst.addOperand(MCOperand::CreateReg( 6846 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); 6847 Inst = TmpInst; 6848 return true; 6849 } 6850 // Handle the ARM mode MOV complex aliases. 6851 case ARM::ASRr: 6852 case ARM::LSRr: 6853 case ARM::LSLr: 6854 case ARM::RORr: { 6855 ARM_AM::ShiftOpc ShiftTy; 6856 switch(Inst.getOpcode()) { 6857 default: llvm_unreachable("unexpected opcode!"); 6858 case ARM::ASRr: ShiftTy = ARM_AM::asr; break; 6859 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break; 6860 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break; 6861 case ARM::RORr: ShiftTy = ARM_AM::ror; break; 6862 } 6863 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0); 6864 MCInst TmpInst; 6865 TmpInst.setOpcode(ARM::MOVsr); 6866 TmpInst.addOperand(Inst.getOperand(0)); // Rd 6867 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6868 TmpInst.addOperand(Inst.getOperand(2)); // Rm 6869 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty 6870 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6871 TmpInst.addOperand(Inst.getOperand(4)); 6872 TmpInst.addOperand(Inst.getOperand(5)); // cc_out 6873 Inst = TmpInst; 6874 return true; 6875 } 6876 case ARM::ASRi: 6877 case ARM::LSRi: 6878 case ARM::LSLi: 6879 case ARM::RORi: { 6880 ARM_AM::ShiftOpc ShiftTy; 6881 switch(Inst.getOpcode()) { 6882 default: llvm_unreachable("unexpected opcode!"); 6883 case ARM::ASRi: ShiftTy = ARM_AM::asr; break; 6884 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break; 6885 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break; 6886 case ARM::RORi: ShiftTy = ARM_AM::ror; break; 6887 } 6888 // A shift by zero is a plain MOVr, not a MOVsi. 6889 unsigned Amt = Inst.getOperand(2).getImm(); 6890 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi; 6891 // A shift by 32 should be encoded as 0 when permitted 6892 if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr)) 6893 Amt = 0; 6894 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt); 6895 MCInst TmpInst; 6896 TmpInst.setOpcode(Opc); 6897 TmpInst.addOperand(Inst.getOperand(0)); // Rd 6898 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6899 if (Opc == ARM::MOVsi) 6900 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty 6901 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6902 TmpInst.addOperand(Inst.getOperand(4)); 6903 TmpInst.addOperand(Inst.getOperand(5)); // cc_out 6904 Inst = TmpInst; 6905 return true; 6906 } 6907 case ARM::RRXi: { 6908 unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0); 6909 MCInst TmpInst; 6910 TmpInst.setOpcode(ARM::MOVsi); 6911 TmpInst.addOperand(Inst.getOperand(0)); // Rd 6912 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6913 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty 6914 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 6915 TmpInst.addOperand(Inst.getOperand(3)); 6916 TmpInst.addOperand(Inst.getOperand(4)); // cc_out 6917 Inst = TmpInst; 6918 return true; 6919 } 6920 case ARM::t2LDMIA_UPD: { 6921 // If this is a load of a single register, then we should use 6922 // a post-indexed LDR instruction instead, per the ARM ARM. 6923 if (Inst.getNumOperands() != 5) 6924 return false; 6925 MCInst TmpInst; 6926 TmpInst.setOpcode(ARM::t2LDR_POST); 6927 TmpInst.addOperand(Inst.getOperand(4)); // Rt 6928 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 6929 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6930 TmpInst.addOperand(MCOperand::CreateImm(4)); 6931 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 6932 TmpInst.addOperand(Inst.getOperand(3)); 6933 Inst = TmpInst; 6934 return true; 6935 } 6936 case ARM::t2STMDB_UPD: { 6937 // If this is a store of a single register, then we should use 6938 // a pre-indexed STR instruction instead, per the ARM ARM. 6939 if (Inst.getNumOperands() != 5) 6940 return false; 6941 MCInst TmpInst; 6942 TmpInst.setOpcode(ARM::t2STR_PRE); 6943 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 6944 TmpInst.addOperand(Inst.getOperand(4)); // Rt 6945 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6946 TmpInst.addOperand(MCOperand::CreateImm(-4)); 6947 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 6948 TmpInst.addOperand(Inst.getOperand(3)); 6949 Inst = TmpInst; 6950 return true; 6951 } 6952 case ARM::LDMIA_UPD: 6953 // If this is a load of a single register via a 'pop', then we should use 6954 // a post-indexed LDR instruction instead, per the ARM ARM. 6955 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" && 6956 Inst.getNumOperands() == 5) { 6957 MCInst TmpInst; 6958 TmpInst.setOpcode(ARM::LDR_POST_IMM); 6959 TmpInst.addOperand(Inst.getOperand(4)); // Rt 6960 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 6961 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6962 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset 6963 TmpInst.addOperand(MCOperand::CreateImm(4)); 6964 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 6965 TmpInst.addOperand(Inst.getOperand(3)); 6966 Inst = TmpInst; 6967 return true; 6968 } 6969 break; 6970 case ARM::STMDB_UPD: 6971 // If this is a store of a single register via a 'push', then we should use 6972 // a pre-indexed STR instruction instead, per the ARM ARM. 6973 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" && 6974 Inst.getNumOperands() == 5) { 6975 MCInst TmpInst; 6976 TmpInst.setOpcode(ARM::STR_PRE_IMM); 6977 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 6978 TmpInst.addOperand(Inst.getOperand(4)); // Rt 6979 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12 6980 TmpInst.addOperand(MCOperand::CreateImm(-4)); 6981 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 6982 TmpInst.addOperand(Inst.getOperand(3)); 6983 Inst = TmpInst; 6984 } 6985 break; 6986 case ARM::t2ADDri12: 6987 // If the immediate fits for encoding T3 (t2ADDri) and the generic "add" 6988 // mnemonic was used (not "addw"), encoding T3 is preferred. 6989 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "add" || 6990 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1) 6991 break; 6992 Inst.setOpcode(ARM::t2ADDri); 6993 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out 6994 break; 6995 case ARM::t2SUBri12: 6996 // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub" 6997 // mnemonic was used (not "subw"), encoding T3 is preferred. 6998 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "sub" || 6999 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1) 7000 break; 7001 Inst.setOpcode(ARM::t2SUBri); 7002 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out 7003 break; 7004 case ARM::tADDi8: 7005 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was 7006 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred 7007 // to encoding T2 if <Rd> is specified and encoding T2 is preferred 7008 // to encoding T1 if <Rd> is omitted." 7009 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) { 7010 Inst.setOpcode(ARM::tADDi3); 7011 return true; 7012 } 7013 break; 7014 case ARM::tSUBi8: 7015 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was 7016 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred 7017 // to encoding T2 if <Rd> is specified and encoding T2 is preferred 7018 // to encoding T1 if <Rd> is omitted." 7019 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) { 7020 Inst.setOpcode(ARM::tSUBi3); 7021 return true; 7022 } 7023 break; 7024 case ARM::t2ADDri: 7025 case ARM::t2SUBri: { 7026 // If the destination and first source operand are the same, and 7027 // the flags are compatible with the current IT status, use encoding T2 7028 // instead of T3. For compatibility with the system 'as'. Make sure the 7029 // wide encoding wasn't explicit. 7030 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() || 7031 !isARMLowRegister(Inst.getOperand(0).getReg()) || 7032 (unsigned)Inst.getOperand(2).getImm() > 255 || 7033 ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) || 7034 (inITBlock() && Inst.getOperand(5).getReg() != 0)) || 7035 (static_cast<ARMOperand*>(Operands[3])->isToken() && 7036 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) 7037 break; 7038 MCInst TmpInst; 7039 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ? 7040 ARM::tADDi8 : ARM::tSUBi8); 7041 TmpInst.addOperand(Inst.getOperand(0)); 7042 TmpInst.addOperand(Inst.getOperand(5)); 7043 TmpInst.addOperand(Inst.getOperand(0)); 7044 TmpInst.addOperand(Inst.getOperand(2)); 7045 TmpInst.addOperand(Inst.getOperand(3)); 7046 TmpInst.addOperand(Inst.getOperand(4)); 7047 Inst = TmpInst; 7048 return true; 7049 } 7050 case ARM::t2ADDrr: { 7051 // If the destination and first source operand are the same, and 7052 // there's no setting of the flags, use encoding T2 instead of T3. 7053 // Note that this is only for ADD, not SUB. This mirrors the system 7054 // 'as' behaviour. Make sure the wide encoding wasn't explicit. 7055 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() || 7056 Inst.getOperand(5).getReg() != 0 || 7057 (static_cast<ARMOperand*>(Operands[3])->isToken() && 7058 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) 7059 break; 7060 MCInst TmpInst; 7061 TmpInst.setOpcode(ARM::tADDhirr); 7062 TmpInst.addOperand(Inst.getOperand(0)); 7063 TmpInst.addOperand(Inst.getOperand(0)); 7064 TmpInst.addOperand(Inst.getOperand(2)); 7065 TmpInst.addOperand(Inst.getOperand(3)); 7066 TmpInst.addOperand(Inst.getOperand(4)); 7067 Inst = TmpInst; 7068 return true; 7069 } 7070 case ARM::tADDrSP: { 7071 // If the non-SP source operand and the destination operand are not the 7072 // same, we need to use the 32-bit encoding if it's available. 7073 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) { 7074 Inst.setOpcode(ARM::t2ADDrr); 7075 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out 7076 return true; 7077 } 7078 break; 7079 } 7080 case ARM::tB: 7081 // A Thumb conditional branch outside of an IT block is a tBcc. 7082 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) { 7083 Inst.setOpcode(ARM::tBcc); 7084 return true; 7085 } 7086 break; 7087 case ARM::t2B: 7088 // A Thumb2 conditional branch outside of an IT block is a t2Bcc. 7089 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){ 7090 Inst.setOpcode(ARM::t2Bcc); 7091 return true; 7092 } 7093 break; 7094 case ARM::t2Bcc: 7095 // If the conditional is AL or we're in an IT block, we really want t2B. 7096 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) { 7097 Inst.setOpcode(ARM::t2B); 7098 return true; 7099 } 7100 break; 7101 case ARM::tBcc: 7102 // If the conditional is AL, we really want tB. 7103 if (Inst.getOperand(1).getImm() == ARMCC::AL) { 7104 Inst.setOpcode(ARM::tB); 7105 return true; 7106 } 7107 break; 7108 case ARM::tLDMIA: { 7109 // If the register list contains any high registers, or if the writeback 7110 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding 7111 // instead if we're in Thumb2. Otherwise, this should have generated 7112 // an error in validateInstruction(). 7113 unsigned Rn = Inst.getOperand(0).getReg(); 7114 bool hasWritebackToken = 7115 (static_cast<ARMOperand*>(Operands[3])->isToken() && 7116 static_cast<ARMOperand*>(Operands[3])->getToken() == "!"); 7117 bool listContainsBase; 7118 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) || 7119 (!listContainsBase && !hasWritebackToken) || 7120 (listContainsBase && hasWritebackToken)) { 7121 // 16-bit encoding isn't sufficient. Switch to the 32-bit version. 7122 assert (isThumbTwo()); 7123 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA); 7124 // If we're switching to the updating version, we need to insert 7125 // the writeback tied operand. 7126 if (hasWritebackToken) 7127 Inst.insert(Inst.begin(), 7128 MCOperand::CreateReg(Inst.getOperand(0).getReg())); 7129 return true; 7130 } 7131 break; 7132 } 7133 case ARM::tSTMIA_UPD: { 7134 // If the register list contains any high registers, we need to use 7135 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this 7136 // should have generated an error in validateInstruction(). 7137 unsigned Rn = Inst.getOperand(0).getReg(); 7138 bool listContainsBase; 7139 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) { 7140 // 16-bit encoding isn't sufficient. Switch to the 32-bit version. 7141 assert (isThumbTwo()); 7142 Inst.setOpcode(ARM::t2STMIA_UPD); 7143 return true; 7144 } 7145 break; 7146 } 7147 case ARM::tPOP: { 7148 bool listContainsBase; 7149 // If the register list contains any high registers, we need to use 7150 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this 7151 // should have generated an error in validateInstruction(). 7152 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase)) 7153 return false; 7154 assert (isThumbTwo()); 7155 Inst.setOpcode(ARM::t2LDMIA_UPD); 7156 // Add the base register and writeback operands. 7157 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); 7158 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); 7159 return true; 7160 } 7161 case ARM::tPUSH: { 7162 bool listContainsBase; 7163 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase)) 7164 return false; 7165 assert (isThumbTwo()); 7166 Inst.setOpcode(ARM::t2STMDB_UPD); 7167 // Add the base register and writeback operands. 7168 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); 7169 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); 7170 return true; 7171 } 7172 case ARM::t2MOVi: { 7173 // If we can use the 16-bit encoding and the user didn't explicitly 7174 // request the 32-bit variant, transform it here. 7175 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 7176 (unsigned)Inst.getOperand(1).getImm() <= 255 && 7177 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL && 7178 Inst.getOperand(4).getReg() == ARM::CPSR) || 7179 (inITBlock() && Inst.getOperand(4).getReg() == 0)) && 7180 (!static_cast<ARMOperand*>(Operands[2])->isToken() || 7181 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) { 7182 // The operands aren't in the same order for tMOVi8... 7183 MCInst TmpInst; 7184 TmpInst.setOpcode(ARM::tMOVi8); 7185 TmpInst.addOperand(Inst.getOperand(0)); 7186 TmpInst.addOperand(Inst.getOperand(4)); 7187 TmpInst.addOperand(Inst.getOperand(1)); 7188 TmpInst.addOperand(Inst.getOperand(2)); 7189 TmpInst.addOperand(Inst.getOperand(3)); 7190 Inst = TmpInst; 7191 return true; 7192 } 7193 break; 7194 } 7195 case ARM::t2MOVr: { 7196 // If we can use the 16-bit encoding and the user didn't explicitly 7197 // request the 32-bit variant, transform it here. 7198 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 7199 isARMLowRegister(Inst.getOperand(1).getReg()) && 7200 Inst.getOperand(2).getImm() == ARMCC::AL && 7201 Inst.getOperand(4).getReg() == ARM::CPSR && 7202 (!static_cast<ARMOperand*>(Operands[2])->isToken() || 7203 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) { 7204 // The operands aren't the same for tMOV[S]r... (no cc_out) 7205 MCInst TmpInst; 7206 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr); 7207 TmpInst.addOperand(Inst.getOperand(0)); 7208 TmpInst.addOperand(Inst.getOperand(1)); 7209 TmpInst.addOperand(Inst.getOperand(2)); 7210 TmpInst.addOperand(Inst.getOperand(3)); 7211 Inst = TmpInst; 7212 return true; 7213 } 7214 break; 7215 } 7216 case ARM::t2SXTH: 7217 case ARM::t2SXTB: 7218 case ARM::t2UXTH: 7219 case ARM::t2UXTB: { 7220 // If we can use the 16-bit encoding and the user didn't explicitly 7221 // request the 32-bit variant, transform it here. 7222 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 7223 isARMLowRegister(Inst.getOperand(1).getReg()) && 7224 Inst.getOperand(2).getImm() == 0 && 7225 (!static_cast<ARMOperand*>(Operands[2])->isToken() || 7226 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) { 7227 unsigned NewOpc; 7228 switch (Inst.getOpcode()) { 7229 default: llvm_unreachable("Illegal opcode!"); 7230 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break; 7231 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break; 7232 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break; 7233 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break; 7234 } 7235 // The operands aren't the same for thumb1 (no rotate operand). 7236 MCInst TmpInst; 7237 TmpInst.setOpcode(NewOpc); 7238 TmpInst.addOperand(Inst.getOperand(0)); 7239 TmpInst.addOperand(Inst.getOperand(1)); 7240 TmpInst.addOperand(Inst.getOperand(3)); 7241 TmpInst.addOperand(Inst.getOperand(4)); 7242 Inst = TmpInst; 7243 return true; 7244 } 7245 break; 7246 } 7247 case ARM::MOVsi: { 7248 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm()); 7249 // rrx shifts and asr/lsr of #32 is encoded as 0 7250 if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr) 7251 return false; 7252 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) { 7253 // Shifting by zero is accepted as a vanilla 'MOVr' 7254 MCInst TmpInst; 7255 TmpInst.setOpcode(ARM::MOVr); 7256 TmpInst.addOperand(Inst.getOperand(0)); 7257 TmpInst.addOperand(Inst.getOperand(1)); 7258 TmpInst.addOperand(Inst.getOperand(3)); 7259 TmpInst.addOperand(Inst.getOperand(4)); 7260 TmpInst.addOperand(Inst.getOperand(5)); 7261 Inst = TmpInst; 7262 return true; 7263 } 7264 return false; 7265 } 7266 case ARM::ANDrsi: 7267 case ARM::ORRrsi: 7268 case ARM::EORrsi: 7269 case ARM::BICrsi: 7270 case ARM::SUBrsi: 7271 case ARM::ADDrsi: { 7272 unsigned newOpc; 7273 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm()); 7274 if (SOpc == ARM_AM::rrx) return false; 7275 switch (Inst.getOpcode()) { 7276 default: llvm_unreachable("unexpected opcode!"); 7277 case ARM::ANDrsi: newOpc = ARM::ANDrr; break; 7278 case ARM::ORRrsi: newOpc = ARM::ORRrr; break; 7279 case ARM::EORrsi: newOpc = ARM::EORrr; break; 7280 case ARM::BICrsi: newOpc = ARM::BICrr; break; 7281 case ARM::SUBrsi: newOpc = ARM::SUBrr; break; 7282 case ARM::ADDrsi: newOpc = ARM::ADDrr; break; 7283 } 7284 // If the shift is by zero, use the non-shifted instruction definition. 7285 // The exception is for right shifts, where 0 == 32 7286 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 && 7287 !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) { 7288 MCInst TmpInst; 7289 TmpInst.setOpcode(newOpc); 7290 TmpInst.addOperand(Inst.getOperand(0)); 7291 TmpInst.addOperand(Inst.getOperand(1)); 7292 TmpInst.addOperand(Inst.getOperand(2)); 7293 TmpInst.addOperand(Inst.getOperand(4)); 7294 TmpInst.addOperand(Inst.getOperand(5)); 7295 TmpInst.addOperand(Inst.getOperand(6)); 7296 Inst = TmpInst; 7297 return true; 7298 } 7299 return false; 7300 } 7301 case ARM::ITasm: 7302 case ARM::t2IT: { 7303 // The mask bits for all but the first condition are represented as 7304 // the low bit of the condition code value implies 't'. We currently 7305 // always have 1 implies 't', so XOR toggle the bits if the low bit 7306 // of the condition code is zero. 7307 MCOperand &MO = Inst.getOperand(1); 7308 unsigned Mask = MO.getImm(); 7309 unsigned OrigMask = Mask; 7310 unsigned TZ = CountTrailingZeros_32(Mask); 7311 if ((Inst.getOperand(0).getImm() & 1) == 0) { 7312 assert(Mask && TZ <= 3 && "illegal IT mask value!"); 7313 for (unsigned i = 3; i != TZ; --i) 7314 Mask ^= 1 << i; 7315 } 7316 MO.setImm(Mask); 7317 7318 // Set up the IT block state according to the IT instruction we just 7319 // matched. 7320 assert(!inITBlock() && "nested IT blocks?!"); 7321 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm()); 7322 ITState.Mask = OrigMask; // Use the original mask, not the updated one. 7323 ITState.CurPosition = 0; 7324 ITState.FirstCond = true; 7325 break; 7326 } 7327 case ARM::t2LSLrr: 7328 case ARM::t2LSRrr: 7329 case ARM::t2ASRrr: 7330 case ARM::t2SBCrr: 7331 case ARM::t2RORrr: 7332 case ARM::t2BICrr: 7333 { 7334 // Assemblers should use the narrow encodings of these instructions when permissible. 7335 if ((isARMLowRegister(Inst.getOperand(1).getReg()) && 7336 isARMLowRegister(Inst.getOperand(2).getReg())) && 7337 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && 7338 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) || 7339 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) && 7340 (!static_cast<ARMOperand*>(Operands[3])->isToken() || 7341 !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) { 7342 unsigned NewOpc; 7343 switch (Inst.getOpcode()) { 7344 default: llvm_unreachable("unexpected opcode"); 7345 case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break; 7346 case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break; 7347 case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break; 7348 case ARM::t2SBCrr: NewOpc = ARM::tSBC; break; 7349 case ARM::t2RORrr: NewOpc = ARM::tROR; break; 7350 case ARM::t2BICrr: NewOpc = ARM::tBIC; break; 7351 } 7352 MCInst TmpInst; 7353 TmpInst.setOpcode(NewOpc); 7354 TmpInst.addOperand(Inst.getOperand(0)); 7355 TmpInst.addOperand(Inst.getOperand(5)); 7356 TmpInst.addOperand(Inst.getOperand(1)); 7357 TmpInst.addOperand(Inst.getOperand(2)); 7358 TmpInst.addOperand(Inst.getOperand(3)); 7359 TmpInst.addOperand(Inst.getOperand(4)); 7360 Inst = TmpInst; 7361 return true; 7362 } 7363 return false; 7364 } 7365 case ARM::t2ANDrr: 7366 case ARM::t2EORrr: 7367 case ARM::t2ADCrr: 7368 case ARM::t2ORRrr: 7369 { 7370 // Assemblers should use the narrow encodings of these instructions when permissible. 7371 // These instructions are special in that they are commutable, so shorter encodings 7372 // are available more often. 7373 if ((isARMLowRegister(Inst.getOperand(1).getReg()) && 7374 isARMLowRegister(Inst.getOperand(2).getReg())) && 7375 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() || 7376 Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) && 7377 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) || 7378 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) && 7379 (!static_cast<ARMOperand*>(Operands[3])->isToken() || 7380 !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) { 7381 unsigned NewOpc; 7382 switch (Inst.getOpcode()) { 7383 default: llvm_unreachable("unexpected opcode"); 7384 case ARM::t2ADCrr: NewOpc = ARM::tADC; break; 7385 case ARM::t2ANDrr: NewOpc = ARM::tAND; break; 7386 case ARM::t2EORrr: NewOpc = ARM::tEOR; break; 7387 case ARM::t2ORRrr: NewOpc = ARM::tORR; break; 7388 } 7389 MCInst TmpInst; 7390 TmpInst.setOpcode(NewOpc); 7391 TmpInst.addOperand(Inst.getOperand(0)); 7392 TmpInst.addOperand(Inst.getOperand(5)); 7393 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) { 7394 TmpInst.addOperand(Inst.getOperand(1)); 7395 TmpInst.addOperand(Inst.getOperand(2)); 7396 } else { 7397 TmpInst.addOperand(Inst.getOperand(2)); 7398 TmpInst.addOperand(Inst.getOperand(1)); 7399 } 7400 TmpInst.addOperand(Inst.getOperand(3)); 7401 TmpInst.addOperand(Inst.getOperand(4)); 7402 Inst = TmpInst; 7403 return true; 7404 } 7405 return false; 7406 } 7407 } 7408 return false; 7409} 7410 7411unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) { 7412 // 16-bit thumb arithmetic instructions either require or preclude the 'S' 7413 // suffix depending on whether they're in an IT block or not. 7414 unsigned Opc = Inst.getOpcode(); 7415 const MCInstrDesc &MCID = getInstDesc(Opc); 7416 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) { 7417 assert(MCID.hasOptionalDef() && 7418 "optionally flag setting instruction missing optional def operand"); 7419 assert(MCID.NumOperands == Inst.getNumOperands() && 7420 "operand count mismatch!"); 7421 // Find the optional-def operand (cc_out). 7422 unsigned OpNo; 7423 for (OpNo = 0; 7424 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands; 7425 ++OpNo) 7426 ; 7427 // If we're parsing Thumb1, reject it completely. 7428 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR) 7429 return Match_MnemonicFail; 7430 // If we're parsing Thumb2, which form is legal depends on whether we're 7431 // in an IT block. 7432 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR && 7433 !inITBlock()) 7434 return Match_RequiresITBlock; 7435 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR && 7436 inITBlock()) 7437 return Match_RequiresNotITBlock; 7438 } 7439 // Some high-register supporting Thumb1 encodings only allow both registers 7440 // to be from r0-r7 when in Thumb2. 7441 else if (Opc == ARM::tADDhirr && isThumbOne() && 7442 isARMLowRegister(Inst.getOperand(1).getReg()) && 7443 isARMLowRegister(Inst.getOperand(2).getReg())) 7444 return Match_RequiresThumb2; 7445 // Others only require ARMv6 or later. 7446 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() && 7447 isARMLowRegister(Inst.getOperand(0).getReg()) && 7448 isARMLowRegister(Inst.getOperand(1).getReg())) 7449 return Match_RequiresV6; 7450 return Match_Success; 7451} 7452 7453static const char *getSubtargetFeatureName(unsigned Val); 7454bool ARMAsmParser:: 7455MatchAndEmitInstruction(SMLoc IDLoc, 7456 SmallVectorImpl<MCParsedAsmOperand*> &Operands, 7457 MCStreamer &Out) { 7458 MCInst Inst; 7459 unsigned ErrorInfo; 7460 unsigned MatchResult; 7461 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo); 7462 switch (MatchResult) { 7463 default: break; 7464 case Match_Success: 7465 // Context sensitive operand constraints aren't handled by the matcher, 7466 // so check them here. 7467 if (validateInstruction(Inst, Operands)) { 7468 // Still progress the IT block, otherwise one wrong condition causes 7469 // nasty cascading errors. 7470 forwardITPosition(); 7471 return true; 7472 } 7473 7474 // Some instructions need post-processing to, for example, tweak which 7475 // encoding is selected. Loop on it while changes happen so the 7476 // individual transformations can chain off each other. E.g., 7477 // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8) 7478 while (processInstruction(Inst, Operands)) 7479 ; 7480 7481 // Only move forward at the very end so that everything in validate 7482 // and process gets a consistent answer about whether we're in an IT 7483 // block. 7484 forwardITPosition(); 7485 7486 // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and 7487 // doesn't actually encode. 7488 if (Inst.getOpcode() == ARM::ITasm) 7489 return false; 7490 7491 Inst.setLoc(IDLoc); 7492 Out.EmitInstruction(Inst); 7493 return false; 7494 case Match_MissingFeature: { 7495 assert(ErrorInfo && "Unknown missing feature!"); 7496 // Special case the error message for the very common case where only 7497 // a single subtarget feature is missing (Thumb vs. ARM, e.g.). 7498 std::string Msg = "instruction requires:"; 7499 unsigned Mask = 1; 7500 for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) { 7501 if (ErrorInfo & Mask) { 7502 Msg += " "; 7503 Msg += getSubtargetFeatureName(ErrorInfo & Mask); 7504 } 7505 Mask <<= 1; 7506 } 7507 return Error(IDLoc, Msg); 7508 } 7509 case Match_InvalidOperand: { 7510 SMLoc ErrorLoc = IDLoc; 7511 if (ErrorInfo != ~0U) { 7512 if (ErrorInfo >= Operands.size()) 7513 return Error(IDLoc, "too few operands for instruction"); 7514 7515 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc(); 7516 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 7517 } 7518 7519 return Error(ErrorLoc, "invalid operand for instruction"); 7520 } 7521 case Match_MnemonicFail: 7522 return Error(IDLoc, "invalid instruction", 7523 ((ARMOperand*)Operands[0])->getLocRange()); 7524 case Match_RequiresNotITBlock: 7525 return Error(IDLoc, "flag setting instruction only valid outside IT block"); 7526 case Match_RequiresITBlock: 7527 return Error(IDLoc, "instruction only valid inside IT block"); 7528 case Match_RequiresV6: 7529 return Error(IDLoc, "instruction variant requires ARMv6 or later"); 7530 case Match_RequiresThumb2: 7531 return Error(IDLoc, "instruction variant requires Thumb2"); 7532 case Match_ImmRange0_15: { 7533 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc(); 7534 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 7535 return Error(ErrorLoc, "immediate operand must be in the range [0,15]"); 7536 } 7537 } 7538 7539 llvm_unreachable("Implement any new match types added!"); 7540} 7541 7542/// parseDirective parses the arm specific directives 7543bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) { 7544 StringRef IDVal = DirectiveID.getIdentifier(); 7545 if (IDVal == ".word") 7546 return parseDirectiveWord(4, DirectiveID.getLoc()); 7547 else if (IDVal == ".thumb") 7548 return parseDirectiveThumb(DirectiveID.getLoc()); 7549 else if (IDVal == ".arm") 7550 return parseDirectiveARM(DirectiveID.getLoc()); 7551 else if (IDVal == ".thumb_func") 7552 return parseDirectiveThumbFunc(DirectiveID.getLoc()); 7553 else if (IDVal == ".code") 7554 return parseDirectiveCode(DirectiveID.getLoc()); 7555 else if (IDVal == ".syntax") 7556 return parseDirectiveSyntax(DirectiveID.getLoc()); 7557 else if (IDVal == ".unreq") 7558 return parseDirectiveUnreq(DirectiveID.getLoc()); 7559 else if (IDVal == ".arch") 7560 return parseDirectiveArch(DirectiveID.getLoc()); 7561 else if (IDVal == ".eabi_attribute") 7562 return parseDirectiveEabiAttr(DirectiveID.getLoc()); 7563 return true; 7564} 7565 7566/// parseDirectiveWord 7567/// ::= .word [ expression (, expression)* ] 7568bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) { 7569 if (getLexer().isNot(AsmToken::EndOfStatement)) { 7570 for (;;) { 7571 const MCExpr *Value; 7572 if (getParser().ParseExpression(Value)) 7573 return true; 7574 7575 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/); 7576 7577 if (getLexer().is(AsmToken::EndOfStatement)) 7578 break; 7579 7580 // FIXME: Improve diagnostic. 7581 if (getLexer().isNot(AsmToken::Comma)) 7582 return Error(L, "unexpected token in directive"); 7583 Parser.Lex(); 7584 } 7585 } 7586 7587 Parser.Lex(); 7588 return false; 7589} 7590 7591/// parseDirectiveThumb 7592/// ::= .thumb 7593bool ARMAsmParser::parseDirectiveThumb(SMLoc L) { 7594 if (getLexer().isNot(AsmToken::EndOfStatement)) 7595 return Error(L, "unexpected token in directive"); 7596 Parser.Lex(); 7597 7598 if (!isThumb()) 7599 SwitchMode(); 7600 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16); 7601 return false; 7602} 7603 7604/// parseDirectiveARM 7605/// ::= .arm 7606bool ARMAsmParser::parseDirectiveARM(SMLoc L) { 7607 if (getLexer().isNot(AsmToken::EndOfStatement)) 7608 return Error(L, "unexpected token in directive"); 7609 Parser.Lex(); 7610 7611 if (isThumb()) 7612 SwitchMode(); 7613 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32); 7614 return false; 7615} 7616 7617/// parseDirectiveThumbFunc 7618/// ::= .thumbfunc symbol_name 7619bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) { 7620 const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo(); 7621 bool isMachO = MAI.hasSubsectionsViaSymbols(); 7622 StringRef Name; 7623 bool needFuncName = true; 7624 7625 // Darwin asm has (optionally) function name after .thumb_func direction 7626 // ELF doesn't 7627 if (isMachO) { 7628 const AsmToken &Tok = Parser.getTok(); 7629 if (Tok.isNot(AsmToken::EndOfStatement)) { 7630 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String)) 7631 return Error(L, "unexpected token in .thumb_func directive"); 7632 Name = Tok.getIdentifier(); 7633 Parser.Lex(); // Consume the identifier token. 7634 needFuncName = false; 7635 } 7636 } 7637 7638 if (getLexer().isNot(AsmToken::EndOfStatement)) 7639 return Error(L, "unexpected token in directive"); 7640 7641 // Eat the end of statement and any blank lines that follow. 7642 while (getLexer().is(AsmToken::EndOfStatement)) 7643 Parser.Lex(); 7644 7645 // FIXME: assuming function name will be the line following .thumb_func 7646 // We really should be checking the next symbol definition even if there's 7647 // stuff in between. 7648 if (needFuncName) { 7649 Name = Parser.getTok().getIdentifier(); 7650 } 7651 7652 // Mark symbol as a thumb symbol. 7653 MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name); 7654 getParser().getStreamer().EmitThumbFunc(Func); 7655 return false; 7656} 7657 7658/// parseDirectiveSyntax 7659/// ::= .syntax unified | divided 7660bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) { 7661 const AsmToken &Tok = Parser.getTok(); 7662 if (Tok.isNot(AsmToken::Identifier)) 7663 return Error(L, "unexpected token in .syntax directive"); 7664 StringRef Mode = Tok.getString(); 7665 if (Mode == "unified" || Mode == "UNIFIED") 7666 Parser.Lex(); 7667 else if (Mode == "divided" || Mode == "DIVIDED") 7668 return Error(L, "'.syntax divided' arm asssembly not supported"); 7669 else 7670 return Error(L, "unrecognized syntax mode in .syntax directive"); 7671 7672 if (getLexer().isNot(AsmToken::EndOfStatement)) 7673 return Error(Parser.getTok().getLoc(), "unexpected token in directive"); 7674 Parser.Lex(); 7675 7676 // TODO tell the MC streamer the mode 7677 // getParser().getStreamer().Emit???(); 7678 return false; 7679} 7680 7681/// parseDirectiveCode 7682/// ::= .code 16 | 32 7683bool ARMAsmParser::parseDirectiveCode(SMLoc L) { 7684 const AsmToken &Tok = Parser.getTok(); 7685 if (Tok.isNot(AsmToken::Integer)) 7686 return Error(L, "unexpected token in .code directive"); 7687 int64_t Val = Parser.getTok().getIntVal(); 7688 if (Val == 16) 7689 Parser.Lex(); 7690 else if (Val == 32) 7691 Parser.Lex(); 7692 else 7693 return Error(L, "invalid operand to .code directive"); 7694 7695 if (getLexer().isNot(AsmToken::EndOfStatement)) 7696 return Error(Parser.getTok().getLoc(), "unexpected token in directive"); 7697 Parser.Lex(); 7698 7699 if (Val == 16) { 7700 if (!isThumb()) 7701 SwitchMode(); 7702 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16); 7703 } else { 7704 if (isThumb()) 7705 SwitchMode(); 7706 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32); 7707 } 7708 7709 return false; 7710} 7711 7712/// parseDirectiveReq 7713/// ::= name .req registername 7714bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) { 7715 Parser.Lex(); // Eat the '.req' token. 7716 unsigned Reg; 7717 SMLoc SRegLoc, ERegLoc; 7718 if (ParseRegister(Reg, SRegLoc, ERegLoc)) { 7719 Parser.EatToEndOfStatement(); 7720 return Error(SRegLoc, "register name expected"); 7721 } 7722 7723 // Shouldn't be anything else. 7724 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) { 7725 Parser.EatToEndOfStatement(); 7726 return Error(Parser.getTok().getLoc(), 7727 "unexpected input in .req directive."); 7728 } 7729 7730 Parser.Lex(); // Consume the EndOfStatement 7731 7732 if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg) 7733 return Error(SRegLoc, "redefinition of '" + Name + 7734 "' does not match original."); 7735 7736 return false; 7737} 7738 7739/// parseDirectiveUneq 7740/// ::= .unreq registername 7741bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) { 7742 if (Parser.getTok().isNot(AsmToken::Identifier)) { 7743 Parser.EatToEndOfStatement(); 7744 return Error(L, "unexpected input in .unreq directive."); 7745 } 7746 RegisterReqs.erase(Parser.getTok().getIdentifier()); 7747 Parser.Lex(); // Eat the identifier. 7748 return false; 7749} 7750 7751/// parseDirectiveArch 7752/// ::= .arch token 7753bool ARMAsmParser::parseDirectiveArch(SMLoc L) { 7754 return true; 7755} 7756 7757/// parseDirectiveEabiAttr 7758/// ::= .eabi_attribute int, int 7759bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) { 7760 return true; 7761} 7762 7763extern "C" void LLVMInitializeARMAsmLexer(); 7764 7765/// Force static initialization. 7766extern "C" void LLVMInitializeARMAsmParser() { 7767 RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget); 7768 RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget); 7769 LLVMInitializeARMAsmLexer(); 7770} 7771 7772#define GET_REGISTER_MATCHER 7773#define GET_SUBTARGET_FEATURE_NAME 7774#define GET_MATCHER_IMPLEMENTATION 7775#include "ARMGenAsmMatcher.inc" 7776