ARMAsmParser.cpp revision 857e1a7b3fcc848a6508f9205f22e8e0d293dcae
1//===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10#include "MCTargetDesc/ARMBaseInfo.h" 11#include "MCTargetDesc/ARMAddressingModes.h" 12#include "MCTargetDesc/ARMMCExpr.h" 13#include "llvm/MC/MCParser/MCAsmLexer.h" 14#include "llvm/MC/MCParser/MCAsmParser.h" 15#include "llvm/MC/MCParser/MCParsedAsmOperand.h" 16#include "llvm/MC/MCAsmInfo.h" 17#include "llvm/MC/MCContext.h" 18#include "llvm/MC/MCStreamer.h" 19#include "llvm/MC/MCExpr.h" 20#include "llvm/MC/MCInst.h" 21#include "llvm/MC/MCRegisterInfo.h" 22#include "llvm/MC/MCSubtargetInfo.h" 23#include "llvm/MC/MCTargetAsmParser.h" 24#include "llvm/Target/TargetRegistry.h" 25#include "llvm/Support/SourceMgr.h" 26#include "llvm/Support/raw_ostream.h" 27#include "llvm/ADT/OwningPtr.h" 28#include "llvm/ADT/STLExtras.h" 29#include "llvm/ADT/SmallVector.h" 30#include "llvm/ADT/StringExtras.h" 31#include "llvm/ADT/StringSwitch.h" 32#include "llvm/ADT/Twine.h" 33 34using namespace llvm; 35 36namespace { 37 38class ARMOperand; 39 40class ARMAsmParser : public MCTargetAsmParser { 41 MCSubtargetInfo &STI; 42 MCAsmParser &Parser; 43 44 MCAsmParser &getParser() const { return Parser; } 45 MCAsmLexer &getLexer() const { return Parser.getLexer(); } 46 47 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); } 48 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); } 49 50 int tryParseRegister(); 51 bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &); 52 int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &); 53 bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &); 54 bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &); 55 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic); 56 bool parsePrefix(ARMMCExpr::VariantKind &RefKind); 57 const MCExpr *applyPrefixToExpr(const MCExpr *E, 58 MCSymbolRefExpr::VariantKind Variant); 59 60 61 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType, 62 unsigned &ShiftAmount); 63 bool parseDirectiveWord(unsigned Size, SMLoc L); 64 bool parseDirectiveThumb(SMLoc L); 65 bool parseDirectiveThumbFunc(SMLoc L); 66 bool parseDirectiveCode(SMLoc L); 67 bool parseDirectiveSyntax(SMLoc L); 68 69 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode, 70 bool &CarrySetting, unsigned &ProcessorIMod); 71 void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet, 72 bool &CanAcceptPredicationCode); 73 74 bool isThumb() const { 75 // FIXME: Can tablegen auto-generate this? 76 return (STI.getFeatureBits() & ARM::ModeThumb) != 0; 77 } 78 bool isThumbOne() const { 79 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0; 80 } 81 void SwitchMode() { 82 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb)); 83 setAvailableFeatures(FB); 84 } 85 86 /// @name Auto-generated Match Functions 87 /// { 88 89#define GET_ASSEMBLER_HEADER 90#include "ARMGenAsmMatcher.inc" 91 92 /// } 93 94 OperandMatchResultTy parseCoprocNumOperand( 95 SmallVectorImpl<MCParsedAsmOperand*>&); 96 OperandMatchResultTy parseCoprocRegOperand( 97 SmallVectorImpl<MCParsedAsmOperand*>&); 98 OperandMatchResultTy parseMemBarrierOptOperand( 99 SmallVectorImpl<MCParsedAsmOperand*>&); 100 OperandMatchResultTy parseProcIFlagsOperand( 101 SmallVectorImpl<MCParsedAsmOperand*>&); 102 OperandMatchResultTy parseMSRMaskOperand( 103 SmallVectorImpl<MCParsedAsmOperand*>&); 104 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O, 105 StringRef Op, int Low, int High); 106 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) { 107 return parsePKHImm(O, "lsl", 0, 31); 108 } 109 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) { 110 return parsePKHImm(O, "asr", 1, 32); 111 } 112 OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&); 113 OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&); 114 OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&); 115 OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&); 116 OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&); 117 OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&); 118 119 // Asm Match Converter Methods 120 bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, 121 const SmallVectorImpl<MCParsedAsmOperand*> &); 122 bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode, 123 const SmallVectorImpl<MCParsedAsmOperand*> &); 124 bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, 125 const SmallVectorImpl<MCParsedAsmOperand*> &); 126 bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, 127 const SmallVectorImpl<MCParsedAsmOperand*> &); 128 bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode, 129 const SmallVectorImpl<MCParsedAsmOperand*> &); 130 bool cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode, 131 const SmallVectorImpl<MCParsedAsmOperand*> &); 132 bool cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode, 133 const SmallVectorImpl<MCParsedAsmOperand*> &); 134 bool cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode, 135 const SmallVectorImpl<MCParsedAsmOperand*> &); 136 bool cvtLdrdPre(MCInst &Inst, unsigned Opcode, 137 const SmallVectorImpl<MCParsedAsmOperand*> &); 138 bool cvtStrdPre(MCInst &Inst, unsigned Opcode, 139 const SmallVectorImpl<MCParsedAsmOperand*> &); 140 bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, 141 const SmallVectorImpl<MCParsedAsmOperand*> &); 142 143 bool validateInstruction(MCInst &Inst, 144 const SmallVectorImpl<MCParsedAsmOperand*> &Ops); 145 void processInstruction(MCInst &Inst, 146 const SmallVectorImpl<MCParsedAsmOperand*> &Ops); 147 148public: 149 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser) 150 : MCTargetAsmParser(), STI(_STI), Parser(_Parser) { 151 MCAsmParserExtension::Initialize(_Parser); 152 153 // Initialize the set of available features. 154 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); 155 } 156 157 // Implementation of the MCTargetAsmParser interface: 158 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc); 159 bool ParseInstruction(StringRef Name, SMLoc NameLoc, 160 SmallVectorImpl<MCParsedAsmOperand*> &Operands); 161 bool ParseDirective(AsmToken DirectiveID); 162 163 bool MatchAndEmitInstruction(SMLoc IDLoc, 164 SmallVectorImpl<MCParsedAsmOperand*> &Operands, 165 MCStreamer &Out); 166}; 167} // end anonymous namespace 168 169namespace { 170 171/// ARMOperand - Instances of this class represent a parsed ARM machine 172/// instruction. 173class ARMOperand : public MCParsedAsmOperand { 174 enum KindTy { 175 CondCode, 176 CCOut, 177 CoprocNum, 178 CoprocReg, 179 Immediate, 180 MemBarrierOpt, 181 Memory, 182 PostIndexRegister, 183 MSRMask, 184 ProcIFlags, 185 Register, 186 RegisterList, 187 DPRRegisterList, 188 SPRRegisterList, 189 ShiftedRegister, 190 ShiftedImmediate, 191 ShifterImmediate, 192 RotateImmediate, 193 BitfieldDescriptor, 194 Token 195 } Kind; 196 197 SMLoc StartLoc, EndLoc; 198 SmallVector<unsigned, 8> Registers; 199 200 union { 201 struct { 202 ARMCC::CondCodes Val; 203 } CC; 204 205 struct { 206 ARM_MB::MemBOpt Val; 207 } MBOpt; 208 209 struct { 210 unsigned Val; 211 } Cop; 212 213 struct { 214 ARM_PROC::IFlags Val; 215 } IFlags; 216 217 struct { 218 unsigned Val; 219 } MMask; 220 221 struct { 222 const char *Data; 223 unsigned Length; 224 } Tok; 225 226 struct { 227 unsigned RegNum; 228 } Reg; 229 230 struct { 231 const MCExpr *Val; 232 } Imm; 233 234 /// Combined record for all forms of ARM address expressions. 235 struct { 236 unsigned BaseRegNum; 237 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset 238 // was specified. 239 const MCConstantExpr *OffsetImm; // Offset immediate value 240 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL 241 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg 242 unsigned ShiftImm; // shift for OffsetReg. 243 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit) 244 } Mem; 245 246 struct { 247 unsigned RegNum; 248 bool isAdd; 249 ARM_AM::ShiftOpc ShiftTy; 250 unsigned ShiftImm; 251 } PostIdxReg; 252 253 struct { 254 bool isASR; 255 unsigned Imm; 256 } ShifterImm; 257 struct { 258 ARM_AM::ShiftOpc ShiftTy; 259 unsigned SrcReg; 260 unsigned ShiftReg; 261 unsigned ShiftImm; 262 } RegShiftedReg; 263 struct { 264 ARM_AM::ShiftOpc ShiftTy; 265 unsigned SrcReg; 266 unsigned ShiftImm; 267 } RegShiftedImm; 268 struct { 269 unsigned Imm; 270 } RotImm; 271 struct { 272 unsigned LSB; 273 unsigned Width; 274 } Bitfield; 275 }; 276 277 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {} 278public: 279 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() { 280 Kind = o.Kind; 281 StartLoc = o.StartLoc; 282 EndLoc = o.EndLoc; 283 switch (Kind) { 284 case CondCode: 285 CC = o.CC; 286 break; 287 case Token: 288 Tok = o.Tok; 289 break; 290 case CCOut: 291 case Register: 292 Reg = o.Reg; 293 break; 294 case RegisterList: 295 case DPRRegisterList: 296 case SPRRegisterList: 297 Registers = o.Registers; 298 break; 299 case CoprocNum: 300 case CoprocReg: 301 Cop = o.Cop; 302 break; 303 case Immediate: 304 Imm = o.Imm; 305 break; 306 case MemBarrierOpt: 307 MBOpt = o.MBOpt; 308 break; 309 case Memory: 310 Mem = o.Mem; 311 break; 312 case PostIndexRegister: 313 PostIdxReg = o.PostIdxReg; 314 break; 315 case MSRMask: 316 MMask = o.MMask; 317 break; 318 case ProcIFlags: 319 IFlags = o.IFlags; 320 break; 321 case ShifterImmediate: 322 ShifterImm = o.ShifterImm; 323 break; 324 case ShiftedRegister: 325 RegShiftedReg = o.RegShiftedReg; 326 break; 327 case ShiftedImmediate: 328 RegShiftedImm = o.RegShiftedImm; 329 break; 330 case RotateImmediate: 331 RotImm = o.RotImm; 332 break; 333 case BitfieldDescriptor: 334 Bitfield = o.Bitfield; 335 break; 336 } 337 } 338 339 /// getStartLoc - Get the location of the first token of this operand. 340 SMLoc getStartLoc() const { return StartLoc; } 341 /// getEndLoc - Get the location of the last token of this operand. 342 SMLoc getEndLoc() const { return EndLoc; } 343 344 ARMCC::CondCodes getCondCode() const { 345 assert(Kind == CondCode && "Invalid access!"); 346 return CC.Val; 347 } 348 349 unsigned getCoproc() const { 350 assert((Kind == CoprocNum || Kind == CoprocReg) && "Invalid access!"); 351 return Cop.Val; 352 } 353 354 StringRef getToken() const { 355 assert(Kind == Token && "Invalid access!"); 356 return StringRef(Tok.Data, Tok.Length); 357 } 358 359 unsigned getReg() const { 360 assert((Kind == Register || Kind == CCOut) && "Invalid access!"); 361 return Reg.RegNum; 362 } 363 364 const SmallVectorImpl<unsigned> &getRegList() const { 365 assert((Kind == RegisterList || Kind == DPRRegisterList || 366 Kind == SPRRegisterList) && "Invalid access!"); 367 return Registers; 368 } 369 370 const MCExpr *getImm() const { 371 assert(Kind == Immediate && "Invalid access!"); 372 return Imm.Val; 373 } 374 375 ARM_MB::MemBOpt getMemBarrierOpt() const { 376 assert(Kind == MemBarrierOpt && "Invalid access!"); 377 return MBOpt.Val; 378 } 379 380 ARM_PROC::IFlags getProcIFlags() const { 381 assert(Kind == ProcIFlags && "Invalid access!"); 382 return IFlags.Val; 383 } 384 385 unsigned getMSRMask() const { 386 assert(Kind == MSRMask && "Invalid access!"); 387 return MMask.Val; 388 } 389 390 bool isCoprocNum() const { return Kind == CoprocNum; } 391 bool isCoprocReg() const { return Kind == CoprocReg; } 392 bool isCondCode() const { return Kind == CondCode; } 393 bool isCCOut() const { return Kind == CCOut; } 394 bool isImm() const { return Kind == Immediate; } 395 bool isImm0_255() const { 396 if (Kind != Immediate) 397 return false; 398 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 399 if (!CE) return false; 400 int64_t Value = CE->getValue(); 401 return Value >= 0 && Value < 256; 402 } 403 bool isImm0_7() const { 404 if (Kind != Immediate) 405 return false; 406 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 407 if (!CE) return false; 408 int64_t Value = CE->getValue(); 409 return Value >= 0 && Value < 8; 410 } 411 bool isImm0_15() const { 412 if (Kind != Immediate) 413 return false; 414 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 415 if (!CE) return false; 416 int64_t Value = CE->getValue(); 417 return Value >= 0 && Value < 16; 418 } 419 bool isImm0_31() const { 420 if (Kind != Immediate) 421 return false; 422 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 423 if (!CE) return false; 424 int64_t Value = CE->getValue(); 425 return Value >= 0 && Value < 32; 426 } 427 bool isImm1_16() const { 428 if (Kind != Immediate) 429 return false; 430 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 431 if (!CE) return false; 432 int64_t Value = CE->getValue(); 433 return Value > 0 && Value < 17; 434 } 435 bool isImm1_32() const { 436 if (Kind != Immediate) 437 return false; 438 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 439 if (!CE) return false; 440 int64_t Value = CE->getValue(); 441 return Value > 0 && Value < 33; 442 } 443 bool isImm0_65535() const { 444 if (Kind != Immediate) 445 return false; 446 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 447 if (!CE) return false; 448 int64_t Value = CE->getValue(); 449 return Value >= 0 && Value < 65536; 450 } 451 bool isImm0_65535Expr() const { 452 if (Kind != Immediate) 453 return false; 454 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 455 // If it's not a constant expression, it'll generate a fixup and be 456 // handled later. 457 if (!CE) return true; 458 int64_t Value = CE->getValue(); 459 return Value >= 0 && Value < 65536; 460 } 461 bool isImm24bit() const { 462 if (Kind != Immediate) 463 return false; 464 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 465 if (!CE) return false; 466 int64_t Value = CE->getValue(); 467 return Value >= 0 && Value <= 0xffffff; 468 } 469 bool isPKHLSLImm() const { 470 if (Kind != Immediate) 471 return false; 472 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 473 if (!CE) return false; 474 int64_t Value = CE->getValue(); 475 return Value >= 0 && Value < 32; 476 } 477 bool isPKHASRImm() const { 478 if (Kind != Immediate) 479 return false; 480 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 481 if (!CE) return false; 482 int64_t Value = CE->getValue(); 483 return Value > 0 && Value <= 32; 484 } 485 bool isARMSOImm() const { 486 if (Kind != Immediate) 487 return false; 488 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 489 if (!CE) return false; 490 int64_t Value = CE->getValue(); 491 return ARM_AM::getSOImmVal(Value) != -1; 492 } 493 bool isT2SOImm() const { 494 if (Kind != Immediate) 495 return false; 496 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 497 if (!CE) return false; 498 int64_t Value = CE->getValue(); 499 return ARM_AM::getT2SOImmVal(Value) != -1; 500 } 501 bool isSetEndImm() const { 502 if (Kind != Immediate) 503 return false; 504 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 505 if (!CE) return false; 506 int64_t Value = CE->getValue(); 507 return Value == 1 || Value == 0; 508 } 509 bool isReg() const { return Kind == Register; } 510 bool isRegList() const { return Kind == RegisterList; } 511 bool isDPRRegList() const { return Kind == DPRRegisterList; } 512 bool isSPRRegList() const { return Kind == SPRRegisterList; } 513 bool isToken() const { return Kind == Token; } 514 bool isMemBarrierOpt() const { return Kind == MemBarrierOpt; } 515 bool isMemory() const { return Kind == Memory; } 516 bool isShifterImm() const { return Kind == ShifterImmediate; } 517 bool isRegShiftedReg() const { return Kind == ShiftedRegister; } 518 bool isRegShiftedImm() const { return Kind == ShiftedImmediate; } 519 bool isRotImm() const { return Kind == RotateImmediate; } 520 bool isBitfield() const { return Kind == BitfieldDescriptor; } 521 bool isPostIdxRegShifted() const { return Kind == PostIndexRegister; } 522 bool isPostIdxReg() const { 523 return Kind == PostIndexRegister && PostIdxReg.ShiftTy == ARM_AM::no_shift; 524 } 525 bool isMemNoOffset() const { 526 if (Kind != Memory) 527 return false; 528 // No offset of any kind. 529 return Mem.OffsetRegNum == 0 && Mem.OffsetImm == 0; 530 } 531 bool isAddrMode2() const { 532 if (Kind != Memory) 533 return false; 534 // Check for register offset. 535 if (Mem.OffsetRegNum) return true; 536 // Immediate offset in range [-4095, 4095]. 537 if (!Mem.OffsetImm) return true; 538 int64_t Val = Mem.OffsetImm->getValue(); 539 return Val > -4096 && Val < 4096; 540 } 541 bool isAM2OffsetImm() const { 542 if (Kind != Immediate) 543 return false; 544 // Immediate offset in range [-4095, 4095]. 545 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 546 if (!CE) return false; 547 int64_t Val = CE->getValue(); 548 return Val > -4096 && Val < 4096; 549 } 550 bool isAddrMode3() const { 551 if (Kind != Memory) 552 return false; 553 // No shifts are legal for AM3. 554 if (Mem.ShiftType != ARM_AM::no_shift) return false; 555 // Check for register offset. 556 if (Mem.OffsetRegNum) return true; 557 // Immediate offset in range [-255, 255]. 558 if (!Mem.OffsetImm) return true; 559 int64_t Val = Mem.OffsetImm->getValue(); 560 return Val > -256 && Val < 256; 561 } 562 bool isAM3Offset() const { 563 if (Kind != Immediate && Kind != PostIndexRegister) 564 return false; 565 if (Kind == PostIndexRegister) 566 return PostIdxReg.ShiftTy == ARM_AM::no_shift; 567 // Immediate offset in range [-255, 255]. 568 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 569 if (!CE) return false; 570 int64_t Val = CE->getValue(); 571 // Special case, #-0 is INT32_MIN. 572 return (Val > -256 && Val < 256) || Val == INT32_MIN; 573 } 574 bool isAddrMode5() const { 575 if (Kind != Memory) 576 return false; 577 // Check for register offset. 578 if (Mem.OffsetRegNum) return false; 579 // Immediate offset in range [-1020, 1020] and a multiple of 4. 580 if (!Mem.OffsetImm) return true; 581 int64_t Val = Mem.OffsetImm->getValue(); 582 return Val >= -1020 && Val <= 1020 && ((Val & 3) == 0); 583 } 584 bool isMemRegOffset() const { 585 if (Kind != Memory || !Mem.OffsetRegNum) 586 return false; 587 return true; 588 } 589 bool isMemThumbRR() const { 590 // Thumb reg+reg addressing is simple. Just two registers, a base and 591 // an offset. No shifts, negations or any other complicating factors. 592 if (Kind != Memory || !Mem.OffsetRegNum || Mem.isNegative || 593 Mem.ShiftType != ARM_AM::no_shift) 594 return false; 595 return true; 596 } 597 bool isMemImm8Offset() const { 598 if (Kind != Memory || Mem.OffsetRegNum != 0) 599 return false; 600 // Immediate offset in range [-255, 255]. 601 if (!Mem.OffsetImm) return true; 602 int64_t Val = Mem.OffsetImm->getValue(); 603 return Val > -256 && Val < 256; 604 } 605 bool isMemImm12Offset() const { 606 // If we have an immediate that's not a constant, treat it as a label 607 // reference needing a fixup. If it is a constant, it's something else 608 // and we reject it. 609 if (Kind == Immediate && !isa<MCConstantExpr>(getImm())) 610 return true; 611 612 if (Kind != Memory || Mem.OffsetRegNum != 0) 613 return false; 614 // Immediate offset in range [-4095, 4095]. 615 if (!Mem.OffsetImm) return true; 616 int64_t Val = Mem.OffsetImm->getValue(); 617 return Val > -4096 && Val < 4096; 618 } 619 bool isPostIdxImm8() const { 620 if (Kind != Immediate) 621 return false; 622 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 623 if (!CE) return false; 624 int64_t Val = CE->getValue(); 625 return Val > -256 && Val < 256; 626 } 627 628 bool isMSRMask() const { return Kind == MSRMask; } 629 bool isProcIFlags() const { return Kind == ProcIFlags; } 630 631 void addExpr(MCInst &Inst, const MCExpr *Expr) const { 632 // Add as immediates when possible. Null MCExpr = 0. 633 if (Expr == 0) 634 Inst.addOperand(MCOperand::CreateImm(0)); 635 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr)) 636 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 637 else 638 Inst.addOperand(MCOperand::CreateExpr(Expr)); 639 } 640 641 void addCondCodeOperands(MCInst &Inst, unsigned N) const { 642 assert(N == 2 && "Invalid number of operands!"); 643 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); 644 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; 645 Inst.addOperand(MCOperand::CreateReg(RegNum)); 646 } 647 648 void addCoprocNumOperands(MCInst &Inst, unsigned N) const { 649 assert(N == 1 && "Invalid number of operands!"); 650 Inst.addOperand(MCOperand::CreateImm(getCoproc())); 651 } 652 653 void addCoprocRegOperands(MCInst &Inst, unsigned N) const { 654 assert(N == 1 && "Invalid number of operands!"); 655 Inst.addOperand(MCOperand::CreateImm(getCoproc())); 656 } 657 658 void addCCOutOperands(MCInst &Inst, unsigned N) const { 659 assert(N == 1 && "Invalid number of operands!"); 660 Inst.addOperand(MCOperand::CreateReg(getReg())); 661 } 662 663 void addRegOperands(MCInst &Inst, unsigned N) const { 664 assert(N == 1 && "Invalid number of operands!"); 665 Inst.addOperand(MCOperand::CreateReg(getReg())); 666 } 667 668 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const { 669 assert(N == 3 && "Invalid number of operands!"); 670 assert(isRegShiftedReg() && "addRegShiftedRegOperands() on non RegShiftedReg!"); 671 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg)); 672 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg)); 673 Inst.addOperand(MCOperand::CreateImm( 674 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm))); 675 } 676 677 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const { 678 assert(N == 2 && "Invalid number of operands!"); 679 assert(isRegShiftedImm() && "addRegShiftedImmOperands() on non RegShiftedImm!"); 680 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg)); 681 Inst.addOperand(MCOperand::CreateImm( 682 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm))); 683 } 684 685 686 void addShifterImmOperands(MCInst &Inst, unsigned N) const { 687 assert(N == 1 && "Invalid number of operands!"); 688 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) | 689 ShifterImm.Imm)); 690 } 691 692 void addRegListOperands(MCInst &Inst, unsigned N) const { 693 assert(N == 1 && "Invalid number of operands!"); 694 const SmallVectorImpl<unsigned> &RegList = getRegList(); 695 for (SmallVectorImpl<unsigned>::const_iterator 696 I = RegList.begin(), E = RegList.end(); I != E; ++I) 697 Inst.addOperand(MCOperand::CreateReg(*I)); 698 } 699 700 void addDPRRegListOperands(MCInst &Inst, unsigned N) const { 701 addRegListOperands(Inst, N); 702 } 703 704 void addSPRRegListOperands(MCInst &Inst, unsigned N) const { 705 addRegListOperands(Inst, N); 706 } 707 708 void addRotImmOperands(MCInst &Inst, unsigned N) const { 709 assert(N == 1 && "Invalid number of operands!"); 710 // Encoded as val>>3. The printer handles display as 8, 16, 24. 711 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3)); 712 } 713 714 void addBitfieldOperands(MCInst &Inst, unsigned N) const { 715 assert(N == 1 && "Invalid number of operands!"); 716 // Munge the lsb/width into a bitfield mask. 717 unsigned lsb = Bitfield.LSB; 718 unsigned width = Bitfield.Width; 719 // Make a 32-bit mask w/ the referenced bits clear and all other bits set. 720 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >> 721 (32 - (lsb + width))); 722 Inst.addOperand(MCOperand::CreateImm(Mask)); 723 } 724 725 void addImmOperands(MCInst &Inst, unsigned N) const { 726 assert(N == 1 && "Invalid number of operands!"); 727 addExpr(Inst, getImm()); 728 } 729 730 void addImm0_255Operands(MCInst &Inst, unsigned N) const { 731 assert(N == 1 && "Invalid number of operands!"); 732 addExpr(Inst, getImm()); 733 } 734 735 void addImm0_7Operands(MCInst &Inst, unsigned N) const { 736 assert(N == 1 && "Invalid number of operands!"); 737 addExpr(Inst, getImm()); 738 } 739 740 void addImm0_15Operands(MCInst &Inst, unsigned N) const { 741 assert(N == 1 && "Invalid number of operands!"); 742 addExpr(Inst, getImm()); 743 } 744 745 void addImm0_31Operands(MCInst &Inst, unsigned N) const { 746 assert(N == 1 && "Invalid number of operands!"); 747 addExpr(Inst, getImm()); 748 } 749 750 void addImm1_16Operands(MCInst &Inst, unsigned N) const { 751 assert(N == 1 && "Invalid number of operands!"); 752 // The constant encodes as the immediate-1, and we store in the instruction 753 // the bits as encoded, so subtract off one here. 754 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 755 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1)); 756 } 757 758 void addImm1_32Operands(MCInst &Inst, unsigned N) const { 759 assert(N == 1 && "Invalid number of operands!"); 760 // The constant encodes as the immediate-1, and we store in the instruction 761 // the bits as encoded, so subtract off one here. 762 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 763 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1)); 764 } 765 766 void addImm0_65535Operands(MCInst &Inst, unsigned N) const { 767 assert(N == 1 && "Invalid number of operands!"); 768 addExpr(Inst, getImm()); 769 } 770 771 void addImm0_65535ExprOperands(MCInst &Inst, unsigned N) const { 772 assert(N == 1 && "Invalid number of operands!"); 773 addExpr(Inst, getImm()); 774 } 775 776 void addImm24bitOperands(MCInst &Inst, unsigned N) const { 777 assert(N == 1 && "Invalid number of operands!"); 778 addExpr(Inst, getImm()); 779 } 780 781 void addPKHLSLImmOperands(MCInst &Inst, unsigned N) const { 782 assert(N == 1 && "Invalid number of operands!"); 783 addExpr(Inst, getImm()); 784 } 785 786 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const { 787 assert(N == 1 && "Invalid number of operands!"); 788 // An ASR value of 32 encodes as 0, so that's how we want to add it to 789 // the instruction as well. 790 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 791 int Val = CE->getValue(); 792 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val)); 793 } 794 795 void addARMSOImmOperands(MCInst &Inst, unsigned N) const { 796 assert(N == 1 && "Invalid number of operands!"); 797 addExpr(Inst, getImm()); 798 } 799 800 void addT2SOImmOperands(MCInst &Inst, unsigned N) const { 801 assert(N == 1 && "Invalid number of operands!"); 802 addExpr(Inst, getImm()); 803 } 804 805 void addSetEndImmOperands(MCInst &Inst, unsigned N) const { 806 assert(N == 1 && "Invalid number of operands!"); 807 addExpr(Inst, getImm()); 808 } 809 810 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const { 811 assert(N == 1 && "Invalid number of operands!"); 812 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt()))); 813 } 814 815 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const { 816 assert(N == 1 && "Invalid number of operands!"); 817 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum)); 818 } 819 820 void addAddrMode2Operands(MCInst &Inst, unsigned N) const { 821 assert(N == 3 && "Invalid number of operands!"); 822 int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0; 823 if (!Mem.OffsetRegNum) { 824 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 825 // Special case for #-0 826 if (Val == INT32_MIN) Val = 0; 827 if (Val < 0) Val = -Val; 828 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); 829 } else { 830 // For register offset, we encode the shift type and negation flag 831 // here. 832 Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add, 833 Mem.ShiftImm, Mem.ShiftType); 834 } 835 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum)); 836 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum)); 837 Inst.addOperand(MCOperand::CreateImm(Val)); 838 } 839 840 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const { 841 assert(N == 2 && "Invalid number of operands!"); 842 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 843 assert(CE && "non-constant AM2OffsetImm operand!"); 844 int32_t Val = CE->getValue(); 845 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 846 // Special case for #-0 847 if (Val == INT32_MIN) Val = 0; 848 if (Val < 0) Val = -Val; 849 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); 850 Inst.addOperand(MCOperand::CreateReg(0)); 851 Inst.addOperand(MCOperand::CreateImm(Val)); 852 } 853 854 void addAddrMode3Operands(MCInst &Inst, unsigned N) const { 855 assert(N == 3 && "Invalid number of operands!"); 856 int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0; 857 if (!Mem.OffsetRegNum) { 858 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 859 // Special case for #-0 860 if (Val == INT32_MIN) Val = 0; 861 if (Val < 0) Val = -Val; 862 Val = ARM_AM::getAM3Opc(AddSub, Val); 863 } else { 864 // For register offset, we encode the shift type and negation flag 865 // here. 866 Val = ARM_AM::getAM3Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add, 0); 867 } 868 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum)); 869 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum)); 870 Inst.addOperand(MCOperand::CreateImm(Val)); 871 } 872 873 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const { 874 assert(N == 2 && "Invalid number of operands!"); 875 if (Kind == PostIndexRegister) { 876 int32_t Val = 877 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0); 878 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 879 Inst.addOperand(MCOperand::CreateImm(Val)); 880 return; 881 } 882 883 // Constant offset. 884 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm()); 885 int32_t Val = CE->getValue(); 886 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 887 // Special case for #-0 888 if (Val == INT32_MIN) Val = 0; 889 if (Val < 0) Val = -Val; 890 Val = ARM_AM::getAM3Opc(AddSub, Val); 891 Inst.addOperand(MCOperand::CreateReg(0)); 892 Inst.addOperand(MCOperand::CreateImm(Val)); 893 } 894 895 void addAddrMode5Operands(MCInst &Inst, unsigned N) const { 896 assert(N == 2 && "Invalid number of operands!"); 897 // The lower two bits are always zero and as such are not encoded. 898 int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() / 4 : 0; 899 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 900 // Special case for #-0 901 if (Val == INT32_MIN) Val = 0; 902 if (Val < 0) Val = -Val; 903 Val = ARM_AM::getAM5Opc(AddSub, Val); 904 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum)); 905 Inst.addOperand(MCOperand::CreateImm(Val)); 906 } 907 908 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const { 909 assert(N == 2 && "Invalid number of operands!"); 910 int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0; 911 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum)); 912 Inst.addOperand(MCOperand::CreateImm(Val)); 913 } 914 915 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const { 916 assert(N == 2 && "Invalid number of operands!"); 917 // If this is an immediate, it's a label reference. 918 if (Kind == Immediate) { 919 addExpr(Inst, getImm()); 920 Inst.addOperand(MCOperand::CreateImm(0)); 921 return; 922 } 923 924 // Otherwise, it's a normal memory reg+offset. 925 int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0; 926 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum)); 927 Inst.addOperand(MCOperand::CreateImm(Val)); 928 } 929 930 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const { 931 assert(N == 3 && "Invalid number of operands!"); 932 unsigned Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add, 933 Mem.ShiftImm, Mem.ShiftType); 934 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum)); 935 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum)); 936 Inst.addOperand(MCOperand::CreateImm(Val)); 937 } 938 939 void addMemThumbRROperands(MCInst &Inst, unsigned N) const { 940 assert(N == 2 && "Invalid number of operands!"); 941 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum)); 942 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum)); 943 } 944 945 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const { 946 assert(N == 1 && "Invalid number of operands!"); 947 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 948 assert(CE && "non-constant post-idx-imm8 operand!"); 949 int Imm = CE->getValue(); 950 bool isAdd = Imm >= 0; 951 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8; 952 Inst.addOperand(MCOperand::CreateImm(Imm)); 953 } 954 955 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const { 956 assert(N == 2 && "Invalid number of operands!"); 957 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 958 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd)); 959 } 960 961 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const { 962 assert(N == 2 && "Invalid number of operands!"); 963 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 964 // The sign, shift type, and shift amount are encoded in a single operand 965 // using the AM2 encoding helpers. 966 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub; 967 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm, 968 PostIdxReg.ShiftTy); 969 Inst.addOperand(MCOperand::CreateImm(Imm)); 970 } 971 972 void addMSRMaskOperands(MCInst &Inst, unsigned N) const { 973 assert(N == 1 && "Invalid number of operands!"); 974 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask()))); 975 } 976 977 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const { 978 assert(N == 1 && "Invalid number of operands!"); 979 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags()))); 980 } 981 982 virtual void print(raw_ostream &OS) const; 983 984 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) { 985 ARMOperand *Op = new ARMOperand(CondCode); 986 Op->CC.Val = CC; 987 Op->StartLoc = S; 988 Op->EndLoc = S; 989 return Op; 990 } 991 992 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) { 993 ARMOperand *Op = new ARMOperand(CoprocNum); 994 Op->Cop.Val = CopVal; 995 Op->StartLoc = S; 996 Op->EndLoc = S; 997 return Op; 998 } 999 1000 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) { 1001 ARMOperand *Op = new ARMOperand(CoprocReg); 1002 Op->Cop.Val = CopVal; 1003 Op->StartLoc = S; 1004 Op->EndLoc = S; 1005 return Op; 1006 } 1007 1008 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) { 1009 ARMOperand *Op = new ARMOperand(CCOut); 1010 Op->Reg.RegNum = RegNum; 1011 Op->StartLoc = S; 1012 Op->EndLoc = S; 1013 return Op; 1014 } 1015 1016 static ARMOperand *CreateToken(StringRef Str, SMLoc S) { 1017 ARMOperand *Op = new ARMOperand(Token); 1018 Op->Tok.Data = Str.data(); 1019 Op->Tok.Length = Str.size(); 1020 Op->StartLoc = S; 1021 Op->EndLoc = S; 1022 return Op; 1023 } 1024 1025 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) { 1026 ARMOperand *Op = new ARMOperand(Register); 1027 Op->Reg.RegNum = RegNum; 1028 Op->StartLoc = S; 1029 Op->EndLoc = E; 1030 return Op; 1031 } 1032 1033 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, 1034 unsigned SrcReg, 1035 unsigned ShiftReg, 1036 unsigned ShiftImm, 1037 SMLoc S, SMLoc E) { 1038 ARMOperand *Op = new ARMOperand(ShiftedRegister); 1039 Op->RegShiftedReg.ShiftTy = ShTy; 1040 Op->RegShiftedReg.SrcReg = SrcReg; 1041 Op->RegShiftedReg.ShiftReg = ShiftReg; 1042 Op->RegShiftedReg.ShiftImm = ShiftImm; 1043 Op->StartLoc = S; 1044 Op->EndLoc = E; 1045 return Op; 1046 } 1047 1048 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, 1049 unsigned SrcReg, 1050 unsigned ShiftImm, 1051 SMLoc S, SMLoc E) { 1052 ARMOperand *Op = new ARMOperand(ShiftedImmediate); 1053 Op->RegShiftedImm.ShiftTy = ShTy; 1054 Op->RegShiftedImm.SrcReg = SrcReg; 1055 Op->RegShiftedImm.ShiftImm = ShiftImm; 1056 Op->StartLoc = S; 1057 Op->EndLoc = E; 1058 return Op; 1059 } 1060 1061 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm, 1062 SMLoc S, SMLoc E) { 1063 ARMOperand *Op = new ARMOperand(ShifterImmediate); 1064 Op->ShifterImm.isASR = isASR; 1065 Op->ShifterImm.Imm = Imm; 1066 Op->StartLoc = S; 1067 Op->EndLoc = E; 1068 return Op; 1069 } 1070 1071 static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) { 1072 ARMOperand *Op = new ARMOperand(RotateImmediate); 1073 Op->RotImm.Imm = Imm; 1074 Op->StartLoc = S; 1075 Op->EndLoc = E; 1076 return Op; 1077 } 1078 1079 static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width, 1080 SMLoc S, SMLoc E) { 1081 ARMOperand *Op = new ARMOperand(BitfieldDescriptor); 1082 Op->Bitfield.LSB = LSB; 1083 Op->Bitfield.Width = Width; 1084 Op->StartLoc = S; 1085 Op->EndLoc = E; 1086 return Op; 1087 } 1088 1089 static ARMOperand * 1090 CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs, 1091 SMLoc StartLoc, SMLoc EndLoc) { 1092 KindTy Kind = RegisterList; 1093 1094 if (llvm::ARMMCRegisterClasses[ARM::DPRRegClassID]. 1095 contains(Regs.front().first)) 1096 Kind = DPRRegisterList; 1097 else if (llvm::ARMMCRegisterClasses[ARM::SPRRegClassID]. 1098 contains(Regs.front().first)) 1099 Kind = SPRRegisterList; 1100 1101 ARMOperand *Op = new ARMOperand(Kind); 1102 for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator 1103 I = Regs.begin(), E = Regs.end(); I != E; ++I) 1104 Op->Registers.push_back(I->first); 1105 array_pod_sort(Op->Registers.begin(), Op->Registers.end()); 1106 Op->StartLoc = StartLoc; 1107 Op->EndLoc = EndLoc; 1108 return Op; 1109 } 1110 1111 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) { 1112 ARMOperand *Op = new ARMOperand(Immediate); 1113 Op->Imm.Val = Val; 1114 Op->StartLoc = S; 1115 Op->EndLoc = E; 1116 return Op; 1117 } 1118 1119 static ARMOperand *CreateMem(unsigned BaseRegNum, 1120 const MCConstantExpr *OffsetImm, 1121 unsigned OffsetRegNum, 1122 ARM_AM::ShiftOpc ShiftType, 1123 unsigned ShiftImm, 1124 bool isNegative, 1125 SMLoc S, SMLoc E) { 1126 ARMOperand *Op = new ARMOperand(Memory); 1127 Op->Mem.BaseRegNum = BaseRegNum; 1128 Op->Mem.OffsetImm = OffsetImm; 1129 Op->Mem.OffsetRegNum = OffsetRegNum; 1130 Op->Mem.ShiftType = ShiftType; 1131 Op->Mem.ShiftImm = ShiftImm; 1132 Op->Mem.isNegative = isNegative; 1133 Op->StartLoc = S; 1134 Op->EndLoc = E; 1135 return Op; 1136 } 1137 1138 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd, 1139 ARM_AM::ShiftOpc ShiftTy, 1140 unsigned ShiftImm, 1141 SMLoc S, SMLoc E) { 1142 ARMOperand *Op = new ARMOperand(PostIndexRegister); 1143 Op->PostIdxReg.RegNum = RegNum; 1144 Op->PostIdxReg.isAdd = isAdd; 1145 Op->PostIdxReg.ShiftTy = ShiftTy; 1146 Op->PostIdxReg.ShiftImm = ShiftImm; 1147 Op->StartLoc = S; 1148 Op->EndLoc = E; 1149 return Op; 1150 } 1151 1152 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) { 1153 ARMOperand *Op = new ARMOperand(MemBarrierOpt); 1154 Op->MBOpt.Val = Opt; 1155 Op->StartLoc = S; 1156 Op->EndLoc = S; 1157 return Op; 1158 } 1159 1160 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) { 1161 ARMOperand *Op = new ARMOperand(ProcIFlags); 1162 Op->IFlags.Val = IFlags; 1163 Op->StartLoc = S; 1164 Op->EndLoc = S; 1165 return Op; 1166 } 1167 1168 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) { 1169 ARMOperand *Op = new ARMOperand(MSRMask); 1170 Op->MMask.Val = MMask; 1171 Op->StartLoc = S; 1172 Op->EndLoc = S; 1173 return Op; 1174 } 1175}; 1176 1177} // end anonymous namespace. 1178 1179void ARMOperand::print(raw_ostream &OS) const { 1180 switch (Kind) { 1181 case CondCode: 1182 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">"; 1183 break; 1184 case CCOut: 1185 OS << "<ccout " << getReg() << ">"; 1186 break; 1187 case CoprocNum: 1188 OS << "<coprocessor number: " << getCoproc() << ">"; 1189 break; 1190 case CoprocReg: 1191 OS << "<coprocessor register: " << getCoproc() << ">"; 1192 break; 1193 case MSRMask: 1194 OS << "<mask: " << getMSRMask() << ">"; 1195 break; 1196 case Immediate: 1197 getImm()->print(OS); 1198 break; 1199 case MemBarrierOpt: 1200 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">"; 1201 break; 1202 case Memory: 1203 OS << "<memory " 1204 << " base:" << Mem.BaseRegNum; 1205 OS << ">"; 1206 break; 1207 case PostIndexRegister: 1208 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-") 1209 << PostIdxReg.RegNum; 1210 if (PostIdxReg.ShiftTy != ARM_AM::no_shift) 1211 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " " 1212 << PostIdxReg.ShiftImm; 1213 OS << ">"; 1214 break; 1215 case ProcIFlags: { 1216 OS << "<ARM_PROC::"; 1217 unsigned IFlags = getProcIFlags(); 1218 for (int i=2; i >= 0; --i) 1219 if (IFlags & (1 << i)) 1220 OS << ARM_PROC::IFlagsToString(1 << i); 1221 OS << ">"; 1222 break; 1223 } 1224 case Register: 1225 OS << "<register " << getReg() << ">"; 1226 break; 1227 case ShifterImmediate: 1228 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl") 1229 << " #" << ShifterImm.Imm << ">"; 1230 break; 1231 case ShiftedRegister: 1232 OS << "<so_reg_reg " 1233 << RegShiftedReg.SrcReg 1234 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedReg.ShiftImm)) 1235 << ", " << RegShiftedReg.ShiftReg << ", " 1236 << ARM_AM::getSORegOffset(RegShiftedReg.ShiftImm) 1237 << ">"; 1238 break; 1239 case ShiftedImmediate: 1240 OS << "<so_reg_imm " 1241 << RegShiftedImm.SrcReg 1242 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedImm.ShiftImm)) 1243 << ", " << ARM_AM::getSORegOffset(RegShiftedImm.ShiftImm) 1244 << ">"; 1245 break; 1246 case RotateImmediate: 1247 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">"; 1248 break; 1249 case BitfieldDescriptor: 1250 OS << "<bitfield " << "lsb: " << Bitfield.LSB 1251 << ", width: " << Bitfield.Width << ">"; 1252 break; 1253 case RegisterList: 1254 case DPRRegisterList: 1255 case SPRRegisterList: { 1256 OS << "<register_list "; 1257 1258 const SmallVectorImpl<unsigned> &RegList = getRegList(); 1259 for (SmallVectorImpl<unsigned>::const_iterator 1260 I = RegList.begin(), E = RegList.end(); I != E; ) { 1261 OS << *I; 1262 if (++I < E) OS << ", "; 1263 } 1264 1265 OS << ">"; 1266 break; 1267 } 1268 case Token: 1269 OS << "'" << getToken() << "'"; 1270 break; 1271 } 1272} 1273 1274/// @name Auto-generated Match Functions 1275/// { 1276 1277static unsigned MatchRegisterName(StringRef Name); 1278 1279/// } 1280 1281bool ARMAsmParser::ParseRegister(unsigned &RegNo, 1282 SMLoc &StartLoc, SMLoc &EndLoc) { 1283 RegNo = tryParseRegister(); 1284 1285 return (RegNo == (unsigned)-1); 1286} 1287 1288/// Try to parse a register name. The token must be an Identifier when called, 1289/// and if it is a register name the token is eaten and the register number is 1290/// returned. Otherwise return -1. 1291/// 1292int ARMAsmParser::tryParseRegister() { 1293 const AsmToken &Tok = Parser.getTok(); 1294 if (Tok.isNot(AsmToken::Identifier)) return -1; 1295 1296 // FIXME: Validate register for the current architecture; we have to do 1297 // validation later, so maybe there is no need for this here. 1298 std::string upperCase = Tok.getString().str(); 1299 std::string lowerCase = LowercaseString(upperCase); 1300 unsigned RegNum = MatchRegisterName(lowerCase); 1301 if (!RegNum) { 1302 RegNum = StringSwitch<unsigned>(lowerCase) 1303 .Case("r13", ARM::SP) 1304 .Case("r14", ARM::LR) 1305 .Case("r15", ARM::PC) 1306 .Case("ip", ARM::R12) 1307 .Default(0); 1308 } 1309 if (!RegNum) return -1; 1310 1311 Parser.Lex(); // Eat identifier token. 1312 return RegNum; 1313} 1314 1315// Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0. 1316// If a recoverable error occurs, return 1. If an irrecoverable error 1317// occurs, return -1. An irrecoverable error is one where tokens have been 1318// consumed in the process of trying to parse the shifter (i.e., when it is 1319// indeed a shifter operand, but malformed). 1320int ARMAsmParser::tryParseShiftRegister( 1321 SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1322 SMLoc S = Parser.getTok().getLoc(); 1323 const AsmToken &Tok = Parser.getTok(); 1324 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 1325 1326 std::string upperCase = Tok.getString().str(); 1327 std::string lowerCase = LowercaseString(upperCase); 1328 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase) 1329 .Case("lsl", ARM_AM::lsl) 1330 .Case("lsr", ARM_AM::lsr) 1331 .Case("asr", ARM_AM::asr) 1332 .Case("ror", ARM_AM::ror) 1333 .Case("rrx", ARM_AM::rrx) 1334 .Default(ARM_AM::no_shift); 1335 1336 if (ShiftTy == ARM_AM::no_shift) 1337 return 1; 1338 1339 Parser.Lex(); // Eat the operator. 1340 1341 // The source register for the shift has already been added to the 1342 // operand list, so we need to pop it off and combine it into the shifted 1343 // register operand instead. 1344 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val()); 1345 if (!PrevOp->isReg()) 1346 return Error(PrevOp->getStartLoc(), "shift must be of a register"); 1347 int SrcReg = PrevOp->getReg(); 1348 int64_t Imm = 0; 1349 int ShiftReg = 0; 1350 if (ShiftTy == ARM_AM::rrx) { 1351 // RRX Doesn't have an explicit shift amount. The encoder expects 1352 // the shift register to be the same as the source register. Seems odd, 1353 // but OK. 1354 ShiftReg = SrcReg; 1355 } else { 1356 // Figure out if this is shifted by a constant or a register (for non-RRX). 1357 if (Parser.getTok().is(AsmToken::Hash)) { 1358 Parser.Lex(); // Eat hash. 1359 SMLoc ImmLoc = Parser.getTok().getLoc(); 1360 const MCExpr *ShiftExpr = 0; 1361 if (getParser().ParseExpression(ShiftExpr)) { 1362 Error(ImmLoc, "invalid immediate shift value"); 1363 return -1; 1364 } 1365 // The expression must be evaluatable as an immediate. 1366 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr); 1367 if (!CE) { 1368 Error(ImmLoc, "invalid immediate shift value"); 1369 return -1; 1370 } 1371 // Range check the immediate. 1372 // lsl, ror: 0 <= imm <= 31 1373 // lsr, asr: 0 <= imm <= 32 1374 Imm = CE->getValue(); 1375 if (Imm < 0 || 1376 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) || 1377 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) { 1378 Error(ImmLoc, "immediate shift value out of range"); 1379 return -1; 1380 } 1381 } else if (Parser.getTok().is(AsmToken::Identifier)) { 1382 ShiftReg = tryParseRegister(); 1383 SMLoc L = Parser.getTok().getLoc(); 1384 if (ShiftReg == -1) { 1385 Error (L, "expected immediate or register in shift operand"); 1386 return -1; 1387 } 1388 } else { 1389 Error (Parser.getTok().getLoc(), 1390 "expected immediate or register in shift operand"); 1391 return -1; 1392 } 1393 } 1394 1395 if (ShiftReg && ShiftTy != ARM_AM::rrx) 1396 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg, 1397 ShiftReg, Imm, 1398 S, Parser.getTok().getLoc())); 1399 else 1400 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm, 1401 S, Parser.getTok().getLoc())); 1402 1403 return 0; 1404} 1405 1406 1407/// Try to parse a register name. The token must be an Identifier when called. 1408/// If it's a register, an AsmOperand is created. Another AsmOperand is created 1409/// if there is a "writeback". 'true' if it's not a register. 1410/// 1411/// TODO this is likely to change to allow different register types and or to 1412/// parse for a specific register type. 1413bool ARMAsmParser:: 1414tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1415 SMLoc S = Parser.getTok().getLoc(); 1416 int RegNo = tryParseRegister(); 1417 if (RegNo == -1) 1418 return true; 1419 1420 Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc())); 1421 1422 const AsmToken &ExclaimTok = Parser.getTok(); 1423 if (ExclaimTok.is(AsmToken::Exclaim)) { 1424 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(), 1425 ExclaimTok.getLoc())); 1426 Parser.Lex(); // Eat exclaim token 1427 } 1428 1429 return false; 1430} 1431 1432/// MatchCoprocessorOperandName - Try to parse an coprocessor related 1433/// instruction with a symbolic operand name. Example: "p1", "p7", "c3", 1434/// "c5", ... 1435static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) { 1436 // Use the same layout as the tablegen'erated register name matcher. Ugly, 1437 // but efficient. 1438 switch (Name.size()) { 1439 default: break; 1440 case 2: 1441 if (Name[0] != CoprocOp) 1442 return -1; 1443 switch (Name[1]) { 1444 default: return -1; 1445 case '0': return 0; 1446 case '1': return 1; 1447 case '2': return 2; 1448 case '3': return 3; 1449 case '4': return 4; 1450 case '5': return 5; 1451 case '6': return 6; 1452 case '7': return 7; 1453 case '8': return 8; 1454 case '9': return 9; 1455 } 1456 break; 1457 case 3: 1458 if (Name[0] != CoprocOp || Name[1] != '1') 1459 return -1; 1460 switch (Name[2]) { 1461 default: return -1; 1462 case '0': return 10; 1463 case '1': return 11; 1464 case '2': return 12; 1465 case '3': return 13; 1466 case '4': return 14; 1467 case '5': return 15; 1468 } 1469 break; 1470 } 1471 1472 return -1; 1473} 1474 1475/// parseCoprocNumOperand - Try to parse an coprocessor number operand. The 1476/// token must be an Identifier when called, and if it is a coprocessor 1477/// number, the token is eaten and the operand is added to the operand list. 1478ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 1479parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1480 SMLoc S = Parser.getTok().getLoc(); 1481 const AsmToken &Tok = Parser.getTok(); 1482 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 1483 1484 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p'); 1485 if (Num == -1) 1486 return MatchOperand_NoMatch; 1487 1488 Parser.Lex(); // Eat identifier token. 1489 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S)); 1490 return MatchOperand_Success; 1491} 1492 1493/// parseCoprocRegOperand - Try to parse an coprocessor register operand. The 1494/// token must be an Identifier when called, and if it is a coprocessor 1495/// number, the token is eaten and the operand is added to the operand list. 1496ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 1497parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1498 SMLoc S = Parser.getTok().getLoc(); 1499 const AsmToken &Tok = Parser.getTok(); 1500 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 1501 1502 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c'); 1503 if (Reg == -1) 1504 return MatchOperand_NoMatch; 1505 1506 Parser.Lex(); // Eat identifier token. 1507 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S)); 1508 return MatchOperand_Success; 1509} 1510 1511/// Parse a register list, return it if successful else return null. The first 1512/// token must be a '{' when called. 1513bool ARMAsmParser:: 1514parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1515 assert(Parser.getTok().is(AsmToken::LCurly) && 1516 "Token is not a Left Curly Brace"); 1517 SMLoc S = Parser.getTok().getLoc(); 1518 1519 // Read the rest of the registers in the list. 1520 unsigned PrevRegNum = 0; 1521 SmallVector<std::pair<unsigned, SMLoc>, 32> Registers; 1522 1523 do { 1524 bool IsRange = Parser.getTok().is(AsmToken::Minus); 1525 Parser.Lex(); // Eat non-identifier token. 1526 1527 const AsmToken &RegTok = Parser.getTok(); 1528 SMLoc RegLoc = RegTok.getLoc(); 1529 if (RegTok.isNot(AsmToken::Identifier)) { 1530 Error(RegLoc, "register expected"); 1531 return true; 1532 } 1533 1534 int RegNum = tryParseRegister(); 1535 if (RegNum == -1) { 1536 Error(RegLoc, "register expected"); 1537 return true; 1538 } 1539 1540 if (IsRange) { 1541 int Reg = PrevRegNum; 1542 do { 1543 ++Reg; 1544 Registers.push_back(std::make_pair(Reg, RegLoc)); 1545 } while (Reg != RegNum); 1546 } else { 1547 Registers.push_back(std::make_pair(RegNum, RegLoc)); 1548 } 1549 1550 PrevRegNum = RegNum; 1551 } while (Parser.getTok().is(AsmToken::Comma) || 1552 Parser.getTok().is(AsmToken::Minus)); 1553 1554 // Process the right curly brace of the list. 1555 const AsmToken &RCurlyTok = Parser.getTok(); 1556 if (RCurlyTok.isNot(AsmToken::RCurly)) { 1557 Error(RCurlyTok.getLoc(), "'}' expected"); 1558 return true; 1559 } 1560 1561 SMLoc E = RCurlyTok.getLoc(); 1562 Parser.Lex(); // Eat right curly brace token. 1563 1564 // Verify the register list. 1565 SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator 1566 RI = Registers.begin(), RE = Registers.end(); 1567 1568 unsigned HighRegNum = getARMRegisterNumbering(RI->first); 1569 bool EmittedWarning = false; 1570 1571 DenseMap<unsigned, bool> RegMap; 1572 RegMap[HighRegNum] = true; 1573 1574 for (++RI; RI != RE; ++RI) { 1575 const std::pair<unsigned, SMLoc> &RegInfo = *RI; 1576 unsigned Reg = getARMRegisterNumbering(RegInfo.first); 1577 1578 if (RegMap[Reg]) { 1579 Error(RegInfo.second, "register duplicated in register list"); 1580 return true; 1581 } 1582 1583 if (!EmittedWarning && Reg < HighRegNum) 1584 Warning(RegInfo.second, 1585 "register not in ascending order in register list"); 1586 1587 RegMap[Reg] = true; 1588 HighRegNum = std::max(Reg, HighRegNum); 1589 } 1590 1591 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E)); 1592 return false; 1593} 1594 1595/// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options. 1596ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 1597parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1598 SMLoc S = Parser.getTok().getLoc(); 1599 const AsmToken &Tok = Parser.getTok(); 1600 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 1601 StringRef OptStr = Tok.getString(); 1602 1603 unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size())) 1604 .Case("sy", ARM_MB::SY) 1605 .Case("st", ARM_MB::ST) 1606 .Case("sh", ARM_MB::ISH) 1607 .Case("ish", ARM_MB::ISH) 1608 .Case("shst", ARM_MB::ISHST) 1609 .Case("ishst", ARM_MB::ISHST) 1610 .Case("nsh", ARM_MB::NSH) 1611 .Case("un", ARM_MB::NSH) 1612 .Case("nshst", ARM_MB::NSHST) 1613 .Case("unst", ARM_MB::NSHST) 1614 .Case("osh", ARM_MB::OSH) 1615 .Case("oshst", ARM_MB::OSHST) 1616 .Default(~0U); 1617 1618 if (Opt == ~0U) 1619 return MatchOperand_NoMatch; 1620 1621 Parser.Lex(); // Eat identifier token. 1622 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S)); 1623 return MatchOperand_Success; 1624} 1625 1626/// parseProcIFlagsOperand - Try to parse iflags from CPS instruction. 1627ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 1628parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1629 SMLoc S = Parser.getTok().getLoc(); 1630 const AsmToken &Tok = Parser.getTok(); 1631 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 1632 StringRef IFlagsStr = Tok.getString(); 1633 1634 unsigned IFlags = 0; 1635 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) { 1636 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1)) 1637 .Case("a", ARM_PROC::A) 1638 .Case("i", ARM_PROC::I) 1639 .Case("f", ARM_PROC::F) 1640 .Default(~0U); 1641 1642 // If some specific iflag is already set, it means that some letter is 1643 // present more than once, this is not acceptable. 1644 if (Flag == ~0U || (IFlags & Flag)) 1645 return MatchOperand_NoMatch; 1646 1647 IFlags |= Flag; 1648 } 1649 1650 Parser.Lex(); // Eat identifier token. 1651 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S)); 1652 return MatchOperand_Success; 1653} 1654 1655/// parseMSRMaskOperand - Try to parse mask flags from MSR instruction. 1656ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 1657parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1658 SMLoc S = Parser.getTok().getLoc(); 1659 const AsmToken &Tok = Parser.getTok(); 1660 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 1661 StringRef Mask = Tok.getString(); 1662 1663 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf" 1664 size_t Start = 0, Next = Mask.find('_'); 1665 StringRef Flags = ""; 1666 std::string SpecReg = LowercaseString(Mask.slice(Start, Next)); 1667 if (Next != StringRef::npos) 1668 Flags = Mask.slice(Next+1, Mask.size()); 1669 1670 // FlagsVal contains the complete mask: 1671 // 3-0: Mask 1672 // 4: Special Reg (cpsr, apsr => 0; spsr => 1) 1673 unsigned FlagsVal = 0; 1674 1675 if (SpecReg == "apsr") { 1676 FlagsVal = StringSwitch<unsigned>(Flags) 1677 .Case("nzcvq", 0x8) // same as CPSR_f 1678 .Case("g", 0x4) // same as CPSR_s 1679 .Case("nzcvqg", 0xc) // same as CPSR_fs 1680 .Default(~0U); 1681 1682 if (FlagsVal == ~0U) { 1683 if (!Flags.empty()) 1684 return MatchOperand_NoMatch; 1685 else 1686 FlagsVal = 0; // No flag 1687 } 1688 } else if (SpecReg == "cpsr" || SpecReg == "spsr") { 1689 if (Flags == "all") // cpsr_all is an alias for cpsr_fc 1690 Flags = "fc"; 1691 for (int i = 0, e = Flags.size(); i != e; ++i) { 1692 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1)) 1693 .Case("c", 1) 1694 .Case("x", 2) 1695 .Case("s", 4) 1696 .Case("f", 8) 1697 .Default(~0U); 1698 1699 // If some specific flag is already set, it means that some letter is 1700 // present more than once, this is not acceptable. 1701 if (FlagsVal == ~0U || (FlagsVal & Flag)) 1702 return MatchOperand_NoMatch; 1703 FlagsVal |= Flag; 1704 } 1705 } else // No match for special register. 1706 return MatchOperand_NoMatch; 1707 1708 // Special register without flags are equivalent to "fc" flags. 1709 if (!FlagsVal) 1710 FlagsVal = 0x9; 1711 1712 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1) 1713 if (SpecReg == "spsr") 1714 FlagsVal |= 16; 1715 1716 Parser.Lex(); // Eat identifier token. 1717 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); 1718 return MatchOperand_Success; 1719} 1720 1721ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 1722parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op, 1723 int Low, int High) { 1724 const AsmToken &Tok = Parser.getTok(); 1725 if (Tok.isNot(AsmToken::Identifier)) { 1726 Error(Parser.getTok().getLoc(), Op + " operand expected."); 1727 return MatchOperand_ParseFail; 1728 } 1729 StringRef ShiftName = Tok.getString(); 1730 std::string LowerOp = LowercaseString(Op); 1731 std::string UpperOp = UppercaseString(Op); 1732 if (ShiftName != LowerOp && ShiftName != UpperOp) { 1733 Error(Parser.getTok().getLoc(), Op + " operand expected."); 1734 return MatchOperand_ParseFail; 1735 } 1736 Parser.Lex(); // Eat shift type token. 1737 1738 // There must be a '#' and a shift amount. 1739 if (Parser.getTok().isNot(AsmToken::Hash)) { 1740 Error(Parser.getTok().getLoc(), "'#' expected"); 1741 return MatchOperand_ParseFail; 1742 } 1743 Parser.Lex(); // Eat hash token. 1744 1745 const MCExpr *ShiftAmount; 1746 SMLoc Loc = Parser.getTok().getLoc(); 1747 if (getParser().ParseExpression(ShiftAmount)) { 1748 Error(Loc, "illegal expression"); 1749 return MatchOperand_ParseFail; 1750 } 1751 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 1752 if (!CE) { 1753 Error(Loc, "constant expression expected"); 1754 return MatchOperand_ParseFail; 1755 } 1756 int Val = CE->getValue(); 1757 if (Val < Low || Val > High) { 1758 Error(Loc, "immediate value out of range"); 1759 return MatchOperand_ParseFail; 1760 } 1761 1762 Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc())); 1763 1764 return MatchOperand_Success; 1765} 1766 1767ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 1768parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1769 const AsmToken &Tok = Parser.getTok(); 1770 SMLoc S = Tok.getLoc(); 1771 if (Tok.isNot(AsmToken::Identifier)) { 1772 Error(Tok.getLoc(), "'be' or 'le' operand expected"); 1773 return MatchOperand_ParseFail; 1774 } 1775 int Val = StringSwitch<int>(Tok.getString()) 1776 .Case("be", 1) 1777 .Case("le", 0) 1778 .Default(-1); 1779 Parser.Lex(); // Eat the token. 1780 1781 if (Val == -1) { 1782 Error(Tok.getLoc(), "'be' or 'le' operand expected"); 1783 return MatchOperand_ParseFail; 1784 } 1785 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val, 1786 getContext()), 1787 S, Parser.getTok().getLoc())); 1788 return MatchOperand_Success; 1789} 1790 1791/// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT 1792/// instructions. Legal values are: 1793/// lsl #n 'n' in [0,31] 1794/// asr #n 'n' in [1,32] 1795/// n == 32 encoded as n == 0. 1796ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 1797parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1798 const AsmToken &Tok = Parser.getTok(); 1799 SMLoc S = Tok.getLoc(); 1800 if (Tok.isNot(AsmToken::Identifier)) { 1801 Error(S, "shift operator 'asr' or 'lsl' expected"); 1802 return MatchOperand_ParseFail; 1803 } 1804 StringRef ShiftName = Tok.getString(); 1805 bool isASR; 1806 if (ShiftName == "lsl" || ShiftName == "LSL") 1807 isASR = false; 1808 else if (ShiftName == "asr" || ShiftName == "ASR") 1809 isASR = true; 1810 else { 1811 Error(S, "shift operator 'asr' or 'lsl' expected"); 1812 return MatchOperand_ParseFail; 1813 } 1814 Parser.Lex(); // Eat the operator. 1815 1816 // A '#' and a shift amount. 1817 if (Parser.getTok().isNot(AsmToken::Hash)) { 1818 Error(Parser.getTok().getLoc(), "'#' expected"); 1819 return MatchOperand_ParseFail; 1820 } 1821 Parser.Lex(); // Eat hash token. 1822 1823 const MCExpr *ShiftAmount; 1824 SMLoc E = Parser.getTok().getLoc(); 1825 if (getParser().ParseExpression(ShiftAmount)) { 1826 Error(E, "malformed shift expression"); 1827 return MatchOperand_ParseFail; 1828 } 1829 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 1830 if (!CE) { 1831 Error(E, "shift amount must be an immediate"); 1832 return MatchOperand_ParseFail; 1833 } 1834 1835 int64_t Val = CE->getValue(); 1836 if (isASR) { 1837 // Shift amount must be in [1,32] 1838 if (Val < 1 || Val > 32) { 1839 Error(E, "'asr' shift amount must be in range [1,32]"); 1840 return MatchOperand_ParseFail; 1841 } 1842 // asr #32 encoded as asr #0. 1843 if (Val == 32) Val = 0; 1844 } else { 1845 // Shift amount must be in [1,32] 1846 if (Val < 0 || Val > 31) { 1847 Error(E, "'lsr' shift amount must be in range [0,31]"); 1848 return MatchOperand_ParseFail; 1849 } 1850 } 1851 1852 E = Parser.getTok().getLoc(); 1853 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E)); 1854 1855 return MatchOperand_Success; 1856} 1857 1858/// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family 1859/// of instructions. Legal values are: 1860/// ror #n 'n' in {0, 8, 16, 24} 1861ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 1862parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1863 const AsmToken &Tok = Parser.getTok(); 1864 SMLoc S = Tok.getLoc(); 1865 if (Tok.isNot(AsmToken::Identifier)) { 1866 Error(S, "rotate operator 'ror' expected"); 1867 return MatchOperand_ParseFail; 1868 } 1869 StringRef ShiftName = Tok.getString(); 1870 if (ShiftName != "ror" && ShiftName != "ROR") { 1871 Error(S, "rotate operator 'ror' expected"); 1872 return MatchOperand_ParseFail; 1873 } 1874 Parser.Lex(); // Eat the operator. 1875 1876 // A '#' and a rotate amount. 1877 if (Parser.getTok().isNot(AsmToken::Hash)) { 1878 Error(Parser.getTok().getLoc(), "'#' expected"); 1879 return MatchOperand_ParseFail; 1880 } 1881 Parser.Lex(); // Eat hash token. 1882 1883 const MCExpr *ShiftAmount; 1884 SMLoc E = Parser.getTok().getLoc(); 1885 if (getParser().ParseExpression(ShiftAmount)) { 1886 Error(E, "malformed rotate expression"); 1887 return MatchOperand_ParseFail; 1888 } 1889 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 1890 if (!CE) { 1891 Error(E, "rotate amount must be an immediate"); 1892 return MatchOperand_ParseFail; 1893 } 1894 1895 int64_t Val = CE->getValue(); 1896 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension) 1897 // normally, zero is represented in asm by omitting the rotate operand 1898 // entirely. 1899 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) { 1900 Error(E, "'ror' rotate amount must be 8, 16, or 24"); 1901 return MatchOperand_ParseFail; 1902 } 1903 1904 E = Parser.getTok().getLoc(); 1905 Operands.push_back(ARMOperand::CreateRotImm(Val, S, E)); 1906 1907 return MatchOperand_Success; 1908} 1909 1910ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 1911parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1912 SMLoc S = Parser.getTok().getLoc(); 1913 // The bitfield descriptor is really two operands, the LSB and the width. 1914 if (Parser.getTok().isNot(AsmToken::Hash)) { 1915 Error(Parser.getTok().getLoc(), "'#' expected"); 1916 return MatchOperand_ParseFail; 1917 } 1918 Parser.Lex(); // Eat hash token. 1919 1920 const MCExpr *LSBExpr; 1921 SMLoc E = Parser.getTok().getLoc(); 1922 if (getParser().ParseExpression(LSBExpr)) { 1923 Error(E, "malformed immediate expression"); 1924 return MatchOperand_ParseFail; 1925 } 1926 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr); 1927 if (!CE) { 1928 Error(E, "'lsb' operand must be an immediate"); 1929 return MatchOperand_ParseFail; 1930 } 1931 1932 int64_t LSB = CE->getValue(); 1933 // The LSB must be in the range [0,31] 1934 if (LSB < 0 || LSB > 31) { 1935 Error(E, "'lsb' operand must be in the range [0,31]"); 1936 return MatchOperand_ParseFail; 1937 } 1938 E = Parser.getTok().getLoc(); 1939 1940 // Expect another immediate operand. 1941 if (Parser.getTok().isNot(AsmToken::Comma)) { 1942 Error(Parser.getTok().getLoc(), "too few operands"); 1943 return MatchOperand_ParseFail; 1944 } 1945 Parser.Lex(); // Eat hash token. 1946 if (Parser.getTok().isNot(AsmToken::Hash)) { 1947 Error(Parser.getTok().getLoc(), "'#' expected"); 1948 return MatchOperand_ParseFail; 1949 } 1950 Parser.Lex(); // Eat hash token. 1951 1952 const MCExpr *WidthExpr; 1953 if (getParser().ParseExpression(WidthExpr)) { 1954 Error(E, "malformed immediate expression"); 1955 return MatchOperand_ParseFail; 1956 } 1957 CE = dyn_cast<MCConstantExpr>(WidthExpr); 1958 if (!CE) { 1959 Error(E, "'width' operand must be an immediate"); 1960 return MatchOperand_ParseFail; 1961 } 1962 1963 int64_t Width = CE->getValue(); 1964 // The LSB must be in the range [1,32-lsb] 1965 if (Width < 1 || Width > 32 - LSB) { 1966 Error(E, "'width' operand must be in the range [1,32-lsb]"); 1967 return MatchOperand_ParseFail; 1968 } 1969 E = Parser.getTok().getLoc(); 1970 1971 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E)); 1972 1973 return MatchOperand_Success; 1974} 1975 1976ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 1977parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1978 // Check for a post-index addressing register operand. Specifically: 1979 // postidx_reg := '+' register {, shift} 1980 // | '-' register {, shift} 1981 // | register {, shift} 1982 1983 // This method must return MatchOperand_NoMatch without consuming any tokens 1984 // in the case where there is no match, as other alternatives take other 1985 // parse methods. 1986 AsmToken Tok = Parser.getTok(); 1987 SMLoc S = Tok.getLoc(); 1988 bool haveEaten = false; 1989 bool isAdd = true; 1990 int Reg = -1; 1991 if (Tok.is(AsmToken::Plus)) { 1992 Parser.Lex(); // Eat the '+' token. 1993 haveEaten = true; 1994 } else if (Tok.is(AsmToken::Minus)) { 1995 Parser.Lex(); // Eat the '-' token. 1996 isAdd = false; 1997 haveEaten = true; 1998 } 1999 if (Parser.getTok().is(AsmToken::Identifier)) 2000 Reg = tryParseRegister(); 2001 if (Reg == -1) { 2002 if (!haveEaten) 2003 return MatchOperand_NoMatch; 2004 Error(Parser.getTok().getLoc(), "register expected"); 2005 return MatchOperand_ParseFail; 2006 } 2007 SMLoc E = Parser.getTok().getLoc(); 2008 2009 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift; 2010 unsigned ShiftImm = 0; 2011 if (Parser.getTok().is(AsmToken::Comma)) { 2012 Parser.Lex(); // Eat the ','. 2013 if (parseMemRegOffsetShift(ShiftTy, ShiftImm)) 2014 return MatchOperand_ParseFail; 2015 } 2016 2017 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy, 2018 ShiftImm, S, E)); 2019 2020 return MatchOperand_Success; 2021} 2022 2023ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2024parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2025 // Check for a post-index addressing register operand. Specifically: 2026 // am3offset := '+' register 2027 // | '-' register 2028 // | register 2029 // | # imm 2030 // | # + imm 2031 // | # - imm 2032 2033 // This method must return MatchOperand_NoMatch without consuming any tokens 2034 // in the case where there is no match, as other alternatives take other 2035 // parse methods. 2036 AsmToken Tok = Parser.getTok(); 2037 SMLoc S = Tok.getLoc(); 2038 2039 // Do immediates first, as we always parse those if we have a '#'. 2040 if (Parser.getTok().is(AsmToken::Hash)) { 2041 Parser.Lex(); // Eat the '#'. 2042 // Explicitly look for a '-', as we need to encode negative zero 2043 // differently. 2044 bool isNegative = Parser.getTok().is(AsmToken::Minus); 2045 const MCExpr *Offset; 2046 if (getParser().ParseExpression(Offset)) 2047 return MatchOperand_ParseFail; 2048 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset); 2049 if (!CE) { 2050 Error(S, "constant expression expected"); 2051 return MatchOperand_ParseFail; 2052 } 2053 SMLoc E = Tok.getLoc(); 2054 // Negative zero is encoded as the flag value INT32_MIN. 2055 int32_t Val = CE->getValue(); 2056 if (isNegative && Val == 0) 2057 Val = INT32_MIN; 2058 2059 Operands.push_back( 2060 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E)); 2061 2062 return MatchOperand_Success; 2063 } 2064 2065 2066 bool haveEaten = false; 2067 bool isAdd = true; 2068 int Reg = -1; 2069 if (Tok.is(AsmToken::Plus)) { 2070 Parser.Lex(); // Eat the '+' token. 2071 haveEaten = true; 2072 } else if (Tok.is(AsmToken::Minus)) { 2073 Parser.Lex(); // Eat the '-' token. 2074 isAdd = false; 2075 haveEaten = true; 2076 } 2077 if (Parser.getTok().is(AsmToken::Identifier)) 2078 Reg = tryParseRegister(); 2079 if (Reg == -1) { 2080 if (!haveEaten) 2081 return MatchOperand_NoMatch; 2082 Error(Parser.getTok().getLoc(), "register expected"); 2083 return MatchOperand_ParseFail; 2084 } 2085 SMLoc E = Parser.getTok().getLoc(); 2086 2087 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift, 2088 0, S, E)); 2089 2090 return MatchOperand_Success; 2091} 2092 2093/// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst. 2094/// Needed here because the Asm Gen Matcher can't handle properly tied operands 2095/// when they refer multiple MIOperands inside a single one. 2096bool ARMAsmParser:: 2097cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, 2098 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2099 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 2100 2101 // Create a writeback register dummy placeholder. 2102 Inst.addOperand(MCOperand::CreateImm(0)); 2103 2104 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3); 2105 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 2106 return true; 2107} 2108 2109/// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst. 2110/// Needed here because the Asm Gen Matcher can't handle properly tied operands 2111/// when they refer multiple MIOperands inside a single one. 2112bool ARMAsmParser:: 2113cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode, 2114 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2115 // Create a writeback register dummy placeholder. 2116 Inst.addOperand(MCOperand::CreateImm(0)); 2117 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 2118 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2); 2119 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 2120 return true; 2121} 2122 2123/// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst. 2124/// Needed here because the Asm Gen Matcher can't handle properly tied operands 2125/// when they refer multiple MIOperands inside a single one. 2126bool ARMAsmParser:: 2127cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, 2128 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2129 // Create a writeback register dummy placeholder. 2130 Inst.addOperand(MCOperand::CreateImm(0)); 2131 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 2132 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3); 2133 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 2134 return true; 2135} 2136 2137/// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst. 2138/// Needed here because the Asm Gen Matcher can't handle properly tied operands 2139/// when they refer multiple MIOperands inside a single one. 2140bool ARMAsmParser:: 2141cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, 2142 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2143 // Create a writeback register dummy placeholder. 2144 Inst.addOperand(MCOperand::CreateImm(0)); 2145 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 2146 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3); 2147 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 2148 return true; 2149} 2150 2151/// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst. 2152/// Needed here because the Asm Gen Matcher can't handle properly tied operands 2153/// when they refer multiple MIOperands inside a single one. 2154bool ARMAsmParser:: 2155cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode, 2156 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2157 // Rt 2158 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 2159 // Create a writeback register dummy placeholder. 2160 Inst.addOperand(MCOperand::CreateImm(0)); 2161 // addr 2162 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 2163 // offset 2164 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1); 2165 // pred 2166 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 2167 return true; 2168} 2169 2170/// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst. 2171/// Needed here because the Asm Gen Matcher can't handle properly tied operands 2172/// when they refer multiple MIOperands inside a single one. 2173bool ARMAsmParser:: 2174cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode, 2175 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2176 // Rt 2177 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 2178 // Create a writeback register dummy placeholder. 2179 Inst.addOperand(MCOperand::CreateImm(0)); 2180 // addr 2181 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 2182 // offset 2183 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2); 2184 // pred 2185 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 2186 return true; 2187} 2188 2189/// cvtStExtTWriteBackImm - Convert parsed operands to MCInst. 2190/// Needed here because the Asm Gen Matcher can't handle properly tied operands 2191/// when they refer multiple MIOperands inside a single one. 2192bool ARMAsmParser:: 2193cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode, 2194 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2195 // Create a writeback register dummy placeholder. 2196 Inst.addOperand(MCOperand::CreateImm(0)); 2197 // Rt 2198 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 2199 // addr 2200 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 2201 // offset 2202 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1); 2203 // pred 2204 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 2205 return true; 2206} 2207 2208/// cvtStExtTWriteBackReg - Convert parsed operands to MCInst. 2209/// Needed here because the Asm Gen Matcher can't handle properly tied operands 2210/// when they refer multiple MIOperands inside a single one. 2211bool ARMAsmParser:: 2212cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode, 2213 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2214 // Create a writeback register dummy placeholder. 2215 Inst.addOperand(MCOperand::CreateImm(0)); 2216 // Rt 2217 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 2218 // addr 2219 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 2220 // offset 2221 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2); 2222 // pred 2223 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 2224 return true; 2225} 2226 2227/// cvtLdrdPre - Convert parsed operands to MCInst. 2228/// Needed here because the Asm Gen Matcher can't handle properly tied operands 2229/// when they refer multiple MIOperands inside a single one. 2230bool ARMAsmParser:: 2231cvtLdrdPre(MCInst &Inst, unsigned Opcode, 2232 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2233 // Rt, Rt2 2234 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 2235 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 2236 // Create a writeback register dummy placeholder. 2237 Inst.addOperand(MCOperand::CreateImm(0)); 2238 // addr 2239 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3); 2240 // pred 2241 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 2242 return true; 2243} 2244 2245/// cvtStrdPre - Convert parsed operands to MCInst. 2246/// Needed here because the Asm Gen Matcher can't handle properly tied operands 2247/// when they refer multiple MIOperands inside a single one. 2248bool ARMAsmParser:: 2249cvtStrdPre(MCInst &Inst, unsigned Opcode, 2250 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2251 // Create a writeback register dummy placeholder. 2252 Inst.addOperand(MCOperand::CreateImm(0)); 2253 // Rt, Rt2 2254 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 2255 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 2256 // addr 2257 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3); 2258 // pred 2259 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 2260 return true; 2261} 2262 2263/// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst. 2264/// Needed here because the Asm Gen Matcher can't handle properly tied operands 2265/// when they refer multiple MIOperands inside a single one. 2266bool ARMAsmParser:: 2267cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, 2268 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2269 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 2270 // Create a writeback register dummy placeholder. 2271 Inst.addOperand(MCOperand::CreateImm(0)); 2272 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3); 2273 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 2274 return true; 2275} 2276 2277 2278/// Parse an ARM memory expression, return false if successful else return true 2279/// or an error. The first token must be a '[' when called. 2280bool ARMAsmParser:: 2281parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2282 SMLoc S, E; 2283 assert(Parser.getTok().is(AsmToken::LBrac) && 2284 "Token is not a Left Bracket"); 2285 S = Parser.getTok().getLoc(); 2286 Parser.Lex(); // Eat left bracket token. 2287 2288 const AsmToken &BaseRegTok = Parser.getTok(); 2289 int BaseRegNum = tryParseRegister(); 2290 if (BaseRegNum == -1) 2291 return Error(BaseRegTok.getLoc(), "register expected"); 2292 2293 // The next token must either be a comma or a closing bracket. 2294 const AsmToken &Tok = Parser.getTok(); 2295 if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac)) 2296 return Error(Tok.getLoc(), "malformed memory operand"); 2297 2298 if (Tok.is(AsmToken::RBrac)) { 2299 E = Tok.getLoc(); 2300 Parser.Lex(); // Eat right bracket token. 2301 2302 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift, 2303 0, false, S, E)); 2304 2305 return false; 2306 } 2307 2308 assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!"); 2309 Parser.Lex(); // Eat the comma. 2310 2311 // If we have a '#' it's an immediate offset, else assume it's a register 2312 // offset. 2313 if (Parser.getTok().is(AsmToken::Hash)) { 2314 Parser.Lex(); // Eat the '#'. 2315 E = Parser.getTok().getLoc(); 2316 2317 // FIXME: Special case #-0 so we can correctly set the U bit. 2318 2319 const MCExpr *Offset; 2320 if (getParser().ParseExpression(Offset)) 2321 return true; 2322 2323 // The expression has to be a constant. Memory references with relocations 2324 // don't come through here, as they use the <label> forms of the relevant 2325 // instructions. 2326 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset); 2327 if (!CE) 2328 return Error (E, "constant expression expected"); 2329 2330 // Now we should have the closing ']' 2331 E = Parser.getTok().getLoc(); 2332 if (Parser.getTok().isNot(AsmToken::RBrac)) 2333 return Error(E, "']' expected"); 2334 Parser.Lex(); // Eat right bracket token. 2335 2336 // Don't worry about range checking the value here. That's handled by 2337 // the is*() predicates. 2338 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0, 2339 ARM_AM::no_shift, 0, false, S,E)); 2340 2341 // If there's a pre-indexing writeback marker, '!', just add it as a token 2342 // operand. 2343 if (Parser.getTok().is(AsmToken::Exclaim)) { 2344 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 2345 Parser.Lex(); // Eat the '!'. 2346 } 2347 2348 return false; 2349 } 2350 2351 // The register offset is optionally preceded by a '+' or '-' 2352 bool isNegative = false; 2353 if (Parser.getTok().is(AsmToken::Minus)) { 2354 isNegative = true; 2355 Parser.Lex(); // Eat the '-'. 2356 } else if (Parser.getTok().is(AsmToken::Plus)) { 2357 // Nothing to do. 2358 Parser.Lex(); // Eat the '+'. 2359 } 2360 2361 E = Parser.getTok().getLoc(); 2362 int OffsetRegNum = tryParseRegister(); 2363 if (OffsetRegNum == -1) 2364 return Error(E, "register expected"); 2365 2366 // If there's a shift operator, handle it. 2367 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift; 2368 unsigned ShiftImm = 0; 2369 if (Parser.getTok().is(AsmToken::Comma)) { 2370 Parser.Lex(); // Eat the ','. 2371 if (parseMemRegOffsetShift(ShiftType, ShiftImm)) 2372 return true; 2373 } 2374 2375 // Now we should have the closing ']' 2376 E = Parser.getTok().getLoc(); 2377 if (Parser.getTok().isNot(AsmToken::RBrac)) 2378 return Error(E, "']' expected"); 2379 Parser.Lex(); // Eat right bracket token. 2380 2381 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum, 2382 ShiftType, ShiftImm, isNegative, 2383 S, E)); 2384 2385 // If there's a pre-indexing writeback marker, '!', just add it as a token 2386 // operand. 2387 if (Parser.getTok().is(AsmToken::Exclaim)) { 2388 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 2389 Parser.Lex(); // Eat the '!'. 2390 } 2391 2392 return false; 2393} 2394 2395/// parseMemRegOffsetShift - one of these two: 2396/// ( lsl | lsr | asr | ror ) , # shift_amount 2397/// rrx 2398/// return true if it parses a shift otherwise it returns false. 2399bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St, 2400 unsigned &Amount) { 2401 SMLoc Loc = Parser.getTok().getLoc(); 2402 const AsmToken &Tok = Parser.getTok(); 2403 if (Tok.isNot(AsmToken::Identifier)) 2404 return true; 2405 StringRef ShiftName = Tok.getString(); 2406 if (ShiftName == "lsl" || ShiftName == "LSL") 2407 St = ARM_AM::lsl; 2408 else if (ShiftName == "lsr" || ShiftName == "LSR") 2409 St = ARM_AM::lsr; 2410 else if (ShiftName == "asr" || ShiftName == "ASR") 2411 St = ARM_AM::asr; 2412 else if (ShiftName == "ror" || ShiftName == "ROR") 2413 St = ARM_AM::ror; 2414 else if (ShiftName == "rrx" || ShiftName == "RRX") 2415 St = ARM_AM::rrx; 2416 else 2417 return Error(Loc, "illegal shift operator"); 2418 Parser.Lex(); // Eat shift type token. 2419 2420 // rrx stands alone. 2421 Amount = 0; 2422 if (St != ARM_AM::rrx) { 2423 Loc = Parser.getTok().getLoc(); 2424 // A '#' and a shift amount. 2425 const AsmToken &HashTok = Parser.getTok(); 2426 if (HashTok.isNot(AsmToken::Hash)) 2427 return Error(HashTok.getLoc(), "'#' expected"); 2428 Parser.Lex(); // Eat hash token. 2429 2430 const MCExpr *Expr; 2431 if (getParser().ParseExpression(Expr)) 2432 return true; 2433 // Range check the immediate. 2434 // lsl, ror: 0 <= imm <= 31 2435 // lsr, asr: 0 <= imm <= 32 2436 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 2437 if (!CE) 2438 return Error(Loc, "shift amount must be an immediate"); 2439 int64_t Imm = CE->getValue(); 2440 if (Imm < 0 || 2441 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) || 2442 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32)) 2443 return Error(Loc, "immediate shift value out of range"); 2444 Amount = Imm; 2445 } 2446 2447 return false; 2448} 2449 2450/// Parse a arm instruction operand. For now this parses the operand regardless 2451/// of the mnemonic. 2452bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands, 2453 StringRef Mnemonic) { 2454 SMLoc S, E; 2455 2456 // Check if the current operand has a custom associated parser, if so, try to 2457 // custom parse the operand, or fallback to the general approach. 2458 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic); 2459 if (ResTy == MatchOperand_Success) 2460 return false; 2461 // If there wasn't a custom match, try the generic matcher below. Otherwise, 2462 // there was a match, but an error occurred, in which case, just return that 2463 // the operand parsing failed. 2464 if (ResTy == MatchOperand_ParseFail) 2465 return true; 2466 2467 switch (getLexer().getKind()) { 2468 default: 2469 Error(Parser.getTok().getLoc(), "unexpected token in operand"); 2470 return true; 2471 case AsmToken::Identifier: { 2472 if (!tryParseRegisterWithWriteBack(Operands)) 2473 return false; 2474 int Res = tryParseShiftRegister(Operands); 2475 if (Res == 0) // success 2476 return false; 2477 else if (Res == -1) // irrecoverable error 2478 return true; 2479 2480 // Fall though for the Identifier case that is not a register or a 2481 // special name. 2482 } 2483 case AsmToken::Integer: // things like 1f and 2b as a branch targets 2484 case AsmToken::Dot: { // . as a branch target 2485 // This was not a register so parse other operands that start with an 2486 // identifier (like labels) as expressions and create them as immediates. 2487 const MCExpr *IdVal; 2488 S = Parser.getTok().getLoc(); 2489 if (getParser().ParseExpression(IdVal)) 2490 return true; 2491 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 2492 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E)); 2493 return false; 2494 } 2495 case AsmToken::LBrac: 2496 return parseMemory(Operands); 2497 case AsmToken::LCurly: 2498 return parseRegisterList(Operands); 2499 case AsmToken::Hash: 2500 // #42 -> immediate. 2501 // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate 2502 S = Parser.getTok().getLoc(); 2503 Parser.Lex(); 2504 const MCExpr *ImmVal; 2505 if (getParser().ParseExpression(ImmVal)) 2506 return true; 2507 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 2508 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E)); 2509 return false; 2510 case AsmToken::Colon: { 2511 // ":lower16:" and ":upper16:" expression prefixes 2512 // FIXME: Check it's an expression prefix, 2513 // e.g. (FOO - :lower16:BAR) isn't legal. 2514 ARMMCExpr::VariantKind RefKind; 2515 if (parsePrefix(RefKind)) 2516 return true; 2517 2518 const MCExpr *SubExprVal; 2519 if (getParser().ParseExpression(SubExprVal)) 2520 return true; 2521 2522 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal, 2523 getContext()); 2524 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 2525 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E)); 2526 return false; 2527 } 2528 } 2529} 2530 2531// parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e. 2532// :lower16: and :upper16:. 2533bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) { 2534 RefKind = ARMMCExpr::VK_ARM_None; 2535 2536 // :lower16: and :upper16: modifiers 2537 assert(getLexer().is(AsmToken::Colon) && "expected a :"); 2538 Parser.Lex(); // Eat ':' 2539 2540 if (getLexer().isNot(AsmToken::Identifier)) { 2541 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand"); 2542 return true; 2543 } 2544 2545 StringRef IDVal = Parser.getTok().getIdentifier(); 2546 if (IDVal == "lower16") { 2547 RefKind = ARMMCExpr::VK_ARM_LO16; 2548 } else if (IDVal == "upper16") { 2549 RefKind = ARMMCExpr::VK_ARM_HI16; 2550 } else { 2551 Error(Parser.getTok().getLoc(), "unexpected prefix in operand"); 2552 return true; 2553 } 2554 Parser.Lex(); 2555 2556 if (getLexer().isNot(AsmToken::Colon)) { 2557 Error(Parser.getTok().getLoc(), "unexpected token after prefix"); 2558 return true; 2559 } 2560 Parser.Lex(); // Eat the last ':' 2561 return false; 2562} 2563 2564const MCExpr * 2565ARMAsmParser::applyPrefixToExpr(const MCExpr *E, 2566 MCSymbolRefExpr::VariantKind Variant) { 2567 // Recurse over the given expression, rebuilding it to apply the given variant 2568 // to the leftmost symbol. 2569 if (Variant == MCSymbolRefExpr::VK_None) 2570 return E; 2571 2572 switch (E->getKind()) { 2573 case MCExpr::Target: 2574 llvm_unreachable("Can't handle target expr yet"); 2575 case MCExpr::Constant: 2576 llvm_unreachable("Can't handle lower16/upper16 of constant yet"); 2577 2578 case MCExpr::SymbolRef: { 2579 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E); 2580 2581 if (SRE->getKind() != MCSymbolRefExpr::VK_None) 2582 return 0; 2583 2584 return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, getContext()); 2585 } 2586 2587 case MCExpr::Unary: 2588 llvm_unreachable("Can't handle unary expressions yet"); 2589 2590 case MCExpr::Binary: { 2591 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E); 2592 const MCExpr *LHS = applyPrefixToExpr(BE->getLHS(), Variant); 2593 const MCExpr *RHS = BE->getRHS(); 2594 if (!LHS) 2595 return 0; 2596 2597 return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, getContext()); 2598 } 2599 } 2600 2601 assert(0 && "Invalid expression kind!"); 2602 return 0; 2603} 2604 2605/// \brief Given a mnemonic, split out possible predication code and carry 2606/// setting letters to form a canonical mnemonic and flags. 2607// 2608// FIXME: Would be nice to autogen this. 2609StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic, 2610 unsigned &PredicationCode, 2611 bool &CarrySetting, 2612 unsigned &ProcessorIMod) { 2613 PredicationCode = ARMCC::AL; 2614 CarrySetting = false; 2615 ProcessorIMod = 0; 2616 2617 // Ignore some mnemonics we know aren't predicated forms. 2618 // 2619 // FIXME: Would be nice to autogen this. 2620 if ((Mnemonic == "movs" && isThumb()) || 2621 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" || 2622 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" || 2623 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" || 2624 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" || 2625 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" || 2626 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" || 2627 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal") 2628 return Mnemonic; 2629 2630 // First, split out any predication code. Ignore mnemonics we know aren't 2631 // predicated but do have a carry-set and so weren't caught above. 2632 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" && 2633 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" && 2634 Mnemonic != "umlals" && Mnemonic != "umulls") { 2635 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2)) 2636 .Case("eq", ARMCC::EQ) 2637 .Case("ne", ARMCC::NE) 2638 .Case("hs", ARMCC::HS) 2639 .Case("cs", ARMCC::HS) 2640 .Case("lo", ARMCC::LO) 2641 .Case("cc", ARMCC::LO) 2642 .Case("mi", ARMCC::MI) 2643 .Case("pl", ARMCC::PL) 2644 .Case("vs", ARMCC::VS) 2645 .Case("vc", ARMCC::VC) 2646 .Case("hi", ARMCC::HI) 2647 .Case("ls", ARMCC::LS) 2648 .Case("ge", ARMCC::GE) 2649 .Case("lt", ARMCC::LT) 2650 .Case("gt", ARMCC::GT) 2651 .Case("le", ARMCC::LE) 2652 .Case("al", ARMCC::AL) 2653 .Default(~0U); 2654 if (CC != ~0U) { 2655 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2); 2656 PredicationCode = CC; 2657 } 2658 } 2659 2660 // Next, determine if we have a carry setting bit. We explicitly ignore all 2661 // the instructions we know end in 's'. 2662 if (Mnemonic.endswith("s") && 2663 !(Mnemonic == "asrs" || Mnemonic == "cps" || Mnemonic == "mls" || 2664 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" || 2665 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" || 2666 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" || 2667 Mnemonic == "vrsqrts" || Mnemonic == "srs" || 2668 (Mnemonic == "movs" && isThumb()))) { 2669 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1); 2670 CarrySetting = true; 2671 } 2672 2673 // The "cps" instruction can have a interrupt mode operand which is glued into 2674 // the mnemonic. Check if this is the case, split it and parse the imod op 2675 if (Mnemonic.startswith("cps")) { 2676 // Split out any imod code. 2677 unsigned IMod = 2678 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2)) 2679 .Case("ie", ARM_PROC::IE) 2680 .Case("id", ARM_PROC::ID) 2681 .Default(~0U); 2682 if (IMod != ~0U) { 2683 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2); 2684 ProcessorIMod = IMod; 2685 } 2686 } 2687 2688 return Mnemonic; 2689} 2690 2691/// \brief Given a canonical mnemonic, determine if the instruction ever allows 2692/// inclusion of carry set or predication code operands. 2693// 2694// FIXME: It would be nice to autogen this. 2695void ARMAsmParser:: 2696getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet, 2697 bool &CanAcceptPredicationCode) { 2698 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" || 2699 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" || 2700 Mnemonic == "smull" || Mnemonic == "add" || Mnemonic == "adc" || 2701 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" || 2702 Mnemonic == "umlal" || Mnemonic == "orr" || Mnemonic == "mvn" || 2703 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" || 2704 Mnemonic == "sbc" || Mnemonic == "mla" || Mnemonic == "umull" || 2705 Mnemonic == "eor" || Mnemonic == "smlal" || 2706 (Mnemonic == "mov" && !isThumbOne())) { 2707 CanAcceptCarrySet = true; 2708 } else { 2709 CanAcceptCarrySet = false; 2710 } 2711 2712 if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" || 2713 Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" || 2714 Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" || 2715 Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" || 2716 Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "clrex" || 2717 Mnemonic == "setend" || 2718 ((Mnemonic == "pld" || Mnemonic == "pli") && !isThumb()) || 2719 ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs")) 2720 && !isThumb()) || 2721 Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumb())) { 2722 CanAcceptPredicationCode = false; 2723 } else { 2724 CanAcceptPredicationCode = true; 2725 } 2726 2727 if (isThumb()) 2728 if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" || 2729 Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp") 2730 CanAcceptPredicationCode = false; 2731} 2732 2733/// Parse an arm instruction mnemonic followed by its operands. 2734bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc, 2735 SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2736 // Create the leading tokens for the mnemonic, split by '.' characters. 2737 size_t Start = 0, Next = Name.find('.'); 2738 StringRef Mnemonic = Name.slice(Start, Next); 2739 2740 // Split out the predication code and carry setting flag from the mnemonic. 2741 unsigned PredicationCode; 2742 unsigned ProcessorIMod; 2743 bool CarrySetting; 2744 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting, 2745 ProcessorIMod); 2746 2747 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc)); 2748 2749 // FIXME: This is all a pretty gross hack. We should automatically handle 2750 // optional operands like this via tblgen. 2751 2752 // Next, add the CCOut and ConditionCode operands, if needed. 2753 // 2754 // For mnemonics which can ever incorporate a carry setting bit or predication 2755 // code, our matching model involves us always generating CCOut and 2756 // ConditionCode operands to match the mnemonic "as written" and then we let 2757 // the matcher deal with finding the right instruction or generating an 2758 // appropriate error. 2759 bool CanAcceptCarrySet, CanAcceptPredicationCode; 2760 getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode); 2761 2762 // If we had a carry-set on an instruction that can't do that, issue an 2763 // error. 2764 if (!CanAcceptCarrySet && CarrySetting) { 2765 Parser.EatToEndOfStatement(); 2766 return Error(NameLoc, "instruction '" + Mnemonic + 2767 "' can not set flags, but 's' suffix specified"); 2768 } 2769 // If we had a predication code on an instruction that can't do that, issue an 2770 // error. 2771 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) { 2772 Parser.EatToEndOfStatement(); 2773 return Error(NameLoc, "instruction '" + Mnemonic + 2774 "' is not predicable, but condition code specified"); 2775 } 2776 2777 // Add the carry setting operand, if necessary. 2778 // 2779 // FIXME: It would be awesome if we could somehow invent a location such that 2780 // match errors on this operand would print a nice diagnostic about how the 2781 // 's' character in the mnemonic resulted in a CCOut operand. 2782 if (CanAcceptCarrySet) 2783 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0, 2784 NameLoc)); 2785 2786 // Add the predication code operand, if necessary. 2787 if (CanAcceptPredicationCode) { 2788 Operands.push_back(ARMOperand::CreateCondCode( 2789 ARMCC::CondCodes(PredicationCode), NameLoc)); 2790 } 2791 2792 // Add the processor imod operand, if necessary. 2793 if (ProcessorIMod) { 2794 Operands.push_back(ARMOperand::CreateImm( 2795 MCConstantExpr::Create(ProcessorIMod, getContext()), 2796 NameLoc, NameLoc)); 2797 } else { 2798 // This mnemonic can't ever accept a imod, but the user wrote 2799 // one (or misspelled another mnemonic). 2800 2801 // FIXME: Issue a nice error. 2802 } 2803 2804 // Add the remaining tokens in the mnemonic. 2805 while (Next != StringRef::npos) { 2806 Start = Next; 2807 Next = Name.find('.', Start + 1); 2808 StringRef ExtraToken = Name.slice(Start, Next); 2809 2810 Operands.push_back(ARMOperand::CreateToken(ExtraToken, NameLoc)); 2811 } 2812 2813 // Read the remaining operands. 2814 if (getLexer().isNot(AsmToken::EndOfStatement)) { 2815 // Read the first operand. 2816 if (parseOperand(Operands, Mnemonic)) { 2817 Parser.EatToEndOfStatement(); 2818 return true; 2819 } 2820 2821 while (getLexer().is(AsmToken::Comma)) { 2822 Parser.Lex(); // Eat the comma. 2823 2824 // Parse and remember the operand. 2825 if (parseOperand(Operands, Mnemonic)) { 2826 Parser.EatToEndOfStatement(); 2827 return true; 2828 } 2829 } 2830 } 2831 2832 if (getLexer().isNot(AsmToken::EndOfStatement)) { 2833 Parser.EatToEndOfStatement(); 2834 return TokError("unexpected token in argument list"); 2835 } 2836 2837 Parser.Lex(); // Consume the EndOfStatement 2838 2839 2840 // The 'mov' mnemonic is special. One variant has a cc_out operand, while 2841 // another does not. Specifically, the MOVW instruction does not. So we 2842 // special case it here and remove the defaulted (non-setting) cc_out 2843 // operand if that's the instruction we're trying to match. 2844 // 2845 // We do this post-processing of the explicit operands rather than just 2846 // conditionally adding the cc_out in the first place because we need 2847 // to check the type of the parsed immediate operand. 2848 if (Mnemonic == "mov" && Operands.size() > 4 && 2849 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() && 2850 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() && 2851 static_cast<ARMOperand*>(Operands[1])->getReg() == 0) { 2852 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]); 2853 Operands.erase(Operands.begin() + 1); 2854 delete Op; 2855 } 2856 2857 // ARM mode 'blx' need special handling, as the register operand version 2858 // is predicable, but the label operand version is not. So, we can't rely 2859 // on the Mnemonic based checking to correctly figure out when to put 2860 // a CondCode operand in the list. If we're trying to match the label 2861 // version, remove the CondCode operand here. 2862 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 && 2863 static_cast<ARMOperand*>(Operands[2])->isImm()) { 2864 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]); 2865 Operands.erase(Operands.begin() + 1); 2866 delete Op; 2867 } 2868 2869 // The vector-compare-to-zero instructions have a literal token "#0" at 2870 // the end that comes to here as an immediate operand. Convert it to a 2871 // token to play nicely with the matcher. 2872 if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" || 2873 Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 && 2874 static_cast<ARMOperand*>(Operands[5])->isImm()) { 2875 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]); 2876 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm()); 2877 if (CE && CE->getValue() == 0) { 2878 Operands.erase(Operands.begin() + 5); 2879 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc())); 2880 delete Op; 2881 } 2882 } 2883 return false; 2884} 2885 2886// Validate context-sensitive operand constraints. 2887// FIXME: We would really like to be able to tablegen'erate this. 2888bool ARMAsmParser:: 2889validateInstruction(MCInst &Inst, 2890 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2891 switch (Inst.getOpcode()) { 2892 case ARM::LDRD: 2893 case ARM::LDRD_PRE: 2894 case ARM::LDRD_POST: 2895 case ARM::LDREXD: { 2896 // Rt2 must be Rt + 1. 2897 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg()); 2898 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg()); 2899 if (Rt2 != Rt + 1) 2900 return Error(Operands[3]->getStartLoc(), 2901 "destination operands must be sequential"); 2902 return false; 2903 } 2904 case ARM::STRD: { 2905 // Rt2 must be Rt + 1. 2906 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg()); 2907 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg()); 2908 if (Rt2 != Rt + 1) 2909 return Error(Operands[3]->getStartLoc(), 2910 "source operands must be sequential"); 2911 return false; 2912 } 2913 case ARM::STRD_PRE: 2914 case ARM::STRD_POST: 2915 case ARM::STREXD: { 2916 // Rt2 must be Rt + 1. 2917 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg()); 2918 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(2).getReg()); 2919 if (Rt2 != Rt + 1) 2920 return Error(Operands[3]->getStartLoc(), 2921 "source operands must be sequential"); 2922 return false; 2923 } 2924 case ARM::SBFX: 2925 case ARM::UBFX: { 2926 // width must be in range [1, 32-lsb] 2927 unsigned lsb = Inst.getOperand(2).getImm(); 2928 unsigned widthm1 = Inst.getOperand(3).getImm(); 2929 if (widthm1 >= 32 - lsb) 2930 return Error(Operands[5]->getStartLoc(), 2931 "bitfield width must be in range [1,32-lsb]"); 2932 } 2933 } 2934 2935 return false; 2936} 2937 2938void ARMAsmParser:: 2939processInstruction(MCInst &Inst, 2940 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2941 switch (Inst.getOpcode()) { 2942 case ARM::LDMIA_UPD: 2943 // If this is a load of a single register via a 'pop', then we should use 2944 // a post-indexed LDR instruction instead, per the ARM ARM. 2945 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" && 2946 Inst.getNumOperands() == 5) { 2947 MCInst TmpInst; 2948 TmpInst.setOpcode(ARM::LDR_POST_IMM); 2949 TmpInst.addOperand(Inst.getOperand(4)); // Rt 2950 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 2951 TmpInst.addOperand(Inst.getOperand(1)); // Rn 2952 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset 2953 TmpInst.addOperand(MCOperand::CreateImm(4)); 2954 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 2955 TmpInst.addOperand(Inst.getOperand(3)); 2956 Inst = TmpInst; 2957 } 2958 break; 2959 case ARM::STMDB_UPD: 2960 // If this is a store of a single register via a 'push', then we should use 2961 // a pre-indexed STR instruction instead, per the ARM ARM. 2962 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" && 2963 Inst.getNumOperands() == 5) { 2964 MCInst TmpInst; 2965 TmpInst.setOpcode(ARM::STR_PRE_IMM); 2966 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 2967 TmpInst.addOperand(Inst.getOperand(4)); // Rt 2968 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12 2969 TmpInst.addOperand(MCOperand::CreateImm(-4)); 2970 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 2971 TmpInst.addOperand(Inst.getOperand(3)); 2972 Inst = TmpInst; 2973 } 2974 break; 2975 } 2976} 2977 2978bool ARMAsmParser:: 2979MatchAndEmitInstruction(SMLoc IDLoc, 2980 SmallVectorImpl<MCParsedAsmOperand*> &Operands, 2981 MCStreamer &Out) { 2982 MCInst Inst; 2983 unsigned ErrorInfo; 2984 MatchResultTy MatchResult; 2985 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo); 2986 switch (MatchResult) { 2987 case Match_Success: 2988 // Context sensitive operand constraints aren't handled by the matcher, 2989 // so check them here. 2990 if (validateInstruction(Inst, Operands)) 2991 return true; 2992 2993 // Some instructions need post-processing to, for example, tweak which 2994 // encoding is selected. 2995 processInstruction(Inst, Operands); 2996 2997 Out.EmitInstruction(Inst); 2998 return false; 2999 case Match_MissingFeature: 3000 Error(IDLoc, "instruction requires a CPU feature not currently enabled"); 3001 return true; 3002 case Match_InvalidOperand: { 3003 SMLoc ErrorLoc = IDLoc; 3004 if (ErrorInfo != ~0U) { 3005 if (ErrorInfo >= Operands.size()) 3006 return Error(IDLoc, "too few operands for instruction"); 3007 3008 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc(); 3009 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 3010 } 3011 3012 return Error(ErrorLoc, "invalid operand for instruction"); 3013 } 3014 case Match_MnemonicFail: 3015 return Error(IDLoc, "unrecognized instruction mnemonic"); 3016 case Match_ConversionFail: 3017 return Error(IDLoc, "unable to convert operands to instruction"); 3018 } 3019 3020 llvm_unreachable("Implement any new match types added!"); 3021 return true; 3022} 3023 3024/// parseDirective parses the arm specific directives 3025bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) { 3026 StringRef IDVal = DirectiveID.getIdentifier(); 3027 if (IDVal == ".word") 3028 return parseDirectiveWord(4, DirectiveID.getLoc()); 3029 else if (IDVal == ".thumb") 3030 return parseDirectiveThumb(DirectiveID.getLoc()); 3031 else if (IDVal == ".thumb_func") 3032 return parseDirectiveThumbFunc(DirectiveID.getLoc()); 3033 else if (IDVal == ".code") 3034 return parseDirectiveCode(DirectiveID.getLoc()); 3035 else if (IDVal == ".syntax") 3036 return parseDirectiveSyntax(DirectiveID.getLoc()); 3037 return true; 3038} 3039 3040/// parseDirectiveWord 3041/// ::= .word [ expression (, expression)* ] 3042bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) { 3043 if (getLexer().isNot(AsmToken::EndOfStatement)) { 3044 for (;;) { 3045 const MCExpr *Value; 3046 if (getParser().ParseExpression(Value)) 3047 return true; 3048 3049 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/); 3050 3051 if (getLexer().is(AsmToken::EndOfStatement)) 3052 break; 3053 3054 // FIXME: Improve diagnostic. 3055 if (getLexer().isNot(AsmToken::Comma)) 3056 return Error(L, "unexpected token in directive"); 3057 Parser.Lex(); 3058 } 3059 } 3060 3061 Parser.Lex(); 3062 return false; 3063} 3064 3065/// parseDirectiveThumb 3066/// ::= .thumb 3067bool ARMAsmParser::parseDirectiveThumb(SMLoc L) { 3068 if (getLexer().isNot(AsmToken::EndOfStatement)) 3069 return Error(L, "unexpected token in directive"); 3070 Parser.Lex(); 3071 3072 // TODO: set thumb mode 3073 // TODO: tell the MC streamer the mode 3074 // getParser().getStreamer().Emit???(); 3075 return false; 3076} 3077 3078/// parseDirectiveThumbFunc 3079/// ::= .thumbfunc symbol_name 3080bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) { 3081 const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo(); 3082 bool isMachO = MAI.hasSubsectionsViaSymbols(); 3083 StringRef Name; 3084 3085 // Darwin asm has function name after .thumb_func direction 3086 // ELF doesn't 3087 if (isMachO) { 3088 const AsmToken &Tok = Parser.getTok(); 3089 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String)) 3090 return Error(L, "unexpected token in .thumb_func directive"); 3091 Name = Tok.getString(); 3092 Parser.Lex(); // Consume the identifier token. 3093 } 3094 3095 if (getLexer().isNot(AsmToken::EndOfStatement)) 3096 return Error(L, "unexpected token in directive"); 3097 Parser.Lex(); 3098 3099 // FIXME: assuming function name will be the line following .thumb_func 3100 if (!isMachO) { 3101 Name = Parser.getTok().getString(); 3102 } 3103 3104 // Mark symbol as a thumb symbol. 3105 MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name); 3106 getParser().getStreamer().EmitThumbFunc(Func); 3107 return false; 3108} 3109 3110/// parseDirectiveSyntax 3111/// ::= .syntax unified | divided 3112bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) { 3113 const AsmToken &Tok = Parser.getTok(); 3114 if (Tok.isNot(AsmToken::Identifier)) 3115 return Error(L, "unexpected token in .syntax directive"); 3116 StringRef Mode = Tok.getString(); 3117 if (Mode == "unified" || Mode == "UNIFIED") 3118 Parser.Lex(); 3119 else if (Mode == "divided" || Mode == "DIVIDED") 3120 return Error(L, "'.syntax divided' arm asssembly not supported"); 3121 else 3122 return Error(L, "unrecognized syntax mode in .syntax directive"); 3123 3124 if (getLexer().isNot(AsmToken::EndOfStatement)) 3125 return Error(Parser.getTok().getLoc(), "unexpected token in directive"); 3126 Parser.Lex(); 3127 3128 // TODO tell the MC streamer the mode 3129 // getParser().getStreamer().Emit???(); 3130 return false; 3131} 3132 3133/// parseDirectiveCode 3134/// ::= .code 16 | 32 3135bool ARMAsmParser::parseDirectiveCode(SMLoc L) { 3136 const AsmToken &Tok = Parser.getTok(); 3137 if (Tok.isNot(AsmToken::Integer)) 3138 return Error(L, "unexpected token in .code directive"); 3139 int64_t Val = Parser.getTok().getIntVal(); 3140 if (Val == 16) 3141 Parser.Lex(); 3142 else if (Val == 32) 3143 Parser.Lex(); 3144 else 3145 return Error(L, "invalid operand to .code directive"); 3146 3147 if (getLexer().isNot(AsmToken::EndOfStatement)) 3148 return Error(Parser.getTok().getLoc(), "unexpected token in directive"); 3149 Parser.Lex(); 3150 3151 if (Val == 16) { 3152 if (!isThumb()) { 3153 SwitchMode(); 3154 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16); 3155 } 3156 } else { 3157 if (isThumb()) { 3158 SwitchMode(); 3159 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32); 3160 } 3161 } 3162 3163 return false; 3164} 3165 3166extern "C" void LLVMInitializeARMAsmLexer(); 3167 3168/// Force static initialization. 3169extern "C" void LLVMInitializeARMAsmParser() { 3170 RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget); 3171 RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget); 3172 LLVMInitializeARMAsmLexer(); 3173} 3174 3175#define GET_REGISTER_MATCHER 3176#define GET_MATCHER_IMPLEMENTATION 3177#include "ARMGenAsmMatcher.inc" 3178