ARMAsmParser.cpp revision 92a202213bb4c20301abf6ab64e46df3695e60bf
1//===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10#include "ARM.h" 11#include "ARMBaseRegisterInfo.h" 12#include "ARMSubtarget.h" 13#include "MCTargetDesc/ARMAddressingModes.h" 14#include "MCTargetDesc/ARMMCExpr.h" 15#include "llvm/MC/MCParser/MCAsmLexer.h" 16#include "llvm/MC/MCParser/MCAsmParser.h" 17#include "llvm/MC/MCParser/MCParsedAsmOperand.h" 18#include "llvm/MC/MCAsmInfo.h" 19#include "llvm/MC/MCContext.h" 20#include "llvm/MC/MCStreamer.h" 21#include "llvm/MC/MCExpr.h" 22#include "llvm/MC/MCInst.h" 23#include "llvm/MC/MCSubtargetInfo.h" 24#include "llvm/Target/TargetRegistry.h" 25#include "llvm/Target/TargetAsmParser.h" 26#include "llvm/Support/SourceMgr.h" 27#include "llvm/Support/raw_ostream.h" 28#include "llvm/ADT/OwningPtr.h" 29#include "llvm/ADT/SmallVector.h" 30#include "llvm/ADT/StringExtras.h" 31#include "llvm/ADT/StringSwitch.h" 32#include "llvm/ADT/Twine.h" 33 34using namespace llvm; 35 36namespace { 37 38class ARMOperand; 39 40class ARMAsmParser : public TargetAsmParser { 41 MCSubtargetInfo &STI; 42 MCAsmParser &Parser; 43 44 MCAsmParser &getParser() const { return Parser; } 45 MCAsmLexer &getLexer() const { return Parser.getLexer(); } 46 47 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); } 48 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); } 49 50 int TryParseRegister(); 51 virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc); 52 bool TryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &); 53 int TryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &); 54 bool ParseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &); 55 bool ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &, 56 ARMII::AddrMode AddrMode); 57 bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic); 58 bool ParsePrefix(ARMMCExpr::VariantKind &RefKind); 59 const MCExpr *ApplyPrefixToExpr(const MCExpr *E, 60 MCSymbolRefExpr::VariantKind Variant); 61 62 63 bool ParseMemoryOffsetReg(bool &Negative, 64 bool &OffsetRegShifted, 65 enum ARM_AM::ShiftOpc &ShiftType, 66 const MCExpr *&ShiftAmount, 67 const MCExpr *&Offset, 68 bool &OffsetIsReg, 69 int &OffsetRegNum, 70 SMLoc &E); 71 bool ParseShift(enum ARM_AM::ShiftOpc &St, 72 const MCExpr *&ShiftAmount, SMLoc &E); 73 bool ParseDirectiveWord(unsigned Size, SMLoc L); 74 bool ParseDirectiveThumb(SMLoc L); 75 bool ParseDirectiveThumbFunc(SMLoc L); 76 bool ParseDirectiveCode(SMLoc L); 77 bool ParseDirectiveSyntax(SMLoc L); 78 79 bool MatchAndEmitInstruction(SMLoc IDLoc, 80 SmallVectorImpl<MCParsedAsmOperand*> &Operands, 81 MCStreamer &Out); 82 StringRef SplitMnemonic(StringRef Mnemonic, unsigned &PredicationCode, 83 bool &CarrySetting, unsigned &ProcessorIMod); 84 void GetMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet, 85 bool &CanAcceptPredicationCode); 86 87 bool isThumb() const { 88 // FIXME: Can tablegen auto-generate this? 89 return (STI.getFeatureBits() & ARM::ModeThumb) != 0; 90 } 91 bool isThumbOne() const { 92 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0; 93 } 94 void SwitchMode() { 95 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb)); 96 setAvailableFeatures(FB); 97 } 98 99 /// @name Auto-generated Match Functions 100 /// { 101 102#define GET_ASSEMBLER_HEADER 103#include "ARMGenAsmMatcher.inc" 104 105 /// } 106 107 OperandMatchResultTy tryParseCoprocNumOperand( 108 SmallVectorImpl<MCParsedAsmOperand*>&); 109 OperandMatchResultTy tryParseCoprocRegOperand( 110 SmallVectorImpl<MCParsedAsmOperand*>&); 111 OperandMatchResultTy tryParseMemBarrierOptOperand( 112 SmallVectorImpl<MCParsedAsmOperand*>&); 113 OperandMatchResultTy tryParseProcIFlagsOperand( 114 SmallVectorImpl<MCParsedAsmOperand*>&); 115 OperandMatchResultTy tryParseMSRMaskOperand( 116 SmallVectorImpl<MCParsedAsmOperand*>&); 117 OperandMatchResultTy tryParseMemMode2Operand( 118 SmallVectorImpl<MCParsedAsmOperand*>&); 119 OperandMatchResultTy tryParseMemMode3Operand( 120 SmallVectorImpl<MCParsedAsmOperand*>&); 121 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O, 122 StringRef Op, int Low, int High); 123 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) { 124 return parsePKHImm(O, "lsl", 0, 31); 125 } 126 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) { 127 return parsePKHImm(O, "asr", 1, 32); 128 } 129 130 // Asm Match Converter Methods 131 bool CvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, 132 const SmallVectorImpl<MCParsedAsmOperand*> &); 133 bool CvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, 134 const SmallVectorImpl<MCParsedAsmOperand*> &); 135 bool CvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, 136 const SmallVectorImpl<MCParsedAsmOperand*> &); 137 bool CvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, 138 const SmallVectorImpl<MCParsedAsmOperand*> &); 139 140public: 141 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser) 142 : TargetAsmParser(), STI(_STI), Parser(_Parser) { 143 MCAsmParserExtension::Initialize(_Parser); 144 145 // Initialize the set of available features. 146 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); 147 } 148 149 virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc, 150 SmallVectorImpl<MCParsedAsmOperand*> &Operands); 151 virtual bool ParseDirective(AsmToken DirectiveID); 152}; 153} // end anonymous namespace 154 155namespace { 156 157/// ARMOperand - Instances of this class represent a parsed ARM machine 158/// instruction. 159class ARMOperand : public MCParsedAsmOperand { 160 enum KindTy { 161 CondCode, 162 CCOut, 163 CoprocNum, 164 CoprocReg, 165 Immediate, 166 MemBarrierOpt, 167 Memory, 168 MSRMask, 169 ProcIFlags, 170 Register, 171 RegisterList, 172 DPRRegisterList, 173 SPRRegisterList, 174 ShiftedRegister, 175 ShiftedImmediate, 176 Shifter, 177 Token 178 } Kind; 179 180 SMLoc StartLoc, EndLoc; 181 SmallVector<unsigned, 8> Registers; 182 183 union { 184 struct { 185 ARMCC::CondCodes Val; 186 } CC; 187 188 struct { 189 ARM_MB::MemBOpt Val; 190 } MBOpt; 191 192 struct { 193 unsigned Val; 194 } Cop; 195 196 struct { 197 ARM_PROC::IFlags Val; 198 } IFlags; 199 200 struct { 201 unsigned Val; 202 } MMask; 203 204 struct { 205 const char *Data; 206 unsigned Length; 207 } Tok; 208 209 struct { 210 unsigned RegNum; 211 } Reg; 212 213 struct { 214 const MCExpr *Val; 215 } Imm; 216 217 /// Combined record for all forms of ARM address expressions. 218 struct { 219 ARMII::AddrMode AddrMode; 220 unsigned BaseRegNum; 221 union { 222 unsigned RegNum; ///< Offset register num, when OffsetIsReg. 223 const MCExpr *Value; ///< Offset value, when !OffsetIsReg. 224 } Offset; 225 const MCExpr *ShiftAmount; // used when OffsetRegShifted is true 226 enum ARM_AM::ShiftOpc ShiftType; // used when OffsetRegShifted is true 227 unsigned OffsetRegShifted : 1; // only used when OffsetIsReg is true 228 unsigned Preindexed : 1; 229 unsigned Postindexed : 1; 230 unsigned OffsetIsReg : 1; 231 unsigned Negative : 1; // only used when OffsetIsReg is true 232 unsigned Writeback : 1; 233 } Mem; 234 235 struct { 236 ARM_AM::ShiftOpc ShiftTy; 237 unsigned Imm; 238 } Shift; 239 struct { 240 ARM_AM::ShiftOpc ShiftTy; 241 unsigned SrcReg; 242 unsigned ShiftReg; 243 unsigned ShiftImm; 244 } ShiftedReg; 245 struct { 246 ARM_AM::ShiftOpc ShiftTy; 247 unsigned SrcReg; 248 unsigned ShiftImm; 249 } ShiftedImm; 250 }; 251 252 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {} 253public: 254 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() { 255 Kind = o.Kind; 256 StartLoc = o.StartLoc; 257 EndLoc = o.EndLoc; 258 switch (Kind) { 259 case CondCode: 260 CC = o.CC; 261 break; 262 case Token: 263 Tok = o.Tok; 264 break; 265 case CCOut: 266 case Register: 267 Reg = o.Reg; 268 break; 269 case RegisterList: 270 case DPRRegisterList: 271 case SPRRegisterList: 272 Registers = o.Registers; 273 break; 274 case CoprocNum: 275 case CoprocReg: 276 Cop = o.Cop; 277 break; 278 case Immediate: 279 Imm = o.Imm; 280 break; 281 case MemBarrierOpt: 282 MBOpt = o.MBOpt; 283 break; 284 case Memory: 285 Mem = o.Mem; 286 break; 287 case MSRMask: 288 MMask = o.MMask; 289 break; 290 case ProcIFlags: 291 IFlags = o.IFlags; 292 break; 293 case Shifter: 294 Shift = o.Shift; 295 break; 296 case ShiftedRegister: 297 ShiftedReg = o.ShiftedReg; 298 break; 299 case ShiftedImmediate: 300 ShiftedImm = o.ShiftedImm; 301 break; 302 } 303 } 304 305 /// getStartLoc - Get the location of the first token of this operand. 306 SMLoc getStartLoc() const { return StartLoc; } 307 /// getEndLoc - Get the location of the last token of this operand. 308 SMLoc getEndLoc() const { return EndLoc; } 309 310 ARMCC::CondCodes getCondCode() const { 311 assert(Kind == CondCode && "Invalid access!"); 312 return CC.Val; 313 } 314 315 unsigned getCoproc() const { 316 assert((Kind == CoprocNum || Kind == CoprocReg) && "Invalid access!"); 317 return Cop.Val; 318 } 319 320 StringRef getToken() const { 321 assert(Kind == Token && "Invalid access!"); 322 return StringRef(Tok.Data, Tok.Length); 323 } 324 325 unsigned getReg() const { 326 assert((Kind == Register || Kind == CCOut) && "Invalid access!"); 327 return Reg.RegNum; 328 } 329 330 const SmallVectorImpl<unsigned> &getRegList() const { 331 assert((Kind == RegisterList || Kind == DPRRegisterList || 332 Kind == SPRRegisterList) && "Invalid access!"); 333 return Registers; 334 } 335 336 const MCExpr *getImm() const { 337 assert(Kind == Immediate && "Invalid access!"); 338 return Imm.Val; 339 } 340 341 ARM_MB::MemBOpt getMemBarrierOpt() const { 342 assert(Kind == MemBarrierOpt && "Invalid access!"); 343 return MBOpt.Val; 344 } 345 346 ARM_PROC::IFlags getProcIFlags() const { 347 assert(Kind == ProcIFlags && "Invalid access!"); 348 return IFlags.Val; 349 } 350 351 unsigned getMSRMask() const { 352 assert(Kind == MSRMask && "Invalid access!"); 353 return MMask.Val; 354 } 355 356 /// @name Memory Operand Accessors 357 /// @{ 358 ARMII::AddrMode getMemAddrMode() const { 359 return Mem.AddrMode; 360 } 361 unsigned getMemBaseRegNum() const { 362 return Mem.BaseRegNum; 363 } 364 unsigned getMemOffsetRegNum() const { 365 assert(Mem.OffsetIsReg && "Invalid access!"); 366 return Mem.Offset.RegNum; 367 } 368 const MCExpr *getMemOffset() const { 369 assert(!Mem.OffsetIsReg && "Invalid access!"); 370 return Mem.Offset.Value; 371 } 372 unsigned getMemOffsetRegShifted() const { 373 assert(Mem.OffsetIsReg && "Invalid access!"); 374 return Mem.OffsetRegShifted; 375 } 376 const MCExpr *getMemShiftAmount() const { 377 assert(Mem.OffsetIsReg && Mem.OffsetRegShifted && "Invalid access!"); 378 return Mem.ShiftAmount; 379 } 380 enum ARM_AM::ShiftOpc getMemShiftType() const { 381 assert(Mem.OffsetIsReg && Mem.OffsetRegShifted && "Invalid access!"); 382 return Mem.ShiftType; 383 } 384 bool getMemPreindexed() const { return Mem.Preindexed; } 385 bool getMemPostindexed() const { return Mem.Postindexed; } 386 bool getMemOffsetIsReg() const { return Mem.OffsetIsReg; } 387 bool getMemNegative() const { return Mem.Negative; } 388 bool getMemWriteback() const { return Mem.Writeback; } 389 390 /// @} 391 392 bool isCoprocNum() const { return Kind == CoprocNum; } 393 bool isCoprocReg() const { return Kind == CoprocReg; } 394 bool isCondCode() const { return Kind == CondCode; } 395 bool isCCOut() const { return Kind == CCOut; } 396 bool isImm() const { return Kind == Immediate; } 397 bool isImm0_255() const { 398 if (Kind != Immediate) 399 return false; 400 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 401 if (!CE) return false; 402 int64_t Value = CE->getValue(); 403 return Value >= 0 && Value < 256; 404 } 405 bool isImm0_7() const { 406 if (Kind != Immediate) 407 return false; 408 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 409 if (!CE) return false; 410 int64_t Value = CE->getValue(); 411 return Value >= 0 && Value < 8; 412 } 413 bool isImm0_15() const { 414 if (Kind != Immediate) 415 return false; 416 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 417 if (!CE) return false; 418 int64_t Value = CE->getValue(); 419 return Value >= 0 && Value < 16; 420 } 421 bool isImm0_65535() const { 422 if (Kind != Immediate) 423 return false; 424 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 425 if (!CE) return false; 426 int64_t Value = CE->getValue(); 427 return Value >= 0 && Value < 65536; 428 } 429 bool isImm0_65535Expr() const { 430 if (Kind != Immediate) 431 return false; 432 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 433 // If it's not a constant expression, it'll generate a fixup and be 434 // handled later. 435 if (!CE) return true; 436 int64_t Value = CE->getValue(); 437 return Value >= 0 && Value < 65536; 438 } 439 bool isPKHLSLImm() const { 440 if (Kind != Immediate) 441 return false; 442 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 443 if (!CE) return false; 444 int64_t Value = CE->getValue(); 445 return Value >= 0 && Value < 32; 446 } 447 bool isPKHASRImm() const { 448 if (Kind != Immediate) 449 return false; 450 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 451 if (!CE) return false; 452 int64_t Value = CE->getValue(); 453 return Value > 0 && Value <= 32; 454 } 455 bool isARMSOImm() const { 456 if (Kind != Immediate) 457 return false; 458 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 459 if (!CE) return false; 460 int64_t Value = CE->getValue(); 461 return ARM_AM::getSOImmVal(Value) != -1; 462 } 463 bool isT2SOImm() const { 464 if (Kind != Immediate) 465 return false; 466 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 467 if (!CE) return false; 468 int64_t Value = CE->getValue(); 469 return ARM_AM::getT2SOImmVal(Value) != -1; 470 } 471 bool isReg() const { return Kind == Register; } 472 bool isRegList() const { return Kind == RegisterList; } 473 bool isDPRRegList() const { return Kind == DPRRegisterList; } 474 bool isSPRRegList() const { return Kind == SPRRegisterList; } 475 bool isToken() const { return Kind == Token; } 476 bool isMemBarrierOpt() const { return Kind == MemBarrierOpt; } 477 bool isMemory() const { return Kind == Memory; } 478 bool isShifter() const { return Kind == Shifter; } 479 bool isShiftedReg() const { return Kind == ShiftedRegister; } 480 bool isShiftedImm() const { return Kind == ShiftedImmediate; } 481 bool isMemMode2() const { 482 if (getMemAddrMode() != ARMII::AddrMode2) 483 return false; 484 485 if (getMemOffsetIsReg()) 486 return true; 487 488 if (getMemNegative() && 489 !(getMemPostindexed() || getMemPreindexed())) 490 return false; 491 492 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset()); 493 if (!CE) return false; 494 int64_t Value = CE->getValue(); 495 496 // The offset must be in the range 0-4095 (imm12). 497 if (Value > 4095 || Value < -4095) 498 return false; 499 500 return true; 501 } 502 bool isMemMode3() const { 503 if (getMemAddrMode() != ARMII::AddrMode3) 504 return false; 505 506 if (getMemOffsetIsReg()) { 507 if (getMemOffsetRegShifted()) 508 return false; // No shift with offset reg allowed 509 return true; 510 } 511 512 if (getMemNegative() && 513 !(getMemPostindexed() || getMemPreindexed())) 514 return false; 515 516 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset()); 517 if (!CE) return false; 518 int64_t Value = CE->getValue(); 519 520 // The offset must be in the range 0-255 (imm8). 521 if (Value > 255 || Value < -255) 522 return false; 523 524 return true; 525 } 526 bool isMemMode5() const { 527 if (!isMemory() || getMemOffsetIsReg() || getMemWriteback() || 528 getMemNegative()) 529 return false; 530 531 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset()); 532 if (!CE) return false; 533 534 // The offset must be a multiple of 4 in the range 0-1020. 535 int64_t Value = CE->getValue(); 536 return ((Value & 0x3) == 0 && Value <= 1020 && Value >= -1020); 537 } 538 bool isMemMode7() const { 539 if (!isMemory() || 540 getMemPreindexed() || 541 getMemPostindexed() || 542 getMemOffsetIsReg() || 543 getMemNegative() || 544 getMemWriteback()) 545 return false; 546 547 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset()); 548 if (!CE) return false; 549 550 if (CE->getValue()) 551 return false; 552 553 return true; 554 } 555 bool isMemModeRegThumb() const { 556 if (!isMemory() || !getMemOffsetIsReg() || getMemWriteback()) 557 return false; 558 return true; 559 } 560 bool isMemModeImmThumb() const { 561 if (!isMemory() || getMemOffsetIsReg() || getMemWriteback()) 562 return false; 563 564 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset()); 565 if (!CE) return false; 566 567 // The offset must be a multiple of 4 in the range 0-124. 568 uint64_t Value = CE->getValue(); 569 return ((Value & 0x3) == 0 && Value <= 124); 570 } 571 bool isMSRMask() const { return Kind == MSRMask; } 572 bool isProcIFlags() const { return Kind == ProcIFlags; } 573 574 void addExpr(MCInst &Inst, const MCExpr *Expr) const { 575 // Add as immediates when possible. Null MCExpr = 0. 576 if (Expr == 0) 577 Inst.addOperand(MCOperand::CreateImm(0)); 578 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr)) 579 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 580 else 581 Inst.addOperand(MCOperand::CreateExpr(Expr)); 582 } 583 584 void addCondCodeOperands(MCInst &Inst, unsigned N) const { 585 assert(N == 2 && "Invalid number of operands!"); 586 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); 587 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; 588 Inst.addOperand(MCOperand::CreateReg(RegNum)); 589 } 590 591 void addCoprocNumOperands(MCInst &Inst, unsigned N) const { 592 assert(N == 1 && "Invalid number of operands!"); 593 Inst.addOperand(MCOperand::CreateImm(getCoproc())); 594 } 595 596 void addCoprocRegOperands(MCInst &Inst, unsigned N) const { 597 assert(N == 1 && "Invalid number of operands!"); 598 Inst.addOperand(MCOperand::CreateImm(getCoproc())); 599 } 600 601 void addCCOutOperands(MCInst &Inst, unsigned N) const { 602 assert(N == 1 && "Invalid number of operands!"); 603 Inst.addOperand(MCOperand::CreateReg(getReg())); 604 } 605 606 void addRegOperands(MCInst &Inst, unsigned N) const { 607 assert(N == 1 && "Invalid number of operands!"); 608 Inst.addOperand(MCOperand::CreateReg(getReg())); 609 } 610 611 void addShiftedRegOperands(MCInst &Inst, unsigned N) const { 612 assert(N == 3 && "Invalid number of operands!"); 613 assert(isShiftedReg() && "addShiftedRegOperands() on non ShiftedReg!"); 614 Inst.addOperand(MCOperand::CreateReg(ShiftedReg.SrcReg)); 615 Inst.addOperand(MCOperand::CreateReg(ShiftedReg.ShiftReg)); 616 Inst.addOperand(MCOperand::CreateImm( 617 ARM_AM::getSORegOpc(ShiftedReg.ShiftTy, ShiftedReg.ShiftImm))); 618 } 619 620 void addShiftedImmOperands(MCInst &Inst, unsigned N) const { 621 assert(N == 3 && "Invalid number of operands!"); 622 assert(isShiftedImm() && "addShiftedImmOperands() on non ShiftedImm!"); 623 Inst.addOperand(MCOperand::CreateReg(ShiftedImm.SrcReg)); 624 if (ShiftedImm.ShiftTy == ARM_AM::rrx) 625 Inst.addOperand(MCOperand::CreateReg(ShiftedImm.SrcReg)); 626 else 627 Inst.addOperand(MCOperand::CreateReg(0)); 628 Inst.addOperand(MCOperand::CreateImm( 629 ARM_AM::getSORegOpc(ShiftedImm.ShiftTy, ShiftedImm.ShiftImm))); 630 } 631 632 633 void addShifterOperands(MCInst &Inst, unsigned N) const { 634 assert(N == 1 && "Invalid number of operands!"); 635 Inst.addOperand(MCOperand::CreateImm( 636 ARM_AM::getSORegOpc(Shift.ShiftTy, 0))); 637 } 638 639 void addRegListOperands(MCInst &Inst, unsigned N) const { 640 assert(N == 1 && "Invalid number of operands!"); 641 const SmallVectorImpl<unsigned> &RegList = getRegList(); 642 for (SmallVectorImpl<unsigned>::const_iterator 643 I = RegList.begin(), E = RegList.end(); I != E; ++I) 644 Inst.addOperand(MCOperand::CreateReg(*I)); 645 } 646 647 void addDPRRegListOperands(MCInst &Inst, unsigned N) const { 648 addRegListOperands(Inst, N); 649 } 650 651 void addSPRRegListOperands(MCInst &Inst, unsigned N) const { 652 addRegListOperands(Inst, N); 653 } 654 655 void addImmOperands(MCInst &Inst, unsigned N) const { 656 assert(N == 1 && "Invalid number of operands!"); 657 addExpr(Inst, getImm()); 658 } 659 660 void addImm0_255Operands(MCInst &Inst, unsigned N) const { 661 assert(N == 1 && "Invalid number of operands!"); 662 addExpr(Inst, getImm()); 663 } 664 665 void addImm0_7Operands(MCInst &Inst, unsigned N) const { 666 assert(N == 1 && "Invalid number of operands!"); 667 addExpr(Inst, getImm()); 668 } 669 670 void addImm0_15Operands(MCInst &Inst, unsigned N) const { 671 assert(N == 1 && "Invalid number of operands!"); 672 addExpr(Inst, getImm()); 673 } 674 675 void addImm0_65535Operands(MCInst &Inst, unsigned N) const { 676 assert(N == 1 && "Invalid number of operands!"); 677 addExpr(Inst, getImm()); 678 } 679 680 void addImm0_65535ExprOperands(MCInst &Inst, unsigned N) const { 681 assert(N == 1 && "Invalid number of operands!"); 682 addExpr(Inst, getImm()); 683 } 684 685 void addPKHLSLImmOperands(MCInst &Inst, unsigned N) const { 686 assert(N == 1 && "Invalid number of operands!"); 687 addExpr(Inst, getImm()); 688 } 689 690 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const { 691 assert(N == 1 && "Invalid number of operands!"); 692 // An ASR value of 32 encodes as 0, so that's how we want to add it to 693 // the instruction as well. 694 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 695 int Val = CE->getValue(); 696 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val)); 697 } 698 699 void addARMSOImmOperands(MCInst &Inst, unsigned N) const { 700 assert(N == 1 && "Invalid number of operands!"); 701 addExpr(Inst, getImm()); 702 } 703 704 void addT2SOImmOperands(MCInst &Inst, unsigned N) const { 705 assert(N == 1 && "Invalid number of operands!"); 706 addExpr(Inst, getImm()); 707 } 708 709 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const { 710 assert(N == 1 && "Invalid number of operands!"); 711 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt()))); 712 } 713 714 void addMemMode7Operands(MCInst &Inst, unsigned N) const { 715 assert(N == 1 && isMemMode7() && "Invalid number of operands!"); 716 Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum())); 717 718 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset()); 719 (void)CE; 720 assert((CE || CE->getValue() == 0) && 721 "No offset operand support in mode 7"); 722 } 723 724 void addMemMode2Operands(MCInst &Inst, unsigned N) const { 725 assert(isMemMode2() && "Invalid mode or number of operands!"); 726 Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum())); 727 unsigned IdxMode = (getMemPreindexed() | getMemPostindexed() << 1); 728 729 if (getMemOffsetIsReg()) { 730 Inst.addOperand(MCOperand::CreateReg(getMemOffsetRegNum())); 731 732 ARM_AM::AddrOpc AMOpc = getMemNegative() ? ARM_AM::sub : ARM_AM::add; 733 ARM_AM::ShiftOpc ShOpc = ARM_AM::no_shift; 734 int64_t ShiftAmount = 0; 735 736 if (getMemOffsetRegShifted()) { 737 ShOpc = getMemShiftType(); 738 const MCConstantExpr *CE = 739 dyn_cast<MCConstantExpr>(getMemShiftAmount()); 740 ShiftAmount = CE->getValue(); 741 } 742 743 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM2Opc(AMOpc, ShiftAmount, 744 ShOpc, IdxMode))); 745 return; 746 } 747 748 // Create a operand placeholder to always yield the same number of operands. 749 Inst.addOperand(MCOperand::CreateReg(0)); 750 751 // FIXME: #-0 is encoded differently than #0. Does the parser preserve 752 // the difference? 753 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset()); 754 assert(CE && "Non-constant mode 2 offset operand!"); 755 int64_t Offset = CE->getValue(); 756 757 if (Offset >= 0) 758 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM2Opc(ARM_AM::add, 759 Offset, ARM_AM::no_shift, IdxMode))); 760 else 761 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM2Opc(ARM_AM::sub, 762 -Offset, ARM_AM::no_shift, IdxMode))); 763 } 764 765 void addMemMode3Operands(MCInst &Inst, unsigned N) const { 766 assert(isMemMode3() && "Invalid mode or number of operands!"); 767 Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum())); 768 unsigned IdxMode = (getMemPreindexed() | getMemPostindexed() << 1); 769 770 if (getMemOffsetIsReg()) { 771 Inst.addOperand(MCOperand::CreateReg(getMemOffsetRegNum())); 772 773 ARM_AM::AddrOpc AMOpc = getMemNegative() ? ARM_AM::sub : ARM_AM::add; 774 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM3Opc(AMOpc, 0, 775 IdxMode))); 776 return; 777 } 778 779 // Create a operand placeholder to always yield the same number of operands. 780 Inst.addOperand(MCOperand::CreateReg(0)); 781 782 // FIXME: #-0 is encoded differently than #0. Does the parser preserve 783 // the difference? 784 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset()); 785 assert(CE && "Non-constant mode 3 offset operand!"); 786 int64_t Offset = CE->getValue(); 787 788 if (Offset >= 0) 789 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM3Opc(ARM_AM::add, 790 Offset, IdxMode))); 791 else 792 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM3Opc(ARM_AM::sub, 793 -Offset, IdxMode))); 794 } 795 796 void addMemMode5Operands(MCInst &Inst, unsigned N) const { 797 assert(N == 2 && isMemMode5() && "Invalid number of operands!"); 798 799 Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum())); 800 assert(!getMemOffsetIsReg() && "Invalid mode 5 operand"); 801 802 // FIXME: #-0 is encoded differently than #0. Does the parser preserve 803 // the difference? 804 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset()); 805 assert(CE && "Non-constant mode 5 offset operand!"); 806 807 // The MCInst offset operand doesn't include the low two bits (like 808 // the instruction encoding). 809 int64_t Offset = CE->getValue() / 4; 810 if (Offset >= 0) 811 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, 812 Offset))); 813 else 814 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, 815 -Offset))); 816 } 817 818 void addMemModeRegThumbOperands(MCInst &Inst, unsigned N) const { 819 assert(N == 2 && isMemModeRegThumb() && "Invalid number of operands!"); 820 Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum())); 821 Inst.addOperand(MCOperand::CreateReg(getMemOffsetRegNum())); 822 } 823 824 void addMemModeImmThumbOperands(MCInst &Inst, unsigned N) const { 825 assert(N == 2 && isMemModeImmThumb() && "Invalid number of operands!"); 826 Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum())); 827 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset()); 828 assert(CE && "Non-constant mode offset operand!"); 829 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 830 } 831 832 void addMSRMaskOperands(MCInst &Inst, unsigned N) const { 833 assert(N == 1 && "Invalid number of operands!"); 834 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask()))); 835 } 836 837 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const { 838 assert(N == 1 && "Invalid number of operands!"); 839 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags()))); 840 } 841 842 virtual void print(raw_ostream &OS) const; 843 844 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) { 845 ARMOperand *Op = new ARMOperand(CondCode); 846 Op->CC.Val = CC; 847 Op->StartLoc = S; 848 Op->EndLoc = S; 849 return Op; 850 } 851 852 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) { 853 ARMOperand *Op = new ARMOperand(CoprocNum); 854 Op->Cop.Val = CopVal; 855 Op->StartLoc = S; 856 Op->EndLoc = S; 857 return Op; 858 } 859 860 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) { 861 ARMOperand *Op = new ARMOperand(CoprocReg); 862 Op->Cop.Val = CopVal; 863 Op->StartLoc = S; 864 Op->EndLoc = S; 865 return Op; 866 } 867 868 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) { 869 ARMOperand *Op = new ARMOperand(CCOut); 870 Op->Reg.RegNum = RegNum; 871 Op->StartLoc = S; 872 Op->EndLoc = S; 873 return Op; 874 } 875 876 static ARMOperand *CreateToken(StringRef Str, SMLoc S) { 877 ARMOperand *Op = new ARMOperand(Token); 878 Op->Tok.Data = Str.data(); 879 Op->Tok.Length = Str.size(); 880 Op->StartLoc = S; 881 Op->EndLoc = S; 882 return Op; 883 } 884 885 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) { 886 ARMOperand *Op = new ARMOperand(Register); 887 Op->Reg.RegNum = RegNum; 888 Op->StartLoc = S; 889 Op->EndLoc = E; 890 return Op; 891 } 892 893 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, 894 unsigned SrcReg, 895 unsigned ShiftReg, 896 unsigned ShiftImm, 897 SMLoc S, SMLoc E) { 898 ARMOperand *Op = new ARMOperand(ShiftedRegister); 899 Op->ShiftedReg.ShiftTy = ShTy; 900 Op->ShiftedReg.SrcReg = SrcReg; 901 Op->ShiftedReg.ShiftReg = ShiftReg; 902 Op->ShiftedReg.ShiftImm = ShiftImm; 903 Op->StartLoc = S; 904 Op->EndLoc = E; 905 return Op; 906 } 907 908 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, 909 unsigned SrcReg, 910 unsigned ShiftImm, 911 SMLoc S, SMLoc E) { 912 ARMOperand *Op = new ARMOperand(ShiftedImmediate); 913 Op->ShiftedImm.ShiftTy = ShTy; 914 Op->ShiftedImm.SrcReg = SrcReg; 915 Op->ShiftedImm.ShiftImm = ShiftImm; 916 Op->StartLoc = S; 917 Op->EndLoc = E; 918 return Op; 919 } 920 921 static ARMOperand *CreateShifter(ARM_AM::ShiftOpc ShTy, 922 SMLoc S, SMLoc E) { 923 ARMOperand *Op = new ARMOperand(Shifter); 924 Op->Shift.ShiftTy = ShTy; 925 Op->StartLoc = S; 926 Op->EndLoc = E; 927 return Op; 928 } 929 930 static ARMOperand * 931 CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs, 932 SMLoc StartLoc, SMLoc EndLoc) { 933 KindTy Kind = RegisterList; 934 935 if (ARM::DPRRegClass.contains(Regs.front().first)) 936 Kind = DPRRegisterList; 937 else if (ARM::SPRRegClass.contains(Regs.front().first)) 938 Kind = SPRRegisterList; 939 940 ARMOperand *Op = new ARMOperand(Kind); 941 for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator 942 I = Regs.begin(), E = Regs.end(); I != E; ++I) 943 Op->Registers.push_back(I->first); 944 array_pod_sort(Op->Registers.begin(), Op->Registers.end()); 945 Op->StartLoc = StartLoc; 946 Op->EndLoc = EndLoc; 947 return Op; 948 } 949 950 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) { 951 ARMOperand *Op = new ARMOperand(Immediate); 952 Op->Imm.Val = Val; 953 Op->StartLoc = S; 954 Op->EndLoc = E; 955 return Op; 956 } 957 958 static ARMOperand *CreateMem(ARMII::AddrMode AddrMode, unsigned BaseRegNum, 959 bool OffsetIsReg, const MCExpr *Offset, 960 int OffsetRegNum, bool OffsetRegShifted, 961 enum ARM_AM::ShiftOpc ShiftType, 962 const MCExpr *ShiftAmount, bool Preindexed, 963 bool Postindexed, bool Negative, bool Writeback, 964 SMLoc S, SMLoc E) { 965 assert((OffsetRegNum == -1 || OffsetIsReg) && 966 "OffsetRegNum must imply OffsetIsReg!"); 967 assert((!OffsetRegShifted || OffsetIsReg) && 968 "OffsetRegShifted must imply OffsetIsReg!"); 969 assert((Offset || OffsetIsReg) && 970 "Offset must exists unless register offset is used!"); 971 assert((!ShiftAmount || (OffsetIsReg && OffsetRegShifted)) && 972 "Cannot have shift amount without shifted register offset!"); 973 assert((!Offset || !OffsetIsReg) && 974 "Cannot have expression offset and register offset!"); 975 976 ARMOperand *Op = new ARMOperand(Memory); 977 Op->Mem.AddrMode = AddrMode; 978 Op->Mem.BaseRegNum = BaseRegNum; 979 Op->Mem.OffsetIsReg = OffsetIsReg; 980 if (OffsetIsReg) 981 Op->Mem.Offset.RegNum = OffsetRegNum; 982 else 983 Op->Mem.Offset.Value = Offset; 984 Op->Mem.OffsetRegShifted = OffsetRegShifted; 985 Op->Mem.ShiftType = ShiftType; 986 Op->Mem.ShiftAmount = ShiftAmount; 987 Op->Mem.Preindexed = Preindexed; 988 Op->Mem.Postindexed = Postindexed; 989 Op->Mem.Negative = Negative; 990 Op->Mem.Writeback = Writeback; 991 992 Op->StartLoc = S; 993 Op->EndLoc = E; 994 return Op; 995 } 996 997 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) { 998 ARMOperand *Op = new ARMOperand(MemBarrierOpt); 999 Op->MBOpt.Val = Opt; 1000 Op->StartLoc = S; 1001 Op->EndLoc = S; 1002 return Op; 1003 } 1004 1005 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) { 1006 ARMOperand *Op = new ARMOperand(ProcIFlags); 1007 Op->IFlags.Val = IFlags; 1008 Op->StartLoc = S; 1009 Op->EndLoc = S; 1010 return Op; 1011 } 1012 1013 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) { 1014 ARMOperand *Op = new ARMOperand(MSRMask); 1015 Op->MMask.Val = MMask; 1016 Op->StartLoc = S; 1017 Op->EndLoc = S; 1018 return Op; 1019 } 1020}; 1021 1022} // end anonymous namespace. 1023 1024void ARMOperand::print(raw_ostream &OS) const { 1025 switch (Kind) { 1026 case CondCode: 1027 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">"; 1028 break; 1029 case CCOut: 1030 OS << "<ccout " << getReg() << ">"; 1031 break; 1032 case CoprocNum: 1033 OS << "<coprocessor number: " << getCoproc() << ">"; 1034 break; 1035 case CoprocReg: 1036 OS << "<coprocessor register: " << getCoproc() << ">"; 1037 break; 1038 case MSRMask: 1039 OS << "<mask: " << getMSRMask() << ">"; 1040 break; 1041 case Immediate: 1042 getImm()->print(OS); 1043 break; 1044 case MemBarrierOpt: 1045 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">"; 1046 break; 1047 case Memory: 1048 OS << "<memory " 1049 << "am:" << ARMII::AddrModeToString(getMemAddrMode()) 1050 << " base:" << getMemBaseRegNum(); 1051 if (getMemOffsetIsReg()) { 1052 OS << " offset:<register " << getMemOffsetRegNum(); 1053 if (getMemOffsetRegShifted()) { 1054 OS << " offset-shift-type:" << getMemShiftType(); 1055 OS << " offset-shift-amount:" << *getMemShiftAmount(); 1056 } 1057 } else { 1058 OS << " offset:" << *getMemOffset(); 1059 } 1060 if (getMemOffsetIsReg()) 1061 OS << " (offset-is-reg)"; 1062 if (getMemPreindexed()) 1063 OS << " (pre-indexed)"; 1064 if (getMemPostindexed()) 1065 OS << " (post-indexed)"; 1066 if (getMemNegative()) 1067 OS << " (negative)"; 1068 if (getMemWriteback()) 1069 OS << " (writeback)"; 1070 OS << ">"; 1071 break; 1072 case ProcIFlags: { 1073 OS << "<ARM_PROC::"; 1074 unsigned IFlags = getProcIFlags(); 1075 for (int i=2; i >= 0; --i) 1076 if (IFlags & (1 << i)) 1077 OS << ARM_PROC::IFlagsToString(1 << i); 1078 OS << ">"; 1079 break; 1080 } 1081 case Register: 1082 OS << "<register " << getReg() << ">"; 1083 break; 1084 case Shifter: 1085 OS << "<shifter " << ARM_AM::getShiftOpcStr(Shift.ShiftTy) << ">"; 1086 break; 1087 case ShiftedRegister: 1088 OS << "<so_reg_reg " 1089 << ShiftedReg.SrcReg 1090 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(ShiftedReg.ShiftImm)) 1091 << ", " << ShiftedReg.ShiftReg << ", " 1092 << ARM_AM::getSORegOffset(ShiftedReg.ShiftImm) 1093 << ">"; 1094 break; 1095 case ShiftedImmediate: 1096 OS << "<so_reg_imm " 1097 << ShiftedImm.SrcReg 1098 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(ShiftedImm.ShiftImm)) 1099 << ", " << ARM_AM::getSORegOffset(ShiftedImm.ShiftImm) 1100 << ">"; 1101 break; 1102 case RegisterList: 1103 case DPRRegisterList: 1104 case SPRRegisterList: { 1105 OS << "<register_list "; 1106 1107 const SmallVectorImpl<unsigned> &RegList = getRegList(); 1108 for (SmallVectorImpl<unsigned>::const_iterator 1109 I = RegList.begin(), E = RegList.end(); I != E; ) { 1110 OS << *I; 1111 if (++I < E) OS << ", "; 1112 } 1113 1114 OS << ">"; 1115 break; 1116 } 1117 case Token: 1118 OS << "'" << getToken() << "'"; 1119 break; 1120 } 1121} 1122 1123/// @name Auto-generated Match Functions 1124/// { 1125 1126static unsigned MatchRegisterName(StringRef Name); 1127 1128/// } 1129 1130bool ARMAsmParser::ParseRegister(unsigned &RegNo, 1131 SMLoc &StartLoc, SMLoc &EndLoc) { 1132 RegNo = TryParseRegister(); 1133 1134 return (RegNo == (unsigned)-1); 1135} 1136 1137/// Try to parse a register name. The token must be an Identifier when called, 1138/// and if it is a register name the token is eaten and the register number is 1139/// returned. Otherwise return -1. 1140/// 1141int ARMAsmParser::TryParseRegister() { 1142 const AsmToken &Tok = Parser.getTok(); 1143 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 1144 1145 // FIXME: Validate register for the current architecture; we have to do 1146 // validation later, so maybe there is no need for this here. 1147 std::string upperCase = Tok.getString().str(); 1148 std::string lowerCase = LowercaseString(upperCase); 1149 unsigned RegNum = MatchRegisterName(lowerCase); 1150 if (!RegNum) { 1151 RegNum = StringSwitch<unsigned>(lowerCase) 1152 .Case("r13", ARM::SP) 1153 .Case("r14", ARM::LR) 1154 .Case("r15", ARM::PC) 1155 .Case("ip", ARM::R12) 1156 .Default(0); 1157 } 1158 if (!RegNum) return -1; 1159 1160 Parser.Lex(); // Eat identifier token. 1161 return RegNum; 1162} 1163 1164// Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0. 1165// If a recoverable error occurs, return 1. If an irrecoverable error 1166// occurs, return -1. An irrecoverable error is one where tokens have been 1167// consumed in the process of trying to parse the shifter (i.e., when it is 1168// indeed a shifter operand, but malformed). 1169int ARMAsmParser::TryParseShiftRegister( 1170 SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1171 SMLoc S = Parser.getTok().getLoc(); 1172 const AsmToken &Tok = Parser.getTok(); 1173 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 1174 1175 std::string upperCase = Tok.getString().str(); 1176 std::string lowerCase = LowercaseString(upperCase); 1177 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase) 1178 .Case("lsl", ARM_AM::lsl) 1179 .Case("lsr", ARM_AM::lsr) 1180 .Case("asr", ARM_AM::asr) 1181 .Case("ror", ARM_AM::ror) 1182 .Case("rrx", ARM_AM::rrx) 1183 .Default(ARM_AM::no_shift); 1184 1185 if (ShiftTy == ARM_AM::no_shift) 1186 return 1; 1187 1188 Parser.Lex(); // Eat the operator. 1189 1190 // The source register for the shift has already been added to the 1191 // operand list, so we need to pop it off and combine it into the shifted 1192 // register operand instead. 1193 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val()); 1194 if (!PrevOp->isReg()) 1195 return Error(PrevOp->getStartLoc(), "shift must be of a register"); 1196 int SrcReg = PrevOp->getReg(); 1197 int64_t Imm = 0; 1198 int ShiftReg = 0; 1199 if (ShiftTy == ARM_AM::rrx) { 1200 // RRX Doesn't have an explicit shift amount. The encoder expects 1201 // the shift register to be the same as the source register. Seems odd, 1202 // but OK. 1203 ShiftReg = SrcReg; 1204 } else { 1205 // Figure out if this is shifted by a constant or a register (for non-RRX). 1206 if (Parser.getTok().is(AsmToken::Hash)) { 1207 Parser.Lex(); // Eat hash. 1208 SMLoc ImmLoc = Parser.getTok().getLoc(); 1209 const MCExpr *ShiftExpr = 0; 1210 if (getParser().ParseExpression(ShiftExpr)) { 1211 Error(ImmLoc, "invalid immediate shift value"); 1212 return -1; 1213 } 1214 // The expression must be evaluatable as an immediate. 1215 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr); 1216 if (!CE) { 1217 Error(ImmLoc, "invalid immediate shift value"); 1218 return -1; 1219 } 1220 // Range check the immediate. 1221 // lsl, ror: 0 <= imm <= 31 1222 // lsr, asr: 0 <= imm <= 32 1223 Imm = CE->getValue(); 1224 if (Imm < 0 || 1225 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) || 1226 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) { 1227 Error(ImmLoc, "immediate shift value out of range"); 1228 return -1; 1229 } 1230 } else if (Parser.getTok().is(AsmToken::Identifier)) { 1231 ShiftReg = TryParseRegister(); 1232 SMLoc L = Parser.getTok().getLoc(); 1233 if (ShiftReg == -1) { 1234 Error (L, "expected immediate or register in shift operand"); 1235 return -1; 1236 } 1237 } else { 1238 Error (Parser.getTok().getLoc(), 1239 "expected immediate or register in shift operand"); 1240 return -1; 1241 } 1242 } 1243 1244 if (ShiftReg && ShiftTy != ARM_AM::rrx) 1245 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg, 1246 ShiftReg, Imm, 1247 S, Parser.getTok().getLoc())); 1248 else 1249 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm, 1250 S, Parser.getTok().getLoc())); 1251 1252 return 0; 1253} 1254 1255 1256/// Try to parse a register name. The token must be an Identifier when called. 1257/// If it's a register, an AsmOperand is created. Another AsmOperand is created 1258/// if there is a "writeback". 'true' if it's not a register. 1259/// 1260/// TODO this is likely to change to allow different register types and or to 1261/// parse for a specific register type. 1262bool ARMAsmParser:: 1263TryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1264 SMLoc S = Parser.getTok().getLoc(); 1265 int RegNo = TryParseRegister(); 1266 if (RegNo == -1) 1267 return true; 1268 1269 Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc())); 1270 1271 const AsmToken &ExclaimTok = Parser.getTok(); 1272 if (ExclaimTok.is(AsmToken::Exclaim)) { 1273 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(), 1274 ExclaimTok.getLoc())); 1275 Parser.Lex(); // Eat exclaim token 1276 } 1277 1278 return false; 1279} 1280 1281/// MatchCoprocessorOperandName - Try to parse an coprocessor related 1282/// instruction with a symbolic operand name. Example: "p1", "p7", "c3", 1283/// "c5", ... 1284static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) { 1285 // Use the same layout as the tablegen'erated register name matcher. Ugly, 1286 // but efficient. 1287 switch (Name.size()) { 1288 default: break; 1289 case 2: 1290 if (Name[0] != CoprocOp) 1291 return -1; 1292 switch (Name[1]) { 1293 default: return -1; 1294 case '0': return 0; 1295 case '1': return 1; 1296 case '2': return 2; 1297 case '3': return 3; 1298 case '4': return 4; 1299 case '5': return 5; 1300 case '6': return 6; 1301 case '7': return 7; 1302 case '8': return 8; 1303 case '9': return 9; 1304 } 1305 break; 1306 case 3: 1307 if (Name[0] != CoprocOp || Name[1] != '1') 1308 return -1; 1309 switch (Name[2]) { 1310 default: return -1; 1311 case '0': return 10; 1312 case '1': return 11; 1313 case '2': return 12; 1314 case '3': return 13; 1315 case '4': return 14; 1316 case '5': return 15; 1317 } 1318 break; 1319 } 1320 1321 return -1; 1322} 1323 1324/// tryParseCoprocNumOperand - Try to parse an coprocessor number operand. The 1325/// token must be an Identifier when called, and if it is a coprocessor 1326/// number, the token is eaten and the operand is added to the operand list. 1327ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 1328tryParseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1329 SMLoc S = Parser.getTok().getLoc(); 1330 const AsmToken &Tok = Parser.getTok(); 1331 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 1332 1333 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p'); 1334 if (Num == -1) 1335 return MatchOperand_NoMatch; 1336 1337 Parser.Lex(); // Eat identifier token. 1338 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S)); 1339 return MatchOperand_Success; 1340} 1341 1342/// tryParseCoprocRegOperand - Try to parse an coprocessor register operand. The 1343/// token must be an Identifier when called, and if it is a coprocessor 1344/// number, the token is eaten and the operand is added to the operand list. 1345ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 1346tryParseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1347 SMLoc S = Parser.getTok().getLoc(); 1348 const AsmToken &Tok = Parser.getTok(); 1349 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 1350 1351 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c'); 1352 if (Reg == -1) 1353 return MatchOperand_NoMatch; 1354 1355 Parser.Lex(); // Eat identifier token. 1356 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S)); 1357 return MatchOperand_Success; 1358} 1359 1360/// Parse a register list, return it if successful else return null. The first 1361/// token must be a '{' when called. 1362bool ARMAsmParser:: 1363ParseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1364 assert(Parser.getTok().is(AsmToken::LCurly) && 1365 "Token is not a Left Curly Brace"); 1366 SMLoc S = Parser.getTok().getLoc(); 1367 1368 // Read the rest of the registers in the list. 1369 unsigned PrevRegNum = 0; 1370 SmallVector<std::pair<unsigned, SMLoc>, 32> Registers; 1371 1372 do { 1373 bool IsRange = Parser.getTok().is(AsmToken::Minus); 1374 Parser.Lex(); // Eat non-identifier token. 1375 1376 const AsmToken &RegTok = Parser.getTok(); 1377 SMLoc RegLoc = RegTok.getLoc(); 1378 if (RegTok.isNot(AsmToken::Identifier)) { 1379 Error(RegLoc, "register expected"); 1380 return true; 1381 } 1382 1383 int RegNum = TryParseRegister(); 1384 if (RegNum == -1) { 1385 Error(RegLoc, "register expected"); 1386 return true; 1387 } 1388 1389 if (IsRange) { 1390 int Reg = PrevRegNum; 1391 do { 1392 ++Reg; 1393 Registers.push_back(std::make_pair(Reg, RegLoc)); 1394 } while (Reg != RegNum); 1395 } else { 1396 Registers.push_back(std::make_pair(RegNum, RegLoc)); 1397 } 1398 1399 PrevRegNum = RegNum; 1400 } while (Parser.getTok().is(AsmToken::Comma) || 1401 Parser.getTok().is(AsmToken::Minus)); 1402 1403 // Process the right curly brace of the list. 1404 const AsmToken &RCurlyTok = Parser.getTok(); 1405 if (RCurlyTok.isNot(AsmToken::RCurly)) { 1406 Error(RCurlyTok.getLoc(), "'}' expected"); 1407 return true; 1408 } 1409 1410 SMLoc E = RCurlyTok.getLoc(); 1411 Parser.Lex(); // Eat right curly brace token. 1412 1413 // Verify the register list. 1414 SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator 1415 RI = Registers.begin(), RE = Registers.end(); 1416 1417 unsigned HighRegNum = getARMRegisterNumbering(RI->first); 1418 bool EmittedWarning = false; 1419 1420 DenseMap<unsigned, bool> RegMap; 1421 RegMap[HighRegNum] = true; 1422 1423 for (++RI; RI != RE; ++RI) { 1424 const std::pair<unsigned, SMLoc> &RegInfo = *RI; 1425 unsigned Reg = getARMRegisterNumbering(RegInfo.first); 1426 1427 if (RegMap[Reg]) { 1428 Error(RegInfo.second, "register duplicated in register list"); 1429 return true; 1430 } 1431 1432 if (!EmittedWarning && Reg < HighRegNum) 1433 Warning(RegInfo.second, 1434 "register not in ascending order in register list"); 1435 1436 RegMap[Reg] = true; 1437 HighRegNum = std::max(Reg, HighRegNum); 1438 } 1439 1440 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E)); 1441 return false; 1442} 1443 1444/// tryParseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options. 1445ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 1446tryParseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1447 SMLoc S = Parser.getTok().getLoc(); 1448 const AsmToken &Tok = Parser.getTok(); 1449 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 1450 StringRef OptStr = Tok.getString(); 1451 1452 unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size())) 1453 .Case("sy", ARM_MB::SY) 1454 .Case("st", ARM_MB::ST) 1455 .Case("sh", ARM_MB::ISH) 1456 .Case("ish", ARM_MB::ISH) 1457 .Case("shst", ARM_MB::ISHST) 1458 .Case("ishst", ARM_MB::ISHST) 1459 .Case("nsh", ARM_MB::NSH) 1460 .Case("un", ARM_MB::NSH) 1461 .Case("nshst", ARM_MB::NSHST) 1462 .Case("unst", ARM_MB::NSHST) 1463 .Case("osh", ARM_MB::OSH) 1464 .Case("oshst", ARM_MB::OSHST) 1465 .Default(~0U); 1466 1467 if (Opt == ~0U) 1468 return MatchOperand_NoMatch; 1469 1470 Parser.Lex(); // Eat identifier token. 1471 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S)); 1472 return MatchOperand_Success; 1473} 1474 1475/// tryParseProcIFlagsOperand - Try to parse iflags from CPS instruction. 1476ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 1477tryParseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1478 SMLoc S = Parser.getTok().getLoc(); 1479 const AsmToken &Tok = Parser.getTok(); 1480 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 1481 StringRef IFlagsStr = Tok.getString(); 1482 1483 unsigned IFlags = 0; 1484 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) { 1485 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1)) 1486 .Case("a", ARM_PROC::A) 1487 .Case("i", ARM_PROC::I) 1488 .Case("f", ARM_PROC::F) 1489 .Default(~0U); 1490 1491 // If some specific iflag is already set, it means that some letter is 1492 // present more than once, this is not acceptable. 1493 if (Flag == ~0U || (IFlags & Flag)) 1494 return MatchOperand_NoMatch; 1495 1496 IFlags |= Flag; 1497 } 1498 1499 Parser.Lex(); // Eat identifier token. 1500 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S)); 1501 return MatchOperand_Success; 1502} 1503 1504/// tryParseMSRMaskOperand - Try to parse mask flags from MSR instruction. 1505ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 1506tryParseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1507 SMLoc S = Parser.getTok().getLoc(); 1508 const AsmToken &Tok = Parser.getTok(); 1509 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 1510 StringRef Mask = Tok.getString(); 1511 1512 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf" 1513 size_t Start = 0, Next = Mask.find('_'); 1514 StringRef Flags = ""; 1515 std::string SpecReg = LowercaseString(Mask.slice(Start, Next)); 1516 if (Next != StringRef::npos) 1517 Flags = Mask.slice(Next+1, Mask.size()); 1518 1519 // FlagsVal contains the complete mask: 1520 // 3-0: Mask 1521 // 4: Special Reg (cpsr, apsr => 0; spsr => 1) 1522 unsigned FlagsVal = 0; 1523 1524 if (SpecReg == "apsr") { 1525 FlagsVal = StringSwitch<unsigned>(Flags) 1526 .Case("nzcvq", 0x8) // same as CPSR_f 1527 .Case("g", 0x4) // same as CPSR_s 1528 .Case("nzcvqg", 0xc) // same as CPSR_fs 1529 .Default(~0U); 1530 1531 if (FlagsVal == ~0U) { 1532 if (!Flags.empty()) 1533 return MatchOperand_NoMatch; 1534 else 1535 FlagsVal = 0; // No flag 1536 } 1537 } else if (SpecReg == "cpsr" || SpecReg == "spsr") { 1538 if (Flags == "all") // cpsr_all is an alias for cpsr_fc 1539 Flags = "fc"; 1540 for (int i = 0, e = Flags.size(); i != e; ++i) { 1541 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1)) 1542 .Case("c", 1) 1543 .Case("x", 2) 1544 .Case("s", 4) 1545 .Case("f", 8) 1546 .Default(~0U); 1547 1548 // If some specific flag is already set, it means that some letter is 1549 // present more than once, this is not acceptable. 1550 if (FlagsVal == ~0U || (FlagsVal & Flag)) 1551 return MatchOperand_NoMatch; 1552 FlagsVal |= Flag; 1553 } 1554 } else // No match for special register. 1555 return MatchOperand_NoMatch; 1556 1557 // Special register without flags are equivalent to "fc" flags. 1558 if (!FlagsVal) 1559 FlagsVal = 0x9; 1560 1561 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1) 1562 if (SpecReg == "spsr") 1563 FlagsVal |= 16; 1564 1565 Parser.Lex(); // Eat identifier token. 1566 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); 1567 return MatchOperand_Success; 1568} 1569 1570/// tryParseMemMode2Operand - Try to parse memory addressing mode 2 operand. 1571ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 1572tryParseMemMode2Operand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1573 assert(Parser.getTok().is(AsmToken::LBrac) && "Token is not a \"[\""); 1574 1575 if (ParseMemory(Operands, ARMII::AddrMode2)) 1576 return MatchOperand_NoMatch; 1577 1578 return MatchOperand_Success; 1579} 1580 1581/// tryParseMemMode3Operand - Try to parse memory addressing mode 3 operand. 1582ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 1583tryParseMemMode3Operand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1584 assert(Parser.getTok().is(AsmToken::LBrac) && "Token is not a \"[\""); 1585 1586 if (ParseMemory(Operands, ARMII::AddrMode3)) 1587 return MatchOperand_NoMatch; 1588 1589 return MatchOperand_Success; 1590} 1591 1592ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 1593parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op, 1594 int Low, int High) { 1595 const AsmToken &Tok = Parser.getTok(); 1596 if (Tok.isNot(AsmToken::Identifier)) { 1597 Error(Parser.getTok().getLoc(), Op + " operand expected."); 1598 return MatchOperand_ParseFail; 1599 } 1600 StringRef ShiftName = Tok.getString(); 1601 std::string LowerOp = LowercaseString(Op); 1602 std::string UpperOp = UppercaseString(Op); 1603 if (ShiftName != LowerOp && ShiftName != UpperOp) { 1604 Error(Parser.getTok().getLoc(), Op + " operand expected."); 1605 return MatchOperand_ParseFail; 1606 } 1607 Parser.Lex(); // Eat shift type token. 1608 1609 // There must be a '#' and a shift amount. 1610 if (Parser.getTok().isNot(AsmToken::Hash)) { 1611 Error(Parser.getTok().getLoc(), "'#' expected"); 1612 return MatchOperand_ParseFail; 1613 } 1614 Parser.Lex(); // Eat hash token. 1615 1616 const MCExpr *ShiftAmount; 1617 SMLoc Loc = Parser.getTok().getLoc(); 1618 if (getParser().ParseExpression(ShiftAmount)) { 1619 Error(Loc, "illegal expression"); 1620 return MatchOperand_ParseFail; 1621 } 1622 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 1623 if (!CE) { 1624 Error(Loc, "constant expression expected"); 1625 return MatchOperand_ParseFail; 1626 } 1627 int Val = CE->getValue(); 1628 if (Val < Low || Val > High) { 1629 Error(Loc, "immediate value out of range"); 1630 return MatchOperand_ParseFail; 1631 } 1632 1633 Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc())); 1634 1635 return MatchOperand_Success; 1636} 1637 1638/// CvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst. 1639/// Needed here because the Asm Gen Matcher can't handle properly tied operands 1640/// when they refer multiple MIOperands inside a single one. 1641bool ARMAsmParser:: 1642CvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, 1643 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1644 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 1645 1646 // Create a writeback register dummy placeholder. 1647 Inst.addOperand(MCOperand::CreateImm(0)); 1648 1649 ((ARMOperand*)Operands[3])->addMemMode2Operands(Inst, 3); 1650 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 1651 return true; 1652} 1653 1654/// CvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst. 1655/// Needed here because the Asm Gen Matcher can't handle properly tied operands 1656/// when they refer multiple MIOperands inside a single one. 1657bool ARMAsmParser:: 1658CvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, 1659 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1660 // Create a writeback register dummy placeholder. 1661 Inst.addOperand(MCOperand::CreateImm(0)); 1662 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 1663 ((ARMOperand*)Operands[3])->addMemMode2Operands(Inst, 3); 1664 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 1665 return true; 1666} 1667 1668/// CvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst. 1669/// Needed here because the Asm Gen Matcher can't handle properly tied operands 1670/// when they refer multiple MIOperands inside a single one. 1671bool ARMAsmParser:: 1672CvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, 1673 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1674 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 1675 1676 // Create a writeback register dummy placeholder. 1677 Inst.addOperand(MCOperand::CreateImm(0)); 1678 1679 ((ARMOperand*)Operands[3])->addMemMode3Operands(Inst, 3); 1680 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 1681 return true; 1682} 1683 1684/// CvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst. 1685/// Needed here because the Asm Gen Matcher can't handle properly tied operands 1686/// when they refer multiple MIOperands inside a single one. 1687bool ARMAsmParser:: 1688CvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, 1689 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1690 // Create a writeback register dummy placeholder. 1691 Inst.addOperand(MCOperand::CreateImm(0)); 1692 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 1693 ((ARMOperand*)Operands[3])->addMemMode3Operands(Inst, 3); 1694 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 1695 return true; 1696} 1697 1698/// Parse an ARM memory expression, return false if successful else return true 1699/// or an error. The first token must be a '[' when called. 1700/// 1701/// TODO Only preindexing and postindexing addressing are started, unindexed 1702/// with option, etc are still to do. 1703bool ARMAsmParser:: 1704ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands, 1705 ARMII::AddrMode AddrMode = ARMII::AddrModeNone) { 1706 SMLoc S, E; 1707 assert(Parser.getTok().is(AsmToken::LBrac) && 1708 "Token is not a Left Bracket"); 1709 S = Parser.getTok().getLoc(); 1710 Parser.Lex(); // Eat left bracket token. 1711 1712 const AsmToken &BaseRegTok = Parser.getTok(); 1713 if (BaseRegTok.isNot(AsmToken::Identifier)) { 1714 Error(BaseRegTok.getLoc(), "register expected"); 1715 return true; 1716 } 1717 int BaseRegNum = TryParseRegister(); 1718 if (BaseRegNum == -1) { 1719 Error(BaseRegTok.getLoc(), "register expected"); 1720 return true; 1721 } 1722 1723 // The next token must either be a comma or a closing bracket. 1724 const AsmToken &Tok = Parser.getTok(); 1725 if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac)) 1726 return true; 1727 1728 bool Preindexed = false; 1729 bool Postindexed = false; 1730 bool OffsetIsReg = false; 1731 bool Negative = false; 1732 bool Writeback = false; 1733 ARMOperand *WBOp = 0; 1734 int OffsetRegNum = -1; 1735 bool OffsetRegShifted = false; 1736 enum ARM_AM::ShiftOpc ShiftType = ARM_AM::lsl; 1737 const MCExpr *ShiftAmount = 0; 1738 const MCExpr *Offset = 0; 1739 1740 // First look for preindexed address forms, that is after the "[Rn" we now 1741 // have to see if the next token is a comma. 1742 if (Tok.is(AsmToken::Comma)) { 1743 Preindexed = true; 1744 Parser.Lex(); // Eat comma token. 1745 1746 if (ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType, ShiftAmount, 1747 Offset, OffsetIsReg, OffsetRegNum, E)) 1748 return true; 1749 const AsmToken &RBracTok = Parser.getTok(); 1750 if (RBracTok.isNot(AsmToken::RBrac)) { 1751 Error(RBracTok.getLoc(), "']' expected"); 1752 return true; 1753 } 1754 E = RBracTok.getLoc(); 1755 Parser.Lex(); // Eat right bracket token. 1756 1757 const AsmToken &ExclaimTok = Parser.getTok(); 1758 if (ExclaimTok.is(AsmToken::Exclaim)) { 1759 // None of addrmode3 instruction uses "!" 1760 if (AddrMode == ARMII::AddrMode3) 1761 return true; 1762 1763 WBOp = ARMOperand::CreateToken(ExclaimTok.getString(), 1764 ExclaimTok.getLoc()); 1765 Writeback = true; 1766 Parser.Lex(); // Eat exclaim token 1767 } else { // In addressing mode 2, pre-indexed mode always end with "!" 1768 if (AddrMode == ARMII::AddrMode2) 1769 Preindexed = false; 1770 } 1771 } else { 1772 // The "[Rn" we have so far was not followed by a comma. 1773 1774 // If there's anything other than the right brace, this is a post indexing 1775 // addressing form. 1776 E = Tok.getLoc(); 1777 Parser.Lex(); // Eat right bracket token. 1778 1779 const AsmToken &NextTok = Parser.getTok(); 1780 1781 if (NextTok.isNot(AsmToken::EndOfStatement)) { 1782 Postindexed = true; 1783 Writeback = true; 1784 1785 if (NextTok.isNot(AsmToken::Comma)) { 1786 Error(NextTok.getLoc(), "',' expected"); 1787 return true; 1788 } 1789 1790 Parser.Lex(); // Eat comma token. 1791 1792 if (ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType, 1793 ShiftAmount, Offset, OffsetIsReg, OffsetRegNum, 1794 E)) 1795 return true; 1796 } 1797 } 1798 1799 // Force Offset to exist if used. 1800 if (!OffsetIsReg) { 1801 if (!Offset) 1802 Offset = MCConstantExpr::Create(0, getContext()); 1803 } else { 1804 if (AddrMode == ARMII::AddrMode3 && OffsetRegShifted) { 1805 Error(E, "shift amount not supported"); 1806 return true; 1807 } 1808 } 1809 1810 Operands.push_back(ARMOperand::CreateMem(AddrMode, BaseRegNum, OffsetIsReg, 1811 Offset, OffsetRegNum, OffsetRegShifted, 1812 ShiftType, ShiftAmount, Preindexed, 1813 Postindexed, Negative, Writeback, S, E)); 1814 if (WBOp) 1815 Operands.push_back(WBOp); 1816 1817 return false; 1818} 1819 1820/// Parse the offset of a memory operand after we have seen "[Rn," or "[Rn]," 1821/// we will parse the following (were +/- means that a plus or minus is 1822/// optional): 1823/// +/-Rm 1824/// +/-Rm, shift 1825/// #offset 1826/// we return false on success or an error otherwise. 1827bool ARMAsmParser::ParseMemoryOffsetReg(bool &Negative, 1828 bool &OffsetRegShifted, 1829 enum ARM_AM::ShiftOpc &ShiftType, 1830 const MCExpr *&ShiftAmount, 1831 const MCExpr *&Offset, 1832 bool &OffsetIsReg, 1833 int &OffsetRegNum, 1834 SMLoc &E) { 1835 Negative = false; 1836 OffsetRegShifted = false; 1837 OffsetIsReg = false; 1838 OffsetRegNum = -1; 1839 const AsmToken &NextTok = Parser.getTok(); 1840 E = NextTok.getLoc(); 1841 if (NextTok.is(AsmToken::Plus)) 1842 Parser.Lex(); // Eat plus token. 1843 else if (NextTok.is(AsmToken::Minus)) { 1844 Negative = true; 1845 Parser.Lex(); // Eat minus token 1846 } 1847 // See if there is a register following the "[Rn," or "[Rn]," we have so far. 1848 const AsmToken &OffsetRegTok = Parser.getTok(); 1849 if (OffsetRegTok.is(AsmToken::Identifier)) { 1850 SMLoc CurLoc = OffsetRegTok.getLoc(); 1851 OffsetRegNum = TryParseRegister(); 1852 if (OffsetRegNum != -1) { 1853 OffsetIsReg = true; 1854 E = CurLoc; 1855 } 1856 } 1857 1858 // If we parsed a register as the offset then there can be a shift after that. 1859 if (OffsetRegNum != -1) { 1860 // Look for a comma then a shift 1861 const AsmToken &Tok = Parser.getTok(); 1862 if (Tok.is(AsmToken::Comma)) { 1863 Parser.Lex(); // Eat comma token. 1864 1865 const AsmToken &Tok = Parser.getTok(); 1866 if (ParseShift(ShiftType, ShiftAmount, E)) 1867 return Error(Tok.getLoc(), "shift expected"); 1868 OffsetRegShifted = true; 1869 } 1870 } 1871 else { // the "[Rn," or "[Rn,]" we have so far was not followed by "Rm" 1872 // Look for #offset following the "[Rn," or "[Rn]," 1873 const AsmToken &HashTok = Parser.getTok(); 1874 if (HashTok.isNot(AsmToken::Hash)) 1875 return Error(HashTok.getLoc(), "'#' expected"); 1876 1877 Parser.Lex(); // Eat hash token. 1878 1879 if (getParser().ParseExpression(Offset)) 1880 return true; 1881 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 1882 } 1883 return false; 1884} 1885 1886/// ParseShift as one of these two: 1887/// ( lsl | lsr | asr | ror ) , # shift_amount 1888/// rrx 1889/// and returns true if it parses a shift otherwise it returns false. 1890bool ARMAsmParser::ParseShift(ARM_AM::ShiftOpc &St, 1891 const MCExpr *&ShiftAmount, SMLoc &E) { 1892 const AsmToken &Tok = Parser.getTok(); 1893 if (Tok.isNot(AsmToken::Identifier)) 1894 return true; 1895 StringRef ShiftName = Tok.getString(); 1896 if (ShiftName == "lsl" || ShiftName == "LSL") 1897 St = ARM_AM::lsl; 1898 else if (ShiftName == "lsr" || ShiftName == "LSR") 1899 St = ARM_AM::lsr; 1900 else if (ShiftName == "asr" || ShiftName == "ASR") 1901 St = ARM_AM::asr; 1902 else if (ShiftName == "ror" || ShiftName == "ROR") 1903 St = ARM_AM::ror; 1904 else if (ShiftName == "rrx" || ShiftName == "RRX") 1905 St = ARM_AM::rrx; 1906 else 1907 return true; 1908 Parser.Lex(); // Eat shift type token. 1909 1910 // Rrx stands alone. 1911 if (St == ARM_AM::rrx) 1912 return false; 1913 1914 // Otherwise, there must be a '#' and a shift amount. 1915 const AsmToken &HashTok = Parser.getTok(); 1916 if (HashTok.isNot(AsmToken::Hash)) 1917 return Error(HashTok.getLoc(), "'#' expected"); 1918 Parser.Lex(); // Eat hash token. 1919 1920 if (getParser().ParseExpression(ShiftAmount)) 1921 return true; 1922 1923 return false; 1924} 1925 1926/// Parse a arm instruction operand. For now this parses the operand regardless 1927/// of the mnemonic. 1928bool ARMAsmParser::ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands, 1929 StringRef Mnemonic) { 1930 SMLoc S, E; 1931 1932 // Check if the current operand has a custom associated parser, if so, try to 1933 // custom parse the operand, or fallback to the general approach. 1934 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic); 1935 if (ResTy == MatchOperand_Success) 1936 return false; 1937 // If there wasn't a custom match, try the generic matcher below. Otherwise, 1938 // there was a match, but an error occurred, in which case, just return that 1939 // the operand parsing failed. 1940 if (ResTy == MatchOperand_ParseFail) 1941 return true; 1942 1943 switch (getLexer().getKind()) { 1944 default: 1945 Error(Parser.getTok().getLoc(), "unexpected token in operand"); 1946 return true; 1947 case AsmToken::Identifier: { 1948 if (!TryParseRegisterWithWriteBack(Operands)) 1949 return false; 1950 int Res = TryParseShiftRegister(Operands); 1951 if (Res == 0) // success 1952 return false; 1953 else if (Res == -1) // irrecoverable error 1954 return true; 1955 1956 // Fall though for the Identifier case that is not a register or a 1957 // special name. 1958 } 1959 case AsmToken::Integer: // things like 1f and 2b as a branch targets 1960 case AsmToken::Dot: { // . as a branch target 1961 // This was not a register so parse other operands that start with an 1962 // identifier (like labels) as expressions and create them as immediates. 1963 const MCExpr *IdVal; 1964 S = Parser.getTok().getLoc(); 1965 if (getParser().ParseExpression(IdVal)) 1966 return true; 1967 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 1968 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E)); 1969 return false; 1970 } 1971 case AsmToken::LBrac: 1972 return ParseMemory(Operands); 1973 case AsmToken::LCurly: 1974 return ParseRegisterList(Operands); 1975 case AsmToken::Hash: 1976 // #42 -> immediate. 1977 // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate 1978 S = Parser.getTok().getLoc(); 1979 Parser.Lex(); 1980 const MCExpr *ImmVal; 1981 if (getParser().ParseExpression(ImmVal)) 1982 return true; 1983 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 1984 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E)); 1985 return false; 1986 case AsmToken::Colon: { 1987 // ":lower16:" and ":upper16:" expression prefixes 1988 // FIXME: Check it's an expression prefix, 1989 // e.g. (FOO - :lower16:BAR) isn't legal. 1990 ARMMCExpr::VariantKind RefKind; 1991 if (ParsePrefix(RefKind)) 1992 return true; 1993 1994 const MCExpr *SubExprVal; 1995 if (getParser().ParseExpression(SubExprVal)) 1996 return true; 1997 1998 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal, 1999 getContext()); 2000 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 2001 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E)); 2002 return false; 2003 } 2004 } 2005} 2006 2007// ParsePrefix - Parse ARM 16-bit relocations expression prefix, i.e. 2008// :lower16: and :upper16:. 2009bool ARMAsmParser::ParsePrefix(ARMMCExpr::VariantKind &RefKind) { 2010 RefKind = ARMMCExpr::VK_ARM_None; 2011 2012 // :lower16: and :upper16: modifiers 2013 assert(getLexer().is(AsmToken::Colon) && "expected a :"); 2014 Parser.Lex(); // Eat ':' 2015 2016 if (getLexer().isNot(AsmToken::Identifier)) { 2017 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand"); 2018 return true; 2019 } 2020 2021 StringRef IDVal = Parser.getTok().getIdentifier(); 2022 if (IDVal == "lower16") { 2023 RefKind = ARMMCExpr::VK_ARM_LO16; 2024 } else if (IDVal == "upper16") { 2025 RefKind = ARMMCExpr::VK_ARM_HI16; 2026 } else { 2027 Error(Parser.getTok().getLoc(), "unexpected prefix in operand"); 2028 return true; 2029 } 2030 Parser.Lex(); 2031 2032 if (getLexer().isNot(AsmToken::Colon)) { 2033 Error(Parser.getTok().getLoc(), "unexpected token after prefix"); 2034 return true; 2035 } 2036 Parser.Lex(); // Eat the last ':' 2037 return false; 2038} 2039 2040const MCExpr * 2041ARMAsmParser::ApplyPrefixToExpr(const MCExpr *E, 2042 MCSymbolRefExpr::VariantKind Variant) { 2043 // Recurse over the given expression, rebuilding it to apply the given variant 2044 // to the leftmost symbol. 2045 if (Variant == MCSymbolRefExpr::VK_None) 2046 return E; 2047 2048 switch (E->getKind()) { 2049 case MCExpr::Target: 2050 llvm_unreachable("Can't handle target expr yet"); 2051 case MCExpr::Constant: 2052 llvm_unreachable("Can't handle lower16/upper16 of constant yet"); 2053 2054 case MCExpr::SymbolRef: { 2055 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E); 2056 2057 if (SRE->getKind() != MCSymbolRefExpr::VK_None) 2058 return 0; 2059 2060 return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, getContext()); 2061 } 2062 2063 case MCExpr::Unary: 2064 llvm_unreachable("Can't handle unary expressions yet"); 2065 2066 case MCExpr::Binary: { 2067 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E); 2068 const MCExpr *LHS = ApplyPrefixToExpr(BE->getLHS(), Variant); 2069 const MCExpr *RHS = BE->getRHS(); 2070 if (!LHS) 2071 return 0; 2072 2073 return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, getContext()); 2074 } 2075 } 2076 2077 assert(0 && "Invalid expression kind!"); 2078 return 0; 2079} 2080 2081/// \brief Given a mnemonic, split out possible predication code and carry 2082/// setting letters to form a canonical mnemonic and flags. 2083// 2084// FIXME: Would be nice to autogen this. 2085StringRef ARMAsmParser::SplitMnemonic(StringRef Mnemonic, 2086 unsigned &PredicationCode, 2087 bool &CarrySetting, 2088 unsigned &ProcessorIMod) { 2089 PredicationCode = ARMCC::AL; 2090 CarrySetting = false; 2091 ProcessorIMod = 0; 2092 2093 // Ignore some mnemonics we know aren't predicated forms. 2094 // 2095 // FIXME: Would be nice to autogen this. 2096 if ((Mnemonic == "movs" && isThumb()) || 2097 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" || 2098 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" || 2099 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" || 2100 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" || 2101 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" || 2102 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" || 2103 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal") 2104 return Mnemonic; 2105 2106 // First, split out any predication code. Ignore mnemonics we know aren't 2107 // predicated but do have a carry-set and so weren't caught above. 2108 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" && 2109 Mnemonic != "muls") { 2110 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2)) 2111 .Case("eq", ARMCC::EQ) 2112 .Case("ne", ARMCC::NE) 2113 .Case("hs", ARMCC::HS) 2114 .Case("cs", ARMCC::HS) 2115 .Case("lo", ARMCC::LO) 2116 .Case("cc", ARMCC::LO) 2117 .Case("mi", ARMCC::MI) 2118 .Case("pl", ARMCC::PL) 2119 .Case("vs", ARMCC::VS) 2120 .Case("vc", ARMCC::VC) 2121 .Case("hi", ARMCC::HI) 2122 .Case("ls", ARMCC::LS) 2123 .Case("ge", ARMCC::GE) 2124 .Case("lt", ARMCC::LT) 2125 .Case("gt", ARMCC::GT) 2126 .Case("le", ARMCC::LE) 2127 .Case("al", ARMCC::AL) 2128 .Default(~0U); 2129 if (CC != ~0U) { 2130 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2); 2131 PredicationCode = CC; 2132 } 2133 } 2134 2135 // Next, determine if we have a carry setting bit. We explicitly ignore all 2136 // the instructions we know end in 's'. 2137 if (Mnemonic.endswith("s") && 2138 !(Mnemonic == "asrs" || Mnemonic == "cps" || Mnemonic == "mls" || 2139 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" || 2140 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" || 2141 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" || 2142 Mnemonic == "vrsqrts" || (Mnemonic == "movs" && isThumb()))) { 2143 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1); 2144 CarrySetting = true; 2145 } 2146 2147 // The "cps" instruction can have a interrupt mode operand which is glued into 2148 // the mnemonic. Check if this is the case, split it and parse the imod op 2149 if (Mnemonic.startswith("cps")) { 2150 // Split out any imod code. 2151 unsigned IMod = 2152 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2)) 2153 .Case("ie", ARM_PROC::IE) 2154 .Case("id", ARM_PROC::ID) 2155 .Default(~0U); 2156 if (IMod != ~0U) { 2157 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2); 2158 ProcessorIMod = IMod; 2159 } 2160 } 2161 2162 return Mnemonic; 2163} 2164 2165/// \brief Given a canonical mnemonic, determine if the instruction ever allows 2166/// inclusion of carry set or predication code operands. 2167// 2168// FIXME: It would be nice to autogen this. 2169void ARMAsmParser:: 2170GetMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet, 2171 bool &CanAcceptPredicationCode) { 2172 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" || 2173 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" || 2174 Mnemonic == "smull" || Mnemonic == "add" || Mnemonic == "adc" || 2175 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" || 2176 Mnemonic == "umlal" || Mnemonic == "orr" || Mnemonic == "mvn" || 2177 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" || 2178 Mnemonic == "sbc" || Mnemonic == "mla" || Mnemonic == "umull" || 2179 Mnemonic == "eor" || Mnemonic == "smlal" || 2180 (Mnemonic == "mov" && !isThumbOne())) { 2181 CanAcceptCarrySet = true; 2182 } else { 2183 CanAcceptCarrySet = false; 2184 } 2185 2186 if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" || 2187 Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" || 2188 Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" || 2189 Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" || 2190 Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "clrex" || 2191 Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumb())) { 2192 CanAcceptPredicationCode = false; 2193 } else { 2194 CanAcceptPredicationCode = true; 2195 } 2196 2197 if (isThumb()) 2198 if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" || 2199 Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp") 2200 CanAcceptPredicationCode = false; 2201} 2202 2203/// Parse an arm instruction mnemonic followed by its operands. 2204bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc, 2205 SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2206 // Create the leading tokens for the mnemonic, split by '.' characters. 2207 size_t Start = 0, Next = Name.find('.'); 2208 StringRef Mnemonic = Name.slice(Start, Next); 2209 2210 // Split out the predication code and carry setting flag from the mnemonic. 2211 unsigned PredicationCode; 2212 unsigned ProcessorIMod; 2213 bool CarrySetting; 2214 Mnemonic = SplitMnemonic(Mnemonic, PredicationCode, CarrySetting, 2215 ProcessorIMod); 2216 2217 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc)); 2218 2219 // FIXME: This is all a pretty gross hack. We should automatically handle 2220 // optional operands like this via tblgen. 2221 2222 // Next, add the CCOut and ConditionCode operands, if needed. 2223 // 2224 // For mnemonics which can ever incorporate a carry setting bit or predication 2225 // code, our matching model involves us always generating CCOut and 2226 // ConditionCode operands to match the mnemonic "as written" and then we let 2227 // the matcher deal with finding the right instruction or generating an 2228 // appropriate error. 2229 bool CanAcceptCarrySet, CanAcceptPredicationCode; 2230 GetMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode); 2231 2232 // If we had a carry-set on an instruction that can't do that, issue an 2233 // error. 2234 if (!CanAcceptCarrySet && CarrySetting) { 2235 Parser.EatToEndOfStatement(); 2236 return Error(NameLoc, "instruction '" + Mnemonic + 2237 "' can not set flags, but 's' suffix specified"); 2238 } 2239 2240 // Add the carry setting operand, if necessary. 2241 // 2242 // FIXME: It would be awesome if we could somehow invent a location such that 2243 // match errors on this operand would print a nice diagnostic about how the 2244 // 's' character in the mnemonic resulted in a CCOut operand. 2245 if (CanAcceptCarrySet) 2246 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0, 2247 NameLoc)); 2248 2249 // Add the predication code operand, if necessary. 2250 if (CanAcceptPredicationCode) { 2251 Operands.push_back(ARMOperand::CreateCondCode( 2252 ARMCC::CondCodes(PredicationCode), NameLoc)); 2253 } else { 2254 // This mnemonic can't ever accept a predication code, but the user wrote 2255 // one (or misspelled another mnemonic). 2256 2257 // FIXME: Issue a nice error. 2258 } 2259 2260 // Add the processor imod operand, if necessary. 2261 if (ProcessorIMod) { 2262 Operands.push_back(ARMOperand::CreateImm( 2263 MCConstantExpr::Create(ProcessorIMod, getContext()), 2264 NameLoc, NameLoc)); 2265 } else { 2266 // This mnemonic can't ever accept a imod, but the user wrote 2267 // one (or misspelled another mnemonic). 2268 2269 // FIXME: Issue a nice error. 2270 } 2271 2272 // Add the remaining tokens in the mnemonic. 2273 while (Next != StringRef::npos) { 2274 Start = Next; 2275 Next = Name.find('.', Start + 1); 2276 StringRef ExtraToken = Name.slice(Start, Next); 2277 2278 Operands.push_back(ARMOperand::CreateToken(ExtraToken, NameLoc)); 2279 } 2280 2281 // Read the remaining operands. 2282 if (getLexer().isNot(AsmToken::EndOfStatement)) { 2283 // Read the first operand. 2284 if (ParseOperand(Operands, Mnemonic)) { 2285 Parser.EatToEndOfStatement(); 2286 return true; 2287 } 2288 2289 while (getLexer().is(AsmToken::Comma)) { 2290 Parser.Lex(); // Eat the comma. 2291 2292 // Parse and remember the operand. 2293 if (ParseOperand(Operands, Mnemonic)) { 2294 Parser.EatToEndOfStatement(); 2295 return true; 2296 } 2297 } 2298 } 2299 2300 if (getLexer().isNot(AsmToken::EndOfStatement)) { 2301 Parser.EatToEndOfStatement(); 2302 return TokError("unexpected token in argument list"); 2303 } 2304 2305 Parser.Lex(); // Consume the EndOfStatement 2306 2307 2308 // The 'mov' mnemonic is special. One variant has a cc_out operand, while 2309 // another does not. Specifically, the MOVW instruction does not. So we 2310 // special case it here and remove the defaulted (non-setting) cc_out 2311 // operand if that's the instruction we're trying to match. 2312 // 2313 // We do this post-processing of the explicit operands rather than just 2314 // conditionally adding the cc_out in the first place because we need 2315 // to check the type of the parsed immediate operand. 2316 if (Mnemonic == "mov" && Operands.size() > 4 && 2317 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() && 2318 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() && 2319 static_cast<ARMOperand*>(Operands[1])->getReg() == 0) { 2320 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]); 2321 Operands.erase(Operands.begin() + 1); 2322 delete Op; 2323 } 2324 2325 2326 2327 return false; 2328} 2329 2330bool ARMAsmParser:: 2331MatchAndEmitInstruction(SMLoc IDLoc, 2332 SmallVectorImpl<MCParsedAsmOperand*> &Operands, 2333 MCStreamer &Out) { 2334 MCInst Inst; 2335 unsigned ErrorInfo; 2336 MatchResultTy MatchResult; 2337 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo); 2338 switch (MatchResult) { 2339 case Match_Success: 2340 Out.EmitInstruction(Inst); 2341 return false; 2342 case Match_MissingFeature: 2343 Error(IDLoc, "instruction requires a CPU feature not currently enabled"); 2344 return true; 2345 case Match_InvalidOperand: { 2346 SMLoc ErrorLoc = IDLoc; 2347 if (ErrorInfo != ~0U) { 2348 if (ErrorInfo >= Operands.size()) 2349 return Error(IDLoc, "too few operands for instruction"); 2350 2351 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc(); 2352 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 2353 } 2354 2355 return Error(ErrorLoc, "invalid operand for instruction"); 2356 } 2357 case Match_MnemonicFail: 2358 return Error(IDLoc, "unrecognized instruction mnemonic"); 2359 case Match_ConversionFail: 2360 return Error(IDLoc, "unable to convert operands to instruction"); 2361 } 2362 2363 llvm_unreachable("Implement any new match types added!"); 2364 return true; 2365} 2366 2367/// ParseDirective parses the arm specific directives 2368bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) { 2369 StringRef IDVal = DirectiveID.getIdentifier(); 2370 if (IDVal == ".word") 2371 return ParseDirectiveWord(4, DirectiveID.getLoc()); 2372 else if (IDVal == ".thumb") 2373 return ParseDirectiveThumb(DirectiveID.getLoc()); 2374 else if (IDVal == ".thumb_func") 2375 return ParseDirectiveThumbFunc(DirectiveID.getLoc()); 2376 else if (IDVal == ".code") 2377 return ParseDirectiveCode(DirectiveID.getLoc()); 2378 else if (IDVal == ".syntax") 2379 return ParseDirectiveSyntax(DirectiveID.getLoc()); 2380 return true; 2381} 2382 2383/// ParseDirectiveWord 2384/// ::= .word [ expression (, expression)* ] 2385bool ARMAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) { 2386 if (getLexer().isNot(AsmToken::EndOfStatement)) { 2387 for (;;) { 2388 const MCExpr *Value; 2389 if (getParser().ParseExpression(Value)) 2390 return true; 2391 2392 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/); 2393 2394 if (getLexer().is(AsmToken::EndOfStatement)) 2395 break; 2396 2397 // FIXME: Improve diagnostic. 2398 if (getLexer().isNot(AsmToken::Comma)) 2399 return Error(L, "unexpected token in directive"); 2400 Parser.Lex(); 2401 } 2402 } 2403 2404 Parser.Lex(); 2405 return false; 2406} 2407 2408/// ParseDirectiveThumb 2409/// ::= .thumb 2410bool ARMAsmParser::ParseDirectiveThumb(SMLoc L) { 2411 if (getLexer().isNot(AsmToken::EndOfStatement)) 2412 return Error(L, "unexpected token in directive"); 2413 Parser.Lex(); 2414 2415 // TODO: set thumb mode 2416 // TODO: tell the MC streamer the mode 2417 // getParser().getStreamer().Emit???(); 2418 return false; 2419} 2420 2421/// ParseDirectiveThumbFunc 2422/// ::= .thumbfunc symbol_name 2423bool ARMAsmParser::ParseDirectiveThumbFunc(SMLoc L) { 2424 const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo(); 2425 bool isMachO = MAI.hasSubsectionsViaSymbols(); 2426 StringRef Name; 2427 2428 // Darwin asm has function name after .thumb_func direction 2429 // ELF doesn't 2430 if (isMachO) { 2431 const AsmToken &Tok = Parser.getTok(); 2432 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String)) 2433 return Error(L, "unexpected token in .thumb_func directive"); 2434 Name = Tok.getString(); 2435 Parser.Lex(); // Consume the identifier token. 2436 } 2437 2438 if (getLexer().isNot(AsmToken::EndOfStatement)) 2439 return Error(L, "unexpected token in directive"); 2440 Parser.Lex(); 2441 2442 // FIXME: assuming function name will be the line following .thumb_func 2443 if (!isMachO) { 2444 Name = Parser.getTok().getString(); 2445 } 2446 2447 // Mark symbol as a thumb symbol. 2448 MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name); 2449 getParser().getStreamer().EmitThumbFunc(Func); 2450 return false; 2451} 2452 2453/// ParseDirectiveSyntax 2454/// ::= .syntax unified | divided 2455bool ARMAsmParser::ParseDirectiveSyntax(SMLoc L) { 2456 const AsmToken &Tok = Parser.getTok(); 2457 if (Tok.isNot(AsmToken::Identifier)) 2458 return Error(L, "unexpected token in .syntax directive"); 2459 StringRef Mode = Tok.getString(); 2460 if (Mode == "unified" || Mode == "UNIFIED") 2461 Parser.Lex(); 2462 else if (Mode == "divided" || Mode == "DIVIDED") 2463 return Error(L, "'.syntax divided' arm asssembly not supported"); 2464 else 2465 return Error(L, "unrecognized syntax mode in .syntax directive"); 2466 2467 if (getLexer().isNot(AsmToken::EndOfStatement)) 2468 return Error(Parser.getTok().getLoc(), "unexpected token in directive"); 2469 Parser.Lex(); 2470 2471 // TODO tell the MC streamer the mode 2472 // getParser().getStreamer().Emit???(); 2473 return false; 2474} 2475 2476/// ParseDirectiveCode 2477/// ::= .code 16 | 32 2478bool ARMAsmParser::ParseDirectiveCode(SMLoc L) { 2479 const AsmToken &Tok = Parser.getTok(); 2480 if (Tok.isNot(AsmToken::Integer)) 2481 return Error(L, "unexpected token in .code directive"); 2482 int64_t Val = Parser.getTok().getIntVal(); 2483 if (Val == 16) 2484 Parser.Lex(); 2485 else if (Val == 32) 2486 Parser.Lex(); 2487 else 2488 return Error(L, "invalid operand to .code directive"); 2489 2490 if (getLexer().isNot(AsmToken::EndOfStatement)) 2491 return Error(Parser.getTok().getLoc(), "unexpected token in directive"); 2492 Parser.Lex(); 2493 2494 if (Val == 16) { 2495 if (!isThumb()) 2496 SwitchMode(); 2497 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16); 2498 } else { 2499 if (isThumb()) 2500 SwitchMode(); 2501 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32); 2502 } 2503 2504 return false; 2505} 2506 2507extern "C" void LLVMInitializeARMAsmLexer(); 2508 2509/// Force static initialization. 2510extern "C" void LLVMInitializeARMAsmParser() { 2511 RegisterAsmParser<ARMAsmParser> X(TheARMTarget); 2512 RegisterAsmParser<ARMAsmParser> Y(TheThumbTarget); 2513 LLVMInitializeARMAsmLexer(); 2514} 2515 2516#define GET_REGISTER_MATCHER 2517#define GET_MATCHER_IMPLEMENTATION 2518#include "ARMGenAsmMatcher.inc" 2519