ARMAsmParser.cpp revision 9ab0f25fc194b4315db1b87d38d4024054120bf6 
1//===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "MCTargetDesc/ARMBaseInfo.h"
11#include "MCTargetDesc/ARMAddressingModes.h"
12#include "MCTargetDesc/ARMMCExpr.h"
13#include "llvm/MC/MCParser/MCAsmLexer.h"
14#include "llvm/MC/MCParser/MCAsmParser.h"
15#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16#include "llvm/MC/MCAsmInfo.h"
17#include "llvm/MC/MCContext.h"
18#include "llvm/MC/MCStreamer.h"
19#include "llvm/MC/MCExpr.h"
20#include "llvm/MC/MCInst.h"
21#include "llvm/MC/MCInstrDesc.h"
22#include "llvm/MC/MCRegisterInfo.h"
23#include "llvm/MC/MCSubtargetInfo.h"
24#include "llvm/MC/MCTargetAsmParser.h"
25#include "llvm/Support/SourceMgr.h"
26#include "llvm/Support/TargetRegistry.h"
27#include "llvm/Support/raw_ostream.h"
28#include "llvm/ADT/BitVector.h"
29#include "llvm/ADT/OwningPtr.h"
30#include "llvm/ADT/STLExtras.h"
31#include "llvm/ADT/SmallVector.h"
32#include "llvm/ADT/StringExtras.h"
33#include "llvm/ADT/StringSwitch.h"
34#include "llvm/ADT/Twine.h"
35
36using namespace llvm;
37
38namespace {
39
40class ARMOperand;
41
42class ARMAsmParser : public MCTargetAsmParser {
43  MCSubtargetInfo &STI;
44  MCAsmParser &Parser;
45
46  MCAsmParser &getParser() const { return Parser; }
47  MCAsmLexer &getLexer() const { return Parser.getLexer(); }
48
49  void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
50  bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
51
52  int tryParseRegister();
53  bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
54  int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
55  bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
56  bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
57  bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
58  bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
59  const MCExpr *applyPrefixToExpr(const MCExpr *E,
60                                  MCSymbolRefExpr::VariantKind Variant);
61
62
63  bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
64                              unsigned &ShiftAmount);
65  bool parseDirectiveWord(unsigned Size, SMLoc L);
66  bool parseDirectiveThumb(SMLoc L);
67  bool parseDirectiveThumbFunc(SMLoc L);
68  bool parseDirectiveCode(SMLoc L);
69  bool parseDirectiveSyntax(SMLoc L);
70
71  StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
72                          bool &CarrySetting, unsigned &ProcessorIMod);
73  void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
74                             bool &CanAcceptPredicationCode);
75
76  bool isThumb() const {
77    // FIXME: Can tablegen auto-generate this?
78    return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
79  }
80  bool isThumbOne() const {
81    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
82  }
83  bool isThumbTwo() const {
84    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
85  }
86  bool hasV6Ops() const {
87    return STI.getFeatureBits() & ARM::HasV6Ops;
88  }
89  void SwitchMode() {
90    unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
91    setAvailableFeatures(FB);
92  }
93
94  /// @name Auto-generated Match Functions
95  /// {
96
97#define GET_ASSEMBLER_HEADER
98#include "ARMGenAsmMatcher.inc"
99
100  /// }
101
102  OperandMatchResultTy parseCoprocNumOperand(
103    SmallVectorImpl<MCParsedAsmOperand*>&);
104  OperandMatchResultTy parseCoprocRegOperand(
105    SmallVectorImpl<MCParsedAsmOperand*>&);
106  OperandMatchResultTy parseMemBarrierOptOperand(
107    SmallVectorImpl<MCParsedAsmOperand*>&);
108  OperandMatchResultTy parseProcIFlagsOperand(
109    SmallVectorImpl<MCParsedAsmOperand*>&);
110  OperandMatchResultTy parseMSRMaskOperand(
111    SmallVectorImpl<MCParsedAsmOperand*>&);
112  OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
113                                   StringRef Op, int Low, int High);
114  OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
115    return parsePKHImm(O, "lsl", 0, 31);
116  }
117  OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
118    return parsePKHImm(O, "asr", 1, 32);
119  }
120  OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
121  OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
122  OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
123  OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
124  OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
125  OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
126
127  // Asm Match Converter Methods
128  bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
129                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
130  bool cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
131                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
132  bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
133                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
134  bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
135                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
136  bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
137                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
138  bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
139                             const SmallVectorImpl<MCParsedAsmOperand*> &);
140  bool cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
141                             const SmallVectorImpl<MCParsedAsmOperand*> &);
142  bool cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
143                             const SmallVectorImpl<MCParsedAsmOperand*> &);
144  bool cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
145                             const SmallVectorImpl<MCParsedAsmOperand*> &);
146  bool cvtLdrdPre(MCInst &Inst, unsigned Opcode,
147                  const SmallVectorImpl<MCParsedAsmOperand*> &);
148  bool cvtStrdPre(MCInst &Inst, unsigned Opcode,
149                  const SmallVectorImpl<MCParsedAsmOperand*> &);
150  bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
151                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
152  bool cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
153                        const SmallVectorImpl<MCParsedAsmOperand*> &);
154
155  bool validateInstruction(MCInst &Inst,
156                           const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
157  void processInstruction(MCInst &Inst,
158                          const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
159  bool shouldOmitCCOutOperand(StringRef Mnemonic,
160                              SmallVectorImpl<MCParsedAsmOperand*> &Operands);
161
162public:
163  enum ARMMatchResultTy {
164    Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
165    Match_RequiresV6,
166    Match_RequiresThumb2
167  };
168
169  ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
170    : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
171    MCAsmParserExtension::Initialize(_Parser);
172
173    // Initialize the set of available features.
174    setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
175  }
176
177  // Implementation of the MCTargetAsmParser interface:
178  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
179  bool ParseInstruction(StringRef Name, SMLoc NameLoc,
180                        SmallVectorImpl<MCParsedAsmOperand*> &Operands);
181  bool ParseDirective(AsmToken DirectiveID);
182
183  unsigned checkTargetMatchPredicate(MCInst &Inst);
184
185  bool MatchAndEmitInstruction(SMLoc IDLoc,
186                               SmallVectorImpl<MCParsedAsmOperand*> &Operands,
187                               MCStreamer &Out);
188};
189} // end anonymous namespace
190
191namespace {
192
193/// ARMOperand - Instances of this class represent a parsed ARM machine
194/// instruction.
195class ARMOperand : public MCParsedAsmOperand {
196  enum KindTy {
197    CondCode,
198    CCOut,
199    CoprocNum,
200    CoprocReg,
201    Immediate,
202    MemBarrierOpt,
203    Memory,
204    PostIndexRegister,
205    MSRMask,
206    ProcIFlags,
207    Register,
208    RegisterList,
209    DPRRegisterList,
210    SPRRegisterList,
211    ShiftedRegister,
212    ShiftedImmediate,
213    ShifterImmediate,
214    RotateImmediate,
215    BitfieldDescriptor,
216    Token
217  } Kind;
218
219  SMLoc StartLoc, EndLoc;
220  SmallVector<unsigned, 8> Registers;
221
222  union {
223    struct {
224      ARMCC::CondCodes Val;
225    } CC;
226
227    struct {
228      ARM_MB::MemBOpt Val;
229    } MBOpt;
230
231    struct {
232      unsigned Val;
233    } Cop;
234
235    struct {
236      ARM_PROC::IFlags Val;
237    } IFlags;
238
239    struct {
240      unsigned Val;
241    } MMask;
242
243    struct {
244      const char *Data;
245      unsigned Length;
246    } Tok;
247
248    struct {
249      unsigned RegNum;
250    } Reg;
251
252    struct {
253      const MCExpr *Val;
254    } Imm;
255
256    /// Combined record for all forms of ARM address expressions.
257    struct {
258      unsigned BaseRegNum;
259      // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
260      // was specified.
261      const MCConstantExpr *OffsetImm;  // Offset immediate value
262      unsigned OffsetRegNum;    // Offset register num, when OffsetImm == NULL
263      ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
264      unsigned ShiftImm;      // shift for OffsetReg.
265      unsigned isNegative : 1;  // Negated OffsetReg? (~'U' bit)
266    } Mem;
267
268    struct {
269      unsigned RegNum;
270      bool isAdd;
271      ARM_AM::ShiftOpc ShiftTy;
272      unsigned ShiftImm;
273    } PostIdxReg;
274
275    struct {
276      bool isASR;
277      unsigned Imm;
278    } ShifterImm;
279    struct {
280      ARM_AM::ShiftOpc ShiftTy;
281      unsigned SrcReg;
282      unsigned ShiftReg;
283      unsigned ShiftImm;
284    } RegShiftedReg;
285    struct {
286      ARM_AM::ShiftOpc ShiftTy;
287      unsigned SrcReg;
288      unsigned ShiftImm;
289    } RegShiftedImm;
290    struct {
291      unsigned Imm;
292    } RotImm;
293    struct {
294      unsigned LSB;
295      unsigned Width;
296    } Bitfield;
297  };
298
299  ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
300public:
301  ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
302    Kind = o.Kind;
303    StartLoc = o.StartLoc;
304    EndLoc = o.EndLoc;
305    switch (Kind) {
306    case CondCode:
307      CC = o.CC;
308      break;
309    case Token:
310      Tok = o.Tok;
311      break;
312    case CCOut:
313    case Register:
314      Reg = o.Reg;
315      break;
316    case RegisterList:
317    case DPRRegisterList:
318    case SPRRegisterList:
319      Registers = o.Registers;
320      break;
321    case CoprocNum:
322    case CoprocReg:
323      Cop = o.Cop;
324      break;
325    case Immediate:
326      Imm = o.Imm;
327      break;
328    case MemBarrierOpt:
329      MBOpt = o.MBOpt;
330      break;
331    case Memory:
332      Mem = o.Mem;
333      break;
334    case PostIndexRegister:
335      PostIdxReg = o.PostIdxReg;
336      break;
337    case MSRMask:
338      MMask = o.MMask;
339      break;
340    case ProcIFlags:
341      IFlags = o.IFlags;
342      break;
343    case ShifterImmediate:
344      ShifterImm = o.ShifterImm;
345      break;
346    case ShiftedRegister:
347      RegShiftedReg = o.RegShiftedReg;
348      break;
349    case ShiftedImmediate:
350      RegShiftedImm = o.RegShiftedImm;
351      break;
352    case RotateImmediate:
353      RotImm = o.RotImm;
354      break;
355    case BitfieldDescriptor:
356      Bitfield = o.Bitfield;
357      break;
358    }
359  }
360
361  /// getStartLoc - Get the location of the first token of this operand.
362  SMLoc getStartLoc() const { return StartLoc; }
363  /// getEndLoc - Get the location of the last token of this operand.
364  SMLoc getEndLoc() const { return EndLoc; }
365
366  ARMCC::CondCodes getCondCode() const {
367    assert(Kind == CondCode && "Invalid access!");
368    return CC.Val;
369  }
370
371  unsigned getCoproc() const {
372    assert((Kind == CoprocNum || Kind == CoprocReg) && "Invalid access!");
373    return Cop.Val;
374  }
375
376  StringRef getToken() const {
377    assert(Kind == Token && "Invalid access!");
378    return StringRef(Tok.Data, Tok.Length);
379  }
380
381  unsigned getReg() const {
382    assert((Kind == Register || Kind == CCOut) && "Invalid access!");
383    return Reg.RegNum;
384  }
385
386  const SmallVectorImpl<unsigned> &getRegList() const {
387    assert((Kind == RegisterList || Kind == DPRRegisterList ||
388            Kind == SPRRegisterList) && "Invalid access!");
389    return Registers;
390  }
391
392  const MCExpr *getImm() const {
393    assert(Kind == Immediate && "Invalid access!");
394    return Imm.Val;
395  }
396
397  ARM_MB::MemBOpt getMemBarrierOpt() const {
398    assert(Kind == MemBarrierOpt && "Invalid access!");
399    return MBOpt.Val;
400  }
401
402  ARM_PROC::IFlags getProcIFlags() const {
403    assert(Kind == ProcIFlags && "Invalid access!");
404    return IFlags.Val;
405  }
406
407  unsigned getMSRMask() const {
408    assert(Kind == MSRMask && "Invalid access!");
409    return MMask.Val;
410  }
411
412  bool isCoprocNum() const { return Kind == CoprocNum; }
413  bool isCoprocReg() const { return Kind == CoprocReg; }
414  bool isCondCode() const { return Kind == CondCode; }
415  bool isCCOut() const { return Kind == CCOut; }
416  bool isImm() const { return Kind == Immediate; }
417  bool isImm0_1020s4() const {
418    if (Kind != Immediate)
419      return false;
420    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
421    if (!CE) return false;
422    int64_t Value = CE->getValue();
423    return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
424  }
425  bool isImm0_508s4() const {
426    if (Kind != Immediate)
427      return false;
428    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
429    if (!CE) return false;
430    int64_t Value = CE->getValue();
431    return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
432  }
433  bool isImm0_255() const {
434    if (Kind != Immediate)
435      return false;
436    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
437    if (!CE) return false;
438    int64_t Value = CE->getValue();
439    return Value >= 0 && Value < 256;
440  }
441  bool isImm0_7() const {
442    if (Kind != Immediate)
443      return false;
444    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
445    if (!CE) return false;
446    int64_t Value = CE->getValue();
447    return Value >= 0 && Value < 8;
448  }
449  bool isImm0_15() const {
450    if (Kind != Immediate)
451      return false;
452    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
453    if (!CE) return false;
454    int64_t Value = CE->getValue();
455    return Value >= 0 && Value < 16;
456  }
457  bool isImm0_31() const {
458    if (Kind != Immediate)
459      return false;
460    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
461    if (!CE) return false;
462    int64_t Value = CE->getValue();
463    return Value >= 0 && Value < 32;
464  }
465  bool isImm1_16() const {
466    if (Kind != Immediate)
467      return false;
468    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
469    if (!CE) return false;
470    int64_t Value = CE->getValue();
471    return Value > 0 && Value < 17;
472  }
473  bool isImm1_32() const {
474    if (Kind != Immediate)
475      return false;
476    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
477    if (!CE) return false;
478    int64_t Value = CE->getValue();
479    return Value > 0 && Value < 33;
480  }
481  bool isImm0_65535() const {
482    if (Kind != Immediate)
483      return false;
484    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
485    if (!CE) return false;
486    int64_t Value = CE->getValue();
487    return Value >= 0 && Value < 65536;
488  }
489  bool isImm0_65535Expr() const {
490    if (Kind != Immediate)
491      return false;
492    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
493    // If it's not a constant expression, it'll generate a fixup and be
494    // handled later.
495    if (!CE) return true;
496    int64_t Value = CE->getValue();
497    return Value >= 0 && Value < 65536;
498  }
499  bool isImm24bit() const {
500    if (Kind != Immediate)
501      return false;
502    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
503    if (!CE) return false;
504    int64_t Value = CE->getValue();
505    return Value >= 0 && Value <= 0xffffff;
506  }
507  bool isImmThumbSR() const {
508    if (Kind != Immediate)
509      return false;
510    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
511    if (!CE) return false;
512    int64_t Value = CE->getValue();
513    return Value > 0 && Value < 33;
514  }
515  bool isPKHLSLImm() const {
516    if (Kind != Immediate)
517      return false;
518    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
519    if (!CE) return false;
520    int64_t Value = CE->getValue();
521    return Value >= 0 && Value < 32;
522  }
523  bool isPKHASRImm() const {
524    if (Kind != Immediate)
525      return false;
526    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
527    if (!CE) return false;
528    int64_t Value = CE->getValue();
529    return Value > 0 && Value <= 32;
530  }
531  bool isARMSOImm() const {
532    if (Kind != Immediate)
533      return false;
534    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
535    if (!CE) return false;
536    int64_t Value = CE->getValue();
537    return ARM_AM::getSOImmVal(Value) != -1;
538  }
539  bool isT2SOImm() const {
540    if (Kind != Immediate)
541      return false;
542    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
543    if (!CE) return false;
544    int64_t Value = CE->getValue();
545    return ARM_AM::getT2SOImmVal(Value) != -1;
546  }
547  bool isSetEndImm() const {
548    if (Kind != Immediate)
549      return false;
550    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
551    if (!CE) return false;
552    int64_t Value = CE->getValue();
553    return Value == 1 || Value == 0;
554  }
555  bool isReg() const { return Kind == Register; }
556  bool isRegList() const { return Kind == RegisterList; }
557  bool isDPRRegList() const { return Kind == DPRRegisterList; }
558  bool isSPRRegList() const { return Kind == SPRRegisterList; }
559  bool isToken() const { return Kind == Token; }
560  bool isMemBarrierOpt() const { return Kind == MemBarrierOpt; }
561  bool isMemory() const { return Kind == Memory; }
562  bool isShifterImm() const { return Kind == ShifterImmediate; }
563  bool isRegShiftedReg() const { return Kind == ShiftedRegister; }
564  bool isRegShiftedImm() const { return Kind == ShiftedImmediate; }
565  bool isRotImm() const { return Kind == RotateImmediate; }
566  bool isBitfield() const { return Kind == BitfieldDescriptor; }
567  bool isPostIdxRegShifted() const { return Kind == PostIndexRegister; }
568  bool isPostIdxReg() const {
569    return Kind == PostIndexRegister && PostIdxReg.ShiftTy == ARM_AM::no_shift;
570  }
571  bool isMemNoOffset() const {
572    if (Kind != Memory)
573      return false;
574    // No offset of any kind.
575    return Mem.OffsetRegNum == 0 && Mem.OffsetImm == 0;
576  }
577  bool isAddrMode2() const {
578    if (Kind != Memory)
579      return false;
580    // Check for register offset.
581    if (Mem.OffsetRegNum) return true;
582    // Immediate offset in range [-4095, 4095].
583    if (!Mem.OffsetImm) return true;
584    int64_t Val = Mem.OffsetImm->getValue();
585    return Val > -4096 && Val < 4096;
586  }
587  bool isAM2OffsetImm() const {
588    if (Kind != Immediate)
589      return false;
590    // Immediate offset in range [-4095, 4095].
591    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
592    if (!CE) return false;
593    int64_t Val = CE->getValue();
594    return Val > -4096 && Val < 4096;
595  }
596  bool isAddrMode3() const {
597    if (Kind != Memory)
598      return false;
599    // No shifts are legal for AM3.
600    if (Mem.ShiftType != ARM_AM::no_shift) return false;
601    // Check for register offset.
602    if (Mem.OffsetRegNum) return true;
603    // Immediate offset in range [-255, 255].
604    if (!Mem.OffsetImm) return true;
605    int64_t Val = Mem.OffsetImm->getValue();
606    return Val > -256 && Val < 256;
607  }
608  bool isAM3Offset() const {
609    if (Kind != Immediate && Kind != PostIndexRegister)
610      return false;
611    if (Kind == PostIndexRegister)
612      return PostIdxReg.ShiftTy == ARM_AM::no_shift;
613    // Immediate offset in range [-255, 255].
614    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
615    if (!CE) return false;
616    int64_t Val = CE->getValue();
617    // Special case, #-0 is INT32_MIN.
618    return (Val > -256 && Val < 256) || Val == INT32_MIN;
619  }
620  bool isAddrMode5() const {
621    if (Kind != Memory)
622      return false;
623    // Check for register offset.
624    if (Mem.OffsetRegNum) return false;
625    // Immediate offset in range [-1020, 1020] and a multiple of 4.
626    if (!Mem.OffsetImm) return true;
627    int64_t Val = Mem.OffsetImm->getValue();
628    return Val >= -1020 && Val <= 1020 && ((Val & 3) == 0);
629  }
630  bool isMemRegOffset() const {
631    if (Kind != Memory || !Mem.OffsetRegNum)
632      return false;
633    return true;
634  }
635  bool isMemThumbRR() const {
636    // Thumb reg+reg addressing is simple. Just two registers, a base and
637    // an offset. No shifts, negations or any other complicating factors.
638    if (Kind != Memory || !Mem.OffsetRegNum || Mem.isNegative ||
639        Mem.ShiftType != ARM_AM::no_shift)
640      return false;
641    return isARMLowRegister(Mem.BaseRegNum) &&
642      (!Mem.OffsetRegNum || isARMLowRegister(Mem.OffsetRegNum));
643  }
644  bool isMemThumbRIs4() const {
645    if (Kind != Memory || Mem.OffsetRegNum != 0 ||
646        !isARMLowRegister(Mem.BaseRegNum))
647      return false;
648    // Immediate offset, multiple of 4 in range [0, 124].
649    if (!Mem.OffsetImm) return true;
650    int64_t Val = Mem.OffsetImm->getValue();
651    return Val >= 0 && Val <= 124 && (Val % 4) == 0;
652  }
653  bool isMemThumbRIs2() const {
654    if (Kind != Memory || Mem.OffsetRegNum != 0 ||
655        !isARMLowRegister(Mem.BaseRegNum))
656      return false;
657    // Immediate offset, multiple of 4 in range [0, 62].
658    if (!Mem.OffsetImm) return true;
659    int64_t Val = Mem.OffsetImm->getValue();
660    return Val >= 0 && Val <= 62 && (Val % 2) == 0;
661  }
662  bool isMemThumbRIs1() const {
663    if (Kind != Memory || Mem.OffsetRegNum != 0 ||
664        !isARMLowRegister(Mem.BaseRegNum))
665      return false;
666    // Immediate offset in range [0, 31].
667    if (!Mem.OffsetImm) return true;
668    int64_t Val = Mem.OffsetImm->getValue();
669    return Val >= 0 && Val <= 31;
670  }
671  bool isMemThumbSPI() const {
672    if (Kind != Memory || Mem.OffsetRegNum != 0 || Mem.BaseRegNum != ARM::SP)
673      return false;
674    // Immediate offset, multiple of 4 in range [0, 1020].
675    if (!Mem.OffsetImm) return true;
676    int64_t Val = Mem.OffsetImm->getValue();
677    return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
678  }
679  bool isMemImm8Offset() const {
680    if (Kind != Memory || Mem.OffsetRegNum != 0)
681      return false;
682    // Immediate offset in range [-255, 255].
683    if (!Mem.OffsetImm) return true;
684    int64_t Val = Mem.OffsetImm->getValue();
685    return Val > -256 && Val < 256;
686  }
687  bool isMemImm12Offset() const {
688    // If we have an immediate that's not a constant, treat it as a label
689    // reference needing a fixup. If it is a constant, it's something else
690    // and we reject it.
691    if (Kind == Immediate && !isa<MCConstantExpr>(getImm()))
692      return true;
693
694    if (Kind != Memory || Mem.OffsetRegNum != 0)
695      return false;
696    // Immediate offset in range [-4095, 4095].
697    if (!Mem.OffsetImm) return true;
698    int64_t Val = Mem.OffsetImm->getValue();
699    return Val > -4096 && Val < 4096;
700  }
701  bool isPostIdxImm8() const {
702    if (Kind != Immediate)
703      return false;
704    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
705    if (!CE) return false;
706    int64_t Val = CE->getValue();
707    return Val > -256 && Val < 256;
708  }
709
710  bool isMSRMask() const { return Kind == MSRMask; }
711  bool isProcIFlags() const { return Kind == ProcIFlags; }
712
713  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
714    // Add as immediates when possible.  Null MCExpr = 0.
715    if (Expr == 0)
716      Inst.addOperand(MCOperand::CreateImm(0));
717    else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
718      Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
719    else
720      Inst.addOperand(MCOperand::CreateExpr(Expr));
721  }
722
723  void addCondCodeOperands(MCInst &Inst, unsigned N) const {
724    assert(N == 2 && "Invalid number of operands!");
725    Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
726    unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
727    Inst.addOperand(MCOperand::CreateReg(RegNum));
728  }
729
730  void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
731    assert(N == 1 && "Invalid number of operands!");
732    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
733  }
734
735  void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
736    assert(N == 1 && "Invalid number of operands!");
737    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
738  }
739
740  void addCCOutOperands(MCInst &Inst, unsigned N) const {
741    assert(N == 1 && "Invalid number of operands!");
742    Inst.addOperand(MCOperand::CreateReg(getReg()));
743  }
744
745  void addRegOperands(MCInst &Inst, unsigned N) const {
746    assert(N == 1 && "Invalid number of operands!");
747    Inst.addOperand(MCOperand::CreateReg(getReg()));
748  }
749
750  void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
751    assert(N == 3 && "Invalid number of operands!");
752    assert(isRegShiftedReg() && "addRegShiftedRegOperands() on non RegShiftedReg!");
753    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
754    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
755    Inst.addOperand(MCOperand::CreateImm(
756      ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
757  }
758
759  void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
760    assert(N == 2 && "Invalid number of operands!");
761    assert(isRegShiftedImm() && "addRegShiftedImmOperands() on non RegShiftedImm!");
762    Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
763    Inst.addOperand(MCOperand::CreateImm(
764      ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm)));
765  }
766
767
768  void addShifterImmOperands(MCInst &Inst, unsigned N) const {
769    assert(N == 1 && "Invalid number of operands!");
770    Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
771                                         ShifterImm.Imm));
772  }
773
774  void addRegListOperands(MCInst &Inst, unsigned N) const {
775    assert(N == 1 && "Invalid number of operands!");
776    const SmallVectorImpl<unsigned> &RegList = getRegList();
777    for (SmallVectorImpl<unsigned>::const_iterator
778           I = RegList.begin(), E = RegList.end(); I != E; ++I)
779      Inst.addOperand(MCOperand::CreateReg(*I));
780  }
781
782  void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
783    addRegListOperands(Inst, N);
784  }
785
786  void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
787    addRegListOperands(Inst, N);
788  }
789
790  void addRotImmOperands(MCInst &Inst, unsigned N) const {
791    assert(N == 1 && "Invalid number of operands!");
792    // Encoded as val>>3. The printer handles display as 8, 16, 24.
793    Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
794  }
795
796  void addBitfieldOperands(MCInst &Inst, unsigned N) const {
797    assert(N == 1 && "Invalid number of operands!");
798    // Munge the lsb/width into a bitfield mask.
799    unsigned lsb = Bitfield.LSB;
800    unsigned width = Bitfield.Width;
801    // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
802    uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
803                      (32 - (lsb + width)));
804    Inst.addOperand(MCOperand::CreateImm(Mask));
805  }
806
807  void addImmOperands(MCInst &Inst, unsigned N) const {
808    assert(N == 1 && "Invalid number of operands!");
809    addExpr(Inst, getImm());
810  }
811
812  void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
813    assert(N == 1 && "Invalid number of operands!");
814    // The immediate is scaled by four in the encoding and is stored
815    // in the MCInst as such. Lop off the low two bits here.
816    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
817    Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
818  }
819
820  void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
821    assert(N == 1 && "Invalid number of operands!");
822    // The immediate is scaled by four in the encoding and is stored
823    // in the MCInst as such. Lop off the low two bits here.
824    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
825    Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
826  }
827
828  void addImm0_255Operands(MCInst &Inst, unsigned N) const {
829    assert(N == 1 && "Invalid number of operands!");
830    addExpr(Inst, getImm());
831  }
832
833  void addImm0_7Operands(MCInst &Inst, unsigned N) const {
834    assert(N == 1 && "Invalid number of operands!");
835    addExpr(Inst, getImm());
836  }
837
838  void addImm0_15Operands(MCInst &Inst, unsigned N) const {
839    assert(N == 1 && "Invalid number of operands!");
840    addExpr(Inst, getImm());
841  }
842
843  void addImm0_31Operands(MCInst &Inst, unsigned N) const {
844    assert(N == 1 && "Invalid number of operands!");
845    addExpr(Inst, getImm());
846  }
847
848  void addImm1_16Operands(MCInst &Inst, unsigned N) const {
849    assert(N == 1 && "Invalid number of operands!");
850    // The constant encodes as the immediate-1, and we store in the instruction
851    // the bits as encoded, so subtract off one here.
852    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
853    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
854  }
855
856  void addImm1_32Operands(MCInst &Inst, unsigned N) const {
857    assert(N == 1 && "Invalid number of operands!");
858    // The constant encodes as the immediate-1, and we store in the instruction
859    // the bits as encoded, so subtract off one here.
860    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
861    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
862  }
863
864  void addImm0_65535Operands(MCInst &Inst, unsigned N) const {
865    assert(N == 1 && "Invalid number of operands!");
866    addExpr(Inst, getImm());
867  }
868
869  void addImm0_65535ExprOperands(MCInst &Inst, unsigned N) const {
870    assert(N == 1 && "Invalid number of operands!");
871    addExpr(Inst, getImm());
872  }
873
874  void addImm24bitOperands(MCInst &Inst, unsigned N) const {
875    assert(N == 1 && "Invalid number of operands!");
876    addExpr(Inst, getImm());
877  }
878
879  void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
880    assert(N == 1 && "Invalid number of operands!");
881    // The constant encodes as the immediate, except for 32, which encodes as
882    // zero.
883    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
884    unsigned Imm = CE->getValue();
885    Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
886  }
887
888  void addPKHLSLImmOperands(MCInst &Inst, unsigned N) const {
889    assert(N == 1 && "Invalid number of operands!");
890    addExpr(Inst, getImm());
891  }
892
893  void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
894    assert(N == 1 && "Invalid number of operands!");
895    // An ASR value of 32 encodes as 0, so that's how we want to add it to
896    // the instruction as well.
897    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
898    int Val = CE->getValue();
899    Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
900  }
901
902  void addARMSOImmOperands(MCInst &Inst, unsigned N) const {
903    assert(N == 1 && "Invalid number of operands!");
904    addExpr(Inst, getImm());
905  }
906
907  void addT2SOImmOperands(MCInst &Inst, unsigned N) const {
908    assert(N == 1 && "Invalid number of operands!");
909    addExpr(Inst, getImm());
910  }
911
912  void addSetEndImmOperands(MCInst &Inst, unsigned N) const {
913    assert(N == 1 && "Invalid number of operands!");
914    addExpr(Inst, getImm());
915  }
916
917  void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
918    assert(N == 1 && "Invalid number of operands!");
919    Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
920  }
921
922  void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
923    assert(N == 1 && "Invalid number of operands!");
924    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
925  }
926
927  void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
928    assert(N == 3 && "Invalid number of operands!");
929    int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
930    if (!Mem.OffsetRegNum) {
931      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
932      // Special case for #-0
933      if (Val == INT32_MIN) Val = 0;
934      if (Val < 0) Val = -Val;
935      Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
936    } else {
937      // For register offset, we encode the shift type and negation flag
938      // here.
939      Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add,
940                              Mem.ShiftImm, Mem.ShiftType);
941    }
942    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
943    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
944    Inst.addOperand(MCOperand::CreateImm(Val));
945  }
946
947  void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
948    assert(N == 2 && "Invalid number of operands!");
949    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
950    assert(CE && "non-constant AM2OffsetImm operand!");
951    int32_t Val = CE->getValue();
952    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
953    // Special case for #-0
954    if (Val == INT32_MIN) Val = 0;
955    if (Val < 0) Val = -Val;
956    Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
957    Inst.addOperand(MCOperand::CreateReg(0));
958    Inst.addOperand(MCOperand::CreateImm(Val));
959  }
960
961  void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
962    assert(N == 3 && "Invalid number of operands!");
963    int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
964    if (!Mem.OffsetRegNum) {
965      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
966      // Special case for #-0
967      if (Val == INT32_MIN) Val = 0;
968      if (Val < 0) Val = -Val;
969      Val = ARM_AM::getAM3Opc(AddSub, Val);
970    } else {
971      // For register offset, we encode the shift type and negation flag
972      // here.
973      Val = ARM_AM::getAM3Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
974    }
975    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
976    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
977    Inst.addOperand(MCOperand::CreateImm(Val));
978  }
979
980  void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
981    assert(N == 2 && "Invalid number of operands!");
982    if (Kind == PostIndexRegister) {
983      int32_t Val =
984        ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
985      Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
986      Inst.addOperand(MCOperand::CreateImm(Val));
987      return;
988    }
989
990    // Constant offset.
991    const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
992    int32_t Val = CE->getValue();
993    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
994    // Special case for #-0
995    if (Val == INT32_MIN) Val = 0;
996    if (Val < 0) Val = -Val;
997    Val = ARM_AM::getAM3Opc(AddSub, Val);
998    Inst.addOperand(MCOperand::CreateReg(0));
999    Inst.addOperand(MCOperand::CreateImm(Val));
1000  }
1001
1002  void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
1003    assert(N == 2 && "Invalid number of operands!");
1004    // The lower two bits are always zero and as such are not encoded.
1005    int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() / 4 : 0;
1006    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1007    // Special case for #-0
1008    if (Val == INT32_MIN) Val = 0;
1009    if (Val < 0) Val = -Val;
1010    Val = ARM_AM::getAM5Opc(AddSub, Val);
1011    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1012    Inst.addOperand(MCOperand::CreateImm(Val));
1013  }
1014
1015  void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1016    assert(N == 2 && "Invalid number of operands!");
1017    int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1018    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1019    Inst.addOperand(MCOperand::CreateImm(Val));
1020  }
1021
1022  void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1023    assert(N == 2 && "Invalid number of operands!");
1024    // If this is an immediate, it's a label reference.
1025    if (Kind == Immediate) {
1026      addExpr(Inst, getImm());
1027      Inst.addOperand(MCOperand::CreateImm(0));
1028      return;
1029    }
1030
1031    // Otherwise, it's a normal memory reg+offset.
1032    int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1033    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1034    Inst.addOperand(MCOperand::CreateImm(Val));
1035  }
1036
1037  void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1038    assert(N == 3 && "Invalid number of operands!");
1039    unsigned Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add,
1040                                     Mem.ShiftImm, Mem.ShiftType);
1041    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1042    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1043    Inst.addOperand(MCOperand::CreateImm(Val));
1044  }
1045
1046  void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
1047    assert(N == 2 && "Invalid number of operands!");
1048    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1049    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1050  }
1051
1052  void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
1053    assert(N == 2 && "Invalid number of operands!");
1054    int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 4) : 0;
1055    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1056    Inst.addOperand(MCOperand::CreateImm(Val));
1057  }
1058
1059  void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
1060    assert(N == 2 && "Invalid number of operands!");
1061    int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 2) : 0;
1062    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1063    Inst.addOperand(MCOperand::CreateImm(Val));
1064  }
1065
1066  void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
1067    assert(N == 2 && "Invalid number of operands!");
1068    int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue()) : 0;
1069    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1070    Inst.addOperand(MCOperand::CreateImm(Val));
1071  }
1072
1073  void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
1074    assert(N == 2 && "Invalid number of operands!");
1075    int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 4) : 0;
1076    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1077    Inst.addOperand(MCOperand::CreateImm(Val));
1078  }
1079
1080  void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
1081    assert(N == 1 && "Invalid number of operands!");
1082    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1083    assert(CE && "non-constant post-idx-imm8 operand!");
1084    int Imm = CE->getValue();
1085    bool isAdd = Imm >= 0;
1086    Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
1087    Inst.addOperand(MCOperand::CreateImm(Imm));
1088  }
1089
1090  void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
1091    assert(N == 2 && "Invalid number of operands!");
1092    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1093    Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
1094  }
1095
1096  void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
1097    assert(N == 2 && "Invalid number of operands!");
1098    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1099    // The sign, shift type, and shift amount are encoded in a single operand
1100    // using the AM2 encoding helpers.
1101    ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
1102    unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
1103                                     PostIdxReg.ShiftTy);
1104    Inst.addOperand(MCOperand::CreateImm(Imm));
1105  }
1106
1107  void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
1108    assert(N == 1 && "Invalid number of operands!");
1109    Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
1110  }
1111
1112  void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
1113    assert(N == 1 && "Invalid number of operands!");
1114    Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
1115  }
1116
1117  virtual void print(raw_ostream &OS) const;
1118
1119  static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
1120    ARMOperand *Op = new ARMOperand(CondCode);
1121    Op->CC.Val = CC;
1122    Op->StartLoc = S;
1123    Op->EndLoc = S;
1124    return Op;
1125  }
1126
1127  static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
1128    ARMOperand *Op = new ARMOperand(CoprocNum);
1129    Op->Cop.Val = CopVal;
1130    Op->StartLoc = S;
1131    Op->EndLoc = S;
1132    return Op;
1133  }
1134
1135  static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
1136    ARMOperand *Op = new ARMOperand(CoprocReg);
1137    Op->Cop.Val = CopVal;
1138    Op->StartLoc = S;
1139    Op->EndLoc = S;
1140    return Op;
1141  }
1142
1143  static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
1144    ARMOperand *Op = new ARMOperand(CCOut);
1145    Op->Reg.RegNum = RegNum;
1146    Op->StartLoc = S;
1147    Op->EndLoc = S;
1148    return Op;
1149  }
1150
1151  static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
1152    ARMOperand *Op = new ARMOperand(Token);
1153    Op->Tok.Data = Str.data();
1154    Op->Tok.Length = Str.size();
1155    Op->StartLoc = S;
1156    Op->EndLoc = S;
1157    return Op;
1158  }
1159
1160  static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
1161    ARMOperand *Op = new ARMOperand(Register);
1162    Op->Reg.RegNum = RegNum;
1163    Op->StartLoc = S;
1164    Op->EndLoc = E;
1165    return Op;
1166  }
1167
1168  static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
1169                                           unsigned SrcReg,
1170                                           unsigned ShiftReg,
1171                                           unsigned ShiftImm,
1172                                           SMLoc S, SMLoc E) {
1173    ARMOperand *Op = new ARMOperand(ShiftedRegister);
1174    Op->RegShiftedReg.ShiftTy = ShTy;
1175    Op->RegShiftedReg.SrcReg = SrcReg;
1176    Op->RegShiftedReg.ShiftReg = ShiftReg;
1177    Op->RegShiftedReg.ShiftImm = ShiftImm;
1178    Op->StartLoc = S;
1179    Op->EndLoc = E;
1180    return Op;
1181  }
1182
1183  static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
1184                                            unsigned SrcReg,
1185                                            unsigned ShiftImm,
1186                                            SMLoc S, SMLoc E) {
1187    ARMOperand *Op = new ARMOperand(ShiftedImmediate);
1188    Op->RegShiftedImm.ShiftTy = ShTy;
1189    Op->RegShiftedImm.SrcReg = SrcReg;
1190    Op->RegShiftedImm.ShiftImm = ShiftImm;
1191    Op->StartLoc = S;
1192    Op->EndLoc = E;
1193    return Op;
1194  }
1195
1196  static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
1197                                   SMLoc S, SMLoc E) {
1198    ARMOperand *Op = new ARMOperand(ShifterImmediate);
1199    Op->ShifterImm.isASR = isASR;
1200    Op->ShifterImm.Imm = Imm;
1201    Op->StartLoc = S;
1202    Op->EndLoc = E;
1203    return Op;
1204  }
1205
1206  static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
1207    ARMOperand *Op = new ARMOperand(RotateImmediate);
1208    Op->RotImm.Imm = Imm;
1209    Op->StartLoc = S;
1210    Op->EndLoc = E;
1211    return Op;
1212  }
1213
1214  static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
1215                                    SMLoc S, SMLoc E) {
1216    ARMOperand *Op = new ARMOperand(BitfieldDescriptor);
1217    Op->Bitfield.LSB = LSB;
1218    Op->Bitfield.Width = Width;
1219    Op->StartLoc = S;
1220    Op->EndLoc = E;
1221    return Op;
1222  }
1223
1224  static ARMOperand *
1225  CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
1226                SMLoc StartLoc, SMLoc EndLoc) {
1227    KindTy Kind = RegisterList;
1228
1229    if (llvm::ARMMCRegisterClasses[ARM::DPRRegClassID].
1230        contains(Regs.front().first))
1231      Kind = DPRRegisterList;
1232    else if (llvm::ARMMCRegisterClasses[ARM::SPRRegClassID].
1233             contains(Regs.front().first))
1234      Kind = SPRRegisterList;
1235
1236    ARMOperand *Op = new ARMOperand(Kind);
1237    for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
1238           I = Regs.begin(), E = Regs.end(); I != E; ++I)
1239      Op->Registers.push_back(I->first);
1240    array_pod_sort(Op->Registers.begin(), Op->Registers.end());
1241    Op->StartLoc = StartLoc;
1242    Op->EndLoc = EndLoc;
1243    return Op;
1244  }
1245
1246  static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
1247    ARMOperand *Op = new ARMOperand(Immediate);
1248    Op->Imm.Val = Val;
1249    Op->StartLoc = S;
1250    Op->EndLoc = E;
1251    return Op;
1252  }
1253
1254  static ARMOperand *CreateMem(unsigned BaseRegNum,
1255                               const MCConstantExpr *OffsetImm,
1256                               unsigned OffsetRegNum,
1257                               ARM_AM::ShiftOpc ShiftType,
1258                               unsigned ShiftImm,
1259                               bool isNegative,
1260                               SMLoc S, SMLoc E) {
1261    ARMOperand *Op = new ARMOperand(Memory);
1262    Op->Mem.BaseRegNum = BaseRegNum;
1263    Op->Mem.OffsetImm = OffsetImm;
1264    Op->Mem.OffsetRegNum = OffsetRegNum;
1265    Op->Mem.ShiftType = ShiftType;
1266    Op->Mem.ShiftImm = ShiftImm;
1267    Op->Mem.isNegative = isNegative;
1268    Op->StartLoc = S;
1269    Op->EndLoc = E;
1270    return Op;
1271  }
1272
1273  static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
1274                                      ARM_AM::ShiftOpc ShiftTy,
1275                                      unsigned ShiftImm,
1276                                      SMLoc S, SMLoc E) {
1277    ARMOperand *Op = new ARMOperand(PostIndexRegister);
1278    Op->PostIdxReg.RegNum = RegNum;
1279    Op->PostIdxReg.isAdd = isAdd;
1280    Op->PostIdxReg.ShiftTy = ShiftTy;
1281    Op->PostIdxReg.ShiftImm = ShiftImm;
1282    Op->StartLoc = S;
1283    Op->EndLoc = E;
1284    return Op;
1285  }
1286
1287  static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
1288    ARMOperand *Op = new ARMOperand(MemBarrierOpt);
1289    Op->MBOpt.Val = Opt;
1290    Op->StartLoc = S;
1291    Op->EndLoc = S;
1292    return Op;
1293  }
1294
1295  static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
1296    ARMOperand *Op = new ARMOperand(ProcIFlags);
1297    Op->IFlags.Val = IFlags;
1298    Op->StartLoc = S;
1299    Op->EndLoc = S;
1300    return Op;
1301  }
1302
1303  static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
1304    ARMOperand *Op = new ARMOperand(MSRMask);
1305    Op->MMask.Val = MMask;
1306    Op->StartLoc = S;
1307    Op->EndLoc = S;
1308    return Op;
1309  }
1310};
1311
1312} // end anonymous namespace.
1313
1314void ARMOperand::print(raw_ostream &OS) const {
1315  switch (Kind) {
1316  case CondCode:
1317    OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
1318    break;
1319  case CCOut:
1320    OS << "<ccout " << getReg() << ">";
1321    break;
1322  case CoprocNum:
1323    OS << "<coprocessor number: " << getCoproc() << ">";
1324    break;
1325  case CoprocReg:
1326    OS << "<coprocessor register: " << getCoproc() << ">";
1327    break;
1328  case MSRMask:
1329    OS << "<mask: " << getMSRMask() << ">";
1330    break;
1331  case Immediate:
1332    getImm()->print(OS);
1333    break;
1334  case MemBarrierOpt:
1335    OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
1336    break;
1337  case Memory:
1338    OS << "<memory "
1339       << " base:" << Mem.BaseRegNum;
1340    OS << ">";
1341    break;
1342  case PostIndexRegister:
1343    OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
1344       << PostIdxReg.RegNum;
1345    if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
1346      OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
1347         << PostIdxReg.ShiftImm;
1348    OS << ">";
1349    break;
1350  case ProcIFlags: {
1351    OS << "<ARM_PROC::";
1352    unsigned IFlags = getProcIFlags();
1353    for (int i=2; i >= 0; --i)
1354      if (IFlags & (1 << i))
1355        OS << ARM_PROC::IFlagsToString(1 << i);
1356    OS << ">";
1357    break;
1358  }
1359  case Register:
1360    OS << "<register " << getReg() << ">";
1361    break;
1362  case ShifterImmediate:
1363    OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
1364       << " #" << ShifterImm.Imm << ">";
1365    break;
1366  case ShiftedRegister:
1367    OS << "<so_reg_reg "
1368       << RegShiftedReg.SrcReg
1369       << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedReg.ShiftImm))
1370       << ", " << RegShiftedReg.ShiftReg << ", "
1371       << ARM_AM::getSORegOffset(RegShiftedReg.ShiftImm)
1372       << ">";
1373    break;
1374  case ShiftedImmediate:
1375    OS << "<so_reg_imm "
1376       << RegShiftedImm.SrcReg
1377       << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedImm.ShiftImm))
1378       << ", " << ARM_AM::getSORegOffset(RegShiftedImm.ShiftImm)
1379       << ">";
1380    break;
1381  case RotateImmediate:
1382    OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
1383    break;
1384  case BitfieldDescriptor:
1385    OS << "<bitfield " << "lsb: " << Bitfield.LSB
1386       << ", width: " << Bitfield.Width << ">";
1387    break;
1388  case RegisterList:
1389  case DPRRegisterList:
1390  case SPRRegisterList: {
1391    OS << "<register_list ";
1392
1393    const SmallVectorImpl<unsigned> &RegList = getRegList();
1394    for (SmallVectorImpl<unsigned>::const_iterator
1395           I = RegList.begin(), E = RegList.end(); I != E; ) {
1396      OS << *I;
1397      if (++I < E) OS << ", ";
1398    }
1399
1400    OS << ">";
1401    break;
1402  }
1403  case Token:
1404    OS << "'" << getToken() << "'";
1405    break;
1406  }
1407}
1408
1409/// @name Auto-generated Match Functions
1410/// {
1411
1412static unsigned MatchRegisterName(StringRef Name);
1413
1414/// }
1415
1416bool ARMAsmParser::ParseRegister(unsigned &RegNo,
1417                                 SMLoc &StartLoc, SMLoc &EndLoc) {
1418  RegNo = tryParseRegister();
1419
1420  return (RegNo == (unsigned)-1);
1421}
1422
1423/// Try to parse a register name.  The token must be an Identifier when called,
1424/// and if it is a register name the token is eaten and the register number is
1425/// returned.  Otherwise return -1.
1426///
1427int ARMAsmParser::tryParseRegister() {
1428  const AsmToken &Tok = Parser.getTok();
1429  if (Tok.isNot(AsmToken::Identifier)) return -1;
1430
1431  // FIXME: Validate register for the current architecture; we have to do
1432  // validation later, so maybe there is no need for this here.
1433  std::string upperCase = Tok.getString().str();
1434  std::string lowerCase = LowercaseString(upperCase);
1435  unsigned RegNum = MatchRegisterName(lowerCase);
1436  if (!RegNum) {
1437    RegNum = StringSwitch<unsigned>(lowerCase)
1438      .Case("r13", ARM::SP)
1439      .Case("r14", ARM::LR)
1440      .Case("r15", ARM::PC)
1441      .Case("ip", ARM::R12)
1442      .Default(0);
1443  }
1444  if (!RegNum) return -1;
1445
1446  Parser.Lex(); // Eat identifier token.
1447  return RegNum;
1448}
1449
1450// Try to parse a shifter  (e.g., "lsl <amt>"). On success, return 0.
1451// If a recoverable error occurs, return 1. If an irrecoverable error
1452// occurs, return -1. An irrecoverable error is one where tokens have been
1453// consumed in the process of trying to parse the shifter (i.e., when it is
1454// indeed a shifter operand, but malformed).
1455int ARMAsmParser::tryParseShiftRegister(
1456                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1457  SMLoc S = Parser.getTok().getLoc();
1458  const AsmToken &Tok = Parser.getTok();
1459  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1460
1461  std::string upperCase = Tok.getString().str();
1462  std::string lowerCase = LowercaseString(upperCase);
1463  ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
1464      .Case("lsl", ARM_AM::lsl)
1465      .Case("lsr", ARM_AM::lsr)
1466      .Case("asr", ARM_AM::asr)
1467      .Case("ror", ARM_AM::ror)
1468      .Case("rrx", ARM_AM::rrx)
1469      .Default(ARM_AM::no_shift);
1470
1471  if (ShiftTy == ARM_AM::no_shift)
1472    return 1;
1473
1474  Parser.Lex(); // Eat the operator.
1475
1476  // The source register for the shift has already been added to the
1477  // operand list, so we need to pop it off and combine it into the shifted
1478  // register operand instead.
1479  OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
1480  if (!PrevOp->isReg())
1481    return Error(PrevOp->getStartLoc(), "shift must be of a register");
1482  int SrcReg = PrevOp->getReg();
1483  int64_t Imm = 0;
1484  int ShiftReg = 0;
1485  if (ShiftTy == ARM_AM::rrx) {
1486    // RRX Doesn't have an explicit shift amount. The encoder expects
1487    // the shift register to be the same as the source register. Seems odd,
1488    // but OK.
1489    ShiftReg = SrcReg;
1490  } else {
1491    // Figure out if this is shifted by a constant or a register (for non-RRX).
1492    if (Parser.getTok().is(AsmToken::Hash)) {
1493      Parser.Lex(); // Eat hash.
1494      SMLoc ImmLoc = Parser.getTok().getLoc();
1495      const MCExpr *ShiftExpr = 0;
1496      if (getParser().ParseExpression(ShiftExpr)) {
1497        Error(ImmLoc, "invalid immediate shift value");
1498        return -1;
1499      }
1500      // The expression must be evaluatable as an immediate.
1501      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
1502      if (!CE) {
1503        Error(ImmLoc, "invalid immediate shift value");
1504        return -1;
1505      }
1506      // Range check the immediate.
1507      // lsl, ror: 0 <= imm <= 31
1508      // lsr, asr: 0 <= imm <= 32
1509      Imm = CE->getValue();
1510      if (Imm < 0 ||
1511          ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
1512          ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
1513        Error(ImmLoc, "immediate shift value out of range");
1514        return -1;
1515      }
1516    } else if (Parser.getTok().is(AsmToken::Identifier)) {
1517      ShiftReg = tryParseRegister();
1518      SMLoc L = Parser.getTok().getLoc();
1519      if (ShiftReg == -1) {
1520        Error (L, "expected immediate or register in shift operand");
1521        return -1;
1522      }
1523    } else {
1524      Error (Parser.getTok().getLoc(),
1525                    "expected immediate or register in shift operand");
1526      return -1;
1527    }
1528  }
1529
1530  if (ShiftReg && ShiftTy != ARM_AM::rrx)
1531    Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
1532                                                         ShiftReg, Imm,
1533                                               S, Parser.getTok().getLoc()));
1534  else
1535    Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
1536                                               S, Parser.getTok().getLoc()));
1537
1538  return 0;
1539}
1540
1541
1542/// Try to parse a register name.  The token must be an Identifier when called.
1543/// If it's a register, an AsmOperand is created. Another AsmOperand is created
1544/// if there is a "writeback". 'true' if it's not a register.
1545///
1546/// TODO this is likely to change to allow different register types and or to
1547/// parse for a specific register type.
1548bool ARMAsmParser::
1549tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1550  SMLoc S = Parser.getTok().getLoc();
1551  int RegNo = tryParseRegister();
1552  if (RegNo == -1)
1553    return true;
1554
1555  Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
1556
1557  const AsmToken &ExclaimTok = Parser.getTok();
1558  if (ExclaimTok.is(AsmToken::Exclaim)) {
1559    Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
1560                                               ExclaimTok.getLoc()));
1561    Parser.Lex(); // Eat exclaim token
1562  }
1563
1564  return false;
1565}
1566
1567/// MatchCoprocessorOperandName - Try to parse an coprocessor related
1568/// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
1569/// "c5", ...
1570static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
1571  // Use the same layout as the tablegen'erated register name matcher. Ugly,
1572  // but efficient.
1573  switch (Name.size()) {
1574  default: break;
1575  case 2:
1576    if (Name[0] != CoprocOp)
1577      return -1;
1578    switch (Name[1]) {
1579    default:  return -1;
1580    case '0': return 0;
1581    case '1': return 1;
1582    case '2': return 2;
1583    case '3': return 3;
1584    case '4': return 4;
1585    case '5': return 5;
1586    case '6': return 6;
1587    case '7': return 7;
1588    case '8': return 8;
1589    case '9': return 9;
1590    }
1591    break;
1592  case 3:
1593    if (Name[0] != CoprocOp || Name[1] != '1')
1594      return -1;
1595    switch (Name[2]) {
1596    default:  return -1;
1597    case '0': return 10;
1598    case '1': return 11;
1599    case '2': return 12;
1600    case '3': return 13;
1601    case '4': return 14;
1602    case '5': return 15;
1603    }
1604    break;
1605  }
1606
1607  return -1;
1608}
1609
1610/// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
1611/// token must be an Identifier when called, and if it is a coprocessor
1612/// number, the token is eaten and the operand is added to the operand list.
1613ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1614parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1615  SMLoc S = Parser.getTok().getLoc();
1616  const AsmToken &Tok = Parser.getTok();
1617  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1618
1619  int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
1620  if (Num == -1)
1621    return MatchOperand_NoMatch;
1622
1623  Parser.Lex(); // Eat identifier token.
1624  Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
1625  return MatchOperand_Success;
1626}
1627
1628/// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
1629/// token must be an Identifier when called, and if it is a coprocessor
1630/// number, the token is eaten and the operand is added to the operand list.
1631ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1632parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1633  SMLoc S = Parser.getTok().getLoc();
1634  const AsmToken &Tok = Parser.getTok();
1635  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1636
1637  int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
1638  if (Reg == -1)
1639    return MatchOperand_NoMatch;
1640
1641  Parser.Lex(); // Eat identifier token.
1642  Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
1643  return MatchOperand_Success;
1644}
1645
1646/// Parse a register list, return it if successful else return null.  The first
1647/// token must be a '{' when called.
1648bool ARMAsmParser::
1649parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1650  assert(Parser.getTok().is(AsmToken::LCurly) &&
1651         "Token is not a Left Curly Brace");
1652  SMLoc S = Parser.getTok().getLoc();
1653
1654  // Read the rest of the registers in the list.
1655  unsigned PrevRegNum = 0;
1656  SmallVector<std::pair<unsigned, SMLoc>, 32> Registers;
1657
1658  do {
1659    bool IsRange = Parser.getTok().is(AsmToken::Minus);
1660    Parser.Lex(); // Eat non-identifier token.
1661
1662    const AsmToken &RegTok = Parser.getTok();
1663    SMLoc RegLoc = RegTok.getLoc();
1664    if (RegTok.isNot(AsmToken::Identifier)) {
1665      Error(RegLoc, "register expected");
1666      return true;
1667    }
1668
1669    int RegNum = tryParseRegister();
1670    if (RegNum == -1) {
1671      Error(RegLoc, "register expected");
1672      return true;
1673    }
1674
1675    if (IsRange) {
1676      int Reg = PrevRegNum;
1677      do {
1678        ++Reg;
1679        Registers.push_back(std::make_pair(Reg, RegLoc));
1680      } while (Reg != RegNum);
1681    } else {
1682      Registers.push_back(std::make_pair(RegNum, RegLoc));
1683    }
1684
1685    PrevRegNum = RegNum;
1686  } while (Parser.getTok().is(AsmToken::Comma) ||
1687           Parser.getTok().is(AsmToken::Minus));
1688
1689  // Process the right curly brace of the list.
1690  const AsmToken &RCurlyTok = Parser.getTok();
1691  if (RCurlyTok.isNot(AsmToken::RCurly)) {
1692    Error(RCurlyTok.getLoc(), "'}' expected");
1693    return true;
1694  }
1695
1696  SMLoc E = RCurlyTok.getLoc();
1697  Parser.Lex(); // Eat right curly brace token.
1698
1699  // Verify the register list.
1700  bool EmittedWarning = false;
1701  unsigned HighRegNum = 0;
1702  BitVector RegMap(32);
1703  for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
1704    const std::pair<unsigned, SMLoc> &RegInfo = Registers[i];
1705    unsigned Reg = getARMRegisterNumbering(RegInfo.first);
1706
1707    if (RegMap[Reg]) {
1708      Error(RegInfo.second, "register duplicated in register list");
1709      return true;
1710    }
1711
1712    if (!EmittedWarning && Reg < HighRegNum)
1713      Warning(RegInfo.second,
1714              "register not in ascending order in register list");
1715
1716    RegMap.set(Reg);
1717    HighRegNum = std::max(Reg, HighRegNum);
1718  }
1719
1720  Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
1721  return false;
1722}
1723
1724/// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
1725ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1726parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1727  SMLoc S = Parser.getTok().getLoc();
1728  const AsmToken &Tok = Parser.getTok();
1729  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1730  StringRef OptStr = Tok.getString();
1731
1732  unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()))
1733    .Case("sy",    ARM_MB::SY)
1734    .Case("st",    ARM_MB::ST)
1735    .Case("sh",    ARM_MB::ISH)
1736    .Case("ish",   ARM_MB::ISH)
1737    .Case("shst",  ARM_MB::ISHST)
1738    .Case("ishst", ARM_MB::ISHST)
1739    .Case("nsh",   ARM_MB::NSH)
1740    .Case("un",    ARM_MB::NSH)
1741    .Case("nshst", ARM_MB::NSHST)
1742    .Case("unst",  ARM_MB::NSHST)
1743    .Case("osh",   ARM_MB::OSH)
1744    .Case("oshst", ARM_MB::OSHST)
1745    .Default(~0U);
1746
1747  if (Opt == ~0U)
1748    return MatchOperand_NoMatch;
1749
1750  Parser.Lex(); // Eat identifier token.
1751  Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
1752  return MatchOperand_Success;
1753}
1754
1755/// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
1756ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1757parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1758  SMLoc S = Parser.getTok().getLoc();
1759  const AsmToken &Tok = Parser.getTok();
1760  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1761  StringRef IFlagsStr = Tok.getString();
1762
1763  unsigned IFlags = 0;
1764  for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
1765    unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
1766    .Case("a", ARM_PROC::A)
1767    .Case("i", ARM_PROC::I)
1768    .Case("f", ARM_PROC::F)
1769    .Default(~0U);
1770
1771    // If some specific iflag is already set, it means that some letter is
1772    // present more than once, this is not acceptable.
1773    if (Flag == ~0U || (IFlags & Flag))
1774      return MatchOperand_NoMatch;
1775
1776    IFlags |= Flag;
1777  }
1778
1779  Parser.Lex(); // Eat identifier token.
1780  Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
1781  return MatchOperand_Success;
1782}
1783
1784/// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
1785ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1786parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1787  SMLoc S = Parser.getTok().getLoc();
1788  const AsmToken &Tok = Parser.getTok();
1789  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1790  StringRef Mask = Tok.getString();
1791
1792  // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
1793  size_t Start = 0, Next = Mask.find('_');
1794  StringRef Flags = "";
1795  std::string SpecReg = LowercaseString(Mask.slice(Start, Next));
1796  if (Next != StringRef::npos)
1797    Flags = Mask.slice(Next+1, Mask.size());
1798
1799  // FlagsVal contains the complete mask:
1800  // 3-0: Mask
1801  // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
1802  unsigned FlagsVal = 0;
1803
1804  if (SpecReg == "apsr") {
1805    FlagsVal = StringSwitch<unsigned>(Flags)
1806    .Case("nzcvq",  0x8) // same as CPSR_f
1807    .Case("g",      0x4) // same as CPSR_s
1808    .Case("nzcvqg", 0xc) // same as CPSR_fs
1809    .Default(~0U);
1810
1811    if (FlagsVal == ~0U) {
1812      if (!Flags.empty())
1813        return MatchOperand_NoMatch;
1814      else
1815        FlagsVal = 0; // No flag
1816    }
1817  } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
1818    if (Flags == "all") // cpsr_all is an alias for cpsr_fc
1819      Flags = "fc";
1820    for (int i = 0, e = Flags.size(); i != e; ++i) {
1821      unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
1822      .Case("c", 1)
1823      .Case("x", 2)
1824      .Case("s", 4)
1825      .Case("f", 8)
1826      .Default(~0U);
1827
1828      // If some specific flag is already set, it means that some letter is
1829      // present more than once, this is not acceptable.
1830      if (FlagsVal == ~0U || (FlagsVal & Flag))
1831        return MatchOperand_NoMatch;
1832      FlagsVal |= Flag;
1833    }
1834  } else // No match for special register.
1835    return MatchOperand_NoMatch;
1836
1837  // Special register without flags are equivalent to "fc" flags.
1838  if (!FlagsVal)
1839    FlagsVal = 0x9;
1840
1841  // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
1842  if (SpecReg == "spsr")
1843    FlagsVal |= 16;
1844
1845  Parser.Lex(); // Eat identifier token.
1846  Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
1847  return MatchOperand_Success;
1848}
1849
1850ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1851parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
1852            int Low, int High) {
1853  const AsmToken &Tok = Parser.getTok();
1854  if (Tok.isNot(AsmToken::Identifier)) {
1855    Error(Parser.getTok().getLoc(), Op + " operand expected.");
1856    return MatchOperand_ParseFail;
1857  }
1858  StringRef ShiftName = Tok.getString();
1859  std::string LowerOp = LowercaseString(Op);
1860  std::string UpperOp = UppercaseString(Op);
1861  if (ShiftName != LowerOp && ShiftName != UpperOp) {
1862    Error(Parser.getTok().getLoc(), Op + " operand expected.");
1863    return MatchOperand_ParseFail;
1864  }
1865  Parser.Lex(); // Eat shift type token.
1866
1867  // There must be a '#' and a shift amount.
1868  if (Parser.getTok().isNot(AsmToken::Hash)) {
1869    Error(Parser.getTok().getLoc(), "'#' expected");
1870    return MatchOperand_ParseFail;
1871  }
1872  Parser.Lex(); // Eat hash token.
1873
1874  const MCExpr *ShiftAmount;
1875  SMLoc Loc = Parser.getTok().getLoc();
1876  if (getParser().ParseExpression(ShiftAmount)) {
1877    Error(Loc, "illegal expression");
1878    return MatchOperand_ParseFail;
1879  }
1880  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
1881  if (!CE) {
1882    Error(Loc, "constant expression expected");
1883    return MatchOperand_ParseFail;
1884  }
1885  int Val = CE->getValue();
1886  if (Val < Low || Val > High) {
1887    Error(Loc, "immediate value out of range");
1888    return MatchOperand_ParseFail;
1889  }
1890
1891  Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc()));
1892
1893  return MatchOperand_Success;
1894}
1895
1896ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1897parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1898  const AsmToken &Tok = Parser.getTok();
1899  SMLoc S = Tok.getLoc();
1900  if (Tok.isNot(AsmToken::Identifier)) {
1901    Error(Tok.getLoc(), "'be' or 'le' operand expected");
1902    return MatchOperand_ParseFail;
1903  }
1904  int Val = StringSwitch<int>(Tok.getString())
1905    .Case("be", 1)
1906    .Case("le", 0)
1907    .Default(-1);
1908  Parser.Lex(); // Eat the token.
1909
1910  if (Val == -1) {
1911    Error(Tok.getLoc(), "'be' or 'le' operand expected");
1912    return MatchOperand_ParseFail;
1913  }
1914  Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
1915                                                                  getContext()),
1916                                           S, Parser.getTok().getLoc()));
1917  return MatchOperand_Success;
1918}
1919
1920/// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
1921/// instructions. Legal values are:
1922///     lsl #n  'n' in [0,31]
1923///     asr #n  'n' in [1,32]
1924///             n == 32 encoded as n == 0.
1925ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1926parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1927  const AsmToken &Tok = Parser.getTok();
1928  SMLoc S = Tok.getLoc();
1929  if (Tok.isNot(AsmToken::Identifier)) {
1930    Error(S, "shift operator 'asr' or 'lsl' expected");
1931    return MatchOperand_ParseFail;
1932  }
1933  StringRef ShiftName = Tok.getString();
1934  bool isASR;
1935  if (ShiftName == "lsl" || ShiftName == "LSL")
1936    isASR = false;
1937  else if (ShiftName == "asr" || ShiftName == "ASR")
1938    isASR = true;
1939  else {
1940    Error(S, "shift operator 'asr' or 'lsl' expected");
1941    return MatchOperand_ParseFail;
1942  }
1943  Parser.Lex(); // Eat the operator.
1944
1945  // A '#' and a shift amount.
1946  if (Parser.getTok().isNot(AsmToken::Hash)) {
1947    Error(Parser.getTok().getLoc(), "'#' expected");
1948    return MatchOperand_ParseFail;
1949  }
1950  Parser.Lex(); // Eat hash token.
1951
1952  const MCExpr *ShiftAmount;
1953  SMLoc E = Parser.getTok().getLoc();
1954  if (getParser().ParseExpression(ShiftAmount)) {
1955    Error(E, "malformed shift expression");
1956    return MatchOperand_ParseFail;
1957  }
1958  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
1959  if (!CE) {
1960    Error(E, "shift amount must be an immediate");
1961    return MatchOperand_ParseFail;
1962  }
1963
1964  int64_t Val = CE->getValue();
1965  if (isASR) {
1966    // Shift amount must be in [1,32]
1967    if (Val < 1 || Val > 32) {
1968      Error(E, "'asr' shift amount must be in range [1,32]");
1969      return MatchOperand_ParseFail;
1970    }
1971    // asr #32 encoded as asr #0.
1972    if (Val == 32) Val = 0;
1973  } else {
1974    // Shift amount must be in [1,32]
1975    if (Val < 0 || Val > 31) {
1976      Error(E, "'lsr' shift amount must be in range [0,31]");
1977      return MatchOperand_ParseFail;
1978    }
1979  }
1980
1981  E = Parser.getTok().getLoc();
1982  Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E));
1983
1984  return MatchOperand_Success;
1985}
1986
1987/// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
1988/// of instructions. Legal values are:
1989///     ror #n  'n' in {0, 8, 16, 24}
1990ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1991parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1992  const AsmToken &Tok = Parser.getTok();
1993  SMLoc S = Tok.getLoc();
1994  if (Tok.isNot(AsmToken::Identifier)) {
1995    Error(S, "rotate operator 'ror' expected");
1996    return MatchOperand_ParseFail;
1997  }
1998  StringRef ShiftName = Tok.getString();
1999  if (ShiftName != "ror" && ShiftName != "ROR") {
2000    Error(S, "rotate operator 'ror' expected");
2001    return MatchOperand_ParseFail;
2002  }
2003  Parser.Lex(); // Eat the operator.
2004
2005  // A '#' and a rotate amount.
2006  if (Parser.getTok().isNot(AsmToken::Hash)) {
2007    Error(Parser.getTok().getLoc(), "'#' expected");
2008    return MatchOperand_ParseFail;
2009  }
2010  Parser.Lex(); // Eat hash token.
2011
2012  const MCExpr *ShiftAmount;
2013  SMLoc E = Parser.getTok().getLoc();
2014  if (getParser().ParseExpression(ShiftAmount)) {
2015    Error(E, "malformed rotate expression");
2016    return MatchOperand_ParseFail;
2017  }
2018  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
2019  if (!CE) {
2020    Error(E, "rotate amount must be an immediate");
2021    return MatchOperand_ParseFail;
2022  }
2023
2024  int64_t Val = CE->getValue();
2025  // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
2026  // normally, zero is represented in asm by omitting the rotate operand
2027  // entirely.
2028  if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
2029    Error(E, "'ror' rotate amount must be 8, 16, or 24");
2030    return MatchOperand_ParseFail;
2031  }
2032
2033  E = Parser.getTok().getLoc();
2034  Operands.push_back(ARMOperand::CreateRotImm(Val, S, E));
2035
2036  return MatchOperand_Success;
2037}
2038
2039ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2040parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2041  SMLoc S = Parser.getTok().getLoc();
2042  // The bitfield descriptor is really two operands, the LSB and the width.
2043  if (Parser.getTok().isNot(AsmToken::Hash)) {
2044    Error(Parser.getTok().getLoc(), "'#' expected");
2045    return MatchOperand_ParseFail;
2046  }
2047  Parser.Lex(); // Eat hash token.
2048
2049  const MCExpr *LSBExpr;
2050  SMLoc E = Parser.getTok().getLoc();
2051  if (getParser().ParseExpression(LSBExpr)) {
2052    Error(E, "malformed immediate expression");
2053    return MatchOperand_ParseFail;
2054  }
2055  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
2056  if (!CE) {
2057    Error(E, "'lsb' operand must be an immediate");
2058    return MatchOperand_ParseFail;
2059  }
2060
2061  int64_t LSB = CE->getValue();
2062  // The LSB must be in the range [0,31]
2063  if (LSB < 0 || LSB > 31) {
2064    Error(E, "'lsb' operand must be in the range [0,31]");
2065    return MatchOperand_ParseFail;
2066  }
2067  E = Parser.getTok().getLoc();
2068
2069  // Expect another immediate operand.
2070  if (Parser.getTok().isNot(AsmToken::Comma)) {
2071    Error(Parser.getTok().getLoc(), "too few operands");
2072    return MatchOperand_ParseFail;
2073  }
2074  Parser.Lex(); // Eat hash token.
2075  if (Parser.getTok().isNot(AsmToken::Hash)) {
2076    Error(Parser.getTok().getLoc(), "'#' expected");
2077    return MatchOperand_ParseFail;
2078  }
2079  Parser.Lex(); // Eat hash token.
2080
2081  const MCExpr *WidthExpr;
2082  if (getParser().ParseExpression(WidthExpr)) {
2083    Error(E, "malformed immediate expression");
2084    return MatchOperand_ParseFail;
2085  }
2086  CE = dyn_cast<MCConstantExpr>(WidthExpr);
2087  if (!CE) {
2088    Error(E, "'width' operand must be an immediate");
2089    return MatchOperand_ParseFail;
2090  }
2091
2092  int64_t Width = CE->getValue();
2093  // The LSB must be in the range [1,32-lsb]
2094  if (Width < 1 || Width > 32 - LSB) {
2095    Error(E, "'width' operand must be in the range [1,32-lsb]");
2096    return MatchOperand_ParseFail;
2097  }
2098  E = Parser.getTok().getLoc();
2099
2100  Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E));
2101
2102  return MatchOperand_Success;
2103}
2104
2105ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2106parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2107  // Check for a post-index addressing register operand. Specifically:
2108  // postidx_reg := '+' register {, shift}
2109  //              | '-' register {, shift}
2110  //              | register {, shift}
2111
2112  // This method must return MatchOperand_NoMatch without consuming any tokens
2113  // in the case where there is no match, as other alternatives take other
2114  // parse methods.
2115  AsmToken Tok = Parser.getTok();
2116  SMLoc S = Tok.getLoc();
2117  bool haveEaten = false;
2118  bool isAdd = true;
2119  int Reg = -1;
2120  if (Tok.is(AsmToken::Plus)) {
2121    Parser.Lex(); // Eat the '+' token.
2122    haveEaten = true;
2123  } else if (Tok.is(AsmToken::Minus)) {
2124    Parser.Lex(); // Eat the '-' token.
2125    isAdd = false;
2126    haveEaten = true;
2127  }
2128  if (Parser.getTok().is(AsmToken::Identifier))
2129    Reg = tryParseRegister();
2130  if (Reg == -1) {
2131    if (!haveEaten)
2132      return MatchOperand_NoMatch;
2133    Error(Parser.getTok().getLoc(), "register expected");
2134    return MatchOperand_ParseFail;
2135  }
2136  SMLoc E = Parser.getTok().getLoc();
2137
2138  ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
2139  unsigned ShiftImm = 0;
2140  if (Parser.getTok().is(AsmToken::Comma)) {
2141    Parser.Lex(); // Eat the ','.
2142    if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
2143      return MatchOperand_ParseFail;
2144  }
2145
2146  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
2147                                                  ShiftImm, S, E));
2148
2149  return MatchOperand_Success;
2150}
2151
2152ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2153parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2154  // Check for a post-index addressing register operand. Specifically:
2155  // am3offset := '+' register
2156  //              | '-' register
2157  //              | register
2158  //              | # imm
2159  //              | # + imm
2160  //              | # - imm
2161
2162  // This method must return MatchOperand_NoMatch without consuming any tokens
2163  // in the case where there is no match, as other alternatives take other
2164  // parse methods.
2165  AsmToken Tok = Parser.getTok();
2166  SMLoc S = Tok.getLoc();
2167
2168  // Do immediates first, as we always parse those if we have a '#'.
2169  if (Parser.getTok().is(AsmToken::Hash)) {
2170    Parser.Lex(); // Eat the '#'.
2171    // Explicitly look for a '-', as we need to encode negative zero
2172    // differently.
2173    bool isNegative = Parser.getTok().is(AsmToken::Minus);
2174    const MCExpr *Offset;
2175    if (getParser().ParseExpression(Offset))
2176      return MatchOperand_ParseFail;
2177    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
2178    if (!CE) {
2179      Error(S, "constant expression expected");
2180      return MatchOperand_ParseFail;
2181    }
2182    SMLoc E = Tok.getLoc();
2183    // Negative zero is encoded as the flag value INT32_MIN.
2184    int32_t Val = CE->getValue();
2185    if (isNegative && Val == 0)
2186      Val = INT32_MIN;
2187
2188    Operands.push_back(
2189      ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
2190
2191    return MatchOperand_Success;
2192  }
2193
2194
2195  bool haveEaten = false;
2196  bool isAdd = true;
2197  int Reg = -1;
2198  if (Tok.is(AsmToken::Plus)) {
2199    Parser.Lex(); // Eat the '+' token.
2200    haveEaten = true;
2201  } else if (Tok.is(AsmToken::Minus)) {
2202    Parser.Lex(); // Eat the '-' token.
2203    isAdd = false;
2204    haveEaten = true;
2205  }
2206  if (Parser.getTok().is(AsmToken::Identifier))
2207    Reg = tryParseRegister();
2208  if (Reg == -1) {
2209    if (!haveEaten)
2210      return MatchOperand_NoMatch;
2211    Error(Parser.getTok().getLoc(), "register expected");
2212    return MatchOperand_ParseFail;
2213  }
2214  SMLoc E = Parser.getTok().getLoc();
2215
2216  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
2217                                                  0, S, E));
2218
2219  return MatchOperand_Success;
2220}
2221
2222/// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
2223/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2224/// when they refer multiple MIOperands inside a single one.
2225bool ARMAsmParser::
2226cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
2227                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2228  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2229
2230  // Create a writeback register dummy placeholder.
2231  Inst.addOperand(MCOperand::CreateImm(0));
2232
2233  ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
2234  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2235  return true;
2236}
2237
2238/// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
2239/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2240/// when they refer multiple MIOperands inside a single one.
2241bool ARMAsmParser::
2242cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
2243                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2244  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2245
2246  // Create a writeback register dummy placeholder.
2247  Inst.addOperand(MCOperand::CreateImm(0));
2248
2249  ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
2250  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2251  return true;
2252}
2253
2254
2255/// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
2256/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2257/// when they refer multiple MIOperands inside a single one.
2258bool ARMAsmParser::
2259cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
2260                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2261  // Create a writeback register dummy placeholder.
2262  Inst.addOperand(MCOperand::CreateImm(0));
2263  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2264  ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
2265  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2266  return true;
2267}
2268
2269/// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
2270/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2271/// when they refer multiple MIOperands inside a single one.
2272bool ARMAsmParser::
2273cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
2274                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2275  // Create a writeback register dummy placeholder.
2276  Inst.addOperand(MCOperand::CreateImm(0));
2277  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2278  ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
2279  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2280  return true;
2281}
2282
2283/// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
2284/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2285/// when they refer multiple MIOperands inside a single one.
2286bool ARMAsmParser::
2287cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
2288                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2289  // Create a writeback register dummy placeholder.
2290  Inst.addOperand(MCOperand::CreateImm(0));
2291  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2292  ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
2293  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2294  return true;
2295}
2296
2297/// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst.
2298/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2299/// when they refer multiple MIOperands inside a single one.
2300bool ARMAsmParser::
2301cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
2302                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2303  // Rt
2304  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2305  // Create a writeback register dummy placeholder.
2306  Inst.addOperand(MCOperand::CreateImm(0));
2307  // addr
2308  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2309  // offset
2310  ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
2311  // pred
2312  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2313  return true;
2314}
2315
2316/// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst.
2317/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2318/// when they refer multiple MIOperands inside a single one.
2319bool ARMAsmParser::
2320cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
2321                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2322  // Rt
2323  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2324  // Create a writeback register dummy placeholder.
2325  Inst.addOperand(MCOperand::CreateImm(0));
2326  // addr
2327  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2328  // offset
2329  ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
2330  // pred
2331  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2332  return true;
2333}
2334
2335/// cvtStExtTWriteBackImm - Convert parsed operands to MCInst.
2336/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2337/// when they refer multiple MIOperands inside a single one.
2338bool ARMAsmParser::
2339cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
2340                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2341  // Create a writeback register dummy placeholder.
2342  Inst.addOperand(MCOperand::CreateImm(0));
2343  // Rt
2344  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2345  // addr
2346  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2347  // offset
2348  ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
2349  // pred
2350  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2351  return true;
2352}
2353
2354/// cvtStExtTWriteBackReg - Convert parsed operands to MCInst.
2355/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2356/// when they refer multiple MIOperands inside a single one.
2357bool ARMAsmParser::
2358cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
2359                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2360  // Create a writeback register dummy placeholder.
2361  Inst.addOperand(MCOperand::CreateImm(0));
2362  // Rt
2363  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2364  // addr
2365  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2366  // offset
2367  ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
2368  // pred
2369  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2370  return true;
2371}
2372
2373/// cvtLdrdPre - Convert parsed operands to MCInst.
2374/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2375/// when they refer multiple MIOperands inside a single one.
2376bool ARMAsmParser::
2377cvtLdrdPre(MCInst &Inst, unsigned Opcode,
2378           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2379  // Rt, Rt2
2380  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2381  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2382  // Create a writeback register dummy placeholder.
2383  Inst.addOperand(MCOperand::CreateImm(0));
2384  // addr
2385  ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
2386  // pred
2387  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2388  return true;
2389}
2390
2391/// cvtStrdPre - Convert parsed operands to MCInst.
2392/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2393/// when they refer multiple MIOperands inside a single one.
2394bool ARMAsmParser::
2395cvtStrdPre(MCInst &Inst, unsigned Opcode,
2396           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2397  // Create a writeback register dummy placeholder.
2398  Inst.addOperand(MCOperand::CreateImm(0));
2399  // Rt, Rt2
2400  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2401  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2402  // addr
2403  ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
2404  // pred
2405  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2406  return true;
2407}
2408
2409/// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
2410/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2411/// when they refer multiple MIOperands inside a single one.
2412bool ARMAsmParser::
2413cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
2414                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2415  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2416  // Create a writeback register dummy placeholder.
2417  Inst.addOperand(MCOperand::CreateImm(0));
2418  ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
2419  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2420  return true;
2421}
2422
2423/// cvtThumbMultiple- Convert parsed operands to MCInst.
2424/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2425/// when they refer multiple MIOperands inside a single one.
2426bool ARMAsmParser::
2427cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
2428           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2429  // The second source operand must be the same register as the destination
2430  // operand.
2431  if (Operands.size() == 6 &&
2432      (((ARMOperand*)Operands[3])->getReg() !=
2433       ((ARMOperand*)Operands[5])->getReg()) &&
2434      (((ARMOperand*)Operands[3])->getReg() !=
2435       ((ARMOperand*)Operands[4])->getReg())) {
2436    Error(Operands[3]->getStartLoc(),
2437          "destination register must match source register");
2438    return false;
2439  }
2440  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2441  ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
2442  ((ARMOperand*)Operands[4])->addRegOperands(Inst, 1);
2443  // If we have a three-operand form, use that, else the second source operand
2444  // is just the destination operand again.
2445  if (Operands.size() == 6)
2446    ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
2447  else
2448    Inst.addOperand(Inst.getOperand(0));
2449  ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
2450
2451  return true;
2452}
2453
2454/// Parse an ARM memory expression, return false if successful else return true
2455/// or an error.  The first token must be a '[' when called.
2456bool ARMAsmParser::
2457parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2458  SMLoc S, E;
2459  assert(Parser.getTok().is(AsmToken::LBrac) &&
2460         "Token is not a Left Bracket");
2461  S = Parser.getTok().getLoc();
2462  Parser.Lex(); // Eat left bracket token.
2463
2464  const AsmToken &BaseRegTok = Parser.getTok();
2465  int BaseRegNum = tryParseRegister();
2466  if (BaseRegNum == -1)
2467    return Error(BaseRegTok.getLoc(), "register expected");
2468
2469  // The next token must either be a comma or a closing bracket.
2470  const AsmToken &Tok = Parser.getTok();
2471  if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac))
2472    return Error(Tok.getLoc(), "malformed memory operand");
2473
2474  if (Tok.is(AsmToken::RBrac)) {
2475    E = Tok.getLoc();
2476    Parser.Lex(); // Eat right bracket token.
2477
2478    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
2479                                             0, false, S, E));
2480
2481    return false;
2482  }
2483
2484  assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!");
2485  Parser.Lex(); // Eat the comma.
2486
2487  // If we have a '#' it's an immediate offset, else assume it's a register
2488  // offset.
2489  if (Parser.getTok().is(AsmToken::Hash)) {
2490    Parser.Lex(); // Eat the '#'.
2491    E = Parser.getTok().getLoc();
2492
2493    // FIXME: Special case #-0 so we can correctly set the U bit.
2494
2495    const MCExpr *Offset;
2496    if (getParser().ParseExpression(Offset))
2497     return true;
2498
2499    // The expression has to be a constant. Memory references with relocations
2500    // don't come through here, as they use the <label> forms of the relevant
2501    // instructions.
2502    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
2503    if (!CE)
2504      return Error (E, "constant expression expected");
2505
2506    // Now we should have the closing ']'
2507    E = Parser.getTok().getLoc();
2508    if (Parser.getTok().isNot(AsmToken::RBrac))
2509      return Error(E, "']' expected");
2510    Parser.Lex(); // Eat right bracket token.
2511
2512    // Don't worry about range checking the value here. That's handled by
2513    // the is*() predicates.
2514    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
2515                                             ARM_AM::no_shift, 0, false, S,E));
2516
2517    // If there's a pre-indexing writeback marker, '!', just add it as a token
2518    // operand.
2519    if (Parser.getTok().is(AsmToken::Exclaim)) {
2520      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
2521      Parser.Lex(); // Eat the '!'.
2522    }
2523
2524    return false;
2525  }
2526
2527  // The register offset is optionally preceded by a '+' or '-'
2528  bool isNegative = false;
2529  if (Parser.getTok().is(AsmToken::Minus)) {
2530    isNegative = true;
2531    Parser.Lex(); // Eat the '-'.
2532  } else if (Parser.getTok().is(AsmToken::Plus)) {
2533    // Nothing to do.
2534    Parser.Lex(); // Eat the '+'.
2535  }
2536
2537  E = Parser.getTok().getLoc();
2538  int OffsetRegNum = tryParseRegister();
2539  if (OffsetRegNum == -1)
2540    return Error(E, "register expected");
2541
2542  // If there's a shift operator, handle it.
2543  ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
2544  unsigned ShiftImm = 0;
2545  if (Parser.getTok().is(AsmToken::Comma)) {
2546    Parser.Lex(); // Eat the ','.
2547    if (parseMemRegOffsetShift(ShiftType, ShiftImm))
2548      return true;
2549  }
2550
2551  // Now we should have the closing ']'
2552  E = Parser.getTok().getLoc();
2553  if (Parser.getTok().isNot(AsmToken::RBrac))
2554    return Error(E, "']' expected");
2555  Parser.Lex(); // Eat right bracket token.
2556
2557  Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
2558                                           ShiftType, ShiftImm, isNegative,
2559                                           S, E));
2560
2561  // If there's a pre-indexing writeback marker, '!', just add it as a token
2562  // operand.
2563  if (Parser.getTok().is(AsmToken::Exclaim)) {
2564    Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
2565    Parser.Lex(); // Eat the '!'.
2566  }
2567
2568  return false;
2569}
2570
2571/// parseMemRegOffsetShift - one of these two:
2572///   ( lsl | lsr | asr | ror ) , # shift_amount
2573///   rrx
2574/// return true if it parses a shift otherwise it returns false.
2575bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
2576                                          unsigned &Amount) {
2577  SMLoc Loc = Parser.getTok().getLoc();
2578  const AsmToken &Tok = Parser.getTok();
2579  if (Tok.isNot(AsmToken::Identifier))
2580    return true;
2581  StringRef ShiftName = Tok.getString();
2582  if (ShiftName == "lsl" || ShiftName == "LSL")
2583    St = ARM_AM::lsl;
2584  else if (ShiftName == "lsr" || ShiftName == "LSR")
2585    St = ARM_AM::lsr;
2586  else if (ShiftName == "asr" || ShiftName == "ASR")
2587    St = ARM_AM::asr;
2588  else if (ShiftName == "ror" || ShiftName == "ROR")
2589    St = ARM_AM::ror;
2590  else if (ShiftName == "rrx" || ShiftName == "RRX")
2591    St = ARM_AM::rrx;
2592  else
2593    return Error(Loc, "illegal shift operator");
2594  Parser.Lex(); // Eat shift type token.
2595
2596  // rrx stands alone.
2597  Amount = 0;
2598  if (St != ARM_AM::rrx) {
2599    Loc = Parser.getTok().getLoc();
2600    // A '#' and a shift amount.
2601    const AsmToken &HashTok = Parser.getTok();
2602    if (HashTok.isNot(AsmToken::Hash))
2603      return Error(HashTok.getLoc(), "'#' expected");
2604    Parser.Lex(); // Eat hash token.
2605
2606    const MCExpr *Expr;
2607    if (getParser().ParseExpression(Expr))
2608      return true;
2609    // Range check the immediate.
2610    // lsl, ror: 0 <= imm <= 31
2611    // lsr, asr: 0 <= imm <= 32
2612    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2613    if (!CE)
2614      return Error(Loc, "shift amount must be an immediate");
2615    int64_t Imm = CE->getValue();
2616    if (Imm < 0 ||
2617        ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
2618        ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
2619      return Error(Loc, "immediate shift value out of range");
2620    Amount = Imm;
2621  }
2622
2623  return false;
2624}
2625
2626/// Parse a arm instruction operand.  For now this parses the operand regardless
2627/// of the mnemonic.
2628bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
2629                                StringRef Mnemonic) {
2630  SMLoc S, E;
2631
2632  // Check if the current operand has a custom associated parser, if so, try to
2633  // custom parse the operand, or fallback to the general approach.
2634  OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
2635  if (ResTy == MatchOperand_Success)
2636    return false;
2637  // If there wasn't a custom match, try the generic matcher below. Otherwise,
2638  // there was a match, but an error occurred, in which case, just return that
2639  // the operand parsing failed.
2640  if (ResTy == MatchOperand_ParseFail)
2641    return true;
2642
2643  switch (getLexer().getKind()) {
2644  default:
2645    Error(Parser.getTok().getLoc(), "unexpected token in operand");
2646    return true;
2647  case AsmToken::Identifier: {
2648    if (!tryParseRegisterWithWriteBack(Operands))
2649      return false;
2650    int Res = tryParseShiftRegister(Operands);
2651    if (Res == 0) // success
2652      return false;
2653    else if (Res == -1) // irrecoverable error
2654      return true;
2655
2656    // Fall though for the Identifier case that is not a register or a
2657    // special name.
2658  }
2659  case AsmToken::Integer: // things like 1f and 2b as a branch targets
2660  case AsmToken::Dot: {   // . as a branch target
2661    // This was not a register so parse other operands that start with an
2662    // identifier (like labels) as expressions and create them as immediates.
2663    const MCExpr *IdVal;
2664    S = Parser.getTok().getLoc();
2665    if (getParser().ParseExpression(IdVal))
2666      return true;
2667    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2668    Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
2669    return false;
2670  }
2671  case AsmToken::LBrac:
2672    return parseMemory(Operands);
2673  case AsmToken::LCurly:
2674    return parseRegisterList(Operands);
2675  case AsmToken::Hash:
2676    // #42 -> immediate.
2677    // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
2678    S = Parser.getTok().getLoc();
2679    Parser.Lex();
2680    const MCExpr *ImmVal;
2681    if (getParser().ParseExpression(ImmVal))
2682      return true;
2683    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2684    Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
2685    return false;
2686  case AsmToken::Colon: {
2687    // ":lower16:" and ":upper16:" expression prefixes
2688    // FIXME: Check it's an expression prefix,
2689    // e.g. (FOO - :lower16:BAR) isn't legal.
2690    ARMMCExpr::VariantKind RefKind;
2691    if (parsePrefix(RefKind))
2692      return true;
2693
2694    const MCExpr *SubExprVal;
2695    if (getParser().ParseExpression(SubExprVal))
2696      return true;
2697
2698    const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
2699                                                   getContext());
2700    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2701    Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
2702    return false;
2703  }
2704  }
2705}
2706
2707// parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
2708//  :lower16: and :upper16:.
2709bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
2710  RefKind = ARMMCExpr::VK_ARM_None;
2711
2712  // :lower16: and :upper16: modifiers
2713  assert(getLexer().is(AsmToken::Colon) && "expected a :");
2714  Parser.Lex(); // Eat ':'
2715
2716  if (getLexer().isNot(AsmToken::Identifier)) {
2717    Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
2718    return true;
2719  }
2720
2721  StringRef IDVal = Parser.getTok().getIdentifier();
2722  if (IDVal == "lower16") {
2723    RefKind = ARMMCExpr::VK_ARM_LO16;
2724  } else if (IDVal == "upper16") {
2725    RefKind = ARMMCExpr::VK_ARM_HI16;
2726  } else {
2727    Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
2728    return true;
2729  }
2730  Parser.Lex();
2731
2732  if (getLexer().isNot(AsmToken::Colon)) {
2733    Error(Parser.getTok().getLoc(), "unexpected token after prefix");
2734    return true;
2735  }
2736  Parser.Lex(); // Eat the last ':'
2737  return false;
2738}
2739
2740const MCExpr *
2741ARMAsmParser::applyPrefixToExpr(const MCExpr *E,
2742                                MCSymbolRefExpr::VariantKind Variant) {
2743  // Recurse over the given expression, rebuilding it to apply the given variant
2744  // to the leftmost symbol.
2745  if (Variant == MCSymbolRefExpr::VK_None)
2746    return E;
2747
2748  switch (E->getKind()) {
2749  case MCExpr::Target:
2750    llvm_unreachable("Can't handle target expr yet");
2751  case MCExpr::Constant:
2752    llvm_unreachable("Can't handle lower16/upper16 of constant yet");
2753
2754  case MCExpr::SymbolRef: {
2755    const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
2756
2757    if (SRE->getKind() != MCSymbolRefExpr::VK_None)
2758      return 0;
2759
2760    return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, getContext());
2761  }
2762
2763  case MCExpr::Unary:
2764    llvm_unreachable("Can't handle unary expressions yet");
2765
2766  case MCExpr::Binary: {
2767    const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
2768    const MCExpr *LHS = applyPrefixToExpr(BE->getLHS(), Variant);
2769    const MCExpr *RHS = BE->getRHS();
2770    if (!LHS)
2771      return 0;
2772
2773    return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, getContext());
2774  }
2775  }
2776
2777  assert(0 && "Invalid expression kind!");
2778  return 0;
2779}
2780
2781/// \brief Given a mnemonic, split out possible predication code and carry
2782/// setting letters to form a canonical mnemonic and flags.
2783//
2784// FIXME: Would be nice to autogen this.
2785StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
2786                                      unsigned &PredicationCode,
2787                                      bool &CarrySetting,
2788                                      unsigned &ProcessorIMod) {
2789  PredicationCode = ARMCC::AL;
2790  CarrySetting = false;
2791  ProcessorIMod = 0;
2792
2793  // Ignore some mnemonics we know aren't predicated forms.
2794  //
2795  // FIXME: Would be nice to autogen this.
2796  if ((Mnemonic == "movs" && isThumb()) ||
2797      Mnemonic == "teq"   || Mnemonic == "vceq"   || Mnemonic == "svc"   ||
2798      Mnemonic == "mls"   || Mnemonic == "smmls"  || Mnemonic == "vcls"  ||
2799      Mnemonic == "vmls"  || Mnemonic == "vnmls"  || Mnemonic == "vacge" ||
2800      Mnemonic == "vcge"  || Mnemonic == "vclt"   || Mnemonic == "vacgt" ||
2801      Mnemonic == "vcgt"  || Mnemonic == "vcle"   || Mnemonic == "smlal" ||
2802      Mnemonic == "umaal" || Mnemonic == "umlal"  || Mnemonic == "vabal" ||
2803      Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal")
2804    return Mnemonic;
2805
2806  // First, split out any predication code. Ignore mnemonics we know aren't
2807  // predicated but do have a carry-set and so weren't caught above.
2808  if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
2809      Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
2810      Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
2811      Mnemonic != "sbcs") {
2812    unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
2813      .Case("eq", ARMCC::EQ)
2814      .Case("ne", ARMCC::NE)
2815      .Case("hs", ARMCC::HS)
2816      .Case("cs", ARMCC::HS)
2817      .Case("lo", ARMCC::LO)
2818      .Case("cc", ARMCC::LO)
2819      .Case("mi", ARMCC::MI)
2820      .Case("pl", ARMCC::PL)
2821      .Case("vs", ARMCC::VS)
2822      .Case("vc", ARMCC::VC)
2823      .Case("hi", ARMCC::HI)
2824      .Case("ls", ARMCC::LS)
2825      .Case("ge", ARMCC::GE)
2826      .Case("lt", ARMCC::LT)
2827      .Case("gt", ARMCC::GT)
2828      .Case("le", ARMCC::LE)
2829      .Case("al", ARMCC::AL)
2830      .Default(~0U);
2831    if (CC != ~0U) {
2832      Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
2833      PredicationCode = CC;
2834    }
2835  }
2836
2837  // Next, determine if we have a carry setting bit. We explicitly ignore all
2838  // the instructions we know end in 's'.
2839  if (Mnemonic.endswith("s") &&
2840      !(Mnemonic == "cps" || Mnemonic == "mls" ||
2841        Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
2842        Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
2843        Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
2844        Mnemonic == "vrsqrts" || Mnemonic == "srs" ||
2845        (Mnemonic == "movs" && isThumb()))) {
2846    Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
2847    CarrySetting = true;
2848  }
2849
2850  // The "cps" instruction can have a interrupt mode operand which is glued into
2851  // the mnemonic. Check if this is the case, split it and parse the imod op
2852  if (Mnemonic.startswith("cps")) {
2853    // Split out any imod code.
2854    unsigned IMod =
2855      StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
2856      .Case("ie", ARM_PROC::IE)
2857      .Case("id", ARM_PROC::ID)
2858      .Default(~0U);
2859    if (IMod != ~0U) {
2860      Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
2861      ProcessorIMod = IMod;
2862    }
2863  }
2864
2865  return Mnemonic;
2866}
2867
2868/// \brief Given a canonical mnemonic, determine if the instruction ever allows
2869/// inclusion of carry set or predication code operands.
2870//
2871// FIXME: It would be nice to autogen this.
2872void ARMAsmParser::
2873getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
2874                      bool &CanAcceptPredicationCode) {
2875  if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
2876      Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
2877      Mnemonic == "smull" || Mnemonic == "add" || Mnemonic == "adc" ||
2878      Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
2879      Mnemonic == "umlal" || Mnemonic == "orr" || Mnemonic == "mvn" ||
2880      Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
2881      Mnemonic == "sbc" || Mnemonic == "mla" || Mnemonic == "umull" ||
2882      Mnemonic == "eor" || Mnemonic == "smlal" || Mnemonic == "neg" ||
2883      // FIXME: We need a better way. This really confused Thumb2
2884      // parsing for 'mov'.
2885      (Mnemonic == "mov" && !isThumbOne())) {
2886    CanAcceptCarrySet = true;
2887  } else {
2888    CanAcceptCarrySet = false;
2889  }
2890
2891  if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
2892      Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
2893      Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
2894      Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
2895      Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "clrex" ||
2896      Mnemonic == "setend" ||
2897      (Mnemonic == "nop" && isThumbOne()) ||
2898      ((Mnemonic == "pld" || Mnemonic == "pli") && !isThumb()) ||
2899      ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs"))
2900        && !isThumb()) ||
2901      Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumb())) {
2902    CanAcceptPredicationCode = false;
2903  } else {
2904    CanAcceptPredicationCode = true;
2905  }
2906
2907  if (isThumb())
2908    if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
2909        Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
2910      CanAcceptPredicationCode = false;
2911}
2912
2913bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
2914                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2915
2916  // The 'mov' mnemonic is special. One variant has a cc_out operand, while
2917  // another does not. Specifically, the MOVW instruction does not. So we
2918  // special case it here and remove the defaulted (non-setting) cc_out
2919  // operand if that's the instruction we're trying to match.
2920  //
2921  // We do this as post-processing of the explicit operands rather than just
2922  // conditionally adding the cc_out in the first place because we need
2923  // to check the type of the parsed immediate operand.
2924  if (Mnemonic == "mov" && Operands.size() > 4 &&
2925      !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
2926      static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
2927      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
2928    return true;
2929
2930  // Register-register 'add' for thumb does not have a cc_out operand
2931  // when there are only two register operands.
2932  if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
2933      static_cast<ARMOperand*>(Operands[3])->isReg() &&
2934      static_cast<ARMOperand*>(Operands[4])->isReg() &&
2935      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
2936    return true;
2937  // Register-register 'add' for thumb does not have a cc_out operand
2938  // when it's an ADD Rdm, SP, {Rdm|#imm} instruction.
2939  if (isThumb() && Mnemonic == "add" && Operands.size() == 6 &&
2940      static_cast<ARMOperand*>(Operands[3])->isReg() &&
2941      static_cast<ARMOperand*>(Operands[4])->isReg() &&
2942      static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
2943      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
2944    return true;
2945  // Register-register 'add/sub' for thumb does not have a cc_out operand
2946  // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
2947  // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
2948  // right, this will result in better diagnostics (which operand is off)
2949  // anyway.
2950  if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
2951      (Operands.size() == 5 || Operands.size() == 6) &&
2952      static_cast<ARMOperand*>(Operands[3])->isReg() &&
2953      static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
2954      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
2955    return true;
2956
2957  return false;
2958}
2959
2960/// Parse an arm instruction mnemonic followed by its operands.
2961bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
2962                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2963  // Create the leading tokens for the mnemonic, split by '.' characters.
2964  size_t Start = 0, Next = Name.find('.');
2965  StringRef Mnemonic = Name.slice(Start, Next);
2966
2967  // Split out the predication code and carry setting flag from the mnemonic.
2968  unsigned PredicationCode;
2969  unsigned ProcessorIMod;
2970  bool CarrySetting;
2971  Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
2972                           ProcessorIMod);
2973
2974  // In Thumb1, only the branch (B) instruction can be predicated.
2975  if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
2976    Parser.EatToEndOfStatement();
2977    return Error(NameLoc, "conditional execution not supported in Thumb1");
2978  }
2979
2980  Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
2981
2982  // FIXME: This is all a pretty gross hack. We should automatically handle
2983  // optional operands like this via tblgen.
2984
2985  // Next, add the CCOut and ConditionCode operands, if needed.
2986  //
2987  // For mnemonics which can ever incorporate a carry setting bit or predication
2988  // code, our matching model involves us always generating CCOut and
2989  // ConditionCode operands to match the mnemonic "as written" and then we let
2990  // the matcher deal with finding the right instruction or generating an
2991  // appropriate error.
2992  bool CanAcceptCarrySet, CanAcceptPredicationCode;
2993  getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
2994
2995  // If we had a carry-set on an instruction that can't do that, issue an
2996  // error.
2997  if (!CanAcceptCarrySet && CarrySetting) {
2998    Parser.EatToEndOfStatement();
2999    return Error(NameLoc, "instruction '" + Mnemonic +
3000                 "' can not set flags, but 's' suffix specified");
3001  }
3002  // If we had a predication code on an instruction that can't do that, issue an
3003  // error.
3004  if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
3005    Parser.EatToEndOfStatement();
3006    return Error(NameLoc, "instruction '" + Mnemonic +
3007                 "' is not predicable, but condition code specified");
3008  }
3009
3010  // Add the carry setting operand, if necessary.
3011  //
3012  // FIXME: It would be awesome if we could somehow invent a location such that
3013  // match errors on this operand would print a nice diagnostic about how the
3014  // 's' character in the mnemonic resulted in a CCOut operand.
3015  if (CanAcceptCarrySet)
3016    Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
3017                                               NameLoc));
3018
3019  // Add the predication code operand, if necessary.
3020  if (CanAcceptPredicationCode) {
3021    Operands.push_back(ARMOperand::CreateCondCode(
3022                         ARMCC::CondCodes(PredicationCode), NameLoc));
3023  }
3024
3025  // Add the processor imod operand, if necessary.
3026  if (ProcessorIMod) {
3027    Operands.push_back(ARMOperand::CreateImm(
3028          MCConstantExpr::Create(ProcessorIMod, getContext()),
3029                                 NameLoc, NameLoc));
3030  } else {
3031    // This mnemonic can't ever accept a imod, but the user wrote
3032    // one (or misspelled another mnemonic).
3033
3034    // FIXME: Issue a nice error.
3035  }
3036
3037  // Add the remaining tokens in the mnemonic.
3038  while (Next != StringRef::npos) {
3039    Start = Next;
3040    Next = Name.find('.', Start + 1);
3041    StringRef ExtraToken = Name.slice(Start, Next);
3042
3043    // For now, we're only parsing Thumb1 (for the most part), so
3044    // just ignore ".n" qualifiers. We'll use them to restrict
3045    // matching when we do Thumb2.
3046    if (ExtraToken != ".n")
3047      Operands.push_back(ARMOperand::CreateToken(ExtraToken, NameLoc));
3048  }
3049
3050  // Read the remaining operands.
3051  if (getLexer().isNot(AsmToken::EndOfStatement)) {
3052    // Read the first operand.
3053    if (parseOperand(Operands, Mnemonic)) {
3054      Parser.EatToEndOfStatement();
3055      return true;
3056    }
3057
3058    while (getLexer().is(AsmToken::Comma)) {
3059      Parser.Lex();  // Eat the comma.
3060
3061      // Parse and remember the operand.
3062      if (parseOperand(Operands, Mnemonic)) {
3063        Parser.EatToEndOfStatement();
3064        return true;
3065      }
3066    }
3067  }
3068
3069  if (getLexer().isNot(AsmToken::EndOfStatement)) {
3070    Parser.EatToEndOfStatement();
3071    return TokError("unexpected token in argument list");
3072  }
3073
3074  Parser.Lex(); // Consume the EndOfStatement
3075
3076  // Some instructions, mostly Thumb, have forms for the same mnemonic that
3077  // do and don't have a cc_out optional-def operand. With some spot-checks
3078  // of the operand list, we can figure out which variant we're trying to
3079  // parse and adjust accordingly before actually matching. Reason number
3080  // #317 the table driven matcher doesn't fit well with the ARM instruction
3081  // set.
3082  if (shouldOmitCCOutOperand(Mnemonic, Operands)) {
3083    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
3084    Operands.erase(Operands.begin() + 1);
3085    delete Op;
3086  }
3087
3088  // ARM mode 'blx' need special handling, as the register operand version
3089  // is predicable, but the label operand version is not. So, we can't rely
3090  // on the Mnemonic based checking to correctly figure out when to put
3091  // a CondCode operand in the list. If we're trying to match the label
3092  // version, remove the CondCode operand here.
3093  if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
3094      static_cast<ARMOperand*>(Operands[2])->isImm()) {
3095    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
3096    Operands.erase(Operands.begin() + 1);
3097    delete Op;
3098  }
3099
3100  // The vector-compare-to-zero instructions have a literal token "#0" at
3101  // the end that comes to here as an immediate operand. Convert it to a
3102  // token to play nicely with the matcher.
3103  if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" ||
3104      Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 &&
3105      static_cast<ARMOperand*>(Operands[5])->isImm()) {
3106    ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
3107    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
3108    if (CE && CE->getValue() == 0) {
3109      Operands.erase(Operands.begin() + 5);
3110      Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
3111      delete Op;
3112    }
3113  }
3114  // Similarly, the Thumb1 "RSB" instruction has a literal "#0" on the
3115  // end. Convert it to a token here.
3116  if (Mnemonic == "rsb" && isThumb() && Operands.size() == 6 &&
3117      static_cast<ARMOperand*>(Operands[5])->isImm()) {
3118    ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
3119    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
3120    if (CE && CE->getValue() == 0) {
3121      Operands.erase(Operands.begin() + 5);
3122      Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
3123      delete Op;
3124    }
3125  }
3126
3127  return false;
3128}
3129
3130// Validate context-sensitive operand constraints.
3131
3132// return 'true' if register list contains non-low GPR registers,
3133// 'false' otherwise. If Reg is in the register list or is HiReg, set
3134// 'containsReg' to true.
3135static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
3136                                 unsigned HiReg, bool &containsReg) {
3137  containsReg = false;
3138  for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
3139    unsigned OpReg = Inst.getOperand(i).getReg();
3140    if (OpReg == Reg)
3141      containsReg = true;
3142    // Anything other than a low register isn't legal here.
3143    if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
3144      return true;
3145  }
3146  return false;
3147}
3148
3149// FIXME: We would really like to be able to tablegen'erate this.
3150bool ARMAsmParser::
3151validateInstruction(MCInst &Inst,
3152                    const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3153  switch (Inst.getOpcode()) {
3154  case ARM::LDRD:
3155  case ARM::LDRD_PRE:
3156  case ARM::LDRD_POST:
3157  case ARM::LDREXD: {
3158    // Rt2 must be Rt + 1.
3159    unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
3160    unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
3161    if (Rt2 != Rt + 1)
3162      return Error(Operands[3]->getStartLoc(),
3163                   "destination operands must be sequential");
3164    return false;
3165  }
3166  case ARM::STRD: {
3167    // Rt2 must be Rt + 1.
3168    unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
3169    unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
3170    if (Rt2 != Rt + 1)
3171      return Error(Operands[3]->getStartLoc(),
3172                   "source operands must be sequential");
3173    return false;
3174  }
3175  case ARM::STRD_PRE:
3176  case ARM::STRD_POST:
3177  case ARM::STREXD: {
3178    // Rt2 must be Rt + 1.
3179    unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg());
3180    unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(2).getReg());
3181    if (Rt2 != Rt + 1)
3182      return Error(Operands[3]->getStartLoc(),
3183                   "source operands must be sequential");
3184    return false;
3185  }
3186  case ARM::SBFX:
3187  case ARM::UBFX: {
3188    // width must be in range [1, 32-lsb]
3189    unsigned lsb = Inst.getOperand(2).getImm();
3190    unsigned widthm1 = Inst.getOperand(3).getImm();
3191    if (widthm1 >= 32 - lsb)
3192      return Error(Operands[5]->getStartLoc(),
3193                   "bitfield width must be in range [1,32-lsb]");
3194    return false;
3195  }
3196  case ARM::tLDMIA: {
3197    // Thumb LDM instructions are writeback iff the base register is not
3198    // in the register list.
3199    unsigned Rn = Inst.getOperand(0).getReg();
3200    bool hasWritebackToken =
3201      (static_cast<ARMOperand*>(Operands[3])->isToken() &&
3202       static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
3203    bool listContainsBase;
3204    if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase))
3205      return Error(Operands[3 + hasWritebackToken]->getStartLoc(),
3206                   "registers must be in range r0-r7");
3207    // If we should have writeback, then there should be a '!' token.
3208    if (!listContainsBase && !hasWritebackToken)
3209      return Error(Operands[2]->getStartLoc(),
3210                   "writeback operator '!' expected");
3211    // Likewise, if we should not have writeback, there must not be a '!'
3212    if (listContainsBase && hasWritebackToken)
3213      return Error(Operands[3]->getStartLoc(),
3214                   "writeback operator '!' not allowed when base register "
3215                   "in register list");
3216
3217    break;
3218  }
3219  case ARM::tPOP: {
3220    bool listContainsBase;
3221    if (checkLowRegisterList(Inst, 3, 0, ARM::PC, listContainsBase))
3222      return Error(Operands[2]->getStartLoc(),
3223                   "registers must be in range r0-r7 or pc");
3224    break;
3225  }
3226  case ARM::tPUSH: {
3227    bool listContainsBase;
3228    if (checkLowRegisterList(Inst, 3, 0, ARM::LR, listContainsBase))
3229      return Error(Operands[2]->getStartLoc(),
3230                   "registers must be in range r0-r7 or lr");
3231    break;
3232  }
3233  case ARM::tSTMIA_UPD: {
3234    bool listContainsBase;
3235    if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase))
3236      return Error(Operands[4]->getStartLoc(),
3237                   "registers must be in range r0-r7");
3238    break;
3239  }
3240  }
3241
3242  return false;
3243}
3244
3245void ARMAsmParser::
3246processInstruction(MCInst &Inst,
3247                   const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3248  switch (Inst.getOpcode()) {
3249  case ARM::LDMIA_UPD:
3250    // If this is a load of a single register via a 'pop', then we should use
3251    // a post-indexed LDR instruction instead, per the ARM ARM.
3252    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
3253        Inst.getNumOperands() == 5) {
3254      MCInst TmpInst;
3255      TmpInst.setOpcode(ARM::LDR_POST_IMM);
3256      TmpInst.addOperand(Inst.getOperand(4)); // Rt
3257      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
3258      TmpInst.addOperand(Inst.getOperand(1)); // Rn
3259      TmpInst.addOperand(MCOperand::CreateReg(0));  // am2offset
3260      TmpInst.addOperand(MCOperand::CreateImm(4));
3261      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
3262      TmpInst.addOperand(Inst.getOperand(3));
3263      Inst = TmpInst;
3264    }
3265    break;
3266  case ARM::STMDB_UPD:
3267    // If this is a store of a single register via a 'push', then we should use
3268    // a pre-indexed STR instruction instead, per the ARM ARM.
3269    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
3270        Inst.getNumOperands() == 5) {
3271      MCInst TmpInst;
3272      TmpInst.setOpcode(ARM::STR_PRE_IMM);
3273      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
3274      TmpInst.addOperand(Inst.getOperand(4)); // Rt
3275      TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
3276      TmpInst.addOperand(MCOperand::CreateImm(-4));
3277      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
3278      TmpInst.addOperand(Inst.getOperand(3));
3279      Inst = TmpInst;
3280    }
3281    break;
3282  case ARM::tADDi8:
3283    // If the immediate is in the range 0-7, we really wanted tADDi3.
3284    if (Inst.getOperand(3).getImm() < 8)
3285      Inst.setOpcode(ARM::tADDi3);
3286    break;
3287  case ARM::tBcc:
3288    // If the conditional is AL, we really want tB.
3289    if (Inst.getOperand(1).getImm() == ARMCC::AL)
3290      Inst.setOpcode(ARM::tB);
3291    break;
3292  }
3293}
3294
3295// FIXME: We would really prefer to have MCInstrInfo (the wrapper around
3296// the ARMInsts array) instead. Getting that here requires awkward
3297// API changes, though. Better way?
3298namespace llvm {
3299extern MCInstrDesc ARMInsts[];
3300}
3301static MCInstrDesc &getInstDesc(unsigned Opcode) {
3302  return ARMInsts[Opcode];
3303}
3304
3305unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
3306  // 16-bit thumb arithmetic instructions either require or preclude the 'S'
3307  // suffix depending on whether they're in an IT block or not.
3308  unsigned Opc = Inst.getOpcode();
3309  MCInstrDesc &MCID = getInstDesc(Opc);
3310  if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
3311    assert(MCID.hasOptionalDef() &&
3312           "optionally flag setting instruction missing optional def operand");
3313    assert(MCID.NumOperands == Inst.getNumOperands() &&
3314           "operand count mismatch!");
3315    // Find the optional-def operand (cc_out).
3316    unsigned OpNo;
3317    for (OpNo = 0;
3318         !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
3319         ++OpNo)
3320      ;
3321    // If we're parsing Thumb1, reject it completely.
3322    if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
3323      return Match_MnemonicFail;
3324    // If we're parsing Thumb2, which form is legal depends on whether we're
3325    // in an IT block.
3326    // FIXME: We don't yet do IT blocks, so just always consider it to be
3327    // that we aren't in one until we do.
3328    if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
3329      return Match_RequiresITBlock;
3330  }
3331  // Some high-register supporting Thumb1 encodings only allow both registers
3332  // to be from r0-r7 when in Thumb2.
3333  else if (Opc == ARM::tADDhirr && isThumbOne() &&
3334           isARMLowRegister(Inst.getOperand(1).getReg()) &&
3335           isARMLowRegister(Inst.getOperand(2).getReg()))
3336    return Match_RequiresThumb2;
3337  // Others only require ARMv6 or later.
3338  else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
3339           isARMLowRegister(Inst.getOperand(0).getReg()) &&
3340           isARMLowRegister(Inst.getOperand(1).getReg()))
3341    return Match_RequiresV6;
3342  return Match_Success;
3343}
3344
3345bool ARMAsmParser::
3346MatchAndEmitInstruction(SMLoc IDLoc,
3347                        SmallVectorImpl<MCParsedAsmOperand*> &Operands,
3348                        MCStreamer &Out) {
3349  MCInst Inst;
3350  unsigned ErrorInfo;
3351  unsigned MatchResult;
3352  MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo);
3353  switch (MatchResult) {
3354  default: break;
3355  case Match_Success:
3356    // Context sensitive operand constraints aren't handled by the matcher,
3357    // so check them here.
3358    if (validateInstruction(Inst, Operands))
3359      return true;
3360
3361    // Some instructions need post-processing to, for example, tweak which
3362    // encoding is selected.
3363    processInstruction(Inst, Operands);
3364
3365    Out.EmitInstruction(Inst);
3366    return false;
3367  case Match_MissingFeature:
3368    Error(IDLoc, "instruction requires a CPU feature not currently enabled");
3369    return true;
3370  case Match_InvalidOperand: {
3371    SMLoc ErrorLoc = IDLoc;
3372    if (ErrorInfo != ~0U) {
3373      if (ErrorInfo >= Operands.size())
3374        return Error(IDLoc, "too few operands for instruction");
3375
3376      ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
3377      if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
3378    }
3379
3380    return Error(ErrorLoc, "invalid operand for instruction");
3381  }
3382  case Match_MnemonicFail:
3383    return Error(IDLoc, "invalid instruction");
3384  case Match_ConversionFail:
3385    // The converter function will have already emited a diagnostic.
3386    return true;
3387  case Match_RequiresITBlock:
3388    return Error(IDLoc, "instruction only valid inside IT block");
3389  case Match_RequiresV6:
3390    return Error(IDLoc, "instruction variant requires ARMv6 or later");
3391  case Match_RequiresThumb2:
3392    return Error(IDLoc, "instruction variant requires Thumb2");
3393  }
3394
3395  llvm_unreachable("Implement any new match types added!");
3396  return true;
3397}
3398
3399/// parseDirective parses the arm specific directives
3400bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
3401  StringRef IDVal = DirectiveID.getIdentifier();
3402  if (IDVal == ".word")
3403    return parseDirectiveWord(4, DirectiveID.getLoc());
3404  else if (IDVal == ".thumb")
3405    return parseDirectiveThumb(DirectiveID.getLoc());
3406  else if (IDVal == ".thumb_func")
3407    return parseDirectiveThumbFunc(DirectiveID.getLoc());
3408  else if (IDVal == ".code")
3409    return parseDirectiveCode(DirectiveID.getLoc());
3410  else if (IDVal == ".syntax")
3411    return parseDirectiveSyntax(DirectiveID.getLoc());
3412  return true;
3413}
3414
3415/// parseDirectiveWord
3416///  ::= .word [ expression (, expression)* ]
3417bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
3418  if (getLexer().isNot(AsmToken::EndOfStatement)) {
3419    for (;;) {
3420      const MCExpr *Value;
3421      if (getParser().ParseExpression(Value))
3422        return true;
3423
3424      getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
3425
3426      if (getLexer().is(AsmToken::EndOfStatement))
3427        break;
3428
3429      // FIXME: Improve diagnostic.
3430      if (getLexer().isNot(AsmToken::Comma))
3431        return Error(L, "unexpected token in directive");
3432      Parser.Lex();
3433    }
3434  }
3435
3436  Parser.Lex();
3437  return false;
3438}
3439
3440/// parseDirectiveThumb
3441///  ::= .thumb
3442bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
3443  if (getLexer().isNot(AsmToken::EndOfStatement))
3444    return Error(L, "unexpected token in directive");
3445  Parser.Lex();
3446
3447  // TODO: set thumb mode
3448  // TODO: tell the MC streamer the mode
3449  // getParser().getStreamer().Emit???();
3450  return false;
3451}
3452
3453/// parseDirectiveThumbFunc
3454///  ::= .thumbfunc symbol_name
3455bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
3456  const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
3457  bool isMachO = MAI.hasSubsectionsViaSymbols();
3458  StringRef Name;
3459
3460  // Darwin asm has function name after .thumb_func direction
3461  // ELF doesn't
3462  if (isMachO) {
3463    const AsmToken &Tok = Parser.getTok();
3464    if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
3465      return Error(L, "unexpected token in .thumb_func directive");
3466    Name = Tok.getString();
3467    Parser.Lex(); // Consume the identifier token.
3468  }
3469
3470  if (getLexer().isNot(AsmToken::EndOfStatement))
3471    return Error(L, "unexpected token in directive");
3472  Parser.Lex();
3473
3474  // FIXME: assuming function name will be the line following .thumb_func
3475  if (!isMachO) {
3476    Name = Parser.getTok().getString();
3477  }
3478
3479  // Mark symbol as a thumb symbol.
3480  MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
3481  getParser().getStreamer().EmitThumbFunc(Func);
3482  return false;
3483}
3484
3485/// parseDirectiveSyntax
3486///  ::= .syntax unified | divided
3487bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
3488  const AsmToken &Tok = Parser.getTok();
3489  if (Tok.isNot(AsmToken::Identifier))
3490    return Error(L, "unexpected token in .syntax directive");
3491  StringRef Mode = Tok.getString();
3492  if (Mode == "unified" || Mode == "UNIFIED")
3493    Parser.Lex();
3494  else if (Mode == "divided" || Mode == "DIVIDED")
3495    return Error(L, "'.syntax divided' arm asssembly not supported");
3496  else
3497    return Error(L, "unrecognized syntax mode in .syntax directive");
3498
3499  if (getLexer().isNot(AsmToken::EndOfStatement))
3500    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
3501  Parser.Lex();
3502
3503  // TODO tell the MC streamer the mode
3504  // getParser().getStreamer().Emit???();
3505  return false;
3506}
3507
3508/// parseDirectiveCode
3509///  ::= .code 16 | 32
3510bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
3511  const AsmToken &Tok = Parser.getTok();
3512  if (Tok.isNot(AsmToken::Integer))
3513    return Error(L, "unexpected token in .code directive");
3514  int64_t Val = Parser.getTok().getIntVal();
3515  if (Val == 16)
3516    Parser.Lex();
3517  else if (Val == 32)
3518    Parser.Lex();
3519  else
3520    return Error(L, "invalid operand to .code directive");
3521
3522  if (getLexer().isNot(AsmToken::EndOfStatement))
3523    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
3524  Parser.Lex();
3525
3526  if (Val == 16) {
3527    if (!isThumb()) {
3528      SwitchMode();
3529      getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
3530    }
3531  } else {
3532    if (isThumb()) {
3533      SwitchMode();
3534      getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
3535    }
3536  }
3537
3538  return false;
3539}
3540
3541extern "C" void LLVMInitializeARMAsmLexer();
3542
3543/// Force static initialization.
3544extern "C" void LLVMInitializeARMAsmParser() {
3545  RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
3546  RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
3547  LLVMInitializeARMAsmLexer();
3548}
3549
3550#define GET_REGISTER_MATCHER
3551#define GET_MATCHER_IMPLEMENTATION
3552#include "ARMGenAsmMatcher.inc"
3553