ARMAsmParser.cpp revision c19bd321362166805194cbaf170e06a4790d2da9 
1//===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "llvm/MC/MCTargetAsmParser.h"
11#include "MCTargetDesc/ARMAddressingModes.h"
12#include "MCTargetDesc/ARMBaseInfo.h"
13#include "MCTargetDesc/ARMMCExpr.h"
14#include "llvm/ADT/BitVector.h"
15#include "llvm/ADT/OwningPtr.h"
16#include "llvm/ADT/STLExtras.h"
17#include "llvm/ADT/SmallVector.h"
18#include "llvm/ADT/StringSwitch.h"
19#include "llvm/ADT/Twine.h"
20#include "llvm/MC/MCAsmInfo.h"
21#include "llvm/MC/MCAssembler.h"
22#include "llvm/MC/MCContext.h"
23#include "llvm/MC/MCELFStreamer.h"
24#include "llvm/MC/MCExpr.h"
25#include "llvm/MC/MCInst.h"
26#include "llvm/MC/MCInstrDesc.h"
27#include "llvm/MC/MCParser/MCAsmLexer.h"
28#include "llvm/MC/MCParser/MCAsmParser.h"
29#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
30#include "llvm/MC/MCRegisterInfo.h"
31#include "llvm/MC/MCStreamer.h"
32#include "llvm/MC/MCSubtargetInfo.h"
33#include "llvm/Support/ELF.h"
34#include "llvm/Support/MathExtras.h"
35#include "llvm/Support/SourceMgr.h"
36#include "llvm/Support/TargetRegistry.h"
37#include "llvm/Support/raw_ostream.h"
38
39using namespace llvm;
40
41namespace {
42
43class ARMOperand;
44
45enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
46
47class ARMAsmParser : public MCTargetAsmParser {
48  MCSubtargetInfo &STI;
49  MCAsmParser &Parser;
50  const MCRegisterInfo *MRI;
51
52  // Unwind directives state
53  SMLoc FnStartLoc;
54  SMLoc CantUnwindLoc;
55  SMLoc PersonalityLoc;
56  SMLoc HandlerDataLoc;
57  int FPReg;
58  void resetUnwindDirectiveParserState() {
59    FnStartLoc = SMLoc();
60    CantUnwindLoc = SMLoc();
61    PersonalityLoc = SMLoc();
62    HandlerDataLoc = SMLoc();
63    FPReg = -1;
64  }
65
66  // Map of register aliases registers via the .req directive.
67  StringMap<unsigned> RegisterReqs;
68
69  struct {
70    ARMCC::CondCodes Cond;    // Condition for IT block.
71    unsigned Mask:4;          // Condition mask for instructions.
72                              // Starting at first 1 (from lsb).
73                              //   '1'  condition as indicated in IT.
74                              //   '0'  inverse of condition (else).
75                              // Count of instructions in IT block is
76                              // 4 - trailingzeroes(mask)
77
78    bool FirstCond;           // Explicit flag for when we're parsing the
79                              // First instruction in the IT block. It's
80                              // implied in the mask, so needs special
81                              // handling.
82
83    unsigned CurPosition;     // Current position in parsing of IT
84                              // block. In range [0,3]. Initialized
85                              // according to count of instructions in block.
86                              // ~0U if no active IT block.
87  } ITState;
88  bool inITBlock() { return ITState.CurPosition != ~0U;}
89  void forwardITPosition() {
90    if (!inITBlock()) return;
91    // Move to the next instruction in the IT block, if there is one. If not,
92    // mark the block as done.
93    unsigned TZ = countTrailingZeros(ITState.Mask);
94    if (++ITState.CurPosition == 5 - TZ)
95      ITState.CurPosition = ~0U; // Done with the IT block after this.
96  }
97
98
99  MCAsmParser &getParser() const { return Parser; }
100  MCAsmLexer &getLexer() const { return Parser.getLexer(); }
101
102  bool Warning(SMLoc L, const Twine &Msg,
103               ArrayRef<SMRange> Ranges = None) {
104    return Parser.Warning(L, Msg, Ranges);
105  }
106  bool Error(SMLoc L, const Twine &Msg,
107             ArrayRef<SMRange> Ranges = None) {
108    return Parser.Error(L, Msg, Ranges);
109  }
110
111  int tryParseRegister();
112  bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
113  int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
114  bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
115  bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
116  bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
117  bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
118  bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
119                              unsigned &ShiftAmount);
120  bool parseDirectiveWord(unsigned Size, SMLoc L);
121  bool parseDirectiveThumb(SMLoc L);
122  bool parseDirectiveARM(SMLoc L);
123  bool parseDirectiveThumbFunc(SMLoc L);
124  bool parseDirectiveCode(SMLoc L);
125  bool parseDirectiveSyntax(SMLoc L);
126  bool parseDirectiveReq(StringRef Name, SMLoc L);
127  bool parseDirectiveUnreq(SMLoc L);
128  bool parseDirectiveArch(SMLoc L);
129  bool parseDirectiveEabiAttr(SMLoc L);
130  bool parseDirectiveFnStart(SMLoc L);
131  bool parseDirectiveFnEnd(SMLoc L);
132  bool parseDirectiveCantUnwind(SMLoc L);
133  bool parseDirectivePersonality(SMLoc L);
134  bool parseDirectiveHandlerData(SMLoc L);
135  bool parseDirectiveSetFP(SMLoc L);
136  bool parseDirectivePad(SMLoc L);
137  bool parseDirectiveRegSave(SMLoc L, bool IsVector);
138
139  StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
140                          bool &CarrySetting, unsigned &ProcessorIMod,
141                          StringRef &ITMask);
142  void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
143                             bool &CanAcceptPredicationCode);
144
145  bool isThumb() const {
146    // FIXME: Can tablegen auto-generate this?
147    return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
148  }
149  bool isThumbOne() const {
150    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
151  }
152  bool isThumbTwo() const {
153    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
154  }
155  bool hasThumb() const {
156    return STI.getFeatureBits() & ARM::HasV4TOps;
157  }
158  bool hasV6Ops() const {
159    return STI.getFeatureBits() & ARM::HasV6Ops;
160  }
161  bool hasV7Ops() const {
162    return STI.getFeatureBits() & ARM::HasV7Ops;
163  }
164  bool hasARM() const {
165    return !(STI.getFeatureBits() & ARM::FeatureNoARM);
166  }
167
168  void SwitchMode() {
169    unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
170    setAvailableFeatures(FB);
171  }
172  bool isMClass() const {
173    return STI.getFeatureBits() & ARM::FeatureMClass;
174  }
175
176  /// @name Auto-generated Match Functions
177  /// {
178
179#define GET_ASSEMBLER_HEADER
180#include "ARMGenAsmMatcher.inc"
181
182  /// }
183
184  OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
185  OperandMatchResultTy parseCoprocNumOperand(
186    SmallVectorImpl<MCParsedAsmOperand*>&);
187  OperandMatchResultTy parseCoprocRegOperand(
188    SmallVectorImpl<MCParsedAsmOperand*>&);
189  OperandMatchResultTy parseCoprocOptionOperand(
190    SmallVectorImpl<MCParsedAsmOperand*>&);
191  OperandMatchResultTy parseMemBarrierOptOperand(
192    SmallVectorImpl<MCParsedAsmOperand*>&);
193  OperandMatchResultTy parseInstSyncBarrierOptOperand(
194    SmallVectorImpl<MCParsedAsmOperand*>&);
195  OperandMatchResultTy parseProcIFlagsOperand(
196    SmallVectorImpl<MCParsedAsmOperand*>&);
197  OperandMatchResultTy parseMSRMaskOperand(
198    SmallVectorImpl<MCParsedAsmOperand*>&);
199  OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
200                                   StringRef Op, int Low, int High);
201  OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
202    return parsePKHImm(O, "lsl", 0, 31);
203  }
204  OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
205    return parsePKHImm(O, "asr", 1, 32);
206  }
207  OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
208  OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
209  OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
210  OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
211  OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
212  OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
213  OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&);
214  OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&);
215  OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
216                                       SMLoc &EndLoc);
217
218  // Asm Match Converter Methods
219  void cvtT2LdrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &);
220  void cvtT2StrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &);
221  void cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst,
222                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
223  void cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst,
224                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
225  void cvtLdWriteBackRegAddrMode2(MCInst &Inst,
226                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
227  void cvtLdWriteBackRegAddrModeImm12(MCInst &Inst,
228                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
229  void cvtStWriteBackRegAddrModeImm12(MCInst &Inst,
230                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
231  void cvtStWriteBackRegAddrMode2(MCInst &Inst,
232                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
233  void cvtStWriteBackRegAddrMode3(MCInst &Inst,
234                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
235  void cvtLdExtTWriteBackImm(MCInst &Inst,
236                             const SmallVectorImpl<MCParsedAsmOperand*> &);
237  void cvtLdExtTWriteBackReg(MCInst &Inst,
238                             const SmallVectorImpl<MCParsedAsmOperand*> &);
239  void cvtStExtTWriteBackImm(MCInst &Inst,
240                             const SmallVectorImpl<MCParsedAsmOperand*> &);
241  void cvtStExtTWriteBackReg(MCInst &Inst,
242                             const SmallVectorImpl<MCParsedAsmOperand*> &);
243  void cvtLdrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &);
244  void cvtStrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &);
245  void cvtLdWriteBackRegAddrMode3(MCInst &Inst,
246                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
247  void cvtThumbMultiply(MCInst &Inst,
248                        const SmallVectorImpl<MCParsedAsmOperand*> &);
249  void cvtVLDwbFixed(MCInst &Inst,
250                     const SmallVectorImpl<MCParsedAsmOperand*> &);
251  void cvtVLDwbRegister(MCInst &Inst,
252                        const SmallVectorImpl<MCParsedAsmOperand*> &);
253  void cvtVSTwbFixed(MCInst &Inst,
254                     const SmallVectorImpl<MCParsedAsmOperand*> &);
255  void cvtVSTwbRegister(MCInst &Inst,
256                        const SmallVectorImpl<MCParsedAsmOperand*> &);
257  bool validateInstruction(MCInst &Inst,
258                           const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
259  bool processInstruction(MCInst &Inst,
260                          const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
261  bool shouldOmitCCOutOperand(StringRef Mnemonic,
262                              SmallVectorImpl<MCParsedAsmOperand*> &Operands);
263
264public:
265  enum ARMMatchResultTy {
266    Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
267    Match_RequiresNotITBlock,
268    Match_RequiresV6,
269    Match_RequiresThumb2,
270#define GET_OPERAND_DIAGNOSTIC_TYPES
271#include "ARMGenAsmMatcher.inc"
272
273  };
274
275  ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
276    : MCTargetAsmParser(), STI(_STI), Parser(_Parser), FPReg(-1) {
277    MCAsmParserExtension::Initialize(_Parser);
278
279    // Cache the MCRegisterInfo.
280    MRI = getContext().getRegisterInfo();
281
282    // Initialize the set of available features.
283    setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
284
285    // Not in an ITBlock to start with.
286    ITState.CurPosition = ~0U;
287
288    // Set ELF header flags.
289    // FIXME: This should eventually end up somewhere else where more
290    // intelligent flag decisions can be made. For now we are just maintaining
291    // the statu/parseDirects quo for ARM and setting EF_ARM_EABI_VER5 as the default.
292    if (MCELFStreamer *MES = dyn_cast<MCELFStreamer>(&Parser.getStreamer()))
293      MES->getAssembler().setELFHeaderEFlags(ELF::EF_ARM_EABI_VER5);
294  }
295
296  // Implementation of the MCTargetAsmParser interface:
297  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
298  bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
299                        SMLoc NameLoc,
300                        SmallVectorImpl<MCParsedAsmOperand*> &Operands);
301  bool ParseDirective(AsmToken DirectiveID);
302
303  unsigned validateTargetOperandClass(MCParsedAsmOperand *Op, unsigned Kind);
304  unsigned checkTargetMatchPredicate(MCInst &Inst);
305
306  bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
307                               SmallVectorImpl<MCParsedAsmOperand*> &Operands,
308                               MCStreamer &Out, unsigned &ErrorInfo,
309                               bool MatchingInlineAsm);
310};
311} // end anonymous namespace
312
313namespace {
314
315/// ARMOperand - Instances of this class represent a parsed ARM machine
316/// operand.
317class ARMOperand : public MCParsedAsmOperand {
318  enum KindTy {
319    k_CondCode,
320    k_CCOut,
321    k_ITCondMask,
322    k_CoprocNum,
323    k_CoprocReg,
324    k_CoprocOption,
325    k_Immediate,
326    k_MemBarrierOpt,
327    k_InstSyncBarrierOpt,
328    k_Memory,
329    k_PostIndexRegister,
330    k_MSRMask,
331    k_ProcIFlags,
332    k_VectorIndex,
333    k_Register,
334    k_RegisterList,
335    k_DPRRegisterList,
336    k_SPRRegisterList,
337    k_VectorList,
338    k_VectorListAllLanes,
339    k_VectorListIndexed,
340    k_ShiftedRegister,
341    k_ShiftedImmediate,
342    k_ShifterImmediate,
343    k_RotateImmediate,
344    k_BitfieldDescriptor,
345    k_Token
346  } Kind;
347
348  SMLoc StartLoc, EndLoc;
349  SmallVector<unsigned, 8> Registers;
350
351  struct CCOp {
352    ARMCC::CondCodes Val;
353  };
354
355  struct CopOp {
356    unsigned Val;
357  };
358
359  struct CoprocOptionOp {
360    unsigned Val;
361  };
362
363  struct ITMaskOp {
364    unsigned Mask:4;
365  };
366
367  struct MBOptOp {
368    ARM_MB::MemBOpt Val;
369  };
370
371  struct ISBOptOp {
372    ARM_ISB::InstSyncBOpt Val;
373  };
374
375  struct IFlagsOp {
376    ARM_PROC::IFlags Val;
377  };
378
379  struct MMaskOp {
380    unsigned Val;
381  };
382
383  struct TokOp {
384    const char *Data;
385    unsigned Length;
386  };
387
388  struct RegOp {
389    unsigned RegNum;
390  };
391
392  // A vector register list is a sequential list of 1 to 4 registers.
393  struct VectorListOp {
394    unsigned RegNum;
395    unsigned Count;
396    unsigned LaneIndex;
397    bool isDoubleSpaced;
398  };
399
400  struct VectorIndexOp {
401    unsigned Val;
402  };
403
404  struct ImmOp {
405    const MCExpr *Val;
406  };
407
408  /// Combined record for all forms of ARM address expressions.
409  struct MemoryOp {
410    unsigned BaseRegNum;
411    // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
412    // was specified.
413    const MCConstantExpr *OffsetImm;  // Offset immediate value
414    unsigned OffsetRegNum;    // Offset register num, when OffsetImm == NULL
415    ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
416    unsigned ShiftImm;        // shift for OffsetReg.
417    unsigned Alignment;       // 0 = no alignment specified
418    // n = alignment in bytes (2, 4, 8, 16, or 32)
419    unsigned isNegative : 1;  // Negated OffsetReg? (~'U' bit)
420  };
421
422  struct PostIdxRegOp {
423    unsigned RegNum;
424    bool isAdd;
425    ARM_AM::ShiftOpc ShiftTy;
426    unsigned ShiftImm;
427  };
428
429  struct ShifterImmOp {
430    bool isASR;
431    unsigned Imm;
432  };
433
434  struct RegShiftedRegOp {
435    ARM_AM::ShiftOpc ShiftTy;
436    unsigned SrcReg;
437    unsigned ShiftReg;
438    unsigned ShiftImm;
439  };
440
441  struct RegShiftedImmOp {
442    ARM_AM::ShiftOpc ShiftTy;
443    unsigned SrcReg;
444    unsigned ShiftImm;
445  };
446
447  struct RotImmOp {
448    unsigned Imm;
449  };
450
451  struct BitfieldOp {
452    unsigned LSB;
453    unsigned Width;
454  };
455
456  union {
457    struct CCOp CC;
458    struct CopOp Cop;
459    struct CoprocOptionOp CoprocOption;
460    struct MBOptOp MBOpt;
461    struct ISBOptOp ISBOpt;
462    struct ITMaskOp ITMask;
463    struct IFlagsOp IFlags;
464    struct MMaskOp MMask;
465    struct TokOp Tok;
466    struct RegOp Reg;
467    struct VectorListOp VectorList;
468    struct VectorIndexOp VectorIndex;
469    struct ImmOp Imm;
470    struct MemoryOp Memory;
471    struct PostIdxRegOp PostIdxReg;
472    struct ShifterImmOp ShifterImm;
473    struct RegShiftedRegOp RegShiftedReg;
474    struct RegShiftedImmOp RegShiftedImm;
475    struct RotImmOp RotImm;
476    struct BitfieldOp Bitfield;
477  };
478
479  ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
480public:
481  ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
482    Kind = o.Kind;
483    StartLoc = o.StartLoc;
484    EndLoc = o.EndLoc;
485    switch (Kind) {
486    case k_CondCode:
487      CC = o.CC;
488      break;
489    case k_ITCondMask:
490      ITMask = o.ITMask;
491      break;
492    case k_Token:
493      Tok = o.Tok;
494      break;
495    case k_CCOut:
496    case k_Register:
497      Reg = o.Reg;
498      break;
499    case k_RegisterList:
500    case k_DPRRegisterList:
501    case k_SPRRegisterList:
502      Registers = o.Registers;
503      break;
504    case k_VectorList:
505    case k_VectorListAllLanes:
506    case k_VectorListIndexed:
507      VectorList = o.VectorList;
508      break;
509    case k_CoprocNum:
510    case k_CoprocReg:
511      Cop = o.Cop;
512      break;
513    case k_CoprocOption:
514      CoprocOption = o.CoprocOption;
515      break;
516    case k_Immediate:
517      Imm = o.Imm;
518      break;
519    case k_MemBarrierOpt:
520      MBOpt = o.MBOpt;
521      break;
522    case k_InstSyncBarrierOpt:
523      ISBOpt = o.ISBOpt;
524    case k_Memory:
525      Memory = o.Memory;
526      break;
527    case k_PostIndexRegister:
528      PostIdxReg = o.PostIdxReg;
529      break;
530    case k_MSRMask:
531      MMask = o.MMask;
532      break;
533    case k_ProcIFlags:
534      IFlags = o.IFlags;
535      break;
536    case k_ShifterImmediate:
537      ShifterImm = o.ShifterImm;
538      break;
539    case k_ShiftedRegister:
540      RegShiftedReg = o.RegShiftedReg;
541      break;
542    case k_ShiftedImmediate:
543      RegShiftedImm = o.RegShiftedImm;
544      break;
545    case k_RotateImmediate:
546      RotImm = o.RotImm;
547      break;
548    case k_BitfieldDescriptor:
549      Bitfield = o.Bitfield;
550      break;
551    case k_VectorIndex:
552      VectorIndex = o.VectorIndex;
553      break;
554    }
555  }
556
557  /// getStartLoc - Get the location of the first token of this operand.
558  SMLoc getStartLoc() const { return StartLoc; }
559  /// getEndLoc - Get the location of the last token of this operand.
560  SMLoc getEndLoc() const { return EndLoc; }
561  /// getLocRange - Get the range between the first and last token of this
562  /// operand.
563  SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
564
565  ARMCC::CondCodes getCondCode() const {
566    assert(Kind == k_CondCode && "Invalid access!");
567    return CC.Val;
568  }
569
570  unsigned getCoproc() const {
571    assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
572    return Cop.Val;
573  }
574
575  StringRef getToken() const {
576    assert(Kind == k_Token && "Invalid access!");
577    return StringRef(Tok.Data, Tok.Length);
578  }
579
580  unsigned getReg() const {
581    assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
582    return Reg.RegNum;
583  }
584
585  const SmallVectorImpl<unsigned> &getRegList() const {
586    assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
587            Kind == k_SPRRegisterList) && "Invalid access!");
588    return Registers;
589  }
590
591  const MCExpr *getImm() const {
592    assert(isImm() && "Invalid access!");
593    return Imm.Val;
594  }
595
596  unsigned getVectorIndex() const {
597    assert(Kind == k_VectorIndex && "Invalid access!");
598    return VectorIndex.Val;
599  }
600
601  ARM_MB::MemBOpt getMemBarrierOpt() const {
602    assert(Kind == k_MemBarrierOpt && "Invalid access!");
603    return MBOpt.Val;
604  }
605
606  ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const {
607    assert(Kind == k_InstSyncBarrierOpt && "Invalid access!");
608    return ISBOpt.Val;
609  }
610
611  ARM_PROC::IFlags getProcIFlags() const {
612    assert(Kind == k_ProcIFlags && "Invalid access!");
613    return IFlags.Val;
614  }
615
616  unsigned getMSRMask() const {
617    assert(Kind == k_MSRMask && "Invalid access!");
618    return MMask.Val;
619  }
620
621  bool isCoprocNum() const { return Kind == k_CoprocNum; }
622  bool isCoprocReg() const { return Kind == k_CoprocReg; }
623  bool isCoprocOption() const { return Kind == k_CoprocOption; }
624  bool isCondCode() const { return Kind == k_CondCode; }
625  bool isCCOut() const { return Kind == k_CCOut; }
626  bool isITMask() const { return Kind == k_ITCondMask; }
627  bool isITCondCode() const { return Kind == k_CondCode; }
628  bool isImm() const { return Kind == k_Immediate; }
629  bool isFPImm() const {
630    if (!isImm()) return false;
631    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
632    if (!CE) return false;
633    int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
634    return Val != -1;
635  }
636  bool isFBits16() const {
637    if (!isImm()) return false;
638    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
639    if (!CE) return false;
640    int64_t Value = CE->getValue();
641    return Value >= 0 && Value <= 16;
642  }
643  bool isFBits32() const {
644    if (!isImm()) return false;
645    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
646    if (!CE) return false;
647    int64_t Value = CE->getValue();
648    return Value >= 1 && Value <= 32;
649  }
650  bool isImm8s4() const {
651    if (!isImm()) return false;
652    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
653    if (!CE) return false;
654    int64_t Value = CE->getValue();
655    return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
656  }
657  bool isImm0_4() const {
658    if (!isImm()) return false;
659    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
660    if (!CE) return false;
661    int64_t Value = CE->getValue();
662    return Value >= 0 && Value < 5;
663  }
664  bool isImm0_1020s4() const {
665    if (!isImm()) return false;
666    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
667    if (!CE) return false;
668    int64_t Value = CE->getValue();
669    return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
670  }
671  bool isImm0_508s4() const {
672    if (!isImm()) return false;
673    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
674    if (!CE) return false;
675    int64_t Value = CE->getValue();
676    return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
677  }
678  bool isImm0_508s4Neg() const {
679    if (!isImm()) return false;
680    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
681    if (!CE) return false;
682    int64_t Value = -CE->getValue();
683    // explicitly exclude zero. we want that to use the normal 0_508 version.
684    return ((Value & 3) == 0) && Value > 0 && Value <= 508;
685  }
686  bool isImm0_255() const {
687    if (!isImm()) return false;
688    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
689    if (!CE) return false;
690    int64_t Value = CE->getValue();
691    return Value >= 0 && Value < 256;
692  }
693  bool isImm0_4095() const {
694    if (!isImm()) return false;
695    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
696    if (!CE) return false;
697    int64_t Value = CE->getValue();
698    return Value >= 0 && Value < 4096;
699  }
700  bool isImm0_4095Neg() const {
701    if (!isImm()) return false;
702    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
703    if (!CE) return false;
704    int64_t Value = -CE->getValue();
705    return Value > 0 && Value < 4096;
706  }
707  bool isImm0_1() const {
708    if (!isImm()) return false;
709    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
710    if (!CE) return false;
711    int64_t Value = CE->getValue();
712    return Value >= 0 && Value < 2;
713  }
714  bool isImm0_3() const {
715    if (!isImm()) return false;
716    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
717    if (!CE) return false;
718    int64_t Value = CE->getValue();
719    return Value >= 0 && Value < 4;
720  }
721  bool isImm0_7() const {
722    if (!isImm()) return false;
723    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
724    if (!CE) return false;
725    int64_t Value = CE->getValue();
726    return Value >= 0 && Value < 8;
727  }
728  bool isImm0_15() const {
729    if (!isImm()) return false;
730    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
731    if (!CE) return false;
732    int64_t Value = CE->getValue();
733    return Value >= 0 && Value < 16;
734  }
735  bool isImm0_31() const {
736    if (!isImm()) return false;
737    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
738    if (!CE) return false;
739    int64_t Value = CE->getValue();
740    return Value >= 0 && Value < 32;
741  }
742  bool isImm0_63() const {
743    if (!isImm()) return false;
744    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
745    if (!CE) return false;
746    int64_t Value = CE->getValue();
747    return Value >= 0 && Value < 64;
748  }
749  bool isImm8() const {
750    if (!isImm()) return false;
751    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
752    if (!CE) return false;
753    int64_t Value = CE->getValue();
754    return Value == 8;
755  }
756  bool isImm16() const {
757    if (!isImm()) return false;
758    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
759    if (!CE) return false;
760    int64_t Value = CE->getValue();
761    return Value == 16;
762  }
763  bool isImm32() const {
764    if (!isImm()) return false;
765    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
766    if (!CE) return false;
767    int64_t Value = CE->getValue();
768    return Value == 32;
769  }
770  bool isShrImm8() const {
771    if (!isImm()) return false;
772    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
773    if (!CE) return false;
774    int64_t Value = CE->getValue();
775    return Value > 0 && Value <= 8;
776  }
777  bool isShrImm16() const {
778    if (!isImm()) return false;
779    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
780    if (!CE) return false;
781    int64_t Value = CE->getValue();
782    return Value > 0 && Value <= 16;
783  }
784  bool isShrImm32() const {
785    if (!isImm()) return false;
786    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
787    if (!CE) return false;
788    int64_t Value = CE->getValue();
789    return Value > 0 && Value <= 32;
790  }
791  bool isShrImm64() const {
792    if (!isImm()) return false;
793    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
794    if (!CE) return false;
795    int64_t Value = CE->getValue();
796    return Value > 0 && Value <= 64;
797  }
798  bool isImm1_7() const {
799    if (!isImm()) return false;
800    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
801    if (!CE) return false;
802    int64_t Value = CE->getValue();
803    return Value > 0 && Value < 8;
804  }
805  bool isImm1_15() const {
806    if (!isImm()) return false;
807    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
808    if (!CE) return false;
809    int64_t Value = CE->getValue();
810    return Value > 0 && Value < 16;
811  }
812  bool isImm1_31() const {
813    if (!isImm()) return false;
814    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
815    if (!CE) return false;
816    int64_t Value = CE->getValue();
817    return Value > 0 && Value < 32;
818  }
819  bool isImm1_16() const {
820    if (!isImm()) return false;
821    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
822    if (!CE) return false;
823    int64_t Value = CE->getValue();
824    return Value > 0 && Value < 17;
825  }
826  bool isImm1_32() const {
827    if (!isImm()) return false;
828    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
829    if (!CE) return false;
830    int64_t Value = CE->getValue();
831    return Value > 0 && Value < 33;
832  }
833  bool isImm0_32() const {
834    if (!isImm()) return false;
835    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
836    if (!CE) return false;
837    int64_t Value = CE->getValue();
838    return Value >= 0 && Value < 33;
839  }
840  bool isImm0_65535() const {
841    if (!isImm()) return false;
842    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
843    if (!CE) return false;
844    int64_t Value = CE->getValue();
845    return Value >= 0 && Value < 65536;
846  }
847  bool isImm0_65535Expr() const {
848    if (!isImm()) return false;
849    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
850    // If it's not a constant expression, it'll generate a fixup and be
851    // handled later.
852    if (!CE) return true;
853    int64_t Value = CE->getValue();
854    return Value >= 0 && Value < 65536;
855  }
856  bool isImm24bit() const {
857    if (!isImm()) return false;
858    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
859    if (!CE) return false;
860    int64_t Value = CE->getValue();
861    return Value >= 0 && Value <= 0xffffff;
862  }
863  bool isImmThumbSR() const {
864    if (!isImm()) return false;
865    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
866    if (!CE) return false;
867    int64_t Value = CE->getValue();
868    return Value > 0 && Value < 33;
869  }
870  bool isPKHLSLImm() const {
871    if (!isImm()) return false;
872    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
873    if (!CE) return false;
874    int64_t Value = CE->getValue();
875    return Value >= 0 && Value < 32;
876  }
877  bool isPKHASRImm() const {
878    if (!isImm()) return false;
879    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
880    if (!CE) return false;
881    int64_t Value = CE->getValue();
882    return Value > 0 && Value <= 32;
883  }
884  bool isAdrLabel() const {
885    // If we have an immediate that's not a constant, treat it as a label
886    // reference needing a fixup. If it is a constant, but it can't fit
887    // into shift immediate encoding, we reject it.
888    if (isImm() && !isa<MCConstantExpr>(getImm())) return true;
889    else return (isARMSOImm() || isARMSOImmNeg());
890  }
891  bool isARMSOImm() const {
892    if (!isImm()) return false;
893    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
894    if (!CE) return false;
895    int64_t Value = CE->getValue();
896    return ARM_AM::getSOImmVal(Value) != -1;
897  }
898  bool isARMSOImmNot() const {
899    if (!isImm()) return false;
900    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
901    if (!CE) return false;
902    int64_t Value = CE->getValue();
903    return ARM_AM::getSOImmVal(~Value) != -1;
904  }
905  bool isARMSOImmNeg() const {
906    if (!isImm()) return false;
907    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
908    if (!CE) return false;
909    int64_t Value = CE->getValue();
910    // Only use this when not representable as a plain so_imm.
911    return ARM_AM::getSOImmVal(Value) == -1 &&
912      ARM_AM::getSOImmVal(-Value) != -1;
913  }
914  bool isT2SOImm() const {
915    if (!isImm()) return false;
916    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
917    if (!CE) return false;
918    int64_t Value = CE->getValue();
919    return ARM_AM::getT2SOImmVal(Value) != -1;
920  }
921  bool isT2SOImmNot() const {
922    if (!isImm()) return false;
923    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
924    if (!CE) return false;
925    int64_t Value = CE->getValue();
926    return ARM_AM::getT2SOImmVal(~Value) != -1;
927  }
928  bool isT2SOImmNeg() const {
929    if (!isImm()) return false;
930    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
931    if (!CE) return false;
932    int64_t Value = CE->getValue();
933    // Only use this when not representable as a plain so_imm.
934    return ARM_AM::getT2SOImmVal(Value) == -1 &&
935      ARM_AM::getT2SOImmVal(-Value) != -1;
936  }
937  bool isSetEndImm() const {
938    if (!isImm()) return false;
939    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
940    if (!CE) return false;
941    int64_t Value = CE->getValue();
942    return Value == 1 || Value == 0;
943  }
944  bool isReg() const { return Kind == k_Register; }
945  bool isRegList() const { return Kind == k_RegisterList; }
946  bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
947  bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
948  bool isToken() const { return Kind == k_Token; }
949  bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
950  bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
951  bool isMem() const { return Kind == k_Memory; }
952  bool isShifterImm() const { return Kind == k_ShifterImmediate; }
953  bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
954  bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
955  bool isRotImm() const { return Kind == k_RotateImmediate; }
956  bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
957  bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
958  bool isPostIdxReg() const {
959    return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
960  }
961  bool isMemNoOffset(bool alignOK = false) const {
962    if (!isMem())
963      return false;
964    // No offset of any kind.
965    return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 &&
966     (alignOK || Memory.Alignment == 0);
967  }
968  bool isMemPCRelImm12() const {
969    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
970      return false;
971    // Base register must be PC.
972    if (Memory.BaseRegNum != ARM::PC)
973      return false;
974    // Immediate offset in range [-4095, 4095].
975    if (!Memory.OffsetImm) return true;
976    int64_t Val = Memory.OffsetImm->getValue();
977    return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
978  }
979  bool isAlignedMemory() const {
980    return isMemNoOffset(true);
981  }
982  bool isAddrMode2() const {
983    if (!isMem() || Memory.Alignment != 0) return false;
984    // Check for register offset.
985    if (Memory.OffsetRegNum) return true;
986    // Immediate offset in range [-4095, 4095].
987    if (!Memory.OffsetImm) return true;
988    int64_t Val = Memory.OffsetImm->getValue();
989    return Val > -4096 && Val < 4096;
990  }
991  bool isAM2OffsetImm() const {
992    if (!isImm()) return false;
993    // Immediate offset in range [-4095, 4095].
994    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
995    if (!CE) return false;
996    int64_t Val = CE->getValue();
997    return (Val == INT32_MIN) || (Val > -4096 && Val < 4096);
998  }
999  bool isAddrMode3() const {
1000    // If we have an immediate that's not a constant, treat it as a label
1001    // reference needing a fixup. If it is a constant, it's something else
1002    // and we reject it.
1003    if (isImm() && !isa<MCConstantExpr>(getImm()))
1004      return true;
1005    if (!isMem() || Memory.Alignment != 0) return false;
1006    // No shifts are legal for AM3.
1007    if (Memory.ShiftType != ARM_AM::no_shift) return false;
1008    // Check for register offset.
1009    if (Memory.OffsetRegNum) return true;
1010    // Immediate offset in range [-255, 255].
1011    if (!Memory.OffsetImm) return true;
1012    int64_t Val = Memory.OffsetImm->getValue();
1013    // The #-0 offset is encoded as INT32_MIN, and we have to check
1014    // for this too.
1015    return (Val > -256 && Val < 256) || Val == INT32_MIN;
1016  }
1017  bool isAM3Offset() const {
1018    if (Kind != k_Immediate && Kind != k_PostIndexRegister)
1019      return false;
1020    if (Kind == k_PostIndexRegister)
1021      return PostIdxReg.ShiftTy == ARM_AM::no_shift;
1022    // Immediate offset in range [-255, 255].
1023    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1024    if (!CE) return false;
1025    int64_t Val = CE->getValue();
1026    // Special case, #-0 is INT32_MIN.
1027    return (Val > -256 && Val < 256) || Val == INT32_MIN;
1028  }
1029  bool isAddrMode5() const {
1030    // If we have an immediate that's not a constant, treat it as a label
1031    // reference needing a fixup. If it is a constant, it's something else
1032    // and we reject it.
1033    if (isImm() && !isa<MCConstantExpr>(getImm()))
1034      return true;
1035    if (!isMem() || Memory.Alignment != 0) return false;
1036    // Check for register offset.
1037    if (Memory.OffsetRegNum) return false;
1038    // Immediate offset in range [-1020, 1020] and a multiple of 4.
1039    if (!Memory.OffsetImm) return true;
1040    int64_t Val = Memory.OffsetImm->getValue();
1041    return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
1042      Val == INT32_MIN;
1043  }
1044  bool isMemTBB() const {
1045    if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1046        Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1047      return false;
1048    return true;
1049  }
1050  bool isMemTBH() const {
1051    if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1052        Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1053        Memory.Alignment != 0 )
1054      return false;
1055    return true;
1056  }
1057  bool isMemRegOffset() const {
1058    if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
1059      return false;
1060    return true;
1061  }
1062  bool isT2MemRegOffset() const {
1063    if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1064        Memory.Alignment != 0)
1065      return false;
1066    // Only lsl #{0, 1, 2, 3} allowed.
1067    if (Memory.ShiftType == ARM_AM::no_shift)
1068      return true;
1069    if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1070      return false;
1071    return true;
1072  }
1073  bool isMemThumbRR() const {
1074    // Thumb reg+reg addressing is simple. Just two registers, a base and
1075    // an offset. No shifts, negations or any other complicating factors.
1076    if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1077        Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1078      return false;
1079    return isARMLowRegister(Memory.BaseRegNum) &&
1080      (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
1081  }
1082  bool isMemThumbRIs4() const {
1083    if (!isMem() || Memory.OffsetRegNum != 0 ||
1084        !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1085      return false;
1086    // Immediate offset, multiple of 4 in range [0, 124].
1087    if (!Memory.OffsetImm) return true;
1088    int64_t Val = Memory.OffsetImm->getValue();
1089    return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1090  }
1091  bool isMemThumbRIs2() const {
1092    if (!isMem() || Memory.OffsetRegNum != 0 ||
1093        !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1094      return false;
1095    // Immediate offset, multiple of 4 in range [0, 62].
1096    if (!Memory.OffsetImm) return true;
1097    int64_t Val = Memory.OffsetImm->getValue();
1098    return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1099  }
1100  bool isMemThumbRIs1() const {
1101    if (!isMem() || Memory.OffsetRegNum != 0 ||
1102        !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1103      return false;
1104    // Immediate offset in range [0, 31].
1105    if (!Memory.OffsetImm) return true;
1106    int64_t Val = Memory.OffsetImm->getValue();
1107    return Val >= 0 && Val <= 31;
1108  }
1109  bool isMemThumbSPI() const {
1110    if (!isMem() || Memory.OffsetRegNum != 0 ||
1111        Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1112      return false;
1113    // Immediate offset, multiple of 4 in range [0, 1020].
1114    if (!Memory.OffsetImm) return true;
1115    int64_t Val = Memory.OffsetImm->getValue();
1116    return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1117  }
1118  bool isMemImm8s4Offset() const {
1119    // If we have an immediate that's not a constant, treat it as a label
1120    // reference needing a fixup. If it is a constant, it's something else
1121    // and we reject it.
1122    if (isImm() && !isa<MCConstantExpr>(getImm()))
1123      return true;
1124    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1125      return false;
1126    // Immediate offset a multiple of 4 in range [-1020, 1020].
1127    if (!Memory.OffsetImm) return true;
1128    int64_t Val = Memory.OffsetImm->getValue();
1129    // Special case, #-0 is INT32_MIN.
1130    return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN;
1131  }
1132  bool isMemImm0_1020s4Offset() const {
1133    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1134      return false;
1135    // Immediate offset a multiple of 4 in range [0, 1020].
1136    if (!Memory.OffsetImm) return true;
1137    int64_t Val = Memory.OffsetImm->getValue();
1138    return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1139  }
1140  bool isMemImm8Offset() const {
1141    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1142      return false;
1143    // Base reg of PC isn't allowed for these encodings.
1144    if (Memory.BaseRegNum == ARM::PC) return false;
1145    // Immediate offset in range [-255, 255].
1146    if (!Memory.OffsetImm) return true;
1147    int64_t Val = Memory.OffsetImm->getValue();
1148    return (Val == INT32_MIN) || (Val > -256 && Val < 256);
1149  }
1150  bool isMemPosImm8Offset() const {
1151    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1152      return false;
1153    // Immediate offset in range [0, 255].
1154    if (!Memory.OffsetImm) return true;
1155    int64_t Val = Memory.OffsetImm->getValue();
1156    return Val >= 0 && Val < 256;
1157  }
1158  bool isMemNegImm8Offset() const {
1159    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1160      return false;
1161    // Base reg of PC isn't allowed for these encodings.
1162    if (Memory.BaseRegNum == ARM::PC) return false;
1163    // Immediate offset in range [-255, -1].
1164    if (!Memory.OffsetImm) return false;
1165    int64_t Val = Memory.OffsetImm->getValue();
1166    return (Val == INT32_MIN) || (Val > -256 && Val < 0);
1167  }
1168  bool isMemUImm12Offset() const {
1169    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1170      return false;
1171    // Immediate offset in range [0, 4095].
1172    if (!Memory.OffsetImm) return true;
1173    int64_t Val = Memory.OffsetImm->getValue();
1174    return (Val >= 0 && Val < 4096);
1175  }
1176  bool isMemImm12Offset() const {
1177    // If we have an immediate that's not a constant, treat it as a label
1178    // reference needing a fixup. If it is a constant, it's something else
1179    // and we reject it.
1180    if (isImm() && !isa<MCConstantExpr>(getImm()))
1181      return true;
1182
1183    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1184      return false;
1185    // Immediate offset in range [-4095, 4095].
1186    if (!Memory.OffsetImm) return true;
1187    int64_t Val = Memory.OffsetImm->getValue();
1188    return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1189  }
1190  bool isPostIdxImm8() const {
1191    if (!isImm()) return false;
1192    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1193    if (!CE) return false;
1194    int64_t Val = CE->getValue();
1195    return (Val > -256 && Val < 256) || (Val == INT32_MIN);
1196  }
1197  bool isPostIdxImm8s4() const {
1198    if (!isImm()) return false;
1199    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1200    if (!CE) return false;
1201    int64_t Val = CE->getValue();
1202    return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1203      (Val == INT32_MIN);
1204  }
1205
1206  bool isMSRMask() const { return Kind == k_MSRMask; }
1207  bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1208
1209  // NEON operands.
1210  bool isSingleSpacedVectorList() const {
1211    return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1212  }
1213  bool isDoubleSpacedVectorList() const {
1214    return Kind == k_VectorList && VectorList.isDoubleSpaced;
1215  }
1216  bool isVecListOneD() const {
1217    if (!isSingleSpacedVectorList()) return false;
1218    return VectorList.Count == 1;
1219  }
1220
1221  bool isVecListDPair() const {
1222    if (!isSingleSpacedVectorList()) return false;
1223    return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1224              .contains(VectorList.RegNum));
1225  }
1226
1227  bool isVecListThreeD() const {
1228    if (!isSingleSpacedVectorList()) return false;
1229    return VectorList.Count == 3;
1230  }
1231
1232  bool isVecListFourD() const {
1233    if (!isSingleSpacedVectorList()) return false;
1234    return VectorList.Count == 4;
1235  }
1236
1237  bool isVecListDPairSpaced() const {
1238    if (isSingleSpacedVectorList()) return false;
1239    return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1240              .contains(VectorList.RegNum));
1241  }
1242
1243  bool isVecListThreeQ() const {
1244    if (!isDoubleSpacedVectorList()) return false;
1245    return VectorList.Count == 3;
1246  }
1247
1248  bool isVecListFourQ() const {
1249    if (!isDoubleSpacedVectorList()) return false;
1250    return VectorList.Count == 4;
1251  }
1252
1253  bool isSingleSpacedVectorAllLanes() const {
1254    return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1255  }
1256  bool isDoubleSpacedVectorAllLanes() const {
1257    return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1258  }
1259  bool isVecListOneDAllLanes() const {
1260    if (!isSingleSpacedVectorAllLanes()) return false;
1261    return VectorList.Count == 1;
1262  }
1263
1264  bool isVecListDPairAllLanes() const {
1265    if (!isSingleSpacedVectorAllLanes()) return false;
1266    return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1267              .contains(VectorList.RegNum));
1268  }
1269
1270  bool isVecListDPairSpacedAllLanes() const {
1271    if (!isDoubleSpacedVectorAllLanes()) return false;
1272    return VectorList.Count == 2;
1273  }
1274
1275  bool isVecListThreeDAllLanes() const {
1276    if (!isSingleSpacedVectorAllLanes()) return false;
1277    return VectorList.Count == 3;
1278  }
1279
1280  bool isVecListThreeQAllLanes() const {
1281    if (!isDoubleSpacedVectorAllLanes()) return false;
1282    return VectorList.Count == 3;
1283  }
1284
1285  bool isVecListFourDAllLanes() const {
1286    if (!isSingleSpacedVectorAllLanes()) return false;
1287    return VectorList.Count == 4;
1288  }
1289
1290  bool isVecListFourQAllLanes() const {
1291    if (!isDoubleSpacedVectorAllLanes()) return false;
1292    return VectorList.Count == 4;
1293  }
1294
1295  bool isSingleSpacedVectorIndexed() const {
1296    return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1297  }
1298  bool isDoubleSpacedVectorIndexed() const {
1299    return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1300  }
1301  bool isVecListOneDByteIndexed() const {
1302    if (!isSingleSpacedVectorIndexed()) return false;
1303    return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1304  }
1305
1306  bool isVecListOneDHWordIndexed() const {
1307    if (!isSingleSpacedVectorIndexed()) return false;
1308    return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1309  }
1310
1311  bool isVecListOneDWordIndexed() const {
1312    if (!isSingleSpacedVectorIndexed()) return false;
1313    return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1314  }
1315
1316  bool isVecListTwoDByteIndexed() const {
1317    if (!isSingleSpacedVectorIndexed()) return false;
1318    return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1319  }
1320
1321  bool isVecListTwoDHWordIndexed() const {
1322    if (!isSingleSpacedVectorIndexed()) return false;
1323    return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1324  }
1325
1326  bool isVecListTwoQWordIndexed() const {
1327    if (!isDoubleSpacedVectorIndexed()) return false;
1328    return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1329  }
1330
1331  bool isVecListTwoQHWordIndexed() const {
1332    if (!isDoubleSpacedVectorIndexed()) return false;
1333    return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1334  }
1335
1336  bool isVecListTwoDWordIndexed() const {
1337    if (!isSingleSpacedVectorIndexed()) return false;
1338    return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1339  }
1340
1341  bool isVecListThreeDByteIndexed() const {
1342    if (!isSingleSpacedVectorIndexed()) return false;
1343    return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
1344  }
1345
1346  bool isVecListThreeDHWordIndexed() const {
1347    if (!isSingleSpacedVectorIndexed()) return false;
1348    return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1349  }
1350
1351  bool isVecListThreeQWordIndexed() const {
1352    if (!isDoubleSpacedVectorIndexed()) return false;
1353    return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1354  }
1355
1356  bool isVecListThreeQHWordIndexed() const {
1357    if (!isDoubleSpacedVectorIndexed()) return false;
1358    return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1359  }
1360
1361  bool isVecListThreeDWordIndexed() const {
1362    if (!isSingleSpacedVectorIndexed()) return false;
1363    return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1364  }
1365
1366  bool isVecListFourDByteIndexed() const {
1367    if (!isSingleSpacedVectorIndexed()) return false;
1368    return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
1369  }
1370
1371  bool isVecListFourDHWordIndexed() const {
1372    if (!isSingleSpacedVectorIndexed()) return false;
1373    return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1374  }
1375
1376  bool isVecListFourQWordIndexed() const {
1377    if (!isDoubleSpacedVectorIndexed()) return false;
1378    return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1379  }
1380
1381  bool isVecListFourQHWordIndexed() const {
1382    if (!isDoubleSpacedVectorIndexed()) return false;
1383    return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1384  }
1385
1386  bool isVecListFourDWordIndexed() const {
1387    if (!isSingleSpacedVectorIndexed()) return false;
1388    return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1389  }
1390
1391  bool isVectorIndex8() const {
1392    if (Kind != k_VectorIndex) return false;
1393    return VectorIndex.Val < 8;
1394  }
1395  bool isVectorIndex16() const {
1396    if (Kind != k_VectorIndex) return false;
1397    return VectorIndex.Val < 4;
1398  }
1399  bool isVectorIndex32() const {
1400    if (Kind != k_VectorIndex) return false;
1401    return VectorIndex.Val < 2;
1402  }
1403
1404  bool isNEONi8splat() const {
1405    if (!isImm()) return false;
1406    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1407    // Must be a constant.
1408    if (!CE) return false;
1409    int64_t Value = CE->getValue();
1410    // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1411    // value.
1412    return Value >= 0 && Value < 256;
1413  }
1414
1415  bool isNEONi16splat() const {
1416    if (!isImm()) return false;
1417    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1418    // Must be a constant.
1419    if (!CE) return false;
1420    int64_t Value = CE->getValue();
1421    // i16 value in the range [0,255] or [0x0100, 0xff00]
1422    return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00);
1423  }
1424
1425  bool isNEONi32splat() const {
1426    if (!isImm()) return false;
1427    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1428    // Must be a constant.
1429    if (!CE) return false;
1430    int64_t Value = CE->getValue();
1431    // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
1432    return (Value >= 0 && Value < 256) ||
1433      (Value >= 0x0100 && Value <= 0xff00) ||
1434      (Value >= 0x010000 && Value <= 0xff0000) ||
1435      (Value >= 0x01000000 && Value <= 0xff000000);
1436  }
1437
1438  bool isNEONi32vmov() const {
1439    if (!isImm()) return false;
1440    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1441    // Must be a constant.
1442    if (!CE) return false;
1443    int64_t Value = CE->getValue();
1444    // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1445    // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1446    return (Value >= 0 && Value < 256) ||
1447      (Value >= 0x0100 && Value <= 0xff00) ||
1448      (Value >= 0x010000 && Value <= 0xff0000) ||
1449      (Value >= 0x01000000 && Value <= 0xff000000) ||
1450      (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1451      (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1452  }
1453  bool isNEONi32vmovNeg() const {
1454    if (!isImm()) return false;
1455    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1456    // Must be a constant.
1457    if (!CE) return false;
1458    int64_t Value = ~CE->getValue();
1459    // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1460    // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1461    return (Value >= 0 && Value < 256) ||
1462      (Value >= 0x0100 && Value <= 0xff00) ||
1463      (Value >= 0x010000 && Value <= 0xff0000) ||
1464      (Value >= 0x01000000 && Value <= 0xff000000) ||
1465      (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1466      (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1467  }
1468
1469  bool isNEONi64splat() const {
1470    if (!isImm()) return false;
1471    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1472    // Must be a constant.
1473    if (!CE) return false;
1474    uint64_t Value = CE->getValue();
1475    // i64 value with each byte being either 0 or 0xff.
1476    for (unsigned i = 0; i < 8; ++i)
1477      if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1478    return true;
1479  }
1480
1481  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1482    // Add as immediates when possible.  Null MCExpr = 0.
1483    if (Expr == 0)
1484      Inst.addOperand(MCOperand::CreateImm(0));
1485    else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1486      Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1487    else
1488      Inst.addOperand(MCOperand::CreateExpr(Expr));
1489  }
1490
1491  void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1492    assert(N == 2 && "Invalid number of operands!");
1493    Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1494    unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1495    Inst.addOperand(MCOperand::CreateReg(RegNum));
1496  }
1497
1498  void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1499    assert(N == 1 && "Invalid number of operands!");
1500    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1501  }
1502
1503  void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1504    assert(N == 1 && "Invalid number of operands!");
1505    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1506  }
1507
1508  void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1509    assert(N == 1 && "Invalid number of operands!");
1510    Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1511  }
1512
1513  void addITMaskOperands(MCInst &Inst, unsigned N) const {
1514    assert(N == 1 && "Invalid number of operands!");
1515    Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1516  }
1517
1518  void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1519    assert(N == 1 && "Invalid number of operands!");
1520    Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1521  }
1522
1523  void addCCOutOperands(MCInst &Inst, unsigned N) const {
1524    assert(N == 1 && "Invalid number of operands!");
1525    Inst.addOperand(MCOperand::CreateReg(getReg()));
1526  }
1527
1528  void addRegOperands(MCInst &Inst, unsigned N) const {
1529    assert(N == 1 && "Invalid number of operands!");
1530    Inst.addOperand(MCOperand::CreateReg(getReg()));
1531  }
1532
1533  void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1534    assert(N == 3 && "Invalid number of operands!");
1535    assert(isRegShiftedReg() &&
1536           "addRegShiftedRegOperands() on non RegShiftedReg!");
1537    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1538    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1539    Inst.addOperand(MCOperand::CreateImm(
1540      ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1541  }
1542
1543  void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1544    assert(N == 2 && "Invalid number of operands!");
1545    assert(isRegShiftedImm() &&
1546           "addRegShiftedImmOperands() on non RegShiftedImm!");
1547    Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1548    // Shift of #32 is encoded as 0 where permitted
1549    unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
1550    Inst.addOperand(MCOperand::CreateImm(
1551      ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
1552  }
1553
1554  void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1555    assert(N == 1 && "Invalid number of operands!");
1556    Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1557                                         ShifterImm.Imm));
1558  }
1559
1560  void addRegListOperands(MCInst &Inst, unsigned N) const {
1561    assert(N == 1 && "Invalid number of operands!");
1562    const SmallVectorImpl<unsigned> &RegList = getRegList();
1563    for (SmallVectorImpl<unsigned>::const_iterator
1564           I = RegList.begin(), E = RegList.end(); I != E; ++I)
1565      Inst.addOperand(MCOperand::CreateReg(*I));
1566  }
1567
1568  void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1569    addRegListOperands(Inst, N);
1570  }
1571
1572  void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1573    addRegListOperands(Inst, N);
1574  }
1575
1576  void addRotImmOperands(MCInst &Inst, unsigned N) const {
1577    assert(N == 1 && "Invalid number of operands!");
1578    // Encoded as val>>3. The printer handles display as 8, 16, 24.
1579    Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1580  }
1581
1582  void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1583    assert(N == 1 && "Invalid number of operands!");
1584    // Munge the lsb/width into a bitfield mask.
1585    unsigned lsb = Bitfield.LSB;
1586    unsigned width = Bitfield.Width;
1587    // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1588    uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1589                      (32 - (lsb + width)));
1590    Inst.addOperand(MCOperand::CreateImm(Mask));
1591  }
1592
1593  void addImmOperands(MCInst &Inst, unsigned N) const {
1594    assert(N == 1 && "Invalid number of operands!");
1595    addExpr(Inst, getImm());
1596  }
1597
1598  void addFBits16Operands(MCInst &Inst, unsigned N) const {
1599    assert(N == 1 && "Invalid number of operands!");
1600    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1601    Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue()));
1602  }
1603
1604  void addFBits32Operands(MCInst &Inst, unsigned N) const {
1605    assert(N == 1 && "Invalid number of operands!");
1606    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1607    Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue()));
1608  }
1609
1610  void addFPImmOperands(MCInst &Inst, unsigned N) const {
1611    assert(N == 1 && "Invalid number of operands!");
1612    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1613    int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1614    Inst.addOperand(MCOperand::CreateImm(Val));
1615  }
1616
1617  void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1618    assert(N == 1 && "Invalid number of operands!");
1619    // FIXME: We really want to scale the value here, but the LDRD/STRD
1620    // instruction don't encode operands that way yet.
1621    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1622    Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1623  }
1624
1625  void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1626    assert(N == 1 && "Invalid number of operands!");
1627    // The immediate is scaled by four in the encoding and is stored
1628    // in the MCInst as such. Lop off the low two bits here.
1629    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1630    Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1631  }
1632
1633  void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
1634    assert(N == 1 && "Invalid number of operands!");
1635    // The immediate is scaled by four in the encoding and is stored
1636    // in the MCInst as such. Lop off the low two bits here.
1637    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1638    Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4)));
1639  }
1640
1641  void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1642    assert(N == 1 && "Invalid number of operands!");
1643    // The immediate is scaled by four in the encoding and is stored
1644    // in the MCInst as such. Lop off the low two bits here.
1645    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1646    Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1647  }
1648
1649  void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1650    assert(N == 1 && "Invalid number of operands!");
1651    // The constant encodes as the immediate-1, and we store in the instruction
1652    // the bits as encoded, so subtract off one here.
1653    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1654    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1655  }
1656
1657  void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1658    assert(N == 1 && "Invalid number of operands!");
1659    // The constant encodes as the immediate-1, and we store in the instruction
1660    // the bits as encoded, so subtract off one here.
1661    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1662    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1663  }
1664
1665  void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1666    assert(N == 1 && "Invalid number of operands!");
1667    // The constant encodes as the immediate, except for 32, which encodes as
1668    // zero.
1669    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1670    unsigned Imm = CE->getValue();
1671    Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1672  }
1673
1674  void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1675    assert(N == 1 && "Invalid number of operands!");
1676    // An ASR value of 32 encodes as 0, so that's how we want to add it to
1677    // the instruction as well.
1678    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1679    int Val = CE->getValue();
1680    Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1681  }
1682
1683  void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1684    assert(N == 1 && "Invalid number of operands!");
1685    // The operand is actually a t2_so_imm, but we have its bitwise
1686    // negation in the assembly source, so twiddle it here.
1687    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1688    Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1689  }
1690
1691  void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
1692    assert(N == 1 && "Invalid number of operands!");
1693    // The operand is actually a t2_so_imm, but we have its
1694    // negation in the assembly source, so twiddle it here.
1695    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1696    Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1697  }
1698
1699  void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
1700    assert(N == 1 && "Invalid number of operands!");
1701    // The operand is actually an imm0_4095, but we have its
1702    // negation in the assembly source, so twiddle it here.
1703    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1704    Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1705  }
1706
1707  void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
1708    assert(N == 1 && "Invalid number of operands!");
1709    // The operand is actually a so_imm, but we have its bitwise
1710    // negation in the assembly source, so twiddle it here.
1711    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1712    Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1713  }
1714
1715  void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const {
1716    assert(N == 1 && "Invalid number of operands!");
1717    // The operand is actually a so_imm, but we have its
1718    // negation in the assembly source, so twiddle it here.
1719    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1720    Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1721  }
1722
1723  void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1724    assert(N == 1 && "Invalid number of operands!");
1725    Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1726  }
1727
1728  void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
1729    assert(N == 1 && "Invalid number of operands!");
1730    Inst.addOperand(MCOperand::CreateImm(unsigned(getInstSyncBarrierOpt())));
1731  }
1732
1733  void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1734    assert(N == 1 && "Invalid number of operands!");
1735    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1736  }
1737
1738  void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
1739    assert(N == 1 && "Invalid number of operands!");
1740    int32_t Imm = Memory.OffsetImm->getValue();
1741    // FIXME: Handle #-0
1742    if (Imm == INT32_MIN) Imm = 0;
1743    Inst.addOperand(MCOperand::CreateImm(Imm));
1744  }
1745
1746  void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
1747    assert(N == 1 && "Invalid number of operands!");
1748    assert(isImm() && "Not an immediate!");
1749
1750    // If we have an immediate that's not a constant, treat it as a label
1751    // reference needing a fixup.
1752    if (!isa<MCConstantExpr>(getImm())) {
1753      Inst.addOperand(MCOperand::CreateExpr(getImm()));
1754      return;
1755    }
1756
1757    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1758    int Val = CE->getValue();
1759    Inst.addOperand(MCOperand::CreateImm(Val));
1760  }
1761
1762  void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
1763    assert(N == 2 && "Invalid number of operands!");
1764    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1765    Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
1766  }
1767
1768  void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
1769    assert(N == 3 && "Invalid number of operands!");
1770    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1771    if (!Memory.OffsetRegNum) {
1772      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1773      // Special case for #-0
1774      if (Val == INT32_MIN) Val = 0;
1775      if (Val < 0) Val = -Val;
1776      Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1777    } else {
1778      // For register offset, we encode the shift type and negation flag
1779      // here.
1780      Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1781                              Memory.ShiftImm, Memory.ShiftType);
1782    }
1783    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1784    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1785    Inst.addOperand(MCOperand::CreateImm(Val));
1786  }
1787
1788  void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
1789    assert(N == 2 && "Invalid number of operands!");
1790    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1791    assert(CE && "non-constant AM2OffsetImm operand!");
1792    int32_t Val = CE->getValue();
1793    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1794    // Special case for #-0
1795    if (Val == INT32_MIN) Val = 0;
1796    if (Val < 0) Val = -Val;
1797    Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1798    Inst.addOperand(MCOperand::CreateReg(0));
1799    Inst.addOperand(MCOperand::CreateImm(Val));
1800  }
1801
1802  void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
1803    assert(N == 3 && "Invalid number of operands!");
1804    // If we have an immediate that's not a constant, treat it as a label
1805    // reference needing a fixup. If it is a constant, it's something else
1806    // and we reject it.
1807    if (isImm()) {
1808      Inst.addOperand(MCOperand::CreateExpr(getImm()));
1809      Inst.addOperand(MCOperand::CreateReg(0));
1810      Inst.addOperand(MCOperand::CreateImm(0));
1811      return;
1812    }
1813
1814    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1815    if (!Memory.OffsetRegNum) {
1816      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1817      // Special case for #-0
1818      if (Val == INT32_MIN) Val = 0;
1819      if (Val < 0) Val = -Val;
1820      Val = ARM_AM::getAM3Opc(AddSub, Val);
1821    } else {
1822      // For register offset, we encode the shift type and negation flag
1823      // here.
1824      Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
1825    }
1826    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1827    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1828    Inst.addOperand(MCOperand::CreateImm(Val));
1829  }
1830
1831  void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
1832    assert(N == 2 && "Invalid number of operands!");
1833    if (Kind == k_PostIndexRegister) {
1834      int32_t Val =
1835        ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
1836      Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1837      Inst.addOperand(MCOperand::CreateImm(Val));
1838      return;
1839    }
1840
1841    // Constant offset.
1842    const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
1843    int32_t Val = CE->getValue();
1844    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1845    // Special case for #-0
1846    if (Val == INT32_MIN) Val = 0;
1847    if (Val < 0) Val = -Val;
1848    Val = ARM_AM::getAM3Opc(AddSub, Val);
1849    Inst.addOperand(MCOperand::CreateReg(0));
1850    Inst.addOperand(MCOperand::CreateImm(Val));
1851  }
1852
1853  void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
1854    assert(N == 2 && "Invalid number of operands!");
1855    // If we have an immediate that's not a constant, treat it as a label
1856    // reference needing a fixup. If it is a constant, it's something else
1857    // and we reject it.
1858    if (isImm()) {
1859      Inst.addOperand(MCOperand::CreateExpr(getImm()));
1860      Inst.addOperand(MCOperand::CreateImm(0));
1861      return;
1862    }
1863
1864    // The lower two bits are always zero and as such are not encoded.
1865    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1866    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1867    // Special case for #-0
1868    if (Val == INT32_MIN) Val = 0;
1869    if (Val < 0) Val = -Val;
1870    Val = ARM_AM::getAM5Opc(AddSub, Val);
1871    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1872    Inst.addOperand(MCOperand::CreateImm(Val));
1873  }
1874
1875  void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
1876    assert(N == 2 && "Invalid number of operands!");
1877    // If we have an immediate that's not a constant, treat it as a label
1878    // reference needing a fixup. If it is a constant, it's something else
1879    // and we reject it.
1880    if (isImm()) {
1881      Inst.addOperand(MCOperand::CreateExpr(getImm()));
1882      Inst.addOperand(MCOperand::CreateImm(0));
1883      return;
1884    }
1885
1886    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1887    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1888    Inst.addOperand(MCOperand::CreateImm(Val));
1889  }
1890
1891  void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
1892    assert(N == 2 && "Invalid number of operands!");
1893    // The lower two bits are always zero and as such are not encoded.
1894    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1895    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1896    Inst.addOperand(MCOperand::CreateImm(Val));
1897  }
1898
1899  void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1900    assert(N == 2 && "Invalid number of operands!");
1901    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1902    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1903    Inst.addOperand(MCOperand::CreateImm(Val));
1904  }
1905
1906  void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1907    addMemImm8OffsetOperands(Inst, N);
1908  }
1909
1910  void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1911    addMemImm8OffsetOperands(Inst, N);
1912  }
1913
1914  void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1915    assert(N == 2 && "Invalid number of operands!");
1916    // If this is an immediate, it's a label reference.
1917    if (isImm()) {
1918      addExpr(Inst, getImm());
1919      Inst.addOperand(MCOperand::CreateImm(0));
1920      return;
1921    }
1922
1923    // Otherwise, it's a normal memory reg+offset.
1924    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1925    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1926    Inst.addOperand(MCOperand::CreateImm(Val));
1927  }
1928
1929  void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1930    assert(N == 2 && "Invalid number of operands!");
1931    // If this is an immediate, it's a label reference.
1932    if (isImm()) {
1933      addExpr(Inst, getImm());
1934      Inst.addOperand(MCOperand::CreateImm(0));
1935      return;
1936    }
1937
1938    // Otherwise, it's a normal memory reg+offset.
1939    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1940    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1941    Inst.addOperand(MCOperand::CreateImm(Val));
1942  }
1943
1944  void addMemTBBOperands(MCInst &Inst, unsigned N) const {
1945    assert(N == 2 && "Invalid number of operands!");
1946    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1947    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1948  }
1949
1950  void addMemTBHOperands(MCInst &Inst, unsigned N) const {
1951    assert(N == 2 && "Invalid number of operands!");
1952    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1953    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1954  }
1955
1956  void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1957    assert(N == 3 && "Invalid number of operands!");
1958    unsigned Val =
1959      ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1960                        Memory.ShiftImm, Memory.ShiftType);
1961    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1962    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1963    Inst.addOperand(MCOperand::CreateImm(Val));
1964  }
1965
1966  void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1967    assert(N == 3 && "Invalid number of operands!");
1968    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1969    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1970    Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
1971  }
1972
1973  void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
1974    assert(N == 2 && "Invalid number of operands!");
1975    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1976    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1977  }
1978
1979  void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
1980    assert(N == 2 && "Invalid number of operands!");
1981    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
1982    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1983    Inst.addOperand(MCOperand::CreateImm(Val));
1984  }
1985
1986  void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
1987    assert(N == 2 && "Invalid number of operands!");
1988    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
1989    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1990    Inst.addOperand(MCOperand::CreateImm(Val));
1991  }
1992
1993  void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
1994    assert(N == 2 && "Invalid number of operands!");
1995    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
1996    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1997    Inst.addOperand(MCOperand::CreateImm(Val));
1998  }
1999
2000  void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
2001    assert(N == 2 && "Invalid number of operands!");
2002    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2003    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2004    Inst.addOperand(MCOperand::CreateImm(Val));
2005  }
2006
2007  void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
2008    assert(N == 1 && "Invalid number of operands!");
2009    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2010    assert(CE && "non-constant post-idx-imm8 operand!");
2011    int Imm = CE->getValue();
2012    bool isAdd = Imm >= 0;
2013    if (Imm == INT32_MIN) Imm = 0;
2014    Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
2015    Inst.addOperand(MCOperand::CreateImm(Imm));
2016  }
2017
2018  void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
2019    assert(N == 1 && "Invalid number of operands!");
2020    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2021    assert(CE && "non-constant post-idx-imm8s4 operand!");
2022    int Imm = CE->getValue();
2023    bool isAdd = Imm >= 0;
2024    if (Imm == INT32_MIN) Imm = 0;
2025    // Immediate is scaled by 4.
2026    Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
2027    Inst.addOperand(MCOperand::CreateImm(Imm));
2028  }
2029
2030  void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
2031    assert(N == 2 && "Invalid number of operands!");
2032    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2033    Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
2034  }
2035
2036  void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
2037    assert(N == 2 && "Invalid number of operands!");
2038    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2039    // The sign, shift type, and shift amount are encoded in a single operand
2040    // using the AM2 encoding helpers.
2041    ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
2042    unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
2043                                     PostIdxReg.ShiftTy);
2044    Inst.addOperand(MCOperand::CreateImm(Imm));
2045  }
2046
2047  void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
2048    assert(N == 1 && "Invalid number of operands!");
2049    Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
2050  }
2051
2052  void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
2053    assert(N == 1 && "Invalid number of operands!");
2054    Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
2055  }
2056
2057  void addVecListOperands(MCInst &Inst, unsigned N) const {
2058    assert(N == 1 && "Invalid number of operands!");
2059    Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2060  }
2061
2062  void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
2063    assert(N == 2 && "Invalid number of operands!");
2064    Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2065    Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex));
2066  }
2067
2068  void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
2069    assert(N == 1 && "Invalid number of operands!");
2070    Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2071  }
2072
2073  void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
2074    assert(N == 1 && "Invalid number of operands!");
2075    Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2076  }
2077
2078  void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
2079    assert(N == 1 && "Invalid number of operands!");
2080    Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2081  }
2082
2083  void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
2084    assert(N == 1 && "Invalid number of operands!");
2085    // The immediate encodes the type of constant as well as the value.
2086    // Mask in that this is an i8 splat.
2087    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2088    Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
2089  }
2090
2091  void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
2092    assert(N == 1 && "Invalid number of operands!");
2093    // The immediate encodes the type of constant as well as the value.
2094    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2095    unsigned Value = CE->getValue();
2096    if (Value >= 256)
2097      Value = (Value >> 8) | 0xa00;
2098    else
2099      Value |= 0x800;
2100    Inst.addOperand(MCOperand::CreateImm(Value));
2101  }
2102
2103  void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
2104    assert(N == 1 && "Invalid number of operands!");
2105    // The immediate encodes the type of constant as well as the value.
2106    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2107    unsigned Value = CE->getValue();
2108    if (Value >= 256 && Value <= 0xff00)
2109      Value = (Value >> 8) | 0x200;
2110    else if (Value > 0xffff && Value <= 0xff0000)
2111      Value = (Value >> 16) | 0x400;
2112    else if (Value > 0xffffff)
2113      Value = (Value >> 24) | 0x600;
2114    Inst.addOperand(MCOperand::CreateImm(Value));
2115  }
2116
2117  void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2118    assert(N == 1 && "Invalid number of operands!");
2119    // The immediate encodes the type of constant as well as the value.
2120    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2121    unsigned Value = CE->getValue();
2122    if (Value >= 256 && Value <= 0xffff)
2123      Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2124    else if (Value > 0xffff && Value <= 0xffffff)
2125      Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2126    else if (Value > 0xffffff)
2127      Value = (Value >> 24) | 0x600;
2128    Inst.addOperand(MCOperand::CreateImm(Value));
2129  }
2130
2131  void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2132    assert(N == 1 && "Invalid number of operands!");
2133    // The immediate encodes the type of constant as well as the value.
2134    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2135    unsigned Value = ~CE->getValue();
2136    if (Value >= 256 && Value <= 0xffff)
2137      Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2138    else if (Value > 0xffff && Value <= 0xffffff)
2139      Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2140    else if (Value > 0xffffff)
2141      Value = (Value >> 24) | 0x600;
2142    Inst.addOperand(MCOperand::CreateImm(Value));
2143  }
2144
2145  void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2146    assert(N == 1 && "Invalid number of operands!");
2147    // The immediate encodes the type of constant as well as the value.
2148    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2149    uint64_t Value = CE->getValue();
2150    unsigned Imm = 0;
2151    for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
2152      Imm |= (Value & 1) << i;
2153    }
2154    Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
2155  }
2156
2157  virtual void print(raw_ostream &OS) const;
2158
2159  static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
2160    ARMOperand *Op = new ARMOperand(k_ITCondMask);
2161    Op->ITMask.Mask = Mask;
2162    Op->StartLoc = S;
2163    Op->EndLoc = S;
2164    return Op;
2165  }
2166
2167  static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
2168    ARMOperand *Op = new ARMOperand(k_CondCode);
2169    Op->CC.Val = CC;
2170    Op->StartLoc = S;
2171    Op->EndLoc = S;
2172    return Op;
2173  }
2174
2175  static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
2176    ARMOperand *Op = new ARMOperand(k_CoprocNum);
2177    Op->Cop.Val = CopVal;
2178    Op->StartLoc = S;
2179    Op->EndLoc = S;
2180    return Op;
2181  }
2182
2183  static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
2184    ARMOperand *Op = new ARMOperand(k_CoprocReg);
2185    Op->Cop.Val = CopVal;
2186    Op->StartLoc = S;
2187    Op->EndLoc = S;
2188    return Op;
2189  }
2190
2191  static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) {
2192    ARMOperand *Op = new ARMOperand(k_CoprocOption);
2193    Op->Cop.Val = Val;
2194    Op->StartLoc = S;
2195    Op->EndLoc = E;
2196    return Op;
2197  }
2198
2199  static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
2200    ARMOperand *Op = new ARMOperand(k_CCOut);
2201    Op->Reg.RegNum = RegNum;
2202    Op->StartLoc = S;
2203    Op->EndLoc = S;
2204    return Op;
2205  }
2206
2207  static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
2208    ARMOperand *Op = new ARMOperand(k_Token);
2209    Op->Tok.Data = Str.data();
2210    Op->Tok.Length = Str.size();
2211    Op->StartLoc = S;
2212    Op->EndLoc = S;
2213    return Op;
2214  }
2215
2216  static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
2217    ARMOperand *Op = new ARMOperand(k_Register);
2218    Op->Reg.RegNum = RegNum;
2219    Op->StartLoc = S;
2220    Op->EndLoc = E;
2221    return Op;
2222  }
2223
2224  static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
2225                                           unsigned SrcReg,
2226                                           unsigned ShiftReg,
2227                                           unsigned ShiftImm,
2228                                           SMLoc S, SMLoc E) {
2229    ARMOperand *Op = new ARMOperand(k_ShiftedRegister);
2230    Op->RegShiftedReg.ShiftTy = ShTy;
2231    Op->RegShiftedReg.SrcReg = SrcReg;
2232    Op->RegShiftedReg.ShiftReg = ShiftReg;
2233    Op->RegShiftedReg.ShiftImm = ShiftImm;
2234    Op->StartLoc = S;
2235    Op->EndLoc = E;
2236    return Op;
2237  }
2238
2239  static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
2240                                            unsigned SrcReg,
2241                                            unsigned ShiftImm,
2242                                            SMLoc S, SMLoc E) {
2243    ARMOperand *Op = new ARMOperand(k_ShiftedImmediate);
2244    Op->RegShiftedImm.ShiftTy = ShTy;
2245    Op->RegShiftedImm.SrcReg = SrcReg;
2246    Op->RegShiftedImm.ShiftImm = ShiftImm;
2247    Op->StartLoc = S;
2248    Op->EndLoc = E;
2249    return Op;
2250  }
2251
2252  static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
2253                                   SMLoc S, SMLoc E) {
2254    ARMOperand *Op = new ARMOperand(k_ShifterImmediate);
2255    Op->ShifterImm.isASR = isASR;
2256    Op->ShifterImm.Imm = Imm;
2257    Op->StartLoc = S;
2258    Op->EndLoc = E;
2259    return Op;
2260  }
2261
2262  static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
2263    ARMOperand *Op = new ARMOperand(k_RotateImmediate);
2264    Op->RotImm.Imm = Imm;
2265    Op->StartLoc = S;
2266    Op->EndLoc = E;
2267    return Op;
2268  }
2269
2270  static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
2271                                    SMLoc S, SMLoc E) {
2272    ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor);
2273    Op->Bitfield.LSB = LSB;
2274    Op->Bitfield.Width = Width;
2275    Op->StartLoc = S;
2276    Op->EndLoc = E;
2277    return Op;
2278  }
2279
2280  static ARMOperand *
2281  CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
2282                SMLoc StartLoc, SMLoc EndLoc) {
2283    KindTy Kind = k_RegisterList;
2284
2285    if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().first))
2286      Kind = k_DPRRegisterList;
2287    else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
2288             contains(Regs.front().first))
2289      Kind = k_SPRRegisterList;
2290
2291    ARMOperand *Op = new ARMOperand(Kind);
2292    for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
2293           I = Regs.begin(), E = Regs.end(); I != E; ++I)
2294      Op->Registers.push_back(I->first);
2295    array_pod_sort(Op->Registers.begin(), Op->Registers.end());
2296    Op->StartLoc = StartLoc;
2297    Op->EndLoc = EndLoc;
2298    return Op;
2299  }
2300
2301  static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count,
2302                                      bool isDoubleSpaced, SMLoc S, SMLoc E) {
2303    ARMOperand *Op = new ARMOperand(k_VectorList);
2304    Op->VectorList.RegNum = RegNum;
2305    Op->VectorList.Count = Count;
2306    Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2307    Op->StartLoc = S;
2308    Op->EndLoc = E;
2309    return Op;
2310  }
2311
2312  static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count,
2313                                              bool isDoubleSpaced,
2314                                              SMLoc S, SMLoc E) {
2315    ARMOperand *Op = new ARMOperand(k_VectorListAllLanes);
2316    Op->VectorList.RegNum = RegNum;
2317    Op->VectorList.Count = Count;
2318    Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2319    Op->StartLoc = S;
2320    Op->EndLoc = E;
2321    return Op;
2322  }
2323
2324  static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count,
2325                                             unsigned Index,
2326                                             bool isDoubleSpaced,
2327                                             SMLoc S, SMLoc E) {
2328    ARMOperand *Op = new ARMOperand(k_VectorListIndexed);
2329    Op->VectorList.RegNum = RegNum;
2330    Op->VectorList.Count = Count;
2331    Op->VectorList.LaneIndex = Index;
2332    Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2333    Op->StartLoc = S;
2334    Op->EndLoc = E;
2335    return Op;
2336  }
2337
2338  static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E,
2339                                       MCContext &Ctx) {
2340    ARMOperand *Op = new ARMOperand(k_VectorIndex);
2341    Op->VectorIndex.Val = Idx;
2342    Op->StartLoc = S;
2343    Op->EndLoc = E;
2344    return Op;
2345  }
2346
2347  static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
2348    ARMOperand *Op = new ARMOperand(k_Immediate);
2349    Op->Imm.Val = Val;
2350    Op->StartLoc = S;
2351    Op->EndLoc = E;
2352    return Op;
2353  }
2354
2355  static ARMOperand *CreateMem(unsigned BaseRegNum,
2356                               const MCConstantExpr *OffsetImm,
2357                               unsigned OffsetRegNum,
2358                               ARM_AM::ShiftOpc ShiftType,
2359                               unsigned ShiftImm,
2360                               unsigned Alignment,
2361                               bool isNegative,
2362                               SMLoc S, SMLoc E) {
2363    ARMOperand *Op = new ARMOperand(k_Memory);
2364    Op->Memory.BaseRegNum = BaseRegNum;
2365    Op->Memory.OffsetImm = OffsetImm;
2366    Op->Memory.OffsetRegNum = OffsetRegNum;
2367    Op->Memory.ShiftType = ShiftType;
2368    Op->Memory.ShiftImm = ShiftImm;
2369    Op->Memory.Alignment = Alignment;
2370    Op->Memory.isNegative = isNegative;
2371    Op->StartLoc = S;
2372    Op->EndLoc = E;
2373    return Op;
2374  }
2375
2376  static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
2377                                      ARM_AM::ShiftOpc ShiftTy,
2378                                      unsigned ShiftImm,
2379                                      SMLoc S, SMLoc E) {
2380    ARMOperand *Op = new ARMOperand(k_PostIndexRegister);
2381    Op->PostIdxReg.RegNum = RegNum;
2382    Op->PostIdxReg.isAdd = isAdd;
2383    Op->PostIdxReg.ShiftTy = ShiftTy;
2384    Op->PostIdxReg.ShiftImm = ShiftImm;
2385    Op->StartLoc = S;
2386    Op->EndLoc = E;
2387    return Op;
2388  }
2389
2390  static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
2391    ARMOperand *Op = new ARMOperand(k_MemBarrierOpt);
2392    Op->MBOpt.Val = Opt;
2393    Op->StartLoc = S;
2394    Op->EndLoc = S;
2395    return Op;
2396  }
2397
2398  static ARMOperand *CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt,
2399                                              SMLoc S) {
2400    ARMOperand *Op = new ARMOperand(k_InstSyncBarrierOpt);
2401    Op->ISBOpt.Val = Opt;
2402    Op->StartLoc = S;
2403    Op->EndLoc = S;
2404    return Op;
2405  }
2406
2407  static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
2408    ARMOperand *Op = new ARMOperand(k_ProcIFlags);
2409    Op->IFlags.Val = IFlags;
2410    Op->StartLoc = S;
2411    Op->EndLoc = S;
2412    return Op;
2413  }
2414
2415  static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
2416    ARMOperand *Op = new ARMOperand(k_MSRMask);
2417    Op->MMask.Val = MMask;
2418    Op->StartLoc = S;
2419    Op->EndLoc = S;
2420    return Op;
2421  }
2422};
2423
2424} // end anonymous namespace.
2425
2426void ARMOperand::print(raw_ostream &OS) const {
2427  switch (Kind) {
2428  case k_CondCode:
2429    OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
2430    break;
2431  case k_CCOut:
2432    OS << "<ccout " << getReg() << ">";
2433    break;
2434  case k_ITCondMask: {
2435    static const char *const MaskStr[] = {
2436      "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
2437      "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
2438    };
2439    assert((ITMask.Mask & 0xf) == ITMask.Mask);
2440    OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
2441    break;
2442  }
2443  case k_CoprocNum:
2444    OS << "<coprocessor number: " << getCoproc() << ">";
2445    break;
2446  case k_CoprocReg:
2447    OS << "<coprocessor register: " << getCoproc() << ">";
2448    break;
2449  case k_CoprocOption:
2450    OS << "<coprocessor option: " << CoprocOption.Val << ">";
2451    break;
2452  case k_MSRMask:
2453    OS << "<mask: " << getMSRMask() << ">";
2454    break;
2455  case k_Immediate:
2456    getImm()->print(OS);
2457    break;
2458  case k_MemBarrierOpt:
2459    OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
2460    break;
2461  case k_InstSyncBarrierOpt:
2462    OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">";
2463    break;
2464  case k_Memory:
2465    OS << "<memory "
2466       << " base:" << Memory.BaseRegNum;
2467    OS << ">";
2468    break;
2469  case k_PostIndexRegister:
2470    OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
2471       << PostIdxReg.RegNum;
2472    if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
2473      OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
2474         << PostIdxReg.ShiftImm;
2475    OS << ">";
2476    break;
2477  case k_ProcIFlags: {
2478    OS << "<ARM_PROC::";
2479    unsigned IFlags = getProcIFlags();
2480    for (int i=2; i >= 0; --i)
2481      if (IFlags & (1 << i))
2482        OS << ARM_PROC::IFlagsToString(1 << i);
2483    OS << ">";
2484    break;
2485  }
2486  case k_Register:
2487    OS << "<register " << getReg() << ">";
2488    break;
2489  case k_ShifterImmediate:
2490    OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
2491       << " #" << ShifterImm.Imm << ">";
2492    break;
2493  case k_ShiftedRegister:
2494    OS << "<so_reg_reg "
2495       << RegShiftedReg.SrcReg << " "
2496       << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
2497       << " " << RegShiftedReg.ShiftReg << ">";
2498    break;
2499  case k_ShiftedImmediate:
2500    OS << "<so_reg_imm "
2501       << RegShiftedImm.SrcReg << " "
2502       << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
2503       << " #" << RegShiftedImm.ShiftImm << ">";
2504    break;
2505  case k_RotateImmediate:
2506    OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
2507    break;
2508  case k_BitfieldDescriptor:
2509    OS << "<bitfield " << "lsb: " << Bitfield.LSB
2510       << ", width: " << Bitfield.Width << ">";
2511    break;
2512  case k_RegisterList:
2513  case k_DPRRegisterList:
2514  case k_SPRRegisterList: {
2515    OS << "<register_list ";
2516
2517    const SmallVectorImpl<unsigned> &RegList = getRegList();
2518    for (SmallVectorImpl<unsigned>::const_iterator
2519           I = RegList.begin(), E = RegList.end(); I != E; ) {
2520      OS << *I;
2521      if (++I < E) OS << ", ";
2522    }
2523
2524    OS << ">";
2525    break;
2526  }
2527  case k_VectorList:
2528    OS << "<vector_list " << VectorList.Count << " * "
2529       << VectorList.RegNum << ">";
2530    break;
2531  case k_VectorListAllLanes:
2532    OS << "<vector_list(all lanes) " << VectorList.Count << " * "
2533       << VectorList.RegNum << ">";
2534    break;
2535  case k_VectorListIndexed:
2536    OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
2537       << VectorList.Count << " * " << VectorList.RegNum << ">";
2538    break;
2539  case k_Token:
2540    OS << "'" << getToken() << "'";
2541    break;
2542  case k_VectorIndex:
2543    OS << "<vectorindex " << getVectorIndex() << ">";
2544    break;
2545  }
2546}
2547
2548/// @name Auto-generated Match Functions
2549/// {
2550
2551static unsigned MatchRegisterName(StringRef Name);
2552
2553/// }
2554
2555bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2556                                 SMLoc &StartLoc, SMLoc &EndLoc) {
2557  StartLoc = Parser.getTok().getLoc();
2558  EndLoc = Parser.getTok().getEndLoc();
2559  RegNo = tryParseRegister();
2560
2561  return (RegNo == (unsigned)-1);
2562}
2563
2564/// Try to parse a register name.  The token must be an Identifier when called,
2565/// and if it is a register name the token is eaten and the register number is
2566/// returned.  Otherwise return -1.
2567///
2568int ARMAsmParser::tryParseRegister() {
2569  const AsmToken &Tok = Parser.getTok();
2570  if (Tok.isNot(AsmToken::Identifier)) return -1;
2571
2572  std::string lowerCase = Tok.getString().lower();
2573  unsigned RegNum = MatchRegisterName(lowerCase);
2574  if (!RegNum) {
2575    RegNum = StringSwitch<unsigned>(lowerCase)
2576      .Case("r13", ARM::SP)
2577      .Case("r14", ARM::LR)
2578      .Case("r15", ARM::PC)
2579      .Case("ip", ARM::R12)
2580      // Additional register name aliases for 'gas' compatibility.
2581      .Case("a1", ARM::R0)
2582      .Case("a2", ARM::R1)
2583      .Case("a3", ARM::R2)
2584      .Case("a4", ARM::R3)
2585      .Case("v1", ARM::R4)
2586      .Case("v2", ARM::R5)
2587      .Case("v3", ARM::R6)
2588      .Case("v4", ARM::R7)
2589      .Case("v5", ARM::R8)
2590      .Case("v6", ARM::R9)
2591      .Case("v7", ARM::R10)
2592      .Case("v8", ARM::R11)
2593      .Case("sb", ARM::R9)
2594      .Case("sl", ARM::R10)
2595      .Case("fp", ARM::R11)
2596      .Default(0);
2597  }
2598  if (!RegNum) {
2599    // Check for aliases registered via .req. Canonicalize to lower case.
2600    // That's more consistent since register names are case insensitive, and
2601    // it's how the original entry was passed in from MC/MCParser/AsmParser.
2602    StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
2603    // If no match, return failure.
2604    if (Entry == RegisterReqs.end())
2605      return -1;
2606    Parser.Lex(); // Eat identifier token.
2607    return Entry->getValue();
2608  }
2609
2610  Parser.Lex(); // Eat identifier token.
2611
2612  return RegNum;
2613}
2614
2615// Try to parse a shifter  (e.g., "lsl <amt>"). On success, return 0.
2616// If a recoverable error occurs, return 1. If an irrecoverable error
2617// occurs, return -1. An irrecoverable error is one where tokens have been
2618// consumed in the process of trying to parse the shifter (i.e., when it is
2619// indeed a shifter operand, but malformed).
2620int ARMAsmParser::tryParseShiftRegister(
2621                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2622  SMLoc S = Parser.getTok().getLoc();
2623  const AsmToken &Tok = Parser.getTok();
2624  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2625
2626  std::string lowerCase = Tok.getString().lower();
2627  ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
2628      .Case("asl", ARM_AM::lsl)
2629      .Case("lsl", ARM_AM::lsl)
2630      .Case("lsr", ARM_AM::lsr)
2631      .Case("asr", ARM_AM::asr)
2632      .Case("ror", ARM_AM::ror)
2633      .Case("rrx", ARM_AM::rrx)
2634      .Default(ARM_AM::no_shift);
2635
2636  if (ShiftTy == ARM_AM::no_shift)
2637    return 1;
2638
2639  Parser.Lex(); // Eat the operator.
2640
2641  // The source register for the shift has already been added to the
2642  // operand list, so we need to pop it off and combine it into the shifted
2643  // register operand instead.
2644  OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
2645  if (!PrevOp->isReg())
2646    return Error(PrevOp->getStartLoc(), "shift must be of a register");
2647  int SrcReg = PrevOp->getReg();
2648
2649  SMLoc EndLoc;
2650  int64_t Imm = 0;
2651  int ShiftReg = 0;
2652  if (ShiftTy == ARM_AM::rrx) {
2653    // RRX Doesn't have an explicit shift amount. The encoder expects
2654    // the shift register to be the same as the source register. Seems odd,
2655    // but OK.
2656    ShiftReg = SrcReg;
2657  } else {
2658    // Figure out if this is shifted by a constant or a register (for non-RRX).
2659    if (Parser.getTok().is(AsmToken::Hash) ||
2660        Parser.getTok().is(AsmToken::Dollar)) {
2661      Parser.Lex(); // Eat hash.
2662      SMLoc ImmLoc = Parser.getTok().getLoc();
2663      const MCExpr *ShiftExpr = 0;
2664      if (getParser().parseExpression(ShiftExpr, EndLoc)) {
2665        Error(ImmLoc, "invalid immediate shift value");
2666        return -1;
2667      }
2668      // The expression must be evaluatable as an immediate.
2669      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
2670      if (!CE) {
2671        Error(ImmLoc, "invalid immediate shift value");
2672        return -1;
2673      }
2674      // Range check the immediate.
2675      // lsl, ror: 0 <= imm <= 31
2676      // lsr, asr: 0 <= imm <= 32
2677      Imm = CE->getValue();
2678      if (Imm < 0 ||
2679          ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
2680          ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
2681        Error(ImmLoc, "immediate shift value out of range");
2682        return -1;
2683      }
2684      // shift by zero is a nop. Always send it through as lsl.
2685      // ('as' compatibility)
2686      if (Imm == 0)
2687        ShiftTy = ARM_AM::lsl;
2688    } else if (Parser.getTok().is(AsmToken::Identifier)) {
2689      SMLoc L = Parser.getTok().getLoc();
2690      EndLoc = Parser.getTok().getEndLoc();
2691      ShiftReg = tryParseRegister();
2692      if (ShiftReg == -1) {
2693        Error (L, "expected immediate or register in shift operand");
2694        return -1;
2695      }
2696    } else {
2697      Error (Parser.getTok().getLoc(),
2698                    "expected immediate or register in shift operand");
2699      return -1;
2700    }
2701  }
2702
2703  if (ShiftReg && ShiftTy != ARM_AM::rrx)
2704    Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
2705                                                         ShiftReg, Imm,
2706                                                         S, EndLoc));
2707  else
2708    Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
2709                                                          S, EndLoc));
2710
2711  return 0;
2712}
2713
2714
2715/// Try to parse a register name.  The token must be an Identifier when called.
2716/// If it's a register, an AsmOperand is created. Another AsmOperand is created
2717/// if there is a "writeback". 'true' if it's not a register.
2718///
2719/// TODO this is likely to change to allow different register types and or to
2720/// parse for a specific register type.
2721bool ARMAsmParser::
2722tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2723  const AsmToken &RegTok = Parser.getTok();
2724  int RegNo = tryParseRegister();
2725  if (RegNo == -1)
2726    return true;
2727
2728  Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(),
2729                                           RegTok.getEndLoc()));
2730
2731  const AsmToken &ExclaimTok = Parser.getTok();
2732  if (ExclaimTok.is(AsmToken::Exclaim)) {
2733    Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
2734                                               ExclaimTok.getLoc()));
2735    Parser.Lex(); // Eat exclaim token
2736    return false;
2737  }
2738
2739  // Also check for an index operand. This is only legal for vector registers,
2740  // but that'll get caught OK in operand matching, so we don't need to
2741  // explicitly filter everything else out here.
2742  if (Parser.getTok().is(AsmToken::LBrac)) {
2743    SMLoc SIdx = Parser.getTok().getLoc();
2744    Parser.Lex(); // Eat left bracket token.
2745
2746    const MCExpr *ImmVal;
2747    if (getParser().parseExpression(ImmVal))
2748      return true;
2749    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
2750    if (!MCE)
2751      return TokError("immediate value expected for vector index");
2752
2753    if (Parser.getTok().isNot(AsmToken::RBrac))
2754      return Error(Parser.getTok().getLoc(), "']' expected");
2755
2756    SMLoc E = Parser.getTok().getEndLoc();
2757    Parser.Lex(); // Eat right bracket token.
2758
2759    Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
2760                                                     SIdx, E,
2761                                                     getContext()));
2762  }
2763
2764  return false;
2765}
2766
2767/// MatchCoprocessorOperandName - Try to parse an coprocessor related
2768/// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
2769/// "c5", ...
2770static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
2771  // Use the same layout as the tablegen'erated register name matcher. Ugly,
2772  // but efficient.
2773  switch (Name.size()) {
2774  default: return -1;
2775  case 2:
2776    if (Name[0] != CoprocOp)
2777      return -1;
2778    switch (Name[1]) {
2779    default:  return -1;
2780    case '0': return 0;
2781    case '1': return 1;
2782    case '2': return 2;
2783    case '3': return 3;
2784    case '4': return 4;
2785    case '5': return 5;
2786    case '6': return 6;
2787    case '7': return 7;
2788    case '8': return 8;
2789    case '9': return 9;
2790    }
2791  case 3:
2792    if (Name[0] != CoprocOp || Name[1] != '1')
2793      return -1;
2794    switch (Name[2]) {
2795    default:  return -1;
2796    case '0': return 10;
2797    case '1': return 11;
2798    case '2': return 12;
2799    case '3': return 13;
2800    case '4': return 14;
2801    case '5': return 15;
2802    }
2803  }
2804}
2805
2806/// parseITCondCode - Try to parse a condition code for an IT instruction.
2807ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2808parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2809  SMLoc S = Parser.getTok().getLoc();
2810  const AsmToken &Tok = Parser.getTok();
2811  if (!Tok.is(AsmToken::Identifier))
2812    return MatchOperand_NoMatch;
2813  unsigned CC = StringSwitch<unsigned>(Tok.getString().lower())
2814    .Case("eq", ARMCC::EQ)
2815    .Case("ne", ARMCC::NE)
2816    .Case("hs", ARMCC::HS)
2817    .Case("cs", ARMCC::HS)
2818    .Case("lo", ARMCC::LO)
2819    .Case("cc", ARMCC::LO)
2820    .Case("mi", ARMCC::MI)
2821    .Case("pl", ARMCC::PL)
2822    .Case("vs", ARMCC::VS)
2823    .Case("vc", ARMCC::VC)
2824    .Case("hi", ARMCC::HI)
2825    .Case("ls", ARMCC::LS)
2826    .Case("ge", ARMCC::GE)
2827    .Case("lt", ARMCC::LT)
2828    .Case("gt", ARMCC::GT)
2829    .Case("le", ARMCC::LE)
2830    .Case("al", ARMCC::AL)
2831    .Default(~0U);
2832  if (CC == ~0U)
2833    return MatchOperand_NoMatch;
2834  Parser.Lex(); // Eat the token.
2835
2836  Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
2837
2838  return MatchOperand_Success;
2839}
2840
2841/// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
2842/// token must be an Identifier when called, and if it is a coprocessor
2843/// number, the token is eaten and the operand is added to the operand list.
2844ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2845parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2846  SMLoc S = Parser.getTok().getLoc();
2847  const AsmToken &Tok = Parser.getTok();
2848  if (Tok.isNot(AsmToken::Identifier))
2849    return MatchOperand_NoMatch;
2850
2851  int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
2852  if (Num == -1)
2853    return MatchOperand_NoMatch;
2854
2855  Parser.Lex(); // Eat identifier token.
2856  Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
2857  return MatchOperand_Success;
2858}
2859
2860/// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
2861/// token must be an Identifier when called, and if it is a coprocessor
2862/// number, the token is eaten and the operand is added to the operand list.
2863ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2864parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2865  SMLoc S = Parser.getTok().getLoc();
2866  const AsmToken &Tok = Parser.getTok();
2867  if (Tok.isNot(AsmToken::Identifier))
2868    return MatchOperand_NoMatch;
2869
2870  int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
2871  if (Reg == -1)
2872    return MatchOperand_NoMatch;
2873
2874  Parser.Lex(); // Eat identifier token.
2875  Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
2876  return MatchOperand_Success;
2877}
2878
2879/// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
2880/// coproc_option : '{' imm0_255 '}'
2881ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2882parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2883  SMLoc S = Parser.getTok().getLoc();
2884
2885  // If this isn't a '{', this isn't a coprocessor immediate operand.
2886  if (Parser.getTok().isNot(AsmToken::LCurly))
2887    return MatchOperand_NoMatch;
2888  Parser.Lex(); // Eat the '{'
2889
2890  const MCExpr *Expr;
2891  SMLoc Loc = Parser.getTok().getLoc();
2892  if (getParser().parseExpression(Expr)) {
2893    Error(Loc, "illegal expression");
2894    return MatchOperand_ParseFail;
2895  }
2896  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2897  if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
2898    Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
2899    return MatchOperand_ParseFail;
2900  }
2901  int Val = CE->getValue();
2902
2903  // Check for and consume the closing '}'
2904  if (Parser.getTok().isNot(AsmToken::RCurly))
2905    return MatchOperand_ParseFail;
2906  SMLoc E = Parser.getTok().getEndLoc();
2907  Parser.Lex(); // Eat the '}'
2908
2909  Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
2910  return MatchOperand_Success;
2911}
2912
2913// For register list parsing, we need to map from raw GPR register numbering
2914// to the enumeration values. The enumeration values aren't sorted by
2915// register number due to our using "sp", "lr" and "pc" as canonical names.
2916static unsigned getNextRegister(unsigned Reg) {
2917  // If this is a GPR, we need to do it manually, otherwise we can rely
2918  // on the sort ordering of the enumeration since the other reg-classes
2919  // are sane.
2920  if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2921    return Reg + 1;
2922  switch(Reg) {
2923  default: llvm_unreachable("Invalid GPR number!");
2924  case ARM::R0:  return ARM::R1;  case ARM::R1:  return ARM::R2;
2925  case ARM::R2:  return ARM::R3;  case ARM::R3:  return ARM::R4;
2926  case ARM::R4:  return ARM::R5;  case ARM::R5:  return ARM::R6;
2927  case ARM::R6:  return ARM::R7;  case ARM::R7:  return ARM::R8;
2928  case ARM::R8:  return ARM::R9;  case ARM::R9:  return ARM::R10;
2929  case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
2930  case ARM::R12: return ARM::SP;  case ARM::SP:  return ARM::LR;
2931  case ARM::LR:  return ARM::PC;  case ARM::PC:  return ARM::R0;
2932  }
2933}
2934
2935// Return the low-subreg of a given Q register.
2936static unsigned getDRegFromQReg(unsigned QReg) {
2937  switch (QReg) {
2938  default: llvm_unreachable("expected a Q register!");
2939  case ARM::Q0:  return ARM::D0;
2940  case ARM::Q1:  return ARM::D2;
2941  case ARM::Q2:  return ARM::D4;
2942  case ARM::Q3:  return ARM::D6;
2943  case ARM::Q4:  return ARM::D8;
2944  case ARM::Q5:  return ARM::D10;
2945  case ARM::Q6:  return ARM::D12;
2946  case ARM::Q7:  return ARM::D14;
2947  case ARM::Q8:  return ARM::D16;
2948  case ARM::Q9:  return ARM::D18;
2949  case ARM::Q10: return ARM::D20;
2950  case ARM::Q11: return ARM::D22;
2951  case ARM::Q12: return ARM::D24;
2952  case ARM::Q13: return ARM::D26;
2953  case ARM::Q14: return ARM::D28;
2954  case ARM::Q15: return ARM::D30;
2955  }
2956}
2957
2958/// Parse a register list.
2959bool ARMAsmParser::
2960parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2961  assert(Parser.getTok().is(AsmToken::LCurly) &&
2962         "Token is not a Left Curly Brace");
2963  SMLoc S = Parser.getTok().getLoc();
2964  Parser.Lex(); // Eat '{' token.
2965  SMLoc RegLoc = Parser.getTok().getLoc();
2966
2967  // Check the first register in the list to see what register class
2968  // this is a list of.
2969  int Reg = tryParseRegister();
2970  if (Reg == -1)
2971    return Error(RegLoc, "register expected");
2972
2973  // The reglist instructions have at most 16 registers, so reserve
2974  // space for that many.
2975  SmallVector<std::pair<unsigned, SMLoc>, 16> Registers;
2976
2977  // Allow Q regs and just interpret them as the two D sub-registers.
2978  if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2979    Reg = getDRegFromQReg(Reg);
2980    Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2981    ++Reg;
2982  }
2983  const MCRegisterClass *RC;
2984  if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2985    RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
2986  else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
2987    RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
2988  else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
2989    RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
2990  else
2991    return Error(RegLoc, "invalid register in register list");
2992
2993  // Store the register.
2994  Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2995
2996  // This starts immediately after the first register token in the list,
2997  // so we can see either a comma or a minus (range separator) as a legal
2998  // next token.
2999  while (Parser.getTok().is(AsmToken::Comma) ||
3000         Parser.getTok().is(AsmToken::Minus)) {
3001    if (Parser.getTok().is(AsmToken::Minus)) {
3002      Parser.Lex(); // Eat the minus.
3003      SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3004      int EndReg = tryParseRegister();
3005      if (EndReg == -1)
3006        return Error(AfterMinusLoc, "register expected");
3007      // Allow Q regs and just interpret them as the two D sub-registers.
3008      if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3009        EndReg = getDRegFromQReg(EndReg) + 1;
3010      // If the register is the same as the start reg, there's nothing
3011      // more to do.
3012      if (Reg == EndReg)
3013        continue;
3014      // The register must be in the same register class as the first.
3015      if (!RC->contains(EndReg))
3016        return Error(AfterMinusLoc, "invalid register in register list");
3017      // Ranges must go from low to high.
3018      if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
3019        return Error(AfterMinusLoc, "bad range in register list");
3020
3021      // Add all the registers in the range to the register list.
3022      while (Reg != EndReg) {
3023        Reg = getNextRegister(Reg);
3024        Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
3025      }
3026      continue;
3027    }
3028    Parser.Lex(); // Eat the comma.
3029    RegLoc = Parser.getTok().getLoc();
3030    int OldReg = Reg;
3031    const AsmToken RegTok = Parser.getTok();
3032    Reg = tryParseRegister();
3033    if (Reg == -1)
3034      return Error(RegLoc, "register expected");
3035    // Allow Q regs and just interpret them as the two D sub-registers.
3036    bool isQReg = false;
3037    if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3038      Reg = getDRegFromQReg(Reg);
3039      isQReg = true;
3040    }
3041    // The register must be in the same register class as the first.
3042    if (!RC->contains(Reg))
3043      return Error(RegLoc, "invalid register in register list");
3044    // List must be monotonically increasing.
3045    if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
3046      if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3047        Warning(RegLoc, "register list not in ascending order");
3048      else
3049        return Error(RegLoc, "register list not in ascending order");
3050    }
3051    if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
3052      Warning(RegLoc, "duplicated register (" + RegTok.getString() +
3053              ") in register list");
3054      continue;
3055    }
3056    // VFP register lists must also be contiguous.
3057    // It's OK to use the enumeration values directly here rather, as the
3058    // VFP register classes have the enum sorted properly.
3059    if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
3060        Reg != OldReg + 1)
3061      return Error(RegLoc, "non-contiguous register range");
3062    Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
3063    if (isQReg)
3064      Registers.push_back(std::pair<unsigned, SMLoc>(++Reg, RegLoc));
3065  }
3066
3067  if (Parser.getTok().isNot(AsmToken::RCurly))
3068    return Error(Parser.getTok().getLoc(), "'}' expected");
3069  SMLoc E = Parser.getTok().getEndLoc();
3070  Parser.Lex(); // Eat '}' token.
3071
3072  // Push the register list operand.
3073  Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
3074
3075  // The ARM system instruction variants for LDM/STM have a '^' token here.
3076  if (Parser.getTok().is(AsmToken::Caret)) {
3077    Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
3078    Parser.Lex(); // Eat '^' token.
3079  }
3080
3081  return false;
3082}
3083
3084// Helper function to parse the lane index for vector lists.
3085ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3086parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
3087  Index = 0; // Always return a defined index value.
3088  if (Parser.getTok().is(AsmToken::LBrac)) {
3089    Parser.Lex(); // Eat the '['.
3090    if (Parser.getTok().is(AsmToken::RBrac)) {
3091      // "Dn[]" is the 'all lanes' syntax.
3092      LaneKind = AllLanes;
3093      EndLoc = Parser.getTok().getEndLoc();
3094      Parser.Lex(); // Eat the ']'.
3095      return MatchOperand_Success;
3096    }
3097
3098    // There's an optional '#' token here. Normally there wouldn't be, but
3099    // inline assemble puts one in, and it's friendly to accept that.
3100    if (Parser.getTok().is(AsmToken::Hash))
3101      Parser.Lex(); // Eat '#' or '$'.
3102
3103    const MCExpr *LaneIndex;
3104    SMLoc Loc = Parser.getTok().getLoc();
3105    if (getParser().parseExpression(LaneIndex)) {
3106      Error(Loc, "illegal expression");
3107      return MatchOperand_ParseFail;
3108    }
3109    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
3110    if (!CE) {
3111      Error(Loc, "lane index must be empty or an integer");
3112      return MatchOperand_ParseFail;
3113    }
3114    if (Parser.getTok().isNot(AsmToken::RBrac)) {
3115      Error(Parser.getTok().getLoc(), "']' expected");
3116      return MatchOperand_ParseFail;
3117    }
3118    EndLoc = Parser.getTok().getEndLoc();
3119    Parser.Lex(); // Eat the ']'.
3120    int64_t Val = CE->getValue();
3121
3122    // FIXME: Make this range check context sensitive for .8, .16, .32.
3123    if (Val < 0 || Val > 7) {
3124      Error(Parser.getTok().getLoc(), "lane index out of range");
3125      return MatchOperand_ParseFail;
3126    }
3127    Index = Val;
3128    LaneKind = IndexedLane;
3129    return MatchOperand_Success;
3130  }
3131  LaneKind = NoLanes;
3132  return MatchOperand_Success;
3133}
3134
3135// parse a vector register list
3136ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3137parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3138  VectorLaneTy LaneKind;
3139  unsigned LaneIndex;
3140  SMLoc S = Parser.getTok().getLoc();
3141  // As an extension (to match gas), support a plain D register or Q register
3142  // (without encosing curly braces) as a single or double entry list,
3143  // respectively.
3144  if (Parser.getTok().is(AsmToken::Identifier)) {
3145    SMLoc E = Parser.getTok().getEndLoc();
3146    int Reg = tryParseRegister();
3147    if (Reg == -1)
3148      return MatchOperand_NoMatch;
3149    if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
3150      OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3151      if (Res != MatchOperand_Success)
3152        return Res;
3153      switch (LaneKind) {
3154      case NoLanes:
3155        Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
3156        break;
3157      case AllLanes:
3158        Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
3159                                                                S, E));
3160        break;
3161      case IndexedLane:
3162        Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
3163                                                               LaneIndex,
3164                                                               false, S, E));
3165        break;
3166      }
3167      return MatchOperand_Success;
3168    }
3169    if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3170      Reg = getDRegFromQReg(Reg);
3171      OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3172      if (Res != MatchOperand_Success)
3173        return Res;
3174      switch (LaneKind) {
3175      case NoLanes:
3176        Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3177                                   &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3178        Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
3179        break;
3180      case AllLanes:
3181        Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3182                                   &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3183        Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
3184                                                                S, E));
3185        break;
3186      case IndexedLane:
3187        Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
3188                                                               LaneIndex,
3189                                                               false, S, E));
3190        break;
3191      }
3192      return MatchOperand_Success;
3193    }
3194    Error(S, "vector register expected");
3195    return MatchOperand_ParseFail;
3196  }
3197
3198  if (Parser.getTok().isNot(AsmToken::LCurly))
3199    return MatchOperand_NoMatch;
3200
3201  Parser.Lex(); // Eat '{' token.
3202  SMLoc RegLoc = Parser.getTok().getLoc();
3203
3204  int Reg = tryParseRegister();
3205  if (Reg == -1) {
3206    Error(RegLoc, "register expected");
3207    return MatchOperand_ParseFail;
3208  }
3209  unsigned Count = 1;
3210  int Spacing = 0;
3211  unsigned FirstReg = Reg;
3212  // The list is of D registers, but we also allow Q regs and just interpret
3213  // them as the two D sub-registers.
3214  if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3215    FirstReg = Reg = getDRegFromQReg(Reg);
3216    Spacing = 1; // double-spacing requires explicit D registers, otherwise
3217                 // it's ambiguous with four-register single spaced.
3218    ++Reg;
3219    ++Count;
3220  }
3221
3222  SMLoc E;
3223  if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success)
3224    return MatchOperand_ParseFail;
3225
3226  while (Parser.getTok().is(AsmToken::Comma) ||
3227         Parser.getTok().is(AsmToken::Minus)) {
3228    if (Parser.getTok().is(AsmToken::Minus)) {
3229      if (!Spacing)
3230        Spacing = 1; // Register range implies a single spaced list.
3231      else if (Spacing == 2) {
3232        Error(Parser.getTok().getLoc(),
3233              "sequential registers in double spaced list");
3234        return MatchOperand_ParseFail;
3235      }
3236      Parser.Lex(); // Eat the minus.
3237      SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3238      int EndReg = tryParseRegister();
3239      if (EndReg == -1) {
3240        Error(AfterMinusLoc, "register expected");
3241        return MatchOperand_ParseFail;
3242      }
3243      // Allow Q regs and just interpret them as the two D sub-registers.
3244      if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3245        EndReg = getDRegFromQReg(EndReg) + 1;
3246      // If the register is the same as the start reg, there's nothing
3247      // more to do.
3248      if (Reg == EndReg)
3249        continue;
3250      // The register must be in the same register class as the first.
3251      if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
3252        Error(AfterMinusLoc, "invalid register in register list");
3253        return MatchOperand_ParseFail;
3254      }
3255      // Ranges must go from low to high.
3256      if (Reg > EndReg) {
3257        Error(AfterMinusLoc, "bad range in register list");
3258        return MatchOperand_ParseFail;
3259      }
3260      // Parse the lane specifier if present.
3261      VectorLaneTy NextLaneKind;
3262      unsigned NextLaneIndex;
3263      if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3264          MatchOperand_Success)
3265        return MatchOperand_ParseFail;
3266      if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3267        Error(AfterMinusLoc, "mismatched lane index in register list");
3268        return MatchOperand_ParseFail;
3269      }
3270
3271      // Add all the registers in the range to the register list.
3272      Count += EndReg - Reg;
3273      Reg = EndReg;
3274      continue;
3275    }
3276    Parser.Lex(); // Eat the comma.
3277    RegLoc = Parser.getTok().getLoc();
3278    int OldReg = Reg;
3279    Reg = tryParseRegister();
3280    if (Reg == -1) {
3281      Error(RegLoc, "register expected");
3282      return MatchOperand_ParseFail;
3283    }
3284    // vector register lists must be contiguous.
3285    // It's OK to use the enumeration values directly here rather, as the
3286    // VFP register classes have the enum sorted properly.
3287    //
3288    // The list is of D registers, but we also allow Q regs and just interpret
3289    // them as the two D sub-registers.
3290    if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3291      if (!Spacing)
3292        Spacing = 1; // Register range implies a single spaced list.
3293      else if (Spacing == 2) {
3294        Error(RegLoc,
3295              "invalid register in double-spaced list (must be 'D' register')");
3296        return MatchOperand_ParseFail;
3297      }
3298      Reg = getDRegFromQReg(Reg);
3299      if (Reg != OldReg + 1) {
3300        Error(RegLoc, "non-contiguous register range");
3301        return MatchOperand_ParseFail;
3302      }
3303      ++Reg;
3304      Count += 2;
3305      // Parse the lane specifier if present.
3306      VectorLaneTy NextLaneKind;
3307      unsigned NextLaneIndex;
3308      SMLoc LaneLoc = Parser.getTok().getLoc();
3309      if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3310          MatchOperand_Success)
3311        return MatchOperand_ParseFail;
3312      if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3313        Error(LaneLoc, "mismatched lane index in register list");
3314        return MatchOperand_ParseFail;
3315      }
3316      continue;
3317    }
3318    // Normal D register.
3319    // Figure out the register spacing (single or double) of the list if
3320    // we don't know it already.
3321    if (!Spacing)
3322      Spacing = 1 + (Reg == OldReg + 2);
3323
3324    // Just check that it's contiguous and keep going.
3325    if (Reg != OldReg + Spacing) {
3326      Error(RegLoc, "non-contiguous register range");
3327      return MatchOperand_ParseFail;
3328    }
3329    ++Count;
3330    // Parse the lane specifier if present.
3331    VectorLaneTy NextLaneKind;
3332    unsigned NextLaneIndex;
3333    SMLoc EndLoc = Parser.getTok().getLoc();
3334    if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success)
3335      return MatchOperand_ParseFail;
3336    if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3337      Error(EndLoc, "mismatched lane index in register list");
3338      return MatchOperand_ParseFail;
3339    }
3340  }
3341
3342  if (Parser.getTok().isNot(AsmToken::RCurly)) {
3343    Error(Parser.getTok().getLoc(), "'}' expected");
3344    return MatchOperand_ParseFail;
3345  }
3346  E = Parser.getTok().getEndLoc();
3347  Parser.Lex(); // Eat '}' token.
3348
3349  switch (LaneKind) {
3350  case NoLanes:
3351    // Two-register operands have been converted to the
3352    // composite register classes.
3353    if (Count == 2) {
3354      const MCRegisterClass *RC = (Spacing == 1) ?
3355        &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3356        &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3357      FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3358    }
3359
3360    Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
3361                                                    (Spacing == 2), S, E));
3362    break;
3363  case AllLanes:
3364    // Two-register operands have been converted to the
3365    // composite register classes.
3366    if (Count == 2) {
3367      const MCRegisterClass *RC = (Spacing == 1) ?
3368        &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3369        &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3370      FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3371    }
3372    Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
3373                                                            (Spacing == 2),
3374                                                            S, E));
3375    break;
3376  case IndexedLane:
3377    Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
3378                                                           LaneIndex,
3379                                                           (Spacing == 2),
3380                                                           S, E));
3381    break;
3382  }
3383  return MatchOperand_Success;
3384}
3385
3386/// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
3387ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3388parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3389  SMLoc S = Parser.getTok().getLoc();
3390  const AsmToken &Tok = Parser.getTok();
3391  unsigned Opt;
3392
3393  if (Tok.is(AsmToken::Identifier)) {
3394    StringRef OptStr = Tok.getString();
3395
3396    Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
3397      .Case("sy",    ARM_MB::SY)
3398      .Case("st",    ARM_MB::ST)
3399      .Case("sh",    ARM_MB::ISH)
3400      .Case("ish",   ARM_MB::ISH)
3401      .Case("shst",  ARM_MB::ISHST)
3402      .Case("ishst", ARM_MB::ISHST)
3403      .Case("nsh",   ARM_MB::NSH)
3404      .Case("un",    ARM_MB::NSH)
3405      .Case("nshst", ARM_MB::NSHST)
3406      .Case("unst",  ARM_MB::NSHST)
3407      .Case("osh",   ARM_MB::OSH)
3408      .Case("oshst", ARM_MB::OSHST)
3409      .Default(~0U);
3410
3411    if (Opt == ~0U)
3412      return MatchOperand_NoMatch;
3413
3414    Parser.Lex(); // Eat identifier token.
3415  } else if (Tok.is(AsmToken::Hash) ||
3416             Tok.is(AsmToken::Dollar) ||
3417             Tok.is(AsmToken::Integer)) {
3418    if (Parser.getTok().isNot(AsmToken::Integer))
3419      Parser.Lex(); // Eat '#' or '$'.
3420    SMLoc Loc = Parser.getTok().getLoc();
3421
3422    const MCExpr *MemBarrierID;
3423    if (getParser().parseExpression(MemBarrierID)) {
3424      Error(Loc, "illegal expression");
3425      return MatchOperand_ParseFail;
3426    }
3427
3428    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
3429    if (!CE) {
3430      Error(Loc, "constant expression expected");
3431      return MatchOperand_ParseFail;
3432    }
3433
3434    int Val = CE->getValue();
3435    if (Val & ~0xf) {
3436      Error(Loc, "immediate value out of range");
3437      return MatchOperand_ParseFail;
3438    }
3439
3440    Opt = ARM_MB::RESERVED_0 + Val;
3441  } else
3442    return MatchOperand_ParseFail;
3443
3444  Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
3445  return MatchOperand_Success;
3446}
3447
3448/// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options.
3449ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3450parseInstSyncBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3451  SMLoc S = Parser.getTok().getLoc();
3452  const AsmToken &Tok = Parser.getTok();
3453  unsigned Opt;
3454
3455  if (Tok.is(AsmToken::Identifier)) {
3456    StringRef OptStr = Tok.getString();
3457
3458    if (OptStr.lower() == "sy")
3459      Opt = ARM_ISB::SY;
3460    else
3461      return MatchOperand_NoMatch;
3462
3463    Parser.Lex(); // Eat identifier token.
3464  } else if (Tok.is(AsmToken::Hash) ||
3465             Tok.is(AsmToken::Dollar) ||
3466             Tok.is(AsmToken::Integer)) {
3467    if (Parser.getTok().isNot(AsmToken::Integer))
3468      Parser.Lex(); // Eat '#' or '$'.
3469    SMLoc Loc = Parser.getTok().getLoc();
3470
3471    const MCExpr *ISBarrierID;
3472    if (getParser().parseExpression(ISBarrierID)) {
3473      Error(Loc, "illegal expression");
3474      return MatchOperand_ParseFail;
3475    }
3476
3477    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID);
3478    if (!CE) {
3479      Error(Loc, "constant expression expected");
3480      return MatchOperand_ParseFail;
3481    }
3482
3483    int Val = CE->getValue();
3484    if (Val & ~0xf) {
3485      Error(Loc, "immediate value out of range");
3486      return MatchOperand_ParseFail;
3487    }
3488
3489    Opt = ARM_ISB::RESERVED_0 + Val;
3490  } else
3491    return MatchOperand_ParseFail;
3492
3493  Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt(
3494          (ARM_ISB::InstSyncBOpt)Opt, S));
3495  return MatchOperand_Success;
3496}
3497
3498
3499/// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
3500ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3501parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3502  SMLoc S = Parser.getTok().getLoc();
3503  const AsmToken &Tok = Parser.getTok();
3504  if (!Tok.is(AsmToken::Identifier))
3505    return MatchOperand_NoMatch;
3506  StringRef IFlagsStr = Tok.getString();
3507
3508  // An iflags string of "none" is interpreted to mean that none of the AIF
3509  // bits are set.  Not a terribly useful instruction, but a valid encoding.
3510  unsigned IFlags = 0;
3511  if (IFlagsStr != "none") {
3512        for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
3513      unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
3514        .Case("a", ARM_PROC::A)
3515        .Case("i", ARM_PROC::I)
3516        .Case("f", ARM_PROC::F)
3517        .Default(~0U);
3518
3519      // If some specific iflag is already set, it means that some letter is
3520      // present more than once, this is not acceptable.
3521      if (Flag == ~0U || (IFlags & Flag))
3522        return MatchOperand_NoMatch;
3523
3524      IFlags |= Flag;
3525    }
3526  }
3527
3528  Parser.Lex(); // Eat identifier token.
3529  Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
3530  return MatchOperand_Success;
3531}
3532
3533/// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
3534ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3535parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3536  SMLoc S = Parser.getTok().getLoc();
3537  const AsmToken &Tok = Parser.getTok();
3538  if (!Tok.is(AsmToken::Identifier))
3539    return MatchOperand_NoMatch;
3540  StringRef Mask = Tok.getString();
3541
3542  if (isMClass()) {
3543    // See ARMv6-M 10.1.1
3544    std::string Name = Mask.lower();
3545    unsigned FlagsVal = StringSwitch<unsigned>(Name)
3546      // Note: in the documentation:
3547      //  ARM deprecates using MSR APSR without a _<bits> qualifier as an alias
3548      //  for MSR APSR_nzcvq.
3549      // but we do make it an alias here.  This is so to get the "mask encoding"
3550      // bits correct on MSR APSR writes.
3551      //
3552      // FIXME: Note the 0xc00 "mask encoding" bits version of the registers
3553      // should really only be allowed when writing a special register.  Note
3554      // they get dropped in the MRS instruction reading a special register as
3555      // the SYSm field is only 8 bits.
3556      //
3557      // FIXME: the _g and _nzcvqg versions are only allowed if the processor
3558      // includes the DSP extension but that is not checked.
3559      .Case("apsr", 0x800)
3560      .Case("apsr_nzcvq", 0x800)
3561      .Case("apsr_g", 0x400)
3562      .Case("apsr_nzcvqg", 0xc00)
3563      .Case("iapsr", 0x801)
3564      .Case("iapsr_nzcvq", 0x801)
3565      .Case("iapsr_g", 0x401)
3566      .Case("iapsr_nzcvqg", 0xc01)
3567      .Case("eapsr", 0x802)
3568      .Case("eapsr_nzcvq", 0x802)
3569      .Case("eapsr_g", 0x402)
3570      .Case("eapsr_nzcvqg", 0xc02)
3571      .Case("xpsr", 0x803)
3572      .Case("xpsr_nzcvq", 0x803)
3573      .Case("xpsr_g", 0x403)
3574      .Case("xpsr_nzcvqg", 0xc03)
3575      .Case("ipsr", 0x805)
3576      .Case("epsr", 0x806)
3577      .Case("iepsr", 0x807)
3578      .Case("msp", 0x808)
3579      .Case("psp", 0x809)
3580      .Case("primask", 0x810)
3581      .Case("basepri", 0x811)
3582      .Case("basepri_max", 0x812)
3583      .Case("faultmask", 0x813)
3584      .Case("control", 0x814)
3585      .Default(~0U);
3586
3587    if (FlagsVal == ~0U)
3588      return MatchOperand_NoMatch;
3589
3590    if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813)
3591      // basepri, basepri_max and faultmask only valid for V7m.
3592      return MatchOperand_NoMatch;
3593
3594    Parser.Lex(); // Eat identifier token.
3595    Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3596    return MatchOperand_Success;
3597  }
3598
3599  // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
3600  size_t Start = 0, Next = Mask.find('_');
3601  StringRef Flags = "";
3602  std::string SpecReg = Mask.slice(Start, Next).lower();
3603  if (Next != StringRef::npos)
3604    Flags = Mask.slice(Next+1, Mask.size());
3605
3606  // FlagsVal contains the complete mask:
3607  // 3-0: Mask
3608  // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3609  unsigned FlagsVal = 0;
3610
3611  if (SpecReg == "apsr") {
3612    FlagsVal = StringSwitch<unsigned>(Flags)
3613    .Case("nzcvq",  0x8) // same as CPSR_f
3614    .Case("g",      0x4) // same as CPSR_s
3615    .Case("nzcvqg", 0xc) // same as CPSR_fs
3616    .Default(~0U);
3617
3618    if (FlagsVal == ~0U) {
3619      if (!Flags.empty())
3620        return MatchOperand_NoMatch;
3621      else
3622        FlagsVal = 8; // No flag
3623    }
3624  } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
3625    // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
3626    if (Flags == "all" || Flags == "")
3627      Flags = "fc";
3628    for (int i = 0, e = Flags.size(); i != e; ++i) {
3629      unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
3630      .Case("c", 1)
3631      .Case("x", 2)
3632      .Case("s", 4)
3633      .Case("f", 8)
3634      .Default(~0U);
3635
3636      // If some specific flag is already set, it means that some letter is
3637      // present more than once, this is not acceptable.
3638      if (FlagsVal == ~0U || (FlagsVal & Flag))
3639        return MatchOperand_NoMatch;
3640      FlagsVal |= Flag;
3641    }
3642  } else // No match for special register.
3643    return MatchOperand_NoMatch;
3644
3645  // Special register without flags is NOT equivalent to "fc" flags.
3646  // NOTE: This is a divergence from gas' behavior.  Uncommenting the following
3647  // two lines would enable gas compatibility at the expense of breaking
3648  // round-tripping.
3649  //
3650  // if (!FlagsVal)
3651  //  FlagsVal = 0x9;
3652
3653  // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3654  if (SpecReg == "spsr")
3655    FlagsVal |= 16;
3656
3657  Parser.Lex(); // Eat identifier token.
3658  Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3659  return MatchOperand_Success;
3660}
3661
3662ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3663parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
3664            int Low, int High) {
3665  const AsmToken &Tok = Parser.getTok();
3666  if (Tok.isNot(AsmToken::Identifier)) {
3667    Error(Parser.getTok().getLoc(), Op + " operand expected.");
3668    return MatchOperand_ParseFail;
3669  }
3670  StringRef ShiftName = Tok.getString();
3671  std::string LowerOp = Op.lower();
3672  std::string UpperOp = Op.upper();
3673  if (ShiftName != LowerOp && ShiftName != UpperOp) {
3674    Error(Parser.getTok().getLoc(), Op + " operand expected.");
3675    return MatchOperand_ParseFail;
3676  }
3677  Parser.Lex(); // Eat shift type token.
3678
3679  // There must be a '#' and a shift amount.
3680  if (Parser.getTok().isNot(AsmToken::Hash) &&
3681      Parser.getTok().isNot(AsmToken::Dollar)) {
3682    Error(Parser.getTok().getLoc(), "'#' expected");
3683    return MatchOperand_ParseFail;
3684  }
3685  Parser.Lex(); // Eat hash token.
3686
3687  const MCExpr *ShiftAmount;
3688  SMLoc Loc = Parser.getTok().getLoc();
3689  SMLoc EndLoc;
3690  if (getParser().parseExpression(ShiftAmount, EndLoc)) {
3691    Error(Loc, "illegal expression");
3692    return MatchOperand_ParseFail;
3693  }
3694  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3695  if (!CE) {
3696    Error(Loc, "constant expression expected");
3697    return MatchOperand_ParseFail;
3698  }
3699  int Val = CE->getValue();
3700  if (Val < Low || Val > High) {
3701    Error(Loc, "immediate value out of range");
3702    return MatchOperand_ParseFail;
3703  }
3704
3705  Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc));
3706
3707  return MatchOperand_Success;
3708}
3709
3710ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3711parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3712  const AsmToken &Tok = Parser.getTok();
3713  SMLoc S = Tok.getLoc();
3714  if (Tok.isNot(AsmToken::Identifier)) {
3715    Error(S, "'be' or 'le' operand expected");
3716    return MatchOperand_ParseFail;
3717  }
3718  int Val = StringSwitch<int>(Tok.getString().lower())
3719    .Case("be", 1)
3720    .Case("le", 0)
3721    .Default(-1);
3722  Parser.Lex(); // Eat the token.
3723
3724  if (Val == -1) {
3725    Error(S, "'be' or 'le' operand expected");
3726    return MatchOperand_ParseFail;
3727  }
3728  Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
3729                                                                  getContext()),
3730                                           S, Tok.getEndLoc()));
3731  return MatchOperand_Success;
3732}
3733
3734/// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
3735/// instructions. Legal values are:
3736///     lsl #n  'n' in [0,31]
3737///     asr #n  'n' in [1,32]
3738///             n == 32 encoded as n == 0.
3739ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3740parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3741  const AsmToken &Tok = Parser.getTok();
3742  SMLoc S = Tok.getLoc();
3743  if (Tok.isNot(AsmToken::Identifier)) {
3744    Error(S, "shift operator 'asr' or 'lsl' expected");
3745    return MatchOperand_ParseFail;
3746  }
3747  StringRef ShiftName = Tok.getString();
3748  bool isASR;
3749  if (ShiftName == "lsl" || ShiftName == "LSL")
3750    isASR = false;
3751  else if (ShiftName == "asr" || ShiftName == "ASR")
3752    isASR = true;
3753  else {
3754    Error(S, "shift operator 'asr' or 'lsl' expected");
3755    return MatchOperand_ParseFail;
3756  }
3757  Parser.Lex(); // Eat the operator.
3758
3759  // A '#' and a shift amount.
3760  if (Parser.getTok().isNot(AsmToken::Hash) &&
3761      Parser.getTok().isNot(AsmToken::Dollar)) {
3762    Error(Parser.getTok().getLoc(), "'#' expected");
3763    return MatchOperand_ParseFail;
3764  }
3765  Parser.Lex(); // Eat hash token.
3766  SMLoc ExLoc = Parser.getTok().getLoc();
3767
3768  const MCExpr *ShiftAmount;
3769  SMLoc EndLoc;
3770  if (getParser().parseExpression(ShiftAmount, EndLoc)) {
3771    Error(ExLoc, "malformed shift expression");
3772    return MatchOperand_ParseFail;
3773  }
3774  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3775  if (!CE) {
3776    Error(ExLoc, "shift amount must be an immediate");
3777    return MatchOperand_ParseFail;
3778  }
3779
3780  int64_t Val = CE->getValue();
3781  if (isASR) {
3782    // Shift amount must be in [1,32]
3783    if (Val < 1 || Val > 32) {
3784      Error(ExLoc, "'asr' shift amount must be in range [1,32]");
3785      return MatchOperand_ParseFail;
3786    }
3787    // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
3788    if (isThumb() && Val == 32) {
3789      Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode");
3790      return MatchOperand_ParseFail;
3791    }
3792    if (Val == 32) Val = 0;
3793  } else {
3794    // Shift amount must be in [1,32]
3795    if (Val < 0 || Val > 31) {
3796      Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
3797      return MatchOperand_ParseFail;
3798    }
3799  }
3800
3801  Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc));
3802
3803  return MatchOperand_Success;
3804}
3805
3806/// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
3807/// of instructions. Legal values are:
3808///     ror #n  'n' in {0, 8, 16, 24}
3809ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3810parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3811  const AsmToken &Tok = Parser.getTok();
3812  SMLoc S = Tok.getLoc();
3813  if (Tok.isNot(AsmToken::Identifier))
3814    return MatchOperand_NoMatch;
3815  StringRef ShiftName = Tok.getString();
3816  if (ShiftName != "ror" && ShiftName != "ROR")
3817    return MatchOperand_NoMatch;
3818  Parser.Lex(); // Eat the operator.
3819
3820  // A '#' and a rotate amount.
3821  if (Parser.getTok().isNot(AsmToken::Hash) &&
3822      Parser.getTok().isNot(AsmToken::Dollar)) {
3823    Error(Parser.getTok().getLoc(), "'#' expected");
3824    return MatchOperand_ParseFail;
3825  }
3826  Parser.Lex(); // Eat hash token.
3827  SMLoc ExLoc = Parser.getTok().getLoc();
3828
3829  const MCExpr *ShiftAmount;
3830  SMLoc EndLoc;
3831  if (getParser().parseExpression(ShiftAmount, EndLoc)) {
3832    Error(ExLoc, "malformed rotate expression");
3833    return MatchOperand_ParseFail;
3834  }
3835  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3836  if (!CE) {
3837    Error(ExLoc, "rotate amount must be an immediate");
3838    return MatchOperand_ParseFail;
3839  }
3840
3841  int64_t Val = CE->getValue();
3842  // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
3843  // normally, zero is represented in asm by omitting the rotate operand
3844  // entirely.
3845  if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
3846    Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24");
3847    return MatchOperand_ParseFail;
3848  }
3849
3850  Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc));
3851
3852  return MatchOperand_Success;
3853}
3854
3855ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3856parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3857  SMLoc S = Parser.getTok().getLoc();
3858  // The bitfield descriptor is really two operands, the LSB and the width.
3859  if (Parser.getTok().isNot(AsmToken::Hash) &&
3860      Parser.getTok().isNot(AsmToken::Dollar)) {
3861    Error(Parser.getTok().getLoc(), "'#' expected");
3862    return MatchOperand_ParseFail;
3863  }
3864  Parser.Lex(); // Eat hash token.
3865
3866  const MCExpr *LSBExpr;
3867  SMLoc E = Parser.getTok().getLoc();
3868  if (getParser().parseExpression(LSBExpr)) {
3869    Error(E, "malformed immediate expression");
3870    return MatchOperand_ParseFail;
3871  }
3872  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
3873  if (!CE) {
3874    Error(E, "'lsb' operand must be an immediate");
3875    return MatchOperand_ParseFail;
3876  }
3877
3878  int64_t LSB = CE->getValue();
3879  // The LSB must be in the range [0,31]
3880  if (LSB < 0 || LSB > 31) {
3881    Error(E, "'lsb' operand must be in the range [0,31]");
3882    return MatchOperand_ParseFail;
3883  }
3884  E = Parser.getTok().getLoc();
3885
3886  // Expect another immediate operand.
3887  if (Parser.getTok().isNot(AsmToken::Comma)) {
3888    Error(Parser.getTok().getLoc(), "too few operands");
3889    return MatchOperand_ParseFail;
3890  }
3891  Parser.Lex(); // Eat hash token.
3892  if (Parser.getTok().isNot(AsmToken::Hash) &&
3893      Parser.getTok().isNot(AsmToken::Dollar)) {
3894    Error(Parser.getTok().getLoc(), "'#' expected");
3895    return MatchOperand_ParseFail;
3896  }
3897  Parser.Lex(); // Eat hash token.
3898
3899  const MCExpr *WidthExpr;
3900  SMLoc EndLoc;
3901  if (getParser().parseExpression(WidthExpr, EndLoc)) {
3902    Error(E, "malformed immediate expression");
3903    return MatchOperand_ParseFail;
3904  }
3905  CE = dyn_cast<MCConstantExpr>(WidthExpr);
3906  if (!CE) {
3907    Error(E, "'width' operand must be an immediate");
3908    return MatchOperand_ParseFail;
3909  }
3910
3911  int64_t Width = CE->getValue();
3912  // The LSB must be in the range [1,32-lsb]
3913  if (Width < 1 || Width > 32 - LSB) {
3914    Error(E, "'width' operand must be in the range [1,32-lsb]");
3915    return MatchOperand_ParseFail;
3916  }
3917
3918  Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc));
3919
3920  return MatchOperand_Success;
3921}
3922
3923ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3924parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3925  // Check for a post-index addressing register operand. Specifically:
3926  // postidx_reg := '+' register {, shift}
3927  //              | '-' register {, shift}
3928  //              | register {, shift}
3929
3930  // This method must return MatchOperand_NoMatch without consuming any tokens
3931  // in the case where there is no match, as other alternatives take other
3932  // parse methods.
3933  AsmToken Tok = Parser.getTok();
3934  SMLoc S = Tok.getLoc();
3935  bool haveEaten = false;
3936  bool isAdd = true;
3937  if (Tok.is(AsmToken::Plus)) {
3938    Parser.Lex(); // Eat the '+' token.
3939    haveEaten = true;
3940  } else if (Tok.is(AsmToken::Minus)) {
3941    Parser.Lex(); // Eat the '-' token.
3942    isAdd = false;
3943    haveEaten = true;
3944  }
3945
3946  SMLoc E = Parser.getTok().getEndLoc();
3947  int Reg = tryParseRegister();
3948  if (Reg == -1) {
3949    if (!haveEaten)
3950      return MatchOperand_NoMatch;
3951    Error(Parser.getTok().getLoc(), "register expected");
3952    return MatchOperand_ParseFail;
3953  }
3954
3955  ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
3956  unsigned ShiftImm = 0;
3957  if (Parser.getTok().is(AsmToken::Comma)) {
3958    Parser.Lex(); // Eat the ','.
3959    if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
3960      return MatchOperand_ParseFail;
3961
3962    // FIXME: Only approximates end...may include intervening whitespace.
3963    E = Parser.getTok().getLoc();
3964  }
3965
3966  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
3967                                                  ShiftImm, S, E));
3968
3969  return MatchOperand_Success;
3970}
3971
3972ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3973parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3974  // Check for a post-index addressing register operand. Specifically:
3975  // am3offset := '+' register
3976  //              | '-' register
3977  //              | register
3978  //              | # imm
3979  //              | # + imm
3980  //              | # - imm
3981
3982  // This method must return MatchOperand_NoMatch without consuming any tokens
3983  // in the case where there is no match, as other alternatives take other
3984  // parse methods.
3985  AsmToken Tok = Parser.getTok();
3986  SMLoc S = Tok.getLoc();
3987
3988  // Do immediates first, as we always parse those if we have a '#'.
3989  if (Parser.getTok().is(AsmToken::Hash) ||
3990      Parser.getTok().is(AsmToken::Dollar)) {
3991    Parser.Lex(); // Eat '#' or '$'.
3992    // Explicitly look for a '-', as we need to encode negative zero
3993    // differently.
3994    bool isNegative = Parser.getTok().is(AsmToken::Minus);
3995    const MCExpr *Offset;
3996    SMLoc E;
3997    if (getParser().parseExpression(Offset, E))
3998      return MatchOperand_ParseFail;
3999    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4000    if (!CE) {
4001      Error(S, "constant expression expected");
4002      return MatchOperand_ParseFail;
4003    }
4004    // Negative zero is encoded as the flag value INT32_MIN.
4005    int32_t Val = CE->getValue();
4006    if (isNegative && Val == 0)
4007      Val = INT32_MIN;
4008
4009    Operands.push_back(
4010      ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
4011
4012    return MatchOperand_Success;
4013  }
4014
4015
4016  bool haveEaten = false;
4017  bool isAdd = true;
4018  if (Tok.is(AsmToken::Plus)) {
4019    Parser.Lex(); // Eat the '+' token.
4020    haveEaten = true;
4021  } else if (Tok.is(AsmToken::Minus)) {
4022    Parser.Lex(); // Eat the '-' token.
4023    isAdd = false;
4024    haveEaten = true;
4025  }
4026
4027  Tok = Parser.getTok();
4028  int Reg = tryParseRegister();
4029  if (Reg == -1) {
4030    if (!haveEaten)
4031      return MatchOperand_NoMatch;
4032    Error(Tok.getLoc(), "register expected");
4033    return MatchOperand_ParseFail;
4034  }
4035
4036  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
4037                                                  0, S, Tok.getEndLoc()));
4038
4039  return MatchOperand_Success;
4040}
4041
4042/// cvtT2LdrdPre - Convert parsed operands to MCInst.
4043/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4044/// when they refer multiple MIOperands inside a single one.
4045void ARMAsmParser::
4046cvtT2LdrdPre(MCInst &Inst,
4047             const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4048  // Rt, Rt2
4049  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4050  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4051  // Create a writeback register dummy placeholder.
4052  Inst.addOperand(MCOperand::CreateReg(0));
4053  // addr
4054  ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
4055  // pred
4056  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4057}
4058
4059/// cvtT2StrdPre - Convert parsed operands to MCInst.
4060/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4061/// when they refer multiple MIOperands inside a single one.
4062void ARMAsmParser::
4063cvtT2StrdPre(MCInst &Inst,
4064             const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4065  // Create a writeback register dummy placeholder.
4066  Inst.addOperand(MCOperand::CreateReg(0));
4067  // Rt, Rt2
4068  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4069  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4070  // addr
4071  ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
4072  // pred
4073  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4074}
4075
4076/// cvtLdWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
4077/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4078/// when they refer multiple MIOperands inside a single one.
4079void ARMAsmParser::
4080cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst,
4081                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4082  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4083
4084  // Create a writeback register dummy placeholder.
4085  Inst.addOperand(MCOperand::CreateImm(0));
4086
4087  ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
4088  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4089}
4090
4091/// cvtStWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
4092/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4093/// when they refer multiple MIOperands inside a single one.
4094void ARMAsmParser::
4095cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst,
4096                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4097  // Create a writeback register dummy placeholder.
4098  Inst.addOperand(MCOperand::CreateImm(0));
4099  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4100  ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
4101  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4102}
4103
4104/// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
4105/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4106/// when they refer multiple MIOperands inside a single one.
4107void ARMAsmParser::
4108cvtLdWriteBackRegAddrMode2(MCInst &Inst,
4109                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4110  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4111
4112  // Create a writeback register dummy placeholder.
4113  Inst.addOperand(MCOperand::CreateImm(0));
4114
4115  ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
4116  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4117}
4118
4119/// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
4120/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4121/// when they refer multiple MIOperands inside a single one.
4122void ARMAsmParser::
4123cvtLdWriteBackRegAddrModeImm12(MCInst &Inst,
4124                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4125  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4126
4127  // Create a writeback register dummy placeholder.
4128  Inst.addOperand(MCOperand::CreateImm(0));
4129
4130  ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
4131  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4132}
4133
4134
4135/// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
4136/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4137/// when they refer multiple MIOperands inside a single one.
4138void ARMAsmParser::
4139cvtStWriteBackRegAddrModeImm12(MCInst &Inst,
4140                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4141  // Create a writeback register dummy placeholder.
4142  Inst.addOperand(MCOperand::CreateImm(0));
4143  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4144  ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
4145  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4146}
4147
4148/// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
4149/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4150/// when they refer multiple MIOperands inside a single one.
4151void ARMAsmParser::
4152cvtStWriteBackRegAddrMode2(MCInst &Inst,
4153                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4154  // Create a writeback register dummy placeholder.
4155  Inst.addOperand(MCOperand::CreateImm(0));
4156  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4157  ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
4158  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4159}
4160
4161/// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
4162/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4163/// when they refer multiple MIOperands inside a single one.
4164void ARMAsmParser::
4165cvtStWriteBackRegAddrMode3(MCInst &Inst,
4166                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4167  // Create a writeback register dummy placeholder.
4168  Inst.addOperand(MCOperand::CreateImm(0));
4169  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4170  ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
4171  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4172}
4173
4174/// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst.
4175/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4176/// when they refer multiple MIOperands inside a single one.
4177void ARMAsmParser::
4178cvtLdExtTWriteBackImm(MCInst &Inst,
4179                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4180  // Rt
4181  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4182  // Create a writeback register dummy placeholder.
4183  Inst.addOperand(MCOperand::CreateImm(0));
4184  // addr
4185  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4186  // offset
4187  ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
4188  // pred
4189  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4190}
4191
4192/// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst.
4193/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4194/// when they refer multiple MIOperands inside a single one.
4195void ARMAsmParser::
4196cvtLdExtTWriteBackReg(MCInst &Inst,
4197                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4198  // Rt
4199  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4200  // Create a writeback register dummy placeholder.
4201  Inst.addOperand(MCOperand::CreateImm(0));
4202  // addr
4203  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4204  // offset
4205  ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
4206  // pred
4207  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4208}
4209
4210/// cvtStExtTWriteBackImm - Convert parsed operands to MCInst.
4211/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4212/// when they refer multiple MIOperands inside a single one.
4213void ARMAsmParser::
4214cvtStExtTWriteBackImm(MCInst &Inst,
4215                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4216  // Create a writeback register dummy placeholder.
4217  Inst.addOperand(MCOperand::CreateImm(0));
4218  // Rt
4219  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4220  // addr
4221  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4222  // offset
4223  ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
4224  // pred
4225  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4226}
4227
4228/// cvtStExtTWriteBackReg - Convert parsed operands to MCInst.
4229/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4230/// when they refer multiple MIOperands inside a single one.
4231void ARMAsmParser::
4232cvtStExtTWriteBackReg(MCInst &Inst,
4233                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4234  // Create a writeback register dummy placeholder.
4235  Inst.addOperand(MCOperand::CreateImm(0));
4236  // Rt
4237  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4238  // addr
4239  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4240  // offset
4241  ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
4242  // pred
4243  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4244}
4245
4246/// cvtLdrdPre - Convert parsed operands to MCInst.
4247/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4248/// when they refer multiple MIOperands inside a single one.
4249void ARMAsmParser::
4250cvtLdrdPre(MCInst &Inst,
4251           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4252  // Rt, Rt2
4253  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4254  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4255  // Create a writeback register dummy placeholder.
4256  Inst.addOperand(MCOperand::CreateImm(0));
4257  // addr
4258  ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
4259  // pred
4260  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4261}
4262
4263/// cvtStrdPre - Convert parsed operands to MCInst.
4264/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4265/// when they refer multiple MIOperands inside a single one.
4266void ARMAsmParser::
4267cvtStrdPre(MCInst &Inst,
4268           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4269  // Create a writeback register dummy placeholder.
4270  Inst.addOperand(MCOperand::CreateImm(0));
4271  // Rt, Rt2
4272  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4273  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4274  // addr
4275  ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
4276  // pred
4277  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4278}
4279
4280/// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
4281/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4282/// when they refer multiple MIOperands inside a single one.
4283void ARMAsmParser::
4284cvtLdWriteBackRegAddrMode3(MCInst &Inst,
4285                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4286  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4287  // Create a writeback register dummy placeholder.
4288  Inst.addOperand(MCOperand::CreateImm(0));
4289  ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
4290  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4291}
4292
4293/// cvtThumbMultiply - Convert parsed operands to MCInst.
4294/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4295/// when they refer multiple MIOperands inside a single one.
4296void ARMAsmParser::
4297cvtThumbMultiply(MCInst &Inst,
4298           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4299  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4300  ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
4301  // If we have a three-operand form, make sure to set Rn to be the operand
4302  // that isn't the same as Rd.
4303  unsigned RegOp = 4;
4304  if (Operands.size() == 6 &&
4305      ((ARMOperand*)Operands[4])->getReg() ==
4306        ((ARMOperand*)Operands[3])->getReg())
4307    RegOp = 5;
4308  ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1);
4309  Inst.addOperand(Inst.getOperand(0));
4310  ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
4311}
4312
4313void ARMAsmParser::
4314cvtVLDwbFixed(MCInst &Inst,
4315              const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4316  // Vd
4317  ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4318  // Create a writeback register dummy placeholder.
4319  Inst.addOperand(MCOperand::CreateImm(0));
4320  // Vn
4321  ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4322  // pred
4323  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4324}
4325
4326void ARMAsmParser::
4327cvtVLDwbRegister(MCInst &Inst,
4328                 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4329  // Vd
4330  ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4331  // Create a writeback register dummy placeholder.
4332  Inst.addOperand(MCOperand::CreateImm(0));
4333  // Vn
4334  ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4335  // Vm
4336  ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
4337  // pred
4338  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4339}
4340
4341void ARMAsmParser::
4342cvtVSTwbFixed(MCInst &Inst,
4343              const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4344  // Create a writeback register dummy placeholder.
4345  Inst.addOperand(MCOperand::CreateImm(0));
4346  // Vn
4347  ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4348  // Vt
4349  ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4350  // pred
4351  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4352}
4353
4354void ARMAsmParser::
4355cvtVSTwbRegister(MCInst &Inst,
4356                 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4357  // Create a writeback register dummy placeholder.
4358  Inst.addOperand(MCOperand::CreateImm(0));
4359  // Vn
4360  ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4361  // Vm
4362  ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
4363  // Vt
4364  ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4365  // pred
4366  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4367}
4368
4369/// Parse an ARM memory expression, return false if successful else return true
4370/// or an error.  The first token must be a '[' when called.
4371bool ARMAsmParser::
4372parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4373  SMLoc S, E;
4374  assert(Parser.getTok().is(AsmToken::LBrac) &&
4375         "Token is not a Left Bracket");
4376  S = Parser.getTok().getLoc();
4377  Parser.Lex(); // Eat left bracket token.
4378
4379  const AsmToken &BaseRegTok = Parser.getTok();
4380  int BaseRegNum = tryParseRegister();
4381  if (BaseRegNum == -1)
4382    return Error(BaseRegTok.getLoc(), "register expected");
4383
4384  // The next token must either be a comma, a colon or a closing bracket.
4385  const AsmToken &Tok = Parser.getTok();
4386  if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) &&
4387      !Tok.is(AsmToken::RBrac))
4388    return Error(Tok.getLoc(), "malformed memory operand");
4389
4390  if (Tok.is(AsmToken::RBrac)) {
4391    E = Tok.getEndLoc();
4392    Parser.Lex(); // Eat right bracket token.
4393
4394    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
4395                                             0, 0, false, S, E));
4396
4397    // If there's a pre-indexing writeback marker, '!', just add it as a token
4398    // operand. It's rather odd, but syntactically valid.
4399    if (Parser.getTok().is(AsmToken::Exclaim)) {
4400      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4401      Parser.Lex(); // Eat the '!'.
4402    }
4403
4404    return false;
4405  }
4406
4407  assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) &&
4408         "Lost colon or comma in memory operand?!");
4409  if (Tok.is(AsmToken::Comma)) {
4410    Parser.Lex(); // Eat the comma.
4411  }
4412
4413  // If we have a ':', it's an alignment specifier.
4414  if (Parser.getTok().is(AsmToken::Colon)) {
4415    Parser.Lex(); // Eat the ':'.
4416    E = Parser.getTok().getLoc();
4417
4418    const MCExpr *Expr;
4419    if (getParser().parseExpression(Expr))
4420     return true;
4421
4422    // The expression has to be a constant. Memory references with relocations
4423    // don't come through here, as they use the <label> forms of the relevant
4424    // instructions.
4425    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4426    if (!CE)
4427      return Error (E, "constant expression expected");
4428
4429    unsigned Align = 0;
4430    switch (CE->getValue()) {
4431    default:
4432      return Error(E,
4433                   "alignment specifier must be 16, 32, 64, 128, or 256 bits");
4434    case 16:  Align = 2; break;
4435    case 32:  Align = 4; break;
4436    case 64:  Align = 8; break;
4437    case 128: Align = 16; break;
4438    case 256: Align = 32; break;
4439    }
4440
4441    // Now we should have the closing ']'
4442    if (Parser.getTok().isNot(AsmToken::RBrac))
4443      return Error(Parser.getTok().getLoc(), "']' expected");
4444    E = Parser.getTok().getEndLoc();
4445    Parser.Lex(); // Eat right bracket token.
4446
4447    // Don't worry about range checking the value here. That's handled by
4448    // the is*() predicates.
4449    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0,
4450                                             ARM_AM::no_shift, 0, Align,
4451                                             false, S, E));
4452
4453    // If there's a pre-indexing writeback marker, '!', just add it as a token
4454    // operand.
4455    if (Parser.getTok().is(AsmToken::Exclaim)) {
4456      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4457      Parser.Lex(); // Eat the '!'.
4458    }
4459
4460    return false;
4461  }
4462
4463  // If we have a '#', it's an immediate offset, else assume it's a register
4464  // offset. Be friendly and also accept a plain integer (without a leading
4465  // hash) for gas compatibility.
4466  if (Parser.getTok().is(AsmToken::Hash) ||
4467      Parser.getTok().is(AsmToken::Dollar) ||
4468      Parser.getTok().is(AsmToken::Integer)) {
4469    if (Parser.getTok().isNot(AsmToken::Integer))
4470      Parser.Lex(); // Eat '#' or '$'.
4471    E = Parser.getTok().getLoc();
4472
4473    bool isNegative = getParser().getTok().is(AsmToken::Minus);
4474    const MCExpr *Offset;
4475    if (getParser().parseExpression(Offset))
4476     return true;
4477
4478    // The expression has to be a constant. Memory references with relocations
4479    // don't come through here, as they use the <label> forms of the relevant
4480    // instructions.
4481    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4482    if (!CE)
4483      return Error (E, "constant expression expected");
4484
4485    // If the constant was #-0, represent it as INT32_MIN.
4486    int32_t Val = CE->getValue();
4487    if (isNegative && Val == 0)
4488      CE = MCConstantExpr::Create(INT32_MIN, getContext());
4489
4490    // Now we should have the closing ']'
4491    if (Parser.getTok().isNot(AsmToken::RBrac))
4492      return Error(Parser.getTok().getLoc(), "']' expected");
4493    E = Parser.getTok().getEndLoc();
4494    Parser.Lex(); // Eat right bracket token.
4495
4496    // Don't worry about range checking the value here. That's handled by
4497    // the is*() predicates.
4498    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
4499                                             ARM_AM::no_shift, 0, 0,
4500                                             false, S, E));
4501
4502    // If there's a pre-indexing writeback marker, '!', just add it as a token
4503    // operand.
4504    if (Parser.getTok().is(AsmToken::Exclaim)) {
4505      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4506      Parser.Lex(); // Eat the '!'.
4507    }
4508
4509    return false;
4510  }
4511
4512  // The register offset is optionally preceded by a '+' or '-'
4513  bool isNegative = false;
4514  if (Parser.getTok().is(AsmToken::Minus)) {
4515    isNegative = true;
4516    Parser.Lex(); // Eat the '-'.
4517  } else if (Parser.getTok().is(AsmToken::Plus)) {
4518    // Nothing to do.
4519    Parser.Lex(); // Eat the '+'.
4520  }
4521
4522  E = Parser.getTok().getLoc();
4523  int OffsetRegNum = tryParseRegister();
4524  if (OffsetRegNum == -1)
4525    return Error(E, "register expected");
4526
4527  // If there's a shift operator, handle it.
4528  ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
4529  unsigned ShiftImm = 0;
4530  if (Parser.getTok().is(AsmToken::Comma)) {
4531    Parser.Lex(); // Eat the ','.
4532    if (parseMemRegOffsetShift(ShiftType, ShiftImm))
4533      return true;
4534  }
4535
4536  // Now we should have the closing ']'
4537  if (Parser.getTok().isNot(AsmToken::RBrac))
4538    return Error(Parser.getTok().getLoc(), "']' expected");
4539  E = Parser.getTok().getEndLoc();
4540  Parser.Lex(); // Eat right bracket token.
4541
4542  Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
4543                                           ShiftType, ShiftImm, 0, isNegative,
4544                                           S, E));
4545
4546  // If there's a pre-indexing writeback marker, '!', just add it as a token
4547  // operand.
4548  if (Parser.getTok().is(AsmToken::Exclaim)) {
4549    Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4550    Parser.Lex(); // Eat the '!'.
4551  }
4552
4553  return false;
4554}
4555
4556/// parseMemRegOffsetShift - one of these two:
4557///   ( lsl | lsr | asr | ror ) , # shift_amount
4558///   rrx
4559/// return true if it parses a shift otherwise it returns false.
4560bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
4561                                          unsigned &Amount) {
4562  SMLoc Loc = Parser.getTok().getLoc();
4563  const AsmToken &Tok = Parser.getTok();
4564  if (Tok.isNot(AsmToken::Identifier))
4565    return true;
4566  StringRef ShiftName = Tok.getString();
4567  if (ShiftName == "lsl" || ShiftName == "LSL" ||
4568      ShiftName == "asl" || ShiftName == "ASL")
4569    St = ARM_AM::lsl;
4570  else if (ShiftName == "lsr" || ShiftName == "LSR")
4571    St = ARM_AM::lsr;
4572  else if (ShiftName == "asr" || ShiftName == "ASR")
4573    St = ARM_AM::asr;
4574  else if (ShiftName == "ror" || ShiftName == "ROR")
4575    St = ARM_AM::ror;
4576  else if (ShiftName == "rrx" || ShiftName == "RRX")
4577    St = ARM_AM::rrx;
4578  else
4579    return Error(Loc, "illegal shift operator");
4580  Parser.Lex(); // Eat shift type token.
4581
4582  // rrx stands alone.
4583  Amount = 0;
4584  if (St != ARM_AM::rrx) {
4585    Loc = Parser.getTok().getLoc();
4586    // A '#' and a shift amount.
4587    const AsmToken &HashTok = Parser.getTok();
4588    if (HashTok.isNot(AsmToken::Hash) &&
4589        HashTok.isNot(AsmToken::Dollar))
4590      return Error(HashTok.getLoc(), "'#' expected");
4591    Parser.Lex(); // Eat hash token.
4592
4593    const MCExpr *Expr;
4594    if (getParser().parseExpression(Expr))
4595      return true;
4596    // Range check the immediate.
4597    // lsl, ror: 0 <= imm <= 31
4598    // lsr, asr: 0 <= imm <= 32
4599    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4600    if (!CE)
4601      return Error(Loc, "shift amount must be an immediate");
4602    int64_t Imm = CE->getValue();
4603    if (Imm < 0 ||
4604        ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
4605        ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
4606      return Error(Loc, "immediate shift value out of range");
4607    // If <ShiftTy> #0, turn it into a no_shift.
4608    if (Imm == 0)
4609      St = ARM_AM::lsl;
4610    // For consistency, treat lsr #32 and asr #32 as having immediate value 0.
4611    if (Imm == 32)
4612      Imm = 0;
4613    Amount = Imm;
4614  }
4615
4616  return false;
4617}
4618
4619/// parseFPImm - A floating point immediate expression operand.
4620ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4621parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4622  // Anything that can accept a floating point constant as an operand
4623  // needs to go through here, as the regular parseExpression is
4624  // integer only.
4625  //
4626  // This routine still creates a generic Immediate operand, containing
4627  // a bitcast of the 64-bit floating point value. The various operands
4628  // that accept floats can check whether the value is valid for them
4629  // via the standard is*() predicates.
4630
4631  SMLoc S = Parser.getTok().getLoc();
4632
4633  if (Parser.getTok().isNot(AsmToken::Hash) &&
4634      Parser.getTok().isNot(AsmToken::Dollar))
4635    return MatchOperand_NoMatch;
4636
4637  // Disambiguate the VMOV forms that can accept an FP immediate.
4638  // vmov.f32 <sreg>, #imm
4639  // vmov.f64 <dreg>, #imm
4640  // vmov.f32 <dreg>, #imm  @ vector f32x2
4641  // vmov.f32 <qreg>, #imm  @ vector f32x4
4642  //
4643  // There are also the NEON VMOV instructions which expect an
4644  // integer constant. Make sure we don't try to parse an FPImm
4645  // for these:
4646  // vmov.i{8|16|32|64} <dreg|qreg>, #imm
4647  ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]);
4648  if (!TyOp->isToken() || (TyOp->getToken() != ".f32" &&
4649                           TyOp->getToken() != ".f64"))
4650    return MatchOperand_NoMatch;
4651
4652  Parser.Lex(); // Eat '#' or '$'.
4653
4654  // Handle negation, as that still comes through as a separate token.
4655  bool isNegative = false;
4656  if (Parser.getTok().is(AsmToken::Minus)) {
4657    isNegative = true;
4658    Parser.Lex();
4659  }
4660  const AsmToken &Tok = Parser.getTok();
4661  SMLoc Loc = Tok.getLoc();
4662  if (Tok.is(AsmToken::Real)) {
4663    APFloat RealVal(APFloat::IEEEsingle, Tok.getString());
4664    uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
4665    // If we had a '-' in front, toggle the sign bit.
4666    IntVal ^= (uint64_t)isNegative << 31;
4667    Parser.Lex(); // Eat the token.
4668    Operands.push_back(ARMOperand::CreateImm(
4669          MCConstantExpr::Create(IntVal, getContext()),
4670          S, Parser.getTok().getLoc()));
4671    return MatchOperand_Success;
4672  }
4673  // Also handle plain integers. Instructions which allow floating point
4674  // immediates also allow a raw encoded 8-bit value.
4675  if (Tok.is(AsmToken::Integer)) {
4676    int64_t Val = Tok.getIntVal();
4677    Parser.Lex(); // Eat the token.
4678    if (Val > 255 || Val < 0) {
4679      Error(Loc, "encoded floating point value out of range");
4680      return MatchOperand_ParseFail;
4681    }
4682    double RealVal = ARM_AM::getFPImmFloat(Val);
4683    Val = APFloat(APFloat::IEEEdouble, RealVal).bitcastToAPInt().getZExtValue();
4684    Operands.push_back(ARMOperand::CreateImm(
4685        MCConstantExpr::Create(Val, getContext()), S,
4686        Parser.getTok().getLoc()));
4687    return MatchOperand_Success;
4688  }
4689
4690  Error(Loc, "invalid floating point immediate");
4691  return MatchOperand_ParseFail;
4692}
4693
4694/// Parse a arm instruction operand.  For now this parses the operand regardless
4695/// of the mnemonic.
4696bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
4697                                StringRef Mnemonic) {
4698  SMLoc S, E;
4699
4700  // Check if the current operand has a custom associated parser, if so, try to
4701  // custom parse the operand, or fallback to the general approach.
4702  OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
4703  if (ResTy == MatchOperand_Success)
4704    return false;
4705  // If there wasn't a custom match, try the generic matcher below. Otherwise,
4706  // there was a match, but an error occurred, in which case, just return that
4707  // the operand parsing failed.
4708  if (ResTy == MatchOperand_ParseFail)
4709    return true;
4710
4711  switch (getLexer().getKind()) {
4712  default:
4713    Error(Parser.getTok().getLoc(), "unexpected token in operand");
4714    return true;
4715  case AsmToken::Identifier: {
4716    // If we've seen a branch mnemonic, the next operand must be a label.  This
4717    // is true even if the label is a register name.  So "br r1" means branch to
4718    // label "r1".
4719    bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl";
4720    if (!ExpectLabel) {
4721      if (!tryParseRegisterWithWriteBack(Operands))
4722        return false;
4723      int Res = tryParseShiftRegister(Operands);
4724      if (Res == 0) // success
4725        return false;
4726      else if (Res == -1) // irrecoverable error
4727        return true;
4728      // If this is VMRS, check for the apsr_nzcv operand.
4729      if (Mnemonic == "vmrs" &&
4730          Parser.getTok().getString().equals_lower("apsr_nzcv")) {
4731        S = Parser.getTok().getLoc();
4732        Parser.Lex();
4733        Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
4734        return false;
4735      }
4736    }
4737
4738    // Fall though for the Identifier case that is not a register or a
4739    // special name.
4740  }
4741  case AsmToken::LParen:  // parenthesized expressions like (_strcmp-4)
4742  case AsmToken::Integer: // things like 1f and 2b as a branch targets
4743  case AsmToken::String:  // quoted label names.
4744  case AsmToken::Dot: {   // . as a branch target
4745    // This was not a register so parse other operands that start with an
4746    // identifier (like labels) as expressions and create them as immediates.
4747    const MCExpr *IdVal;
4748    S = Parser.getTok().getLoc();
4749    if (getParser().parseExpression(IdVal))
4750      return true;
4751    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4752    Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
4753    return false;
4754  }
4755  case AsmToken::LBrac:
4756    return parseMemory(Operands);
4757  case AsmToken::LCurly:
4758    return parseRegisterList(Operands);
4759  case AsmToken::Dollar:
4760  case AsmToken::Hash: {
4761    // #42 -> immediate.
4762    S = Parser.getTok().getLoc();
4763    Parser.Lex();
4764
4765    if (Parser.getTok().isNot(AsmToken::Colon)) {
4766      bool isNegative = Parser.getTok().is(AsmToken::Minus);
4767      const MCExpr *ImmVal;
4768      if (getParser().parseExpression(ImmVal))
4769        return true;
4770      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
4771      if (CE) {
4772        int32_t Val = CE->getValue();
4773        if (isNegative && Val == 0)
4774          ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
4775      }
4776      E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4777      Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
4778
4779      // There can be a trailing '!' on operands that we want as a separate
4780      // '!' Token operand. Handle that here. For example, the compatibilty
4781      // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'.
4782      if (Parser.getTok().is(AsmToken::Exclaim)) {
4783        Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(),
4784                                                   Parser.getTok().getLoc()));
4785        Parser.Lex(); // Eat exclaim token
4786      }
4787      return false;
4788    }
4789    // w/ a ':' after the '#', it's just like a plain ':'.
4790    // FALLTHROUGH
4791  }
4792  case AsmToken::Colon: {
4793    // ":lower16:" and ":upper16:" expression prefixes
4794    // FIXME: Check it's an expression prefix,
4795    // e.g. (FOO - :lower16:BAR) isn't legal.
4796    ARMMCExpr::VariantKind RefKind;
4797    if (parsePrefix(RefKind))
4798      return true;
4799
4800    const MCExpr *SubExprVal;
4801    if (getParser().parseExpression(SubExprVal))
4802      return true;
4803
4804    const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
4805                                              getContext());
4806    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4807    Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
4808    return false;
4809  }
4810  }
4811}
4812
4813// parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
4814//  :lower16: and :upper16:.
4815bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
4816  RefKind = ARMMCExpr::VK_ARM_None;
4817
4818  // :lower16: and :upper16: modifiers
4819  assert(getLexer().is(AsmToken::Colon) && "expected a :");
4820  Parser.Lex(); // Eat ':'
4821
4822  if (getLexer().isNot(AsmToken::Identifier)) {
4823    Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
4824    return true;
4825  }
4826
4827  StringRef IDVal = Parser.getTok().getIdentifier();
4828  if (IDVal == "lower16") {
4829    RefKind = ARMMCExpr::VK_ARM_LO16;
4830  } else if (IDVal == "upper16") {
4831    RefKind = ARMMCExpr::VK_ARM_HI16;
4832  } else {
4833    Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
4834    return true;
4835  }
4836  Parser.Lex();
4837
4838  if (getLexer().isNot(AsmToken::Colon)) {
4839    Error(Parser.getTok().getLoc(), "unexpected token after prefix");
4840    return true;
4841  }
4842  Parser.Lex(); // Eat the last ':'
4843  return false;
4844}
4845
4846/// \brief Given a mnemonic, split out possible predication code and carry
4847/// setting letters to form a canonical mnemonic and flags.
4848//
4849// FIXME: Would be nice to autogen this.
4850// FIXME: This is a bit of a maze of special cases.
4851StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
4852                                      unsigned &PredicationCode,
4853                                      bool &CarrySetting,
4854                                      unsigned &ProcessorIMod,
4855                                      StringRef &ITMask) {
4856  PredicationCode = ARMCC::AL;
4857  CarrySetting = false;
4858  ProcessorIMod = 0;
4859
4860  // Ignore some mnemonics we know aren't predicated forms.
4861  //
4862  // FIXME: Would be nice to autogen this.
4863  if ((Mnemonic == "movs" && isThumb()) ||
4864      Mnemonic == "teq"   || Mnemonic == "vceq"   || Mnemonic == "svc"   ||
4865      Mnemonic == "mls"   || Mnemonic == "smmls"  || Mnemonic == "vcls"  ||
4866      Mnemonic == "vmls"  || Mnemonic == "vnmls"  || Mnemonic == "vacge" ||
4867      Mnemonic == "vcge"  || Mnemonic == "vclt"   || Mnemonic == "vacgt" ||
4868      Mnemonic == "vaclt" || Mnemonic == "vacle"  ||
4869      Mnemonic == "vcgt"  || Mnemonic == "vcle"   || Mnemonic == "smlal" ||
4870      Mnemonic == "umaal" || Mnemonic == "umlal"  || Mnemonic == "vabal" ||
4871      Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
4872      Mnemonic == "fmuls")
4873    return Mnemonic;
4874
4875  // First, split out any predication code. Ignore mnemonics we know aren't
4876  // predicated but do have a carry-set and so weren't caught above.
4877  if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
4878      Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
4879      Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
4880      Mnemonic != "sbcs" && Mnemonic != "rscs") {
4881    unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
4882      .Case("eq", ARMCC::EQ)
4883      .Case("ne", ARMCC::NE)
4884      .Case("hs", ARMCC::HS)
4885      .Case("cs", ARMCC::HS)
4886      .Case("lo", ARMCC::LO)
4887      .Case("cc", ARMCC::LO)
4888      .Case("mi", ARMCC::MI)
4889      .Case("pl", ARMCC::PL)
4890      .Case("vs", ARMCC::VS)
4891      .Case("vc", ARMCC::VC)
4892      .Case("hi", ARMCC::HI)
4893      .Case("ls", ARMCC::LS)
4894      .Case("ge", ARMCC::GE)
4895      .Case("lt", ARMCC::LT)
4896      .Case("gt", ARMCC::GT)
4897      .Case("le", ARMCC::LE)
4898      .Case("al", ARMCC::AL)
4899      .Default(~0U);
4900    if (CC != ~0U) {
4901      Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
4902      PredicationCode = CC;
4903    }
4904  }
4905
4906  // Next, determine if we have a carry setting bit. We explicitly ignore all
4907  // the instructions we know end in 's'.
4908  if (Mnemonic.endswith("s") &&
4909      !(Mnemonic == "cps" || Mnemonic == "mls" ||
4910        Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
4911        Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
4912        Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
4913        Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
4914        Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
4915        Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
4916        Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
4917        Mnemonic == "vfms" || Mnemonic == "vfnms" ||
4918        (Mnemonic == "movs" && isThumb()))) {
4919    Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
4920    CarrySetting = true;
4921  }
4922
4923  // The "cps" instruction can have a interrupt mode operand which is glued into
4924  // the mnemonic. Check if this is the case, split it and parse the imod op
4925  if (Mnemonic.startswith("cps")) {
4926    // Split out any imod code.
4927    unsigned IMod =
4928      StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
4929      .Case("ie", ARM_PROC::IE)
4930      .Case("id", ARM_PROC::ID)
4931      .Default(~0U);
4932    if (IMod != ~0U) {
4933      Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
4934      ProcessorIMod = IMod;
4935    }
4936  }
4937
4938  // The "it" instruction has the condition mask on the end of the mnemonic.
4939  if (Mnemonic.startswith("it")) {
4940    ITMask = Mnemonic.slice(2, Mnemonic.size());
4941    Mnemonic = Mnemonic.slice(0, 2);
4942  }
4943
4944  return Mnemonic;
4945}
4946
4947/// \brief Given a canonical mnemonic, determine if the instruction ever allows
4948/// inclusion of carry set or predication code operands.
4949//
4950// FIXME: It would be nice to autogen this.
4951void ARMAsmParser::
4952getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
4953                      bool &CanAcceptPredicationCode) {
4954  if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
4955      Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
4956      Mnemonic == "add" || Mnemonic == "adc" ||
4957      Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
4958      Mnemonic == "orr" || Mnemonic == "mvn" ||
4959      Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
4960      Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
4961      Mnemonic == "vfm" || Mnemonic == "vfnm" ||
4962      (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
4963                      Mnemonic == "mla" || Mnemonic == "smlal" ||
4964                      Mnemonic == "umlal" || Mnemonic == "umull"))) {
4965    CanAcceptCarrySet = true;
4966  } else
4967    CanAcceptCarrySet = false;
4968
4969  if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
4970      Mnemonic == "cps" ||  Mnemonic == "it" ||  Mnemonic == "cbz" ||
4971      Mnemonic == "trap" || Mnemonic == "setend" ||
4972      Mnemonic.startswith("cps")) {
4973    // These mnemonics are never predicable
4974    CanAcceptPredicationCode = false;
4975  } else if (!isThumb()) {
4976    // Some instructions are only predicable in Thumb mode
4977    CanAcceptPredicationCode
4978      = Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" &&
4979        Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" &&
4980        Mnemonic != "dmb" && Mnemonic != "dsb" && Mnemonic != "isb" &&
4981        Mnemonic != "pld" && Mnemonic != "pli" && Mnemonic != "pldw" &&
4982        Mnemonic != "ldc2" && Mnemonic != "ldc2l" &&
4983        Mnemonic != "stc2" && Mnemonic != "stc2l" &&
4984        !Mnemonic.startswith("rfe") && !Mnemonic.startswith("srs");
4985  } else if (isThumbOne()) {
4986    CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs";
4987  } else
4988    CanAcceptPredicationCode = true;
4989}
4990
4991bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
4992                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4993  // FIXME: This is all horribly hacky. We really need a better way to deal
4994  // with optional operands like this in the matcher table.
4995
4996  // The 'mov' mnemonic is special. One variant has a cc_out operand, while
4997  // another does not. Specifically, the MOVW instruction does not. So we
4998  // special case it here and remove the defaulted (non-setting) cc_out
4999  // operand if that's the instruction we're trying to match.
5000  //
5001  // We do this as post-processing of the explicit operands rather than just
5002  // conditionally adding the cc_out in the first place because we need
5003  // to check the type of the parsed immediate operand.
5004  if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
5005      !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
5006      static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
5007      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
5008    return true;
5009
5010  // Register-register 'add' for thumb does not have a cc_out operand
5011  // when there are only two register operands.
5012  if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
5013      static_cast<ARMOperand*>(Operands[3])->isReg() &&
5014      static_cast<ARMOperand*>(Operands[4])->isReg() &&
5015      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
5016    return true;
5017  // Register-register 'add' for thumb does not have a cc_out operand
5018  // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
5019  // have to check the immediate range here since Thumb2 has a variant
5020  // that can handle a different range and has a cc_out operand.
5021  if (((isThumb() && Mnemonic == "add") ||
5022       (isThumbTwo() && Mnemonic == "sub")) &&
5023      Operands.size() == 6 &&
5024      static_cast<ARMOperand*>(Operands[3])->isReg() &&
5025      static_cast<ARMOperand*>(Operands[4])->isReg() &&
5026      static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
5027      static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
5028      ((Mnemonic == "add" &&static_cast<ARMOperand*>(Operands[5])->isReg()) ||
5029       static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
5030    return true;
5031  // For Thumb2, add/sub immediate does not have a cc_out operand for the
5032  // imm0_4095 variant. That's the least-preferred variant when
5033  // selecting via the generic "add" mnemonic, so to know that we
5034  // should remove the cc_out operand, we have to explicitly check that
5035  // it's not one of the other variants. Ugh.
5036  if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
5037      Operands.size() == 6 &&
5038      static_cast<ARMOperand*>(Operands[3])->isReg() &&
5039      static_cast<ARMOperand*>(Operands[4])->isReg() &&
5040      static_cast<ARMOperand*>(Operands[5])->isImm()) {
5041    // Nest conditions rather than one big 'if' statement for readability.
5042    //
5043    // If either register is a high reg, it's either one of the SP
5044    // variants (handled above) or a 32-bit encoding, so we just
5045    // check against T3. If the second register is the PC, this is an
5046    // alternate form of ADR, which uses encoding T4, so check for that too.
5047    if ((!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
5048         !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg())) &&
5049        static_cast<ARMOperand*>(Operands[4])->getReg() != ARM::PC &&
5050        static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
5051      return false;
5052    // If both registers are low, we're in an IT block, and the immediate is
5053    // in range, we should use encoding T1 instead, which has a cc_out.
5054    if (inITBlock() &&
5055        isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
5056        isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
5057        static_cast<ARMOperand*>(Operands[5])->isImm0_7())
5058      return false;
5059
5060    // Otherwise, we use encoding T4, which does not have a cc_out
5061    // operand.
5062    return true;
5063  }
5064
5065  // The thumb2 multiply instruction doesn't have a CCOut register, so
5066  // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
5067  // use the 16-bit encoding or not.
5068  if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
5069      static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
5070      static_cast<ARMOperand*>(Operands[3])->isReg() &&
5071      static_cast<ARMOperand*>(Operands[4])->isReg() &&
5072      static_cast<ARMOperand*>(Operands[5])->isReg() &&
5073      // If the registers aren't low regs, the destination reg isn't the
5074      // same as one of the source regs, or the cc_out operand is zero
5075      // outside of an IT block, we have to use the 32-bit encoding, so
5076      // remove the cc_out operand.
5077      (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
5078       !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
5079       !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) ||
5080       !inITBlock() ||
5081       (static_cast<ARMOperand*>(Operands[3])->getReg() !=
5082        static_cast<ARMOperand*>(Operands[5])->getReg() &&
5083        static_cast<ARMOperand*>(Operands[3])->getReg() !=
5084        static_cast<ARMOperand*>(Operands[4])->getReg())))
5085    return true;
5086
5087  // Also check the 'mul' syntax variant that doesn't specify an explicit
5088  // destination register.
5089  if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
5090      static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
5091      static_cast<ARMOperand*>(Operands[3])->isReg() &&
5092      static_cast<ARMOperand*>(Operands[4])->isReg() &&
5093      // If the registers aren't low regs  or the cc_out operand is zero
5094      // outside of an IT block, we have to use the 32-bit encoding, so
5095      // remove the cc_out operand.
5096      (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
5097       !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
5098       !inITBlock()))
5099    return true;
5100
5101
5102
5103  // Register-register 'add/sub' for thumb does not have a cc_out operand
5104  // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
5105  // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
5106  // right, this will result in better diagnostics (which operand is off)
5107  // anyway.
5108  if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
5109      (Operands.size() == 5 || Operands.size() == 6) &&
5110      static_cast<ARMOperand*>(Operands[3])->isReg() &&
5111      static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
5112      static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
5113      (static_cast<ARMOperand*>(Operands[4])->isImm() ||
5114       (Operands.size() == 6 &&
5115        static_cast<ARMOperand*>(Operands[5])->isImm())))
5116    return true;
5117
5118  return false;
5119}
5120
5121static bool isDataTypeToken(StringRef Tok) {
5122  return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
5123    Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
5124    Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
5125    Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
5126    Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
5127    Tok == ".f" || Tok == ".d";
5128}
5129
5130// FIXME: This bit should probably be handled via an explicit match class
5131// in the .td files that matches the suffix instead of having it be
5132// a literal string token the way it is now.
5133static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
5134  return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
5135}
5136static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features,
5137                                 unsigned VariantID);
5138/// Parse an arm instruction mnemonic followed by its operands.
5139bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
5140                                    SMLoc NameLoc,
5141                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5142  // Apply mnemonic aliases before doing anything else, as the destination
5143  // mnemnonic may include suffices and we want to handle them normally.
5144  // The generic tblgen'erated code does this later, at the start of
5145  // MatchInstructionImpl(), but that's too late for aliases that include
5146  // any sort of suffix.
5147  unsigned AvailableFeatures = getAvailableFeatures();
5148  unsigned AssemblerDialect = getParser().getAssemblerDialect();
5149  applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect);
5150
5151  // First check for the ARM-specific .req directive.
5152  if (Parser.getTok().is(AsmToken::Identifier) &&
5153      Parser.getTok().getIdentifier() == ".req") {
5154    parseDirectiveReq(Name, NameLoc);
5155    // We always return 'error' for this, as we're done with this
5156    // statement and don't need to match the 'instruction."
5157    return true;
5158  }
5159
5160  // Create the leading tokens for the mnemonic, split by '.' characters.
5161  size_t Start = 0, Next = Name.find('.');
5162  StringRef Mnemonic = Name.slice(Start, Next);
5163
5164  // Split out the predication code and carry setting flag from the mnemonic.
5165  unsigned PredicationCode;
5166  unsigned ProcessorIMod;
5167  bool CarrySetting;
5168  StringRef ITMask;
5169  Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
5170                           ProcessorIMod, ITMask);
5171
5172  // In Thumb1, only the branch (B) instruction can be predicated.
5173  if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
5174    Parser.eatToEndOfStatement();
5175    return Error(NameLoc, "conditional execution not supported in Thumb1");
5176  }
5177
5178  Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
5179
5180  // Handle the IT instruction ITMask. Convert it to a bitmask. This
5181  // is the mask as it will be for the IT encoding if the conditional
5182  // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
5183  // where the conditional bit0 is zero, the instruction post-processing
5184  // will adjust the mask accordingly.
5185  if (Mnemonic == "it") {
5186    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
5187    if (ITMask.size() > 3) {
5188      Parser.eatToEndOfStatement();
5189      return Error(Loc, "too many conditions on IT instruction");
5190    }
5191    unsigned Mask = 8;
5192    for (unsigned i = ITMask.size(); i != 0; --i) {
5193      char pos = ITMask[i - 1];
5194      if (pos != 't' && pos != 'e') {
5195        Parser.eatToEndOfStatement();
5196        return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
5197      }
5198      Mask >>= 1;
5199      if (ITMask[i - 1] == 't')
5200        Mask |= 8;
5201    }
5202    Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
5203  }
5204
5205  // FIXME: This is all a pretty gross hack. We should automatically handle
5206  // optional operands like this via tblgen.
5207
5208  // Next, add the CCOut and ConditionCode operands, if needed.
5209  //
5210  // For mnemonics which can ever incorporate a carry setting bit or predication
5211  // code, our matching model involves us always generating CCOut and
5212  // ConditionCode operands to match the mnemonic "as written" and then we let
5213  // the matcher deal with finding the right instruction or generating an
5214  // appropriate error.
5215  bool CanAcceptCarrySet, CanAcceptPredicationCode;
5216  getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
5217
5218  // If we had a carry-set on an instruction that can't do that, issue an
5219  // error.
5220  if (!CanAcceptCarrySet && CarrySetting) {
5221    Parser.eatToEndOfStatement();
5222    return Error(NameLoc, "instruction '" + Mnemonic +
5223                 "' can not set flags, but 's' suffix specified");
5224  }
5225  // If we had a predication code on an instruction that can't do that, issue an
5226  // error.
5227  if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
5228    Parser.eatToEndOfStatement();
5229    return Error(NameLoc, "instruction '" + Mnemonic +
5230                 "' is not predicable, but condition code specified");
5231  }
5232
5233  // Add the carry setting operand, if necessary.
5234  if (CanAcceptCarrySet) {
5235    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
5236    Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
5237                                               Loc));
5238  }
5239
5240  // Add the predication code operand, if necessary.
5241  if (CanAcceptPredicationCode) {
5242    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
5243                                      CarrySetting);
5244    Operands.push_back(ARMOperand::CreateCondCode(
5245                         ARMCC::CondCodes(PredicationCode), Loc));
5246  }
5247
5248  // Add the processor imod operand, if necessary.
5249  if (ProcessorIMod) {
5250    Operands.push_back(ARMOperand::CreateImm(
5251          MCConstantExpr::Create(ProcessorIMod, getContext()),
5252                                 NameLoc, NameLoc));
5253  }
5254
5255  // Add the remaining tokens in the mnemonic.
5256  while (Next != StringRef::npos) {
5257    Start = Next;
5258    Next = Name.find('.', Start + 1);
5259    StringRef ExtraToken = Name.slice(Start, Next);
5260
5261    // Some NEON instructions have an optional datatype suffix that is
5262    // completely ignored. Check for that.
5263    if (isDataTypeToken(ExtraToken) &&
5264        doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
5265      continue;
5266
5267    // For for ARM mode generate an error if the .n qualifier is used.
5268    if (ExtraToken == ".n" && !isThumb()) {
5269      SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5270      return Error(Loc, "instruction with .n (narrow) qualifier not allowed in "
5271                   "arm mode");
5272    }
5273
5274    // The .n qualifier is always discarded as that is what the tables
5275    // and matcher expect.  In ARM mode the .w qualifier has no effect,
5276    // so discard it to avoid errors that can be caused by the matcher.
5277    if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) {
5278      SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5279      Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
5280    }
5281  }
5282
5283  // Read the remaining operands.
5284  if (getLexer().isNot(AsmToken::EndOfStatement)) {
5285    // Read the first operand.
5286    if (parseOperand(Operands, Mnemonic)) {
5287      Parser.eatToEndOfStatement();
5288      return true;
5289    }
5290
5291    while (getLexer().is(AsmToken::Comma)) {
5292      Parser.Lex();  // Eat the comma.
5293
5294      // Parse and remember the operand.
5295      if (parseOperand(Operands, Mnemonic)) {
5296        Parser.eatToEndOfStatement();
5297        return true;
5298      }
5299    }
5300  }
5301
5302  if (getLexer().isNot(AsmToken::EndOfStatement)) {
5303    SMLoc Loc = getLexer().getLoc();
5304    Parser.eatToEndOfStatement();
5305    return Error(Loc, "unexpected token in argument list");
5306  }
5307
5308  Parser.Lex(); // Consume the EndOfStatement
5309
5310  // Some instructions, mostly Thumb, have forms for the same mnemonic that
5311  // do and don't have a cc_out optional-def operand. With some spot-checks
5312  // of the operand list, we can figure out which variant we're trying to
5313  // parse and adjust accordingly before actually matching. We shouldn't ever
5314  // try to remove a cc_out operand that was explicitly set on the the
5315  // mnemonic, of course (CarrySetting == true). Reason number #317 the
5316  // table driven matcher doesn't fit well with the ARM instruction set.
5317  if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
5318    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5319    Operands.erase(Operands.begin() + 1);
5320    delete Op;
5321  }
5322
5323  // ARM mode 'blx' need special handling, as the register operand version
5324  // is predicable, but the label operand version is not. So, we can't rely
5325  // on the Mnemonic based checking to correctly figure out when to put
5326  // a k_CondCode operand in the list. If we're trying to match the label
5327  // version, remove the k_CondCode operand here.
5328  if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
5329      static_cast<ARMOperand*>(Operands[2])->isImm()) {
5330    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5331    Operands.erase(Operands.begin() + 1);
5332    delete Op;
5333  }
5334
5335  // Adjust operands of ldrexd/strexd to MCK_GPRPair.
5336  // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
5337  // a single GPRPair reg operand is used in the .td file to replace the two
5338  // GPRs. However, when parsing from asm, the two GRPs cannot be automatically
5339  // expressed as a GPRPair, so we have to manually merge them.
5340  // FIXME: We would really like to be able to tablegen'erate this.
5341  if (!isThumb() && Operands.size() > 4 &&
5342      (Mnemonic == "ldrexd" || Mnemonic == "strexd")) {
5343    bool isLoad = (Mnemonic == "ldrexd");
5344    unsigned Idx = isLoad ? 2 : 3;
5345    ARMOperand* Op1 = static_cast<ARMOperand*>(Operands[Idx]);
5346    ARMOperand* Op2 = static_cast<ARMOperand*>(Operands[Idx+1]);
5347
5348    const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID);
5349    // Adjust only if Op1 and Op2 are GPRs.
5350    if (Op1->isReg() && Op2->isReg() && MRC.contains(Op1->getReg()) &&
5351        MRC.contains(Op2->getReg())) {
5352      unsigned Reg1 = Op1->getReg();
5353      unsigned Reg2 = Op2->getReg();
5354      unsigned Rt = MRI->getEncodingValue(Reg1);
5355      unsigned Rt2 = MRI->getEncodingValue(Reg2);
5356
5357      // Rt2 must be Rt + 1 and Rt must be even.
5358      if (Rt + 1 != Rt2 || (Rt & 1)) {
5359        Error(Op2->getStartLoc(), isLoad ?
5360            "destination operands must be sequential" :
5361            "source operands must be sequential");
5362        return true;
5363      }
5364      unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0,
5365          &(MRI->getRegClass(ARM::GPRPairRegClassID)));
5366      Operands.erase(Operands.begin() + Idx, Operands.begin() + Idx + 2);
5367      Operands.insert(Operands.begin() + Idx, ARMOperand::CreateReg(
5368            NewReg, Op1->getStartLoc(), Op2->getEndLoc()));
5369      delete Op1;
5370      delete Op2;
5371    }
5372  }
5373
5374  return false;
5375}
5376
5377// Validate context-sensitive operand constraints.
5378
5379// return 'true' if register list contains non-low GPR registers,
5380// 'false' otherwise. If Reg is in the register list or is HiReg, set
5381// 'containsReg' to true.
5382static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
5383                                 unsigned HiReg, bool &containsReg) {
5384  containsReg = false;
5385  for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5386    unsigned OpReg = Inst.getOperand(i).getReg();
5387    if (OpReg == Reg)
5388      containsReg = true;
5389    // Anything other than a low register isn't legal here.
5390    if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
5391      return true;
5392  }
5393  return false;
5394}
5395
5396// Check if the specified regisgter is in the register list of the inst,
5397// starting at the indicated operand number.
5398static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
5399  for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5400    unsigned OpReg = Inst.getOperand(i).getReg();
5401    if (OpReg == Reg)
5402      return true;
5403  }
5404  return false;
5405}
5406
5407// FIXME: We would really prefer to have MCInstrInfo (the wrapper around
5408// the ARMInsts array) instead. Getting that here requires awkward
5409// API changes, though. Better way?
5410namespace llvm {
5411extern const MCInstrDesc ARMInsts[];
5412}
5413static const MCInstrDesc &getInstDesc(unsigned Opcode) {
5414  return ARMInsts[Opcode];
5415}
5416
5417// FIXME: We would really like to be able to tablegen'erate this.
5418bool ARMAsmParser::
5419validateInstruction(MCInst &Inst,
5420                    const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5421  const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
5422  SMLoc Loc = Operands[0]->getStartLoc();
5423  // Check the IT block state first.
5424  // NOTE: BKPT instruction has the interesting property of being
5425  // allowed in IT blocks, but not being predicable.  It just always
5426  // executes.
5427  if (inITBlock() && Inst.getOpcode() != ARM::tBKPT &&
5428      Inst.getOpcode() != ARM::BKPT) {
5429    unsigned bit = 1;
5430    if (ITState.FirstCond)
5431      ITState.FirstCond = false;
5432    else
5433      bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
5434    // The instruction must be predicable.
5435    if (!MCID.isPredicable())
5436      return Error(Loc, "instructions in IT block must be predicable");
5437    unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
5438    unsigned ITCond = bit ? ITState.Cond :
5439      ARMCC::getOppositeCondition(ITState.Cond);
5440    if (Cond != ITCond) {
5441      // Find the condition code Operand to get its SMLoc information.
5442      SMLoc CondLoc;
5443      for (unsigned i = 1; i < Operands.size(); ++i)
5444        if (static_cast<ARMOperand*>(Operands[i])->isCondCode())
5445          CondLoc = Operands[i]->getStartLoc();
5446      return Error(CondLoc, "incorrect condition in IT block; got '" +
5447                   StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
5448                   "', but expected '" +
5449                   ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
5450    }
5451  // Check for non-'al' condition codes outside of the IT block.
5452  } else if (isThumbTwo() && MCID.isPredicable() &&
5453             Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
5454             ARMCC::AL && Inst.getOpcode() != ARM::tB &&
5455             Inst.getOpcode() != ARM::t2B)
5456    return Error(Loc, "predicated instructions must be in IT block");
5457
5458  switch (Inst.getOpcode()) {
5459  case ARM::LDRD:
5460  case ARM::LDRD_PRE:
5461  case ARM::LDRD_POST: {
5462    // Rt2 must be Rt + 1.
5463    unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5464    unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5465    if (Rt2 != Rt + 1)
5466      return Error(Operands[3]->getStartLoc(),
5467                   "destination operands must be sequential");
5468    return false;
5469  }
5470  case ARM::STRD: {
5471    // Rt2 must be Rt + 1.
5472    unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5473    unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5474    if (Rt2 != Rt + 1)
5475      return Error(Operands[3]->getStartLoc(),
5476                   "source operands must be sequential");
5477    return false;
5478  }
5479  case ARM::STRD_PRE:
5480  case ARM::STRD_POST: {
5481    // Rt2 must be Rt + 1.
5482    unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5483    unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
5484    if (Rt2 != Rt + 1)
5485      return Error(Operands[3]->getStartLoc(),
5486                   "source operands must be sequential");
5487    return false;
5488  }
5489  case ARM::SBFX:
5490  case ARM::UBFX: {
5491    // width must be in range [1, 32-lsb]
5492    unsigned lsb = Inst.getOperand(2).getImm();
5493    unsigned widthm1 = Inst.getOperand(3).getImm();
5494    if (widthm1 >= 32 - lsb)
5495      return Error(Operands[5]->getStartLoc(),
5496                   "bitfield width must be in range [1,32-lsb]");
5497    return false;
5498  }
5499  case ARM::tLDMIA: {
5500    // If we're parsing Thumb2, the .w variant is available and handles
5501    // most cases that are normally illegal for a Thumb1 LDM
5502    // instruction. We'll make the transformation in processInstruction()
5503    // if necessary.
5504    //
5505    // Thumb LDM instructions are writeback iff the base register is not
5506    // in the register list.
5507    unsigned Rn = Inst.getOperand(0).getReg();
5508    bool hasWritebackToken =
5509      (static_cast<ARMOperand*>(Operands[3])->isToken() &&
5510       static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
5511    bool listContainsBase;
5512    if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo())
5513      return Error(Operands[3 + hasWritebackToken]->getStartLoc(),
5514                   "registers must be in range r0-r7");
5515    // If we should have writeback, then there should be a '!' token.
5516    if (!listContainsBase && !hasWritebackToken && !isThumbTwo())
5517      return Error(Operands[2]->getStartLoc(),
5518                   "writeback operator '!' expected");
5519    // If we should not have writeback, there must not be a '!'. This is
5520    // true even for the 32-bit wide encodings.
5521    if (listContainsBase && hasWritebackToken)
5522      return Error(Operands[3]->getStartLoc(),
5523                   "writeback operator '!' not allowed when base register "
5524                   "in register list");
5525
5526    break;
5527  }
5528  case ARM::t2LDMIA_UPD: {
5529    if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
5530      return Error(Operands[4]->getStartLoc(),
5531                   "writeback operator '!' not allowed when base register "
5532                   "in register list");
5533    break;
5534  }
5535  case ARM::tMUL: {
5536    // The second source operand must be the same register as the destination
5537    // operand.
5538    //
5539    // In this case, we must directly check the parsed operands because the
5540    // cvtThumbMultiply() function is written in such a way that it guarantees
5541    // this first statement is always true for the new Inst.  Essentially, the
5542    // destination is unconditionally copied into the second source operand
5543    // without checking to see if it matches what we actually parsed.
5544    if (Operands.size() == 6 &&
5545        (((ARMOperand*)Operands[3])->getReg() !=
5546         ((ARMOperand*)Operands[5])->getReg()) &&
5547        (((ARMOperand*)Operands[3])->getReg() !=
5548         ((ARMOperand*)Operands[4])->getReg())) {
5549      return Error(Operands[3]->getStartLoc(),
5550                   "destination register must match source register");
5551    }
5552    break;
5553  }
5554  // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
5555  // so only issue a diagnostic for thumb1. The instructions will be
5556  // switched to the t2 encodings in processInstruction() if necessary.
5557  case ARM::tPOP: {
5558    bool listContainsBase;
5559    if (checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase) &&
5560        !isThumbTwo())
5561      return Error(Operands[2]->getStartLoc(),
5562                   "registers must be in range r0-r7 or pc");
5563    break;
5564  }
5565  case ARM::tPUSH: {
5566    bool listContainsBase;
5567    if (checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase) &&
5568        !isThumbTwo())
5569      return Error(Operands[2]->getStartLoc(),
5570                   "registers must be in range r0-r7 or lr");
5571    break;
5572  }
5573  case ARM::tSTMIA_UPD: {
5574    bool listContainsBase;
5575    if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase) && !isThumbTwo())
5576      return Error(Operands[4]->getStartLoc(),
5577                   "registers must be in range r0-r7");
5578    break;
5579  }
5580  case ARM::tADDrSP: {
5581    // If the non-SP source operand and the destination operand are not the
5582    // same, we need thumb2 (for the wide encoding), or we have an error.
5583    if (!isThumbTwo() &&
5584        Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
5585      return Error(Operands[4]->getStartLoc(),
5586                   "source register must be the same as destination");
5587    }
5588    break;
5589  }
5590  }
5591
5592  return false;
5593}
5594
5595static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
5596  switch(Opc) {
5597  default: llvm_unreachable("unexpected opcode!");
5598  // VST1LN
5599  case ARM::VST1LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST1LNd8_UPD;
5600  case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5601  case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5602  case ARM::VST1LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST1LNd8_UPD;
5603  case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5604  case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5605  case ARM::VST1LNdAsm_8:  Spacing = 1; return ARM::VST1LNd8;
5606  case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
5607  case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
5608
5609  // VST2LN
5610  case ARM::VST2LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST2LNd8_UPD;
5611  case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5612  case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5613  case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5614  case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5615
5616  case ARM::VST2LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST2LNd8_UPD;
5617  case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5618  case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5619  case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5620  case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5621
5622  case ARM::VST2LNdAsm_8:  Spacing = 1; return ARM::VST2LNd8;
5623  case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
5624  case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
5625  case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
5626  case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
5627
5628  // VST3LN
5629  case ARM::VST3LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST3LNd8_UPD;
5630  case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5631  case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5632  case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
5633  case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5634  case ARM::VST3LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST3LNd8_UPD;
5635  case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5636  case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5637  case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
5638  case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5639  case ARM::VST3LNdAsm_8:  Spacing = 1; return ARM::VST3LNd8;
5640  case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
5641  case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
5642  case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
5643  case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
5644
5645  // VST3
5646  case ARM::VST3dWB_fixed_Asm_8:  Spacing = 1; return ARM::VST3d8_UPD;
5647  case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5648  case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5649  case ARM::VST3qWB_fixed_Asm_8:  Spacing = 2; return ARM::VST3q8_UPD;
5650  case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5651  case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5652  case ARM::VST3dWB_register_Asm_8:  Spacing = 1; return ARM::VST3d8_UPD;
5653  case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5654  case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5655  case ARM::VST3qWB_register_Asm_8:  Spacing = 2; return ARM::VST3q8_UPD;
5656  case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5657  case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5658  case ARM::VST3dAsm_8:  Spacing = 1; return ARM::VST3d8;
5659  case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
5660  case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
5661  case ARM::VST3qAsm_8:  Spacing = 2; return ARM::VST3q8;
5662  case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
5663  case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
5664
5665  // VST4LN
5666  case ARM::VST4LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST4LNd8_UPD;
5667  case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5668  case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5669  case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
5670  case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5671  case ARM::VST4LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST4LNd8_UPD;
5672  case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5673  case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5674  case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
5675  case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5676  case ARM::VST4LNdAsm_8:  Spacing = 1; return ARM::VST4LNd8;
5677  case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
5678  case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
5679  case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
5680  case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
5681
5682  // VST4
5683  case ARM::VST4dWB_fixed_Asm_8:  Spacing = 1; return ARM::VST4d8_UPD;
5684  case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5685  case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5686  case ARM::VST4qWB_fixed_Asm_8:  Spacing = 2; return ARM::VST4q8_UPD;
5687  case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5688  case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5689  case ARM::VST4dWB_register_Asm_8:  Spacing = 1; return ARM::VST4d8_UPD;
5690  case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5691  case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5692  case ARM::VST4qWB_register_Asm_8:  Spacing = 2; return ARM::VST4q8_UPD;
5693  case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5694  case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5695  case ARM::VST4dAsm_8:  Spacing = 1; return ARM::VST4d8;
5696  case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
5697  case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
5698  case ARM::VST4qAsm_8:  Spacing = 2; return ARM::VST4q8;
5699  case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
5700  case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
5701  }
5702}
5703
5704static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
5705  switch(Opc) {
5706  default: llvm_unreachable("unexpected opcode!");
5707  // VLD1LN
5708  case ARM::VLD1LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD1LNd8_UPD;
5709  case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5710  case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5711  case ARM::VLD1LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD1LNd8_UPD;
5712  case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5713  case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5714  case ARM::VLD1LNdAsm_8:  Spacing = 1; return ARM::VLD1LNd8;
5715  case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
5716  case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
5717
5718  // VLD2LN
5719  case ARM::VLD2LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD2LNd8_UPD;
5720  case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5721  case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5722  case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
5723  case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5724  case ARM::VLD2LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD2LNd8_UPD;
5725  case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5726  case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5727  case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
5728  case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5729  case ARM::VLD2LNdAsm_8:  Spacing = 1; return ARM::VLD2LNd8;
5730  case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
5731  case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
5732  case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
5733  case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
5734
5735  // VLD3DUP
5736  case ARM::VLD3DUPdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3DUPd8_UPD;
5737  case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5738  case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5739  case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
5740  case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPq16_UPD;
5741  case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5742  case ARM::VLD3DUPdWB_register_Asm_8:  Spacing = 1; return ARM::VLD3DUPd8_UPD;
5743  case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5744  case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5745  case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
5746  case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
5747  case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5748  case ARM::VLD3DUPdAsm_8:  Spacing = 1; return ARM::VLD3DUPd8;
5749  case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
5750  case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
5751  case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
5752  case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
5753  case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
5754
5755  // VLD3LN
5756  case ARM::VLD3LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3LNd8_UPD;
5757  case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5758  case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5759  case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
5760  case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5761  case ARM::VLD3LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD3LNd8_UPD;
5762  case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5763  case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5764  case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
5765  case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5766  case ARM::VLD3LNdAsm_8:  Spacing = 1; return ARM::VLD3LNd8;
5767  case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
5768  case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
5769  case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
5770  case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
5771
5772  // VLD3
5773  case ARM::VLD3dWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3d8_UPD;
5774  case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5775  case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5776  case ARM::VLD3qWB_fixed_Asm_8:  Spacing = 2; return ARM::VLD3q8_UPD;
5777  case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5778  case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5779  case ARM::VLD3dWB_register_Asm_8:  Spacing = 1; return ARM::VLD3d8_UPD;
5780  case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5781  case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5782  case ARM::VLD3qWB_register_Asm_8:  Spacing = 2; return ARM::VLD3q8_UPD;
5783  case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5784  case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5785  case ARM::VLD3dAsm_8:  Spacing = 1; return ARM::VLD3d8;
5786  case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
5787  case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
5788  case ARM::VLD3qAsm_8:  Spacing = 2; return ARM::VLD3q8;
5789  case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
5790  case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
5791
5792  // VLD4LN
5793  case ARM::VLD4LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4LNd8_UPD;
5794  case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5795  case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5796  case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNq16_UPD;
5797  case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5798  case ARM::VLD4LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD4LNd8_UPD;
5799  case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5800  case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5801  case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
5802  case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5803  case ARM::VLD4LNdAsm_8:  Spacing = 1; return ARM::VLD4LNd8;
5804  case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
5805  case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
5806  case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
5807  case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
5808
5809  // VLD4DUP
5810  case ARM::VLD4DUPdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4DUPd8_UPD;
5811  case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5812  case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5813  case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
5814  case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
5815  case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5816  case ARM::VLD4DUPdWB_register_Asm_8:  Spacing = 1; return ARM::VLD4DUPd8_UPD;
5817  case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5818  case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5819  case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
5820  case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
5821  case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5822  case ARM::VLD4DUPdAsm_8:  Spacing = 1; return ARM::VLD4DUPd8;
5823  case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
5824  case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
5825  case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
5826  case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
5827  case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
5828
5829  // VLD4
5830  case ARM::VLD4dWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4d8_UPD;
5831  case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5832  case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5833  case ARM::VLD4qWB_fixed_Asm_8:  Spacing = 2; return ARM::VLD4q8_UPD;
5834  case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5835  case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5836  case ARM::VLD4dWB_register_Asm_8:  Spacing = 1; return ARM::VLD4d8_UPD;
5837  case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5838  case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5839  case ARM::VLD4qWB_register_Asm_8:  Spacing = 2; return ARM::VLD4q8_UPD;
5840  case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5841  case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5842  case ARM::VLD4dAsm_8:  Spacing = 1; return ARM::VLD4d8;
5843  case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
5844  case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
5845  case ARM::VLD4qAsm_8:  Spacing = 2; return ARM::VLD4q8;
5846  case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
5847  case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
5848  }
5849}
5850
5851bool ARMAsmParser::
5852processInstruction(MCInst &Inst,
5853                   const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5854  switch (Inst.getOpcode()) {
5855  // Alias for alternate form of 'ADR Rd, #imm' instruction.
5856  case ARM::ADDri: {
5857    if (Inst.getOperand(1).getReg() != ARM::PC ||
5858        Inst.getOperand(5).getReg() != 0)
5859      return false;
5860    MCInst TmpInst;
5861    TmpInst.setOpcode(ARM::ADR);
5862    TmpInst.addOperand(Inst.getOperand(0));
5863    TmpInst.addOperand(Inst.getOperand(2));
5864    TmpInst.addOperand(Inst.getOperand(3));
5865    TmpInst.addOperand(Inst.getOperand(4));
5866    Inst = TmpInst;
5867    return true;
5868  }
5869  // Aliases for alternate PC+imm syntax of LDR instructions.
5870  case ARM::t2LDRpcrel:
5871    // Select the narrow version if the immediate will fit.
5872    if (Inst.getOperand(1).getImm() > 0 &&
5873        Inst.getOperand(1).getImm() <= 0xff &&
5874        !(static_cast<ARMOperand*>(Operands[2])->isToken() &&
5875         static_cast<ARMOperand*>(Operands[2])->getToken() == ".w"))
5876      Inst.setOpcode(ARM::tLDRpci);
5877    else
5878      Inst.setOpcode(ARM::t2LDRpci);
5879    return true;
5880  case ARM::t2LDRBpcrel:
5881    Inst.setOpcode(ARM::t2LDRBpci);
5882    return true;
5883  case ARM::t2LDRHpcrel:
5884    Inst.setOpcode(ARM::t2LDRHpci);
5885    return true;
5886  case ARM::t2LDRSBpcrel:
5887    Inst.setOpcode(ARM::t2LDRSBpci);
5888    return true;
5889  case ARM::t2LDRSHpcrel:
5890    Inst.setOpcode(ARM::t2LDRSHpci);
5891    return true;
5892  // Handle NEON VST complex aliases.
5893  case ARM::VST1LNdWB_register_Asm_8:
5894  case ARM::VST1LNdWB_register_Asm_16:
5895  case ARM::VST1LNdWB_register_Asm_32: {
5896    MCInst TmpInst;
5897    // Shuffle the operands around so the lane index operand is in the
5898    // right place.
5899    unsigned Spacing;
5900    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5901    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5902    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5903    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5904    TmpInst.addOperand(Inst.getOperand(4)); // Rm
5905    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5906    TmpInst.addOperand(Inst.getOperand(1)); // lane
5907    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5908    TmpInst.addOperand(Inst.getOperand(6));
5909    Inst = TmpInst;
5910    return true;
5911  }
5912
5913  case ARM::VST2LNdWB_register_Asm_8:
5914  case ARM::VST2LNdWB_register_Asm_16:
5915  case ARM::VST2LNdWB_register_Asm_32:
5916  case ARM::VST2LNqWB_register_Asm_16:
5917  case ARM::VST2LNqWB_register_Asm_32: {
5918    MCInst TmpInst;
5919    // Shuffle the operands around so the lane index operand is in the
5920    // right place.
5921    unsigned Spacing;
5922    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5923    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5924    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5925    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5926    TmpInst.addOperand(Inst.getOperand(4)); // Rm
5927    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5928    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5929                                            Spacing));
5930    TmpInst.addOperand(Inst.getOperand(1)); // lane
5931    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5932    TmpInst.addOperand(Inst.getOperand(6));
5933    Inst = TmpInst;
5934    return true;
5935  }
5936
5937  case ARM::VST3LNdWB_register_Asm_8:
5938  case ARM::VST3LNdWB_register_Asm_16:
5939  case ARM::VST3LNdWB_register_Asm_32:
5940  case ARM::VST3LNqWB_register_Asm_16:
5941  case ARM::VST3LNqWB_register_Asm_32: {
5942    MCInst TmpInst;
5943    // Shuffle the operands around so the lane index operand is in the
5944    // right place.
5945    unsigned Spacing;
5946    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5947    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5948    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5949    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5950    TmpInst.addOperand(Inst.getOperand(4)); // Rm
5951    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5952    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5953                                            Spacing));
5954    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5955                                            Spacing * 2));
5956    TmpInst.addOperand(Inst.getOperand(1)); // lane
5957    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5958    TmpInst.addOperand(Inst.getOperand(6));
5959    Inst = TmpInst;
5960    return true;
5961  }
5962
5963  case ARM::VST4LNdWB_register_Asm_8:
5964  case ARM::VST4LNdWB_register_Asm_16:
5965  case ARM::VST4LNdWB_register_Asm_32:
5966  case ARM::VST4LNqWB_register_Asm_16:
5967  case ARM::VST4LNqWB_register_Asm_32: {
5968    MCInst TmpInst;
5969    // Shuffle the operands around so the lane index operand is in the
5970    // right place.
5971    unsigned Spacing;
5972    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5973    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5974    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5975    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5976    TmpInst.addOperand(Inst.getOperand(4)); // Rm
5977    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5978    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5979                                            Spacing));
5980    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5981                                            Spacing * 2));
5982    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5983                                            Spacing * 3));
5984    TmpInst.addOperand(Inst.getOperand(1)); // lane
5985    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5986    TmpInst.addOperand(Inst.getOperand(6));
5987    Inst = TmpInst;
5988    return true;
5989  }
5990
5991  case ARM::VST1LNdWB_fixed_Asm_8:
5992  case ARM::VST1LNdWB_fixed_Asm_16:
5993  case ARM::VST1LNdWB_fixed_Asm_32: {
5994    MCInst TmpInst;
5995    // Shuffle the operands around so the lane index operand is in the
5996    // right place.
5997    unsigned Spacing;
5998    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5999    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6000    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6001    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6002    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6003    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6004    TmpInst.addOperand(Inst.getOperand(1)); // lane
6005    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6006    TmpInst.addOperand(Inst.getOperand(5));
6007    Inst = TmpInst;
6008    return true;
6009  }
6010
6011  case ARM::VST2LNdWB_fixed_Asm_8:
6012  case ARM::VST2LNdWB_fixed_Asm_16:
6013  case ARM::VST2LNdWB_fixed_Asm_32:
6014  case ARM::VST2LNqWB_fixed_Asm_16:
6015  case ARM::VST2LNqWB_fixed_Asm_32: {
6016    MCInst TmpInst;
6017    // Shuffle the operands around so the lane index operand is in the
6018    // right place.
6019    unsigned Spacing;
6020    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6021    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6022    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6023    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6024    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6025    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6026    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6027                                            Spacing));
6028    TmpInst.addOperand(Inst.getOperand(1)); // lane
6029    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6030    TmpInst.addOperand(Inst.getOperand(5));
6031    Inst = TmpInst;
6032    return true;
6033  }
6034
6035  case ARM::VST3LNdWB_fixed_Asm_8:
6036  case ARM::VST3LNdWB_fixed_Asm_16:
6037  case ARM::VST3LNdWB_fixed_Asm_32:
6038  case ARM::VST3LNqWB_fixed_Asm_16:
6039  case ARM::VST3LNqWB_fixed_Asm_32: {
6040    MCInst TmpInst;
6041    // Shuffle the operands around so the lane index operand is in the
6042    // right place.
6043    unsigned Spacing;
6044    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6045    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6046    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6047    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6048    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6049    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6050    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6051                                            Spacing));
6052    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6053                                            Spacing * 2));
6054    TmpInst.addOperand(Inst.getOperand(1)); // lane
6055    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6056    TmpInst.addOperand(Inst.getOperand(5));
6057    Inst = TmpInst;
6058    return true;
6059  }
6060
6061  case ARM::VST4LNdWB_fixed_Asm_8:
6062  case ARM::VST4LNdWB_fixed_Asm_16:
6063  case ARM::VST4LNdWB_fixed_Asm_32:
6064  case ARM::VST4LNqWB_fixed_Asm_16:
6065  case ARM::VST4LNqWB_fixed_Asm_32: {
6066    MCInst TmpInst;
6067    // Shuffle the operands around so the lane index operand is in the
6068    // right place.
6069    unsigned Spacing;
6070    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6071    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6072    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6073    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6074    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6075    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6076    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6077                                            Spacing));
6078    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6079                                            Spacing * 2));
6080    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6081                                            Spacing * 3));
6082    TmpInst.addOperand(Inst.getOperand(1)); // lane
6083    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6084    TmpInst.addOperand(Inst.getOperand(5));
6085    Inst = TmpInst;
6086    return true;
6087  }
6088
6089  case ARM::VST1LNdAsm_8:
6090  case ARM::VST1LNdAsm_16:
6091  case ARM::VST1LNdAsm_32: {
6092    MCInst TmpInst;
6093    // Shuffle the operands around so the lane index operand is in the
6094    // right place.
6095    unsigned Spacing;
6096    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6097    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6098    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6099    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6100    TmpInst.addOperand(Inst.getOperand(1)); // lane
6101    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6102    TmpInst.addOperand(Inst.getOperand(5));
6103    Inst = TmpInst;
6104    return true;
6105  }
6106
6107  case ARM::VST2LNdAsm_8:
6108  case ARM::VST2LNdAsm_16:
6109  case ARM::VST2LNdAsm_32:
6110  case ARM::VST2LNqAsm_16:
6111  case ARM::VST2LNqAsm_32: {
6112    MCInst TmpInst;
6113    // Shuffle the operands around so the lane index operand is in the
6114    // right place.
6115    unsigned Spacing;
6116    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6117    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6118    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6119    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6120    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6121                                            Spacing));
6122    TmpInst.addOperand(Inst.getOperand(1)); // lane
6123    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6124    TmpInst.addOperand(Inst.getOperand(5));
6125    Inst = TmpInst;
6126    return true;
6127  }
6128
6129  case ARM::VST3LNdAsm_8:
6130  case ARM::VST3LNdAsm_16:
6131  case ARM::VST3LNdAsm_32:
6132  case ARM::VST3LNqAsm_16:
6133  case ARM::VST3LNqAsm_32: {
6134    MCInst TmpInst;
6135    // Shuffle the operands around so the lane index operand is in the
6136    // right place.
6137    unsigned Spacing;
6138    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6139    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6140    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6141    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6142    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6143                                            Spacing));
6144    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6145                                            Spacing * 2));
6146    TmpInst.addOperand(Inst.getOperand(1)); // lane
6147    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6148    TmpInst.addOperand(Inst.getOperand(5));
6149    Inst = TmpInst;
6150    return true;
6151  }
6152
6153  case ARM::VST4LNdAsm_8:
6154  case ARM::VST4LNdAsm_16:
6155  case ARM::VST4LNdAsm_32:
6156  case ARM::VST4LNqAsm_16:
6157  case ARM::VST4LNqAsm_32: {
6158    MCInst TmpInst;
6159    // Shuffle the operands around so the lane index operand is in the
6160    // right place.
6161    unsigned Spacing;
6162    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6163    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6164    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6165    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6166    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6167                                            Spacing));
6168    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6169                                            Spacing * 2));
6170    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6171                                            Spacing * 3));
6172    TmpInst.addOperand(Inst.getOperand(1)); // lane
6173    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6174    TmpInst.addOperand(Inst.getOperand(5));
6175    Inst = TmpInst;
6176    return true;
6177  }
6178
6179  // Handle NEON VLD complex aliases.
6180  case ARM::VLD1LNdWB_register_Asm_8:
6181  case ARM::VLD1LNdWB_register_Asm_16:
6182  case ARM::VLD1LNdWB_register_Asm_32: {
6183    MCInst TmpInst;
6184    // Shuffle the operands around so the lane index operand is in the
6185    // right place.
6186    unsigned Spacing;
6187    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6188    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6189    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6190    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6191    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6192    TmpInst.addOperand(Inst.getOperand(4)); // Rm
6193    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6194    TmpInst.addOperand(Inst.getOperand(1)); // lane
6195    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6196    TmpInst.addOperand(Inst.getOperand(6));
6197    Inst = TmpInst;
6198    return true;
6199  }
6200
6201  case ARM::VLD2LNdWB_register_Asm_8:
6202  case ARM::VLD2LNdWB_register_Asm_16:
6203  case ARM::VLD2LNdWB_register_Asm_32:
6204  case ARM::VLD2LNqWB_register_Asm_16:
6205  case ARM::VLD2LNqWB_register_Asm_32: {
6206    MCInst TmpInst;
6207    // Shuffle the operands around so the lane index operand is in the
6208    // right place.
6209    unsigned Spacing;
6210    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6211    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6212    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6213                                            Spacing));
6214    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6215    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6216    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6217    TmpInst.addOperand(Inst.getOperand(4)); // Rm
6218    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6219    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6220                                            Spacing));
6221    TmpInst.addOperand(Inst.getOperand(1)); // lane
6222    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6223    TmpInst.addOperand(Inst.getOperand(6));
6224    Inst = TmpInst;
6225    return true;
6226  }
6227
6228  case ARM::VLD3LNdWB_register_Asm_8:
6229  case ARM::VLD3LNdWB_register_Asm_16:
6230  case ARM::VLD3LNdWB_register_Asm_32:
6231  case ARM::VLD3LNqWB_register_Asm_16:
6232  case ARM::VLD3LNqWB_register_Asm_32: {
6233    MCInst TmpInst;
6234    // Shuffle the operands around so the lane index operand is in the
6235    // right place.
6236    unsigned Spacing;
6237    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6238    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6239    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6240                                            Spacing));
6241    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6242                                            Spacing * 2));
6243    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6244    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6245    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6246    TmpInst.addOperand(Inst.getOperand(4)); // Rm
6247    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6248    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6249                                            Spacing));
6250    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6251                                            Spacing * 2));
6252    TmpInst.addOperand(Inst.getOperand(1)); // lane
6253    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6254    TmpInst.addOperand(Inst.getOperand(6));
6255    Inst = TmpInst;
6256    return true;
6257  }
6258
6259  case ARM::VLD4LNdWB_register_Asm_8:
6260  case ARM::VLD4LNdWB_register_Asm_16:
6261  case ARM::VLD4LNdWB_register_Asm_32:
6262  case ARM::VLD4LNqWB_register_Asm_16:
6263  case ARM::VLD4LNqWB_register_Asm_32: {
6264    MCInst TmpInst;
6265    // Shuffle the operands around so the lane index operand is in the
6266    // right place.
6267    unsigned Spacing;
6268    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6269    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6270    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6271                                            Spacing));
6272    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6273                                            Spacing * 2));
6274    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6275                                            Spacing * 3));
6276    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6277    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6278    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6279    TmpInst.addOperand(Inst.getOperand(4)); // Rm
6280    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6281    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6282                                            Spacing));
6283    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6284                                            Spacing * 2));
6285    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6286                                            Spacing * 3));
6287    TmpInst.addOperand(Inst.getOperand(1)); // lane
6288    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6289    TmpInst.addOperand(Inst.getOperand(6));
6290    Inst = TmpInst;
6291    return true;
6292  }
6293
6294  case ARM::VLD1LNdWB_fixed_Asm_8:
6295  case ARM::VLD1LNdWB_fixed_Asm_16:
6296  case ARM::VLD1LNdWB_fixed_Asm_32: {
6297    MCInst TmpInst;
6298    // Shuffle the operands around so the lane index operand is in the
6299    // right place.
6300    unsigned Spacing;
6301    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6302    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6303    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6304    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6305    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6306    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6307    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6308    TmpInst.addOperand(Inst.getOperand(1)); // lane
6309    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6310    TmpInst.addOperand(Inst.getOperand(5));
6311    Inst = TmpInst;
6312    return true;
6313  }
6314
6315  case ARM::VLD2LNdWB_fixed_Asm_8:
6316  case ARM::VLD2LNdWB_fixed_Asm_16:
6317  case ARM::VLD2LNdWB_fixed_Asm_32:
6318  case ARM::VLD2LNqWB_fixed_Asm_16:
6319  case ARM::VLD2LNqWB_fixed_Asm_32: {
6320    MCInst TmpInst;
6321    // Shuffle the operands around so the lane index operand is in the
6322    // right place.
6323    unsigned Spacing;
6324    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6325    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6326    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6327                                            Spacing));
6328    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6329    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6330    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6331    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6332    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6333    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6334                                            Spacing));
6335    TmpInst.addOperand(Inst.getOperand(1)); // lane
6336    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6337    TmpInst.addOperand(Inst.getOperand(5));
6338    Inst = TmpInst;
6339    return true;
6340  }
6341
6342  case ARM::VLD3LNdWB_fixed_Asm_8:
6343  case ARM::VLD3LNdWB_fixed_Asm_16:
6344  case ARM::VLD3LNdWB_fixed_Asm_32:
6345  case ARM::VLD3LNqWB_fixed_Asm_16:
6346  case ARM::VLD3LNqWB_fixed_Asm_32: {
6347    MCInst TmpInst;
6348    // Shuffle the operands around so the lane index operand is in the
6349    // right place.
6350    unsigned Spacing;
6351    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6352    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6353    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6354                                            Spacing));
6355    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6356                                            Spacing * 2));
6357    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6358    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6359    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6360    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6361    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6362    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6363                                            Spacing));
6364    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6365                                            Spacing * 2));
6366    TmpInst.addOperand(Inst.getOperand(1)); // lane
6367    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6368    TmpInst.addOperand(Inst.getOperand(5));
6369    Inst = TmpInst;
6370    return true;
6371  }
6372
6373  case ARM::VLD4LNdWB_fixed_Asm_8:
6374  case ARM::VLD4LNdWB_fixed_Asm_16:
6375  case ARM::VLD4LNdWB_fixed_Asm_32:
6376  case ARM::VLD4LNqWB_fixed_Asm_16:
6377  case ARM::VLD4LNqWB_fixed_Asm_32: {
6378    MCInst TmpInst;
6379    // Shuffle the operands around so the lane index operand is in the
6380    // right place.
6381    unsigned Spacing;
6382    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6383    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6384    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6385                                            Spacing));
6386    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6387                                            Spacing * 2));
6388    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6389                                            Spacing * 3));
6390    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6391    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6392    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6393    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6394    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6395    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6396                                            Spacing));
6397    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6398                                            Spacing * 2));
6399    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6400                                            Spacing * 3));
6401    TmpInst.addOperand(Inst.getOperand(1)); // lane
6402    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6403    TmpInst.addOperand(Inst.getOperand(5));
6404    Inst = TmpInst;
6405    return true;
6406  }
6407
6408  case ARM::VLD1LNdAsm_8:
6409  case ARM::VLD1LNdAsm_16:
6410  case ARM::VLD1LNdAsm_32: {
6411    MCInst TmpInst;
6412    // Shuffle the operands around so the lane index operand is in the
6413    // right place.
6414    unsigned Spacing;
6415    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6416    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6417    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6418    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6419    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6420    TmpInst.addOperand(Inst.getOperand(1)); // lane
6421    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6422    TmpInst.addOperand(Inst.getOperand(5));
6423    Inst = TmpInst;
6424    return true;
6425  }
6426
6427  case ARM::VLD2LNdAsm_8:
6428  case ARM::VLD2LNdAsm_16:
6429  case ARM::VLD2LNdAsm_32:
6430  case ARM::VLD2LNqAsm_16:
6431  case ARM::VLD2LNqAsm_32: {
6432    MCInst TmpInst;
6433    // Shuffle the operands around so the lane index operand is in the
6434    // right place.
6435    unsigned Spacing;
6436    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6437    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6438    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6439                                            Spacing));
6440    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6441    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6442    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6443    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6444                                            Spacing));
6445    TmpInst.addOperand(Inst.getOperand(1)); // lane
6446    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6447    TmpInst.addOperand(Inst.getOperand(5));
6448    Inst = TmpInst;
6449    return true;
6450  }
6451
6452  case ARM::VLD3LNdAsm_8:
6453  case ARM::VLD3LNdAsm_16:
6454  case ARM::VLD3LNdAsm_32:
6455  case ARM::VLD3LNqAsm_16:
6456  case ARM::VLD3LNqAsm_32: {
6457    MCInst TmpInst;
6458    // Shuffle the operands around so the lane index operand is in the
6459    // right place.
6460    unsigned Spacing;
6461    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6462    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6463    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6464                                            Spacing));
6465    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6466                                            Spacing * 2));
6467    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6468    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6469    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6470    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6471                                            Spacing));
6472    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6473                                            Spacing * 2));
6474    TmpInst.addOperand(Inst.getOperand(1)); // lane
6475    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6476    TmpInst.addOperand(Inst.getOperand(5));
6477    Inst = TmpInst;
6478    return true;
6479  }
6480
6481  case ARM::VLD4LNdAsm_8:
6482  case ARM::VLD4LNdAsm_16:
6483  case ARM::VLD4LNdAsm_32:
6484  case ARM::VLD4LNqAsm_16:
6485  case ARM::VLD4LNqAsm_32: {
6486    MCInst TmpInst;
6487    // Shuffle the operands around so the lane index operand is in the
6488    // right place.
6489    unsigned Spacing;
6490    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6491    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6492    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6493                                            Spacing));
6494    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6495                                            Spacing * 2));
6496    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6497                                            Spacing * 3));
6498    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6499    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6500    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6501    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6502                                            Spacing));
6503    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6504                                            Spacing * 2));
6505    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6506                                            Spacing * 3));
6507    TmpInst.addOperand(Inst.getOperand(1)); // lane
6508    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6509    TmpInst.addOperand(Inst.getOperand(5));
6510    Inst = TmpInst;
6511    return true;
6512  }
6513
6514  // VLD3DUP single 3-element structure to all lanes instructions.
6515  case ARM::VLD3DUPdAsm_8:
6516  case ARM::VLD3DUPdAsm_16:
6517  case ARM::VLD3DUPdAsm_32:
6518  case ARM::VLD3DUPqAsm_8:
6519  case ARM::VLD3DUPqAsm_16:
6520  case ARM::VLD3DUPqAsm_32: {
6521    MCInst TmpInst;
6522    unsigned Spacing;
6523    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6524    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6525    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6526                                            Spacing));
6527    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6528                                            Spacing * 2));
6529    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6530    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6531    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6532    TmpInst.addOperand(Inst.getOperand(4));
6533    Inst = TmpInst;
6534    return true;
6535  }
6536
6537  case ARM::VLD3DUPdWB_fixed_Asm_8:
6538  case ARM::VLD3DUPdWB_fixed_Asm_16:
6539  case ARM::VLD3DUPdWB_fixed_Asm_32:
6540  case ARM::VLD3DUPqWB_fixed_Asm_8:
6541  case ARM::VLD3DUPqWB_fixed_Asm_16:
6542  case ARM::VLD3DUPqWB_fixed_Asm_32: {
6543    MCInst TmpInst;
6544    unsigned Spacing;
6545    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6546    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6547    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6548                                            Spacing));
6549    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6550                                            Spacing * 2));
6551    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6552    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6553    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6554    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6555    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6556    TmpInst.addOperand(Inst.getOperand(4));
6557    Inst = TmpInst;
6558    return true;
6559  }
6560
6561  case ARM::VLD3DUPdWB_register_Asm_8:
6562  case ARM::VLD3DUPdWB_register_Asm_16:
6563  case ARM::VLD3DUPdWB_register_Asm_32:
6564  case ARM::VLD3DUPqWB_register_Asm_8:
6565  case ARM::VLD3DUPqWB_register_Asm_16:
6566  case ARM::VLD3DUPqWB_register_Asm_32: {
6567    MCInst TmpInst;
6568    unsigned Spacing;
6569    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6570    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6571    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6572                                            Spacing));
6573    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6574                                            Spacing * 2));
6575    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6576    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6577    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6578    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6579    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6580    TmpInst.addOperand(Inst.getOperand(5));
6581    Inst = TmpInst;
6582    return true;
6583  }
6584
6585  // VLD3 multiple 3-element structure instructions.
6586  case ARM::VLD3dAsm_8:
6587  case ARM::VLD3dAsm_16:
6588  case ARM::VLD3dAsm_32:
6589  case ARM::VLD3qAsm_8:
6590  case ARM::VLD3qAsm_16:
6591  case ARM::VLD3qAsm_32: {
6592    MCInst TmpInst;
6593    unsigned Spacing;
6594    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6595    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6596    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6597                                            Spacing));
6598    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6599                                            Spacing * 2));
6600    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6601    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6602    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6603    TmpInst.addOperand(Inst.getOperand(4));
6604    Inst = TmpInst;
6605    return true;
6606  }
6607
6608  case ARM::VLD3dWB_fixed_Asm_8:
6609  case ARM::VLD3dWB_fixed_Asm_16:
6610  case ARM::VLD3dWB_fixed_Asm_32:
6611  case ARM::VLD3qWB_fixed_Asm_8:
6612  case ARM::VLD3qWB_fixed_Asm_16:
6613  case ARM::VLD3qWB_fixed_Asm_32: {
6614    MCInst TmpInst;
6615    unsigned Spacing;
6616    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6617    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6618    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6619                                            Spacing));
6620    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6621                                            Spacing * 2));
6622    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6623    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6624    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6625    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6626    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6627    TmpInst.addOperand(Inst.getOperand(4));
6628    Inst = TmpInst;
6629    return true;
6630  }
6631
6632  case ARM::VLD3dWB_register_Asm_8:
6633  case ARM::VLD3dWB_register_Asm_16:
6634  case ARM::VLD3dWB_register_Asm_32:
6635  case ARM::VLD3qWB_register_Asm_8:
6636  case ARM::VLD3qWB_register_Asm_16:
6637  case ARM::VLD3qWB_register_Asm_32: {
6638    MCInst TmpInst;
6639    unsigned Spacing;
6640    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6641    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6642    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6643                                            Spacing));
6644    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6645                                            Spacing * 2));
6646    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6647    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6648    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6649    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6650    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6651    TmpInst.addOperand(Inst.getOperand(5));
6652    Inst = TmpInst;
6653    return true;
6654  }
6655
6656  // VLD4DUP single 3-element structure to all lanes instructions.
6657  case ARM::VLD4DUPdAsm_8:
6658  case ARM::VLD4DUPdAsm_16:
6659  case ARM::VLD4DUPdAsm_32:
6660  case ARM::VLD4DUPqAsm_8:
6661  case ARM::VLD4DUPqAsm_16:
6662  case ARM::VLD4DUPqAsm_32: {
6663    MCInst TmpInst;
6664    unsigned Spacing;
6665    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6666    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6667    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6668                                            Spacing));
6669    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6670                                            Spacing * 2));
6671    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6672                                            Spacing * 3));
6673    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6674    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6675    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6676    TmpInst.addOperand(Inst.getOperand(4));
6677    Inst = TmpInst;
6678    return true;
6679  }
6680
6681  case ARM::VLD4DUPdWB_fixed_Asm_8:
6682  case ARM::VLD4DUPdWB_fixed_Asm_16:
6683  case ARM::VLD4DUPdWB_fixed_Asm_32:
6684  case ARM::VLD4DUPqWB_fixed_Asm_8:
6685  case ARM::VLD4DUPqWB_fixed_Asm_16:
6686  case ARM::VLD4DUPqWB_fixed_Asm_32: {
6687    MCInst TmpInst;
6688    unsigned Spacing;
6689    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6690    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6691    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6692                                            Spacing));
6693    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6694                                            Spacing * 2));
6695    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6696                                            Spacing * 3));
6697    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6698    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6699    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6700    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6701    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6702    TmpInst.addOperand(Inst.getOperand(4));
6703    Inst = TmpInst;
6704    return true;
6705  }
6706
6707  case ARM::VLD4DUPdWB_register_Asm_8:
6708  case ARM::VLD4DUPdWB_register_Asm_16:
6709  case ARM::VLD4DUPdWB_register_Asm_32:
6710  case ARM::VLD4DUPqWB_register_Asm_8:
6711  case ARM::VLD4DUPqWB_register_Asm_16:
6712  case ARM::VLD4DUPqWB_register_Asm_32: {
6713    MCInst TmpInst;
6714    unsigned Spacing;
6715    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6716    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6717    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6718                                            Spacing));
6719    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6720                                            Spacing * 2));
6721    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6722                                            Spacing * 3));
6723    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6724    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6725    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6726    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6727    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6728    TmpInst.addOperand(Inst.getOperand(5));
6729    Inst = TmpInst;
6730    return true;
6731  }
6732
6733  // VLD4 multiple 4-element structure instructions.
6734  case ARM::VLD4dAsm_8:
6735  case ARM::VLD4dAsm_16:
6736  case ARM::VLD4dAsm_32:
6737  case ARM::VLD4qAsm_8:
6738  case ARM::VLD4qAsm_16:
6739  case ARM::VLD4qAsm_32: {
6740    MCInst TmpInst;
6741    unsigned Spacing;
6742    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6743    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6744    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6745                                            Spacing));
6746    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6747                                            Spacing * 2));
6748    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6749                                            Spacing * 3));
6750    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6751    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6752    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6753    TmpInst.addOperand(Inst.getOperand(4));
6754    Inst = TmpInst;
6755    return true;
6756  }
6757
6758  case ARM::VLD4dWB_fixed_Asm_8:
6759  case ARM::VLD4dWB_fixed_Asm_16:
6760  case ARM::VLD4dWB_fixed_Asm_32:
6761  case ARM::VLD4qWB_fixed_Asm_8:
6762  case ARM::VLD4qWB_fixed_Asm_16:
6763  case ARM::VLD4qWB_fixed_Asm_32: {
6764    MCInst TmpInst;
6765    unsigned Spacing;
6766    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6767    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6768    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6769                                            Spacing));
6770    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6771                                            Spacing * 2));
6772    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6773                                            Spacing * 3));
6774    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6775    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6776    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6777    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6778    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6779    TmpInst.addOperand(Inst.getOperand(4));
6780    Inst = TmpInst;
6781    return true;
6782  }
6783
6784  case ARM::VLD4dWB_register_Asm_8:
6785  case ARM::VLD4dWB_register_Asm_16:
6786  case ARM::VLD4dWB_register_Asm_32:
6787  case ARM::VLD4qWB_register_Asm_8:
6788  case ARM::VLD4qWB_register_Asm_16:
6789  case ARM::VLD4qWB_register_Asm_32: {
6790    MCInst TmpInst;
6791    unsigned Spacing;
6792    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6793    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6794    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6795                                            Spacing));
6796    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6797                                            Spacing * 2));
6798    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6799                                            Spacing * 3));
6800    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6801    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6802    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6803    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6804    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6805    TmpInst.addOperand(Inst.getOperand(5));
6806    Inst = TmpInst;
6807    return true;
6808  }
6809
6810  // VST3 multiple 3-element structure instructions.
6811  case ARM::VST3dAsm_8:
6812  case ARM::VST3dAsm_16:
6813  case ARM::VST3dAsm_32:
6814  case ARM::VST3qAsm_8:
6815  case ARM::VST3qAsm_16:
6816  case ARM::VST3qAsm_32: {
6817    MCInst TmpInst;
6818    unsigned Spacing;
6819    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6820    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6821    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6822    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6823    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6824                                            Spacing));
6825    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6826                                            Spacing * 2));
6827    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6828    TmpInst.addOperand(Inst.getOperand(4));
6829    Inst = TmpInst;
6830    return true;
6831  }
6832
6833  case ARM::VST3dWB_fixed_Asm_8:
6834  case ARM::VST3dWB_fixed_Asm_16:
6835  case ARM::VST3dWB_fixed_Asm_32:
6836  case ARM::VST3qWB_fixed_Asm_8:
6837  case ARM::VST3qWB_fixed_Asm_16:
6838  case ARM::VST3qWB_fixed_Asm_32: {
6839    MCInst TmpInst;
6840    unsigned Spacing;
6841    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6842    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6843    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6844    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6845    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6846    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6847    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6848                                            Spacing));
6849    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6850                                            Spacing * 2));
6851    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6852    TmpInst.addOperand(Inst.getOperand(4));
6853    Inst = TmpInst;
6854    return true;
6855  }
6856
6857  case ARM::VST3dWB_register_Asm_8:
6858  case ARM::VST3dWB_register_Asm_16:
6859  case ARM::VST3dWB_register_Asm_32:
6860  case ARM::VST3qWB_register_Asm_8:
6861  case ARM::VST3qWB_register_Asm_16:
6862  case ARM::VST3qWB_register_Asm_32: {
6863    MCInst TmpInst;
6864    unsigned Spacing;
6865    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6866    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6867    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6868    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6869    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6870    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6871    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6872                                            Spacing));
6873    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6874                                            Spacing * 2));
6875    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6876    TmpInst.addOperand(Inst.getOperand(5));
6877    Inst = TmpInst;
6878    return true;
6879  }
6880
6881  // VST4 multiple 3-element structure instructions.
6882  case ARM::VST4dAsm_8:
6883  case ARM::VST4dAsm_16:
6884  case ARM::VST4dAsm_32:
6885  case ARM::VST4qAsm_8:
6886  case ARM::VST4qAsm_16:
6887  case ARM::VST4qAsm_32: {
6888    MCInst TmpInst;
6889    unsigned Spacing;
6890    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6891    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6892    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6893    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6894    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6895                                            Spacing));
6896    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6897                                            Spacing * 2));
6898    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6899                                            Spacing * 3));
6900    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6901    TmpInst.addOperand(Inst.getOperand(4));
6902    Inst = TmpInst;
6903    return true;
6904  }
6905
6906  case ARM::VST4dWB_fixed_Asm_8:
6907  case ARM::VST4dWB_fixed_Asm_16:
6908  case ARM::VST4dWB_fixed_Asm_32:
6909  case ARM::VST4qWB_fixed_Asm_8:
6910  case ARM::VST4qWB_fixed_Asm_16:
6911  case ARM::VST4qWB_fixed_Asm_32: {
6912    MCInst TmpInst;
6913    unsigned Spacing;
6914    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6915    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6916    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6917    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6918    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6919    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6920    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6921                                            Spacing));
6922    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6923                                            Spacing * 2));
6924    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6925                                            Spacing * 3));
6926    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6927    TmpInst.addOperand(Inst.getOperand(4));
6928    Inst = TmpInst;
6929    return true;
6930  }
6931
6932  case ARM::VST4dWB_register_Asm_8:
6933  case ARM::VST4dWB_register_Asm_16:
6934  case ARM::VST4dWB_register_Asm_32:
6935  case ARM::VST4qWB_register_Asm_8:
6936  case ARM::VST4qWB_register_Asm_16:
6937  case ARM::VST4qWB_register_Asm_32: {
6938    MCInst TmpInst;
6939    unsigned Spacing;
6940    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6941    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6942    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6943    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6944    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6945    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6946    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6947                                            Spacing));
6948    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6949                                            Spacing * 2));
6950    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6951                                            Spacing * 3));
6952    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6953    TmpInst.addOperand(Inst.getOperand(5));
6954    Inst = TmpInst;
6955    return true;
6956  }
6957
6958  // Handle encoding choice for the shift-immediate instructions.
6959  case ARM::t2LSLri:
6960  case ARM::t2LSRri:
6961  case ARM::t2ASRri: {
6962    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6963        Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
6964        Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
6965        !(static_cast<ARMOperand*>(Operands[3])->isToken() &&
6966         static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) {
6967      unsigned NewOpc;
6968      switch (Inst.getOpcode()) {
6969      default: llvm_unreachable("unexpected opcode");
6970      case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
6971      case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
6972      case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
6973      }
6974      // The Thumb1 operands aren't in the same order. Awesome, eh?
6975      MCInst TmpInst;
6976      TmpInst.setOpcode(NewOpc);
6977      TmpInst.addOperand(Inst.getOperand(0));
6978      TmpInst.addOperand(Inst.getOperand(5));
6979      TmpInst.addOperand(Inst.getOperand(1));
6980      TmpInst.addOperand(Inst.getOperand(2));
6981      TmpInst.addOperand(Inst.getOperand(3));
6982      TmpInst.addOperand(Inst.getOperand(4));
6983      Inst = TmpInst;
6984      return true;
6985    }
6986    return false;
6987  }
6988
6989  // Handle the Thumb2 mode MOV complex aliases.
6990  case ARM::t2MOVsr:
6991  case ARM::t2MOVSsr: {
6992    // Which instruction to expand to depends on the CCOut operand and
6993    // whether we're in an IT block if the register operands are low
6994    // registers.
6995    bool isNarrow = false;
6996    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6997        isARMLowRegister(Inst.getOperand(1).getReg()) &&
6998        isARMLowRegister(Inst.getOperand(2).getReg()) &&
6999        Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7000        inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
7001      isNarrow = true;
7002    MCInst TmpInst;
7003    unsigned newOpc;
7004    switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
7005    default: llvm_unreachable("unexpected opcode!");
7006    case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
7007    case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
7008    case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
7009    case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR   : ARM::t2RORrr; break;
7010    }
7011    TmpInst.setOpcode(newOpc);
7012    TmpInst.addOperand(Inst.getOperand(0)); // Rd
7013    if (isNarrow)
7014      TmpInst.addOperand(MCOperand::CreateReg(
7015          Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7016    TmpInst.addOperand(Inst.getOperand(1)); // Rn
7017    TmpInst.addOperand(Inst.getOperand(2)); // Rm
7018    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7019    TmpInst.addOperand(Inst.getOperand(5));
7020    if (!isNarrow)
7021      TmpInst.addOperand(MCOperand::CreateReg(
7022          Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7023    Inst = TmpInst;
7024    return true;
7025  }
7026  case ARM::t2MOVsi:
7027  case ARM::t2MOVSsi: {
7028    // Which instruction to expand to depends on the CCOut operand and
7029    // whether we're in an IT block if the register operands are low
7030    // registers.
7031    bool isNarrow = false;
7032    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7033        isARMLowRegister(Inst.getOperand(1).getReg()) &&
7034        inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
7035      isNarrow = true;
7036    MCInst TmpInst;
7037    unsigned newOpc;
7038    switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
7039    default: llvm_unreachable("unexpected opcode!");
7040    case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
7041    case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
7042    case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
7043    case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
7044    case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
7045    }
7046    unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
7047    if (Amount == 32) Amount = 0;
7048    TmpInst.setOpcode(newOpc);
7049    TmpInst.addOperand(Inst.getOperand(0)); // Rd
7050    if (isNarrow)
7051      TmpInst.addOperand(MCOperand::CreateReg(
7052          Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7053    TmpInst.addOperand(Inst.getOperand(1)); // Rn
7054    if (newOpc != ARM::t2RRX)
7055      TmpInst.addOperand(MCOperand::CreateImm(Amount));
7056    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7057    TmpInst.addOperand(Inst.getOperand(4));
7058    if (!isNarrow)
7059      TmpInst.addOperand(MCOperand::CreateReg(
7060          Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7061    Inst = TmpInst;
7062    return true;
7063  }
7064  // Handle the ARM mode MOV complex aliases.
7065  case ARM::ASRr:
7066  case ARM::LSRr:
7067  case ARM::LSLr:
7068  case ARM::RORr: {
7069    ARM_AM::ShiftOpc ShiftTy;
7070    switch(Inst.getOpcode()) {
7071    default: llvm_unreachable("unexpected opcode!");
7072    case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
7073    case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
7074    case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
7075    case ARM::RORr: ShiftTy = ARM_AM::ror; break;
7076    }
7077    unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
7078    MCInst TmpInst;
7079    TmpInst.setOpcode(ARM::MOVsr);
7080    TmpInst.addOperand(Inst.getOperand(0)); // Rd
7081    TmpInst.addOperand(Inst.getOperand(1)); // Rn
7082    TmpInst.addOperand(Inst.getOperand(2)); // Rm
7083    TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7084    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7085    TmpInst.addOperand(Inst.getOperand(4));
7086    TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7087    Inst = TmpInst;
7088    return true;
7089  }
7090  case ARM::ASRi:
7091  case ARM::LSRi:
7092  case ARM::LSLi:
7093  case ARM::RORi: {
7094    ARM_AM::ShiftOpc ShiftTy;
7095    switch(Inst.getOpcode()) {
7096    default: llvm_unreachable("unexpected opcode!");
7097    case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
7098    case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
7099    case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
7100    case ARM::RORi: ShiftTy = ARM_AM::ror; break;
7101    }
7102    // A shift by zero is a plain MOVr, not a MOVsi.
7103    unsigned Amt = Inst.getOperand(2).getImm();
7104    unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
7105    // A shift by 32 should be encoded as 0 when permitted
7106    if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
7107      Amt = 0;
7108    unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
7109    MCInst TmpInst;
7110    TmpInst.setOpcode(Opc);
7111    TmpInst.addOperand(Inst.getOperand(0)); // Rd
7112    TmpInst.addOperand(Inst.getOperand(1)); // Rn
7113    if (Opc == ARM::MOVsi)
7114      TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7115    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7116    TmpInst.addOperand(Inst.getOperand(4));
7117    TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7118    Inst = TmpInst;
7119    return true;
7120  }
7121  case ARM::RRXi: {
7122    unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
7123    MCInst TmpInst;
7124    TmpInst.setOpcode(ARM::MOVsi);
7125    TmpInst.addOperand(Inst.getOperand(0)); // Rd
7126    TmpInst.addOperand(Inst.getOperand(1)); // Rn
7127    TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7128    TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7129    TmpInst.addOperand(Inst.getOperand(3));
7130    TmpInst.addOperand(Inst.getOperand(4)); // cc_out
7131    Inst = TmpInst;
7132    return true;
7133  }
7134  case ARM::t2LDMIA_UPD: {
7135    // If this is a load of a single register, then we should use
7136    // a post-indexed LDR instruction instead, per the ARM ARM.
7137    if (Inst.getNumOperands() != 5)
7138      return false;
7139    MCInst TmpInst;
7140    TmpInst.setOpcode(ARM::t2LDR_POST);
7141    TmpInst.addOperand(Inst.getOperand(4)); // Rt
7142    TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7143    TmpInst.addOperand(Inst.getOperand(1)); // Rn
7144    TmpInst.addOperand(MCOperand::CreateImm(4));
7145    TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7146    TmpInst.addOperand(Inst.getOperand(3));
7147    Inst = TmpInst;
7148    return true;
7149  }
7150  case ARM::t2STMDB_UPD: {
7151    // If this is a store of a single register, then we should use
7152    // a pre-indexed STR instruction instead, per the ARM ARM.
7153    if (Inst.getNumOperands() != 5)
7154      return false;
7155    MCInst TmpInst;
7156    TmpInst.setOpcode(ARM::t2STR_PRE);
7157    TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7158    TmpInst.addOperand(Inst.getOperand(4)); // Rt
7159    TmpInst.addOperand(Inst.getOperand(1)); // Rn
7160    TmpInst.addOperand(MCOperand::CreateImm(-4));
7161    TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7162    TmpInst.addOperand(Inst.getOperand(3));
7163    Inst = TmpInst;
7164    return true;
7165  }
7166  case ARM::LDMIA_UPD:
7167    // If this is a load of a single register via a 'pop', then we should use
7168    // a post-indexed LDR instruction instead, per the ARM ARM.
7169    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
7170        Inst.getNumOperands() == 5) {
7171      MCInst TmpInst;
7172      TmpInst.setOpcode(ARM::LDR_POST_IMM);
7173      TmpInst.addOperand(Inst.getOperand(4)); // Rt
7174      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7175      TmpInst.addOperand(Inst.getOperand(1)); // Rn
7176      TmpInst.addOperand(MCOperand::CreateReg(0));  // am2offset
7177      TmpInst.addOperand(MCOperand::CreateImm(4));
7178      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7179      TmpInst.addOperand(Inst.getOperand(3));
7180      Inst = TmpInst;
7181      return true;
7182    }
7183    break;
7184  case ARM::STMDB_UPD:
7185    // If this is a store of a single register via a 'push', then we should use
7186    // a pre-indexed STR instruction instead, per the ARM ARM.
7187    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
7188        Inst.getNumOperands() == 5) {
7189      MCInst TmpInst;
7190      TmpInst.setOpcode(ARM::STR_PRE_IMM);
7191      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7192      TmpInst.addOperand(Inst.getOperand(4)); // Rt
7193      TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
7194      TmpInst.addOperand(MCOperand::CreateImm(-4));
7195      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7196      TmpInst.addOperand(Inst.getOperand(3));
7197      Inst = TmpInst;
7198    }
7199    break;
7200  case ARM::t2ADDri12:
7201    // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
7202    // mnemonic was used (not "addw"), encoding T3 is preferred.
7203    if (static_cast<ARMOperand*>(Operands[0])->getToken() != "add" ||
7204        ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7205      break;
7206    Inst.setOpcode(ARM::t2ADDri);
7207    Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7208    break;
7209  case ARM::t2SUBri12:
7210    // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
7211    // mnemonic was used (not "subw"), encoding T3 is preferred.
7212    if (static_cast<ARMOperand*>(Operands[0])->getToken() != "sub" ||
7213        ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7214      break;
7215    Inst.setOpcode(ARM::t2SUBri);
7216    Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7217    break;
7218  case ARM::tADDi8:
7219    // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7220    // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7221    // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7222    // to encoding T1 if <Rd> is omitted."
7223    if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7224      Inst.setOpcode(ARM::tADDi3);
7225      return true;
7226    }
7227    break;
7228  case ARM::tSUBi8:
7229    // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7230    // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7231    // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7232    // to encoding T1 if <Rd> is omitted."
7233    if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7234      Inst.setOpcode(ARM::tSUBi3);
7235      return true;
7236    }
7237    break;
7238  case ARM::t2ADDri:
7239  case ARM::t2SUBri: {
7240    // If the destination and first source operand are the same, and
7241    // the flags are compatible with the current IT status, use encoding T2
7242    // instead of T3. For compatibility with the system 'as'. Make sure the
7243    // wide encoding wasn't explicit.
7244    if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7245        !isARMLowRegister(Inst.getOperand(0).getReg()) ||
7246        (unsigned)Inst.getOperand(2).getImm() > 255 ||
7247        ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
7248        (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
7249        (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7250         static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7251      break;
7252    MCInst TmpInst;
7253    TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
7254                      ARM::tADDi8 : ARM::tSUBi8);
7255    TmpInst.addOperand(Inst.getOperand(0));
7256    TmpInst.addOperand(Inst.getOperand(5));
7257    TmpInst.addOperand(Inst.getOperand(0));
7258    TmpInst.addOperand(Inst.getOperand(2));
7259    TmpInst.addOperand(Inst.getOperand(3));
7260    TmpInst.addOperand(Inst.getOperand(4));
7261    Inst = TmpInst;
7262    return true;
7263  }
7264  case ARM::t2ADDrr: {
7265    // If the destination and first source operand are the same, and
7266    // there's no setting of the flags, use encoding T2 instead of T3.
7267    // Note that this is only for ADD, not SUB. This mirrors the system
7268    // 'as' behaviour. Make sure the wide encoding wasn't explicit.
7269    if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7270        Inst.getOperand(5).getReg() != 0 ||
7271        (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7272         static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7273      break;
7274    MCInst TmpInst;
7275    TmpInst.setOpcode(ARM::tADDhirr);
7276    TmpInst.addOperand(Inst.getOperand(0));
7277    TmpInst.addOperand(Inst.getOperand(0));
7278    TmpInst.addOperand(Inst.getOperand(2));
7279    TmpInst.addOperand(Inst.getOperand(3));
7280    TmpInst.addOperand(Inst.getOperand(4));
7281    Inst = TmpInst;
7282    return true;
7283  }
7284  case ARM::tADDrSP: {
7285    // If the non-SP source operand and the destination operand are not the
7286    // same, we need to use the 32-bit encoding if it's available.
7287    if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
7288      Inst.setOpcode(ARM::t2ADDrr);
7289      Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7290      return true;
7291    }
7292    break;
7293  }
7294  case ARM::tB:
7295    // A Thumb conditional branch outside of an IT block is a tBcc.
7296    if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
7297      Inst.setOpcode(ARM::tBcc);
7298      return true;
7299    }
7300    break;
7301  case ARM::t2B:
7302    // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
7303    if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
7304      Inst.setOpcode(ARM::t2Bcc);
7305      return true;
7306    }
7307    break;
7308  case ARM::t2Bcc:
7309    // If the conditional is AL or we're in an IT block, we really want t2B.
7310    if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
7311      Inst.setOpcode(ARM::t2B);
7312      return true;
7313    }
7314    break;
7315  case ARM::tBcc:
7316    // If the conditional is AL, we really want tB.
7317    if (Inst.getOperand(1).getImm() == ARMCC::AL) {
7318      Inst.setOpcode(ARM::tB);
7319      return true;
7320    }
7321    break;
7322  case ARM::tLDMIA: {
7323    // If the register list contains any high registers, or if the writeback
7324    // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
7325    // instead if we're in Thumb2. Otherwise, this should have generated
7326    // an error in validateInstruction().
7327    unsigned Rn = Inst.getOperand(0).getReg();
7328    bool hasWritebackToken =
7329      (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7330       static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
7331    bool listContainsBase;
7332    if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
7333        (!listContainsBase && !hasWritebackToken) ||
7334        (listContainsBase && hasWritebackToken)) {
7335      // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7336      assert (isThumbTwo());
7337      Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
7338      // If we're switching to the updating version, we need to insert
7339      // the writeback tied operand.
7340      if (hasWritebackToken)
7341        Inst.insert(Inst.begin(),
7342                    MCOperand::CreateReg(Inst.getOperand(0).getReg()));
7343      return true;
7344    }
7345    break;
7346  }
7347  case ARM::tSTMIA_UPD: {
7348    // If the register list contains any high registers, we need to use
7349    // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7350    // should have generated an error in validateInstruction().
7351    unsigned Rn = Inst.getOperand(0).getReg();
7352    bool listContainsBase;
7353    if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
7354      // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7355      assert (isThumbTwo());
7356      Inst.setOpcode(ARM::t2STMIA_UPD);
7357      return true;
7358    }
7359    break;
7360  }
7361  case ARM::tPOP: {
7362    bool listContainsBase;
7363    // If the register list contains any high registers, we need to use
7364    // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7365    // should have generated an error in validateInstruction().
7366    if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
7367      return false;
7368    assert (isThumbTwo());
7369    Inst.setOpcode(ARM::t2LDMIA_UPD);
7370    // Add the base register and writeback operands.
7371    Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7372    Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7373    return true;
7374  }
7375  case ARM::tPUSH: {
7376    bool listContainsBase;
7377    if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
7378      return false;
7379    assert (isThumbTwo());
7380    Inst.setOpcode(ARM::t2STMDB_UPD);
7381    // Add the base register and writeback operands.
7382    Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7383    Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7384    return true;
7385  }
7386  case ARM::t2MOVi: {
7387    // If we can use the 16-bit encoding and the user didn't explicitly
7388    // request the 32-bit variant, transform it here.
7389    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7390        (unsigned)Inst.getOperand(1).getImm() <= 255 &&
7391        ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
7392         Inst.getOperand(4).getReg() == ARM::CPSR) ||
7393        (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
7394        (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7395         static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7396      // The operands aren't in the same order for tMOVi8...
7397      MCInst TmpInst;
7398      TmpInst.setOpcode(ARM::tMOVi8);
7399      TmpInst.addOperand(Inst.getOperand(0));
7400      TmpInst.addOperand(Inst.getOperand(4));
7401      TmpInst.addOperand(Inst.getOperand(1));
7402      TmpInst.addOperand(Inst.getOperand(2));
7403      TmpInst.addOperand(Inst.getOperand(3));
7404      Inst = TmpInst;
7405      return true;
7406    }
7407    break;
7408  }
7409  case ARM::t2MOVr: {
7410    // If we can use the 16-bit encoding and the user didn't explicitly
7411    // request the 32-bit variant, transform it here.
7412    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7413        isARMLowRegister(Inst.getOperand(1).getReg()) &&
7414        Inst.getOperand(2).getImm() == ARMCC::AL &&
7415        Inst.getOperand(4).getReg() == ARM::CPSR &&
7416        (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7417         static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7418      // The operands aren't the same for tMOV[S]r... (no cc_out)
7419      MCInst TmpInst;
7420      TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
7421      TmpInst.addOperand(Inst.getOperand(0));
7422      TmpInst.addOperand(Inst.getOperand(1));
7423      TmpInst.addOperand(Inst.getOperand(2));
7424      TmpInst.addOperand(Inst.getOperand(3));
7425      Inst = TmpInst;
7426      return true;
7427    }
7428    break;
7429  }
7430  case ARM::t2SXTH:
7431  case ARM::t2SXTB:
7432  case ARM::t2UXTH:
7433  case ARM::t2UXTB: {
7434    // If we can use the 16-bit encoding and the user didn't explicitly
7435    // request the 32-bit variant, transform it here.
7436    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7437        isARMLowRegister(Inst.getOperand(1).getReg()) &&
7438        Inst.getOperand(2).getImm() == 0 &&
7439        (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7440         static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7441      unsigned NewOpc;
7442      switch (Inst.getOpcode()) {
7443      default: llvm_unreachable("Illegal opcode!");
7444      case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
7445      case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
7446      case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
7447      case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
7448      }
7449      // The operands aren't the same for thumb1 (no rotate operand).
7450      MCInst TmpInst;
7451      TmpInst.setOpcode(NewOpc);
7452      TmpInst.addOperand(Inst.getOperand(0));
7453      TmpInst.addOperand(Inst.getOperand(1));
7454      TmpInst.addOperand(Inst.getOperand(3));
7455      TmpInst.addOperand(Inst.getOperand(4));
7456      Inst = TmpInst;
7457      return true;
7458    }
7459    break;
7460  }
7461  case ARM::MOVsi: {
7462    ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
7463    // rrx shifts and asr/lsr of #32 is encoded as 0
7464    if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
7465      return false;
7466    if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
7467      // Shifting by zero is accepted as a vanilla 'MOVr'
7468      MCInst TmpInst;
7469      TmpInst.setOpcode(ARM::MOVr);
7470      TmpInst.addOperand(Inst.getOperand(0));
7471      TmpInst.addOperand(Inst.getOperand(1));
7472      TmpInst.addOperand(Inst.getOperand(3));
7473      TmpInst.addOperand(Inst.getOperand(4));
7474      TmpInst.addOperand(Inst.getOperand(5));
7475      Inst = TmpInst;
7476      return true;
7477    }
7478    return false;
7479  }
7480  case ARM::ANDrsi:
7481  case ARM::ORRrsi:
7482  case ARM::EORrsi:
7483  case ARM::BICrsi:
7484  case ARM::SUBrsi:
7485  case ARM::ADDrsi: {
7486    unsigned newOpc;
7487    ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
7488    if (SOpc == ARM_AM::rrx) return false;
7489    switch (Inst.getOpcode()) {
7490    default: llvm_unreachable("unexpected opcode!");
7491    case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
7492    case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
7493    case ARM::EORrsi: newOpc = ARM::EORrr; break;
7494    case ARM::BICrsi: newOpc = ARM::BICrr; break;
7495    case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
7496    case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
7497    }
7498    // If the shift is by zero, use the non-shifted instruction definition.
7499    // The exception is for right shifts, where 0 == 32
7500    if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
7501        !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
7502      MCInst TmpInst;
7503      TmpInst.setOpcode(newOpc);
7504      TmpInst.addOperand(Inst.getOperand(0));
7505      TmpInst.addOperand(Inst.getOperand(1));
7506      TmpInst.addOperand(Inst.getOperand(2));
7507      TmpInst.addOperand(Inst.getOperand(4));
7508      TmpInst.addOperand(Inst.getOperand(5));
7509      TmpInst.addOperand(Inst.getOperand(6));
7510      Inst = TmpInst;
7511      return true;
7512    }
7513    return false;
7514  }
7515  case ARM::ITasm:
7516  case ARM::t2IT: {
7517    // The mask bits for all but the first condition are represented as
7518    // the low bit of the condition code value implies 't'. We currently
7519    // always have 1 implies 't', so XOR toggle the bits if the low bit
7520    // of the condition code is zero.
7521    MCOperand &MO = Inst.getOperand(1);
7522    unsigned Mask = MO.getImm();
7523    unsigned OrigMask = Mask;
7524    unsigned TZ = countTrailingZeros(Mask);
7525    if ((Inst.getOperand(0).getImm() & 1) == 0) {
7526      assert(Mask && TZ <= 3 && "illegal IT mask value!");
7527      Mask ^= (0xE << TZ) & 0xF;
7528    }
7529    MO.setImm(Mask);
7530
7531    // Set up the IT block state according to the IT instruction we just
7532    // matched.
7533    assert(!inITBlock() && "nested IT blocks?!");
7534    ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
7535    ITState.Mask = OrigMask; // Use the original mask, not the updated one.
7536    ITState.CurPosition = 0;
7537    ITState.FirstCond = true;
7538    break;
7539  }
7540  case ARM::t2LSLrr:
7541  case ARM::t2LSRrr:
7542  case ARM::t2ASRrr:
7543  case ARM::t2SBCrr:
7544  case ARM::t2RORrr:
7545  case ARM::t2BICrr:
7546  {
7547    // Assemblers should use the narrow encodings of these instructions when permissible.
7548    if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7549         isARMLowRegister(Inst.getOperand(2).getReg())) &&
7550        Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7551        ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7552         (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7553        (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7554         !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7555      unsigned NewOpc;
7556      switch (Inst.getOpcode()) {
7557        default: llvm_unreachable("unexpected opcode");
7558        case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
7559        case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
7560        case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
7561        case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
7562        case ARM::t2RORrr: NewOpc = ARM::tROR; break;
7563        case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
7564      }
7565      MCInst TmpInst;
7566      TmpInst.setOpcode(NewOpc);
7567      TmpInst.addOperand(Inst.getOperand(0));
7568      TmpInst.addOperand(Inst.getOperand(5));
7569      TmpInst.addOperand(Inst.getOperand(1));
7570      TmpInst.addOperand(Inst.getOperand(2));
7571      TmpInst.addOperand(Inst.getOperand(3));
7572      TmpInst.addOperand(Inst.getOperand(4));
7573      Inst = TmpInst;
7574      return true;
7575    }
7576    return false;
7577  }
7578  case ARM::t2ANDrr:
7579  case ARM::t2EORrr:
7580  case ARM::t2ADCrr:
7581  case ARM::t2ORRrr:
7582  {
7583    // Assemblers should use the narrow encodings of these instructions when permissible.
7584    // These instructions are special in that they are commutable, so shorter encodings
7585    // are available more often.
7586    if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7587         isARMLowRegister(Inst.getOperand(2).getReg())) &&
7588        (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
7589         Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
7590        ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7591         (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7592        (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7593         !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7594      unsigned NewOpc;
7595      switch (Inst.getOpcode()) {
7596        default: llvm_unreachable("unexpected opcode");
7597        case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
7598        case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
7599        case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
7600        case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
7601      }
7602      MCInst TmpInst;
7603      TmpInst.setOpcode(NewOpc);
7604      TmpInst.addOperand(Inst.getOperand(0));
7605      TmpInst.addOperand(Inst.getOperand(5));
7606      if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
7607        TmpInst.addOperand(Inst.getOperand(1));
7608        TmpInst.addOperand(Inst.getOperand(2));
7609      } else {
7610        TmpInst.addOperand(Inst.getOperand(2));
7611        TmpInst.addOperand(Inst.getOperand(1));
7612      }
7613      TmpInst.addOperand(Inst.getOperand(3));
7614      TmpInst.addOperand(Inst.getOperand(4));
7615      Inst = TmpInst;
7616      return true;
7617    }
7618    return false;
7619  }
7620  }
7621  return false;
7622}
7623
7624unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
7625  // 16-bit thumb arithmetic instructions either require or preclude the 'S'
7626  // suffix depending on whether they're in an IT block or not.
7627  unsigned Opc = Inst.getOpcode();
7628  const MCInstrDesc &MCID = getInstDesc(Opc);
7629  if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
7630    assert(MCID.hasOptionalDef() &&
7631           "optionally flag setting instruction missing optional def operand");
7632    assert(MCID.NumOperands == Inst.getNumOperands() &&
7633           "operand count mismatch!");
7634    // Find the optional-def operand (cc_out).
7635    unsigned OpNo;
7636    for (OpNo = 0;
7637         !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
7638         ++OpNo)
7639      ;
7640    // If we're parsing Thumb1, reject it completely.
7641    if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
7642      return Match_MnemonicFail;
7643    // If we're parsing Thumb2, which form is legal depends on whether we're
7644    // in an IT block.
7645    if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
7646        !inITBlock())
7647      return Match_RequiresITBlock;
7648    if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
7649        inITBlock())
7650      return Match_RequiresNotITBlock;
7651  }
7652  // Some high-register supporting Thumb1 encodings only allow both registers
7653  // to be from r0-r7 when in Thumb2.
7654  else if (Opc == ARM::tADDhirr && isThumbOne() &&
7655           isARMLowRegister(Inst.getOperand(1).getReg()) &&
7656           isARMLowRegister(Inst.getOperand(2).getReg()))
7657    return Match_RequiresThumb2;
7658  // Others only require ARMv6 or later.
7659  else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
7660           isARMLowRegister(Inst.getOperand(0).getReg()) &&
7661           isARMLowRegister(Inst.getOperand(1).getReg()))
7662    return Match_RequiresV6;
7663  return Match_Success;
7664}
7665
7666static const char *getSubtargetFeatureName(unsigned Val);
7667bool ARMAsmParser::
7668MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
7669                        SmallVectorImpl<MCParsedAsmOperand*> &Operands,
7670                        MCStreamer &Out, unsigned &ErrorInfo,
7671                        bool MatchingInlineAsm) {
7672  MCInst Inst;
7673  unsigned MatchResult;
7674
7675  MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
7676                                     MatchingInlineAsm);
7677  switch (MatchResult) {
7678  default: break;
7679  case Match_Success:
7680    // Context sensitive operand constraints aren't handled by the matcher,
7681    // so check them here.
7682    if (validateInstruction(Inst, Operands)) {
7683      // Still progress the IT block, otherwise one wrong condition causes
7684      // nasty cascading errors.
7685      forwardITPosition();
7686      return true;
7687    }
7688
7689    // Some instructions need post-processing to, for example, tweak which
7690    // encoding is selected. Loop on it while changes happen so the
7691    // individual transformations can chain off each other. E.g.,
7692    // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
7693    while (processInstruction(Inst, Operands))
7694      ;
7695
7696    // Only move forward at the very end so that everything in validate
7697    // and process gets a consistent answer about whether we're in an IT
7698    // block.
7699    forwardITPosition();
7700
7701    // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
7702    // doesn't actually encode.
7703    if (Inst.getOpcode() == ARM::ITasm)
7704      return false;
7705
7706    Inst.setLoc(IDLoc);
7707    Out.EmitInstruction(Inst);
7708    return false;
7709  case Match_MissingFeature: {
7710    assert(ErrorInfo && "Unknown missing feature!");
7711    // Special case the error message for the very common case where only
7712    // a single subtarget feature is missing (Thumb vs. ARM, e.g.).
7713    std::string Msg = "instruction requires:";
7714    unsigned Mask = 1;
7715    for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
7716      if (ErrorInfo & Mask) {
7717        Msg += " ";
7718        Msg += getSubtargetFeatureName(ErrorInfo & Mask);
7719      }
7720      Mask <<= 1;
7721    }
7722    return Error(IDLoc, Msg);
7723  }
7724  case Match_InvalidOperand: {
7725    SMLoc ErrorLoc = IDLoc;
7726    if (ErrorInfo != ~0U) {
7727      if (ErrorInfo >= Operands.size())
7728        return Error(IDLoc, "too few operands for instruction");
7729
7730      ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7731      if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7732    }
7733
7734    return Error(ErrorLoc, "invalid operand for instruction");
7735  }
7736  case Match_MnemonicFail:
7737    return Error(IDLoc, "invalid instruction",
7738                 ((ARMOperand*)Operands[0])->getLocRange());
7739  case Match_RequiresNotITBlock:
7740    return Error(IDLoc, "flag setting instruction only valid outside IT block");
7741  case Match_RequiresITBlock:
7742    return Error(IDLoc, "instruction only valid inside IT block");
7743  case Match_RequiresV6:
7744    return Error(IDLoc, "instruction variant requires ARMv6 or later");
7745  case Match_RequiresThumb2:
7746    return Error(IDLoc, "instruction variant requires Thumb2");
7747  case Match_ImmRange0_4: {
7748    SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7749    if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7750    return Error(ErrorLoc, "immediate operand must be in the range [0,4]");
7751  }
7752  case Match_ImmRange0_15: {
7753    SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7754    if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7755    return Error(ErrorLoc, "immediate operand must be in the range [0,15]");
7756  }
7757  }
7758
7759  llvm_unreachable("Implement any new match types added!");
7760}
7761
7762/// parseDirective parses the arm specific directives
7763bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
7764  StringRef IDVal = DirectiveID.getIdentifier();
7765  if (IDVal == ".word")
7766    return parseDirectiveWord(4, DirectiveID.getLoc());
7767  else if (IDVal == ".thumb")
7768    return parseDirectiveThumb(DirectiveID.getLoc());
7769  else if (IDVal == ".arm")
7770    return parseDirectiveARM(DirectiveID.getLoc());
7771  else if (IDVal == ".thumb_func")
7772    return parseDirectiveThumbFunc(DirectiveID.getLoc());
7773  else if (IDVal == ".code")
7774    return parseDirectiveCode(DirectiveID.getLoc());
7775  else if (IDVal == ".syntax")
7776    return parseDirectiveSyntax(DirectiveID.getLoc());
7777  else if (IDVal == ".unreq")
7778    return parseDirectiveUnreq(DirectiveID.getLoc());
7779  else if (IDVal == ".arch")
7780    return parseDirectiveArch(DirectiveID.getLoc());
7781  else if (IDVal == ".eabi_attribute")
7782    return parseDirectiveEabiAttr(DirectiveID.getLoc());
7783  else if (IDVal == ".fnstart")
7784    return parseDirectiveFnStart(DirectiveID.getLoc());
7785  else if (IDVal == ".fnend")
7786    return parseDirectiveFnEnd(DirectiveID.getLoc());
7787  else if (IDVal == ".cantunwind")
7788    return parseDirectiveCantUnwind(DirectiveID.getLoc());
7789  else if (IDVal == ".personality")
7790    return parseDirectivePersonality(DirectiveID.getLoc());
7791  else if (IDVal == ".handlerdata")
7792    return parseDirectiveHandlerData(DirectiveID.getLoc());
7793  else if (IDVal == ".setfp")
7794    return parseDirectiveSetFP(DirectiveID.getLoc());
7795  else if (IDVal == ".pad")
7796    return parseDirectivePad(DirectiveID.getLoc());
7797  else if (IDVal == ".save")
7798    return parseDirectiveRegSave(DirectiveID.getLoc(), false);
7799  else if (IDVal == ".vsave")
7800    return parseDirectiveRegSave(DirectiveID.getLoc(), true);
7801  return true;
7802}
7803
7804/// parseDirectiveWord
7805///  ::= .word [ expression (, expression)* ]
7806bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
7807  if (getLexer().isNot(AsmToken::EndOfStatement)) {
7808    for (;;) {
7809      const MCExpr *Value;
7810      if (getParser().parseExpression(Value))
7811        return true;
7812
7813      getParser().getStreamer().EmitValue(Value, Size);
7814
7815      if (getLexer().is(AsmToken::EndOfStatement))
7816        break;
7817
7818      // FIXME: Improve diagnostic.
7819      if (getLexer().isNot(AsmToken::Comma))
7820        return Error(L, "unexpected token in directive");
7821      Parser.Lex();
7822    }
7823  }
7824
7825  Parser.Lex();
7826  return false;
7827}
7828
7829/// parseDirectiveThumb
7830///  ::= .thumb
7831bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
7832  if (getLexer().isNot(AsmToken::EndOfStatement))
7833    return Error(L, "unexpected token in directive");
7834  Parser.Lex();
7835
7836  if (!hasThumb())
7837    return Error(L, "target does not support Thumb mode");
7838
7839  if (!isThumb())
7840    SwitchMode();
7841  getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
7842  return false;
7843}
7844
7845/// parseDirectiveARM
7846///  ::= .arm
7847bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
7848  if (getLexer().isNot(AsmToken::EndOfStatement))
7849    return Error(L, "unexpected token in directive");
7850  Parser.Lex();
7851
7852  if (!hasARM())
7853    return Error(L, "target does not support ARM mode");
7854
7855  if (isThumb())
7856    SwitchMode();
7857  getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
7858  return false;
7859}
7860
7861/// parseDirectiveThumbFunc
7862///  ::= .thumbfunc symbol_name
7863bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
7864  const MCAsmInfo *MAI = getParser().getStreamer().getContext().getAsmInfo();
7865  bool isMachO = MAI->hasSubsectionsViaSymbols();
7866  StringRef Name;
7867  bool needFuncName = true;
7868
7869  // Darwin asm has (optionally) function name after .thumb_func direction
7870  // ELF doesn't
7871  if (isMachO) {
7872    const AsmToken &Tok = Parser.getTok();
7873    if (Tok.isNot(AsmToken::EndOfStatement)) {
7874      if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
7875        return Error(L, "unexpected token in .thumb_func directive");
7876      Name = Tok.getIdentifier();
7877      Parser.Lex(); // Consume the identifier token.
7878      needFuncName = false;
7879    }
7880  }
7881
7882  if (getLexer().isNot(AsmToken::EndOfStatement))
7883    return Error(L, "unexpected token in directive");
7884
7885  // Eat the end of statement and any blank lines that follow.
7886  while (getLexer().is(AsmToken::EndOfStatement))
7887    Parser.Lex();
7888
7889  // FIXME: assuming function name will be the line following .thumb_func
7890  // We really should be checking the next symbol definition even if there's
7891  // stuff in between.
7892  if (needFuncName) {
7893    Name = Parser.getTok().getIdentifier();
7894  }
7895
7896  // Mark symbol as a thumb symbol.
7897  MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
7898  getParser().getStreamer().EmitThumbFunc(Func);
7899  return false;
7900}
7901
7902/// parseDirectiveSyntax
7903///  ::= .syntax unified | divided
7904bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
7905  const AsmToken &Tok = Parser.getTok();
7906  if (Tok.isNot(AsmToken::Identifier))
7907    return Error(L, "unexpected token in .syntax directive");
7908  StringRef Mode = Tok.getString();
7909  if (Mode == "unified" || Mode == "UNIFIED")
7910    Parser.Lex();
7911  else if (Mode == "divided" || Mode == "DIVIDED")
7912    return Error(L, "'.syntax divided' arm asssembly not supported");
7913  else
7914    return Error(L, "unrecognized syntax mode in .syntax directive");
7915
7916  if (getLexer().isNot(AsmToken::EndOfStatement))
7917    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
7918  Parser.Lex();
7919
7920  // TODO tell the MC streamer the mode
7921  // getParser().getStreamer().Emit???();
7922  return false;
7923}
7924
7925/// parseDirectiveCode
7926///  ::= .code 16 | 32
7927bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
7928  const AsmToken &Tok = Parser.getTok();
7929  if (Tok.isNot(AsmToken::Integer))
7930    return Error(L, "unexpected token in .code directive");
7931  int64_t Val = Parser.getTok().getIntVal();
7932  if (Val == 16)
7933    Parser.Lex();
7934  else if (Val == 32)
7935    Parser.Lex();
7936  else
7937    return Error(L, "invalid operand to .code directive");
7938
7939  if (getLexer().isNot(AsmToken::EndOfStatement))
7940    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
7941  Parser.Lex();
7942
7943  if (Val == 16) {
7944    if (!hasThumb())
7945      return Error(L, "target does not support Thumb mode");
7946
7947    if (!isThumb())
7948      SwitchMode();
7949    getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
7950  } else {
7951    if (!hasARM())
7952      return Error(L, "target does not support ARM mode");
7953
7954    if (isThumb())
7955      SwitchMode();
7956    getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
7957  }
7958
7959  return false;
7960}
7961
7962/// parseDirectiveReq
7963///  ::= name .req registername
7964bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
7965  Parser.Lex(); // Eat the '.req' token.
7966  unsigned Reg;
7967  SMLoc SRegLoc, ERegLoc;
7968  if (ParseRegister(Reg, SRegLoc, ERegLoc)) {
7969    Parser.eatToEndOfStatement();
7970    return Error(SRegLoc, "register name expected");
7971  }
7972
7973  // Shouldn't be anything else.
7974  if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
7975    Parser.eatToEndOfStatement();
7976    return Error(Parser.getTok().getLoc(),
7977                 "unexpected input in .req directive.");
7978  }
7979
7980  Parser.Lex(); // Consume the EndOfStatement
7981
7982  if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg)
7983    return Error(SRegLoc, "redefinition of '" + Name +
7984                          "' does not match original.");
7985
7986  return false;
7987}
7988
7989/// parseDirectiveUneq
7990///  ::= .unreq registername
7991bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
7992  if (Parser.getTok().isNot(AsmToken::Identifier)) {
7993    Parser.eatToEndOfStatement();
7994    return Error(L, "unexpected input in .unreq directive.");
7995  }
7996  RegisterReqs.erase(Parser.getTok().getIdentifier());
7997  Parser.Lex(); // Eat the identifier.
7998  return false;
7999}
8000
8001/// parseDirectiveArch
8002///  ::= .arch token
8003bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
8004  return true;
8005}
8006
8007/// parseDirectiveEabiAttr
8008///  ::= .eabi_attribute int, int
8009bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
8010  return true;
8011}
8012
8013/// parseDirectiveFnStart
8014///  ::= .fnstart
8015bool ARMAsmParser::parseDirectiveFnStart(SMLoc L) {
8016  if (FnStartLoc.isValid()) {
8017    Error(L, ".fnstart starts before the end of previous one");
8018    Error(FnStartLoc, "previous .fnstart starts here");
8019    return true;
8020  }
8021
8022  FnStartLoc = L;
8023  getParser().getStreamer().EmitFnStart();
8024  return false;
8025}
8026
8027/// parseDirectiveFnEnd
8028///  ::= .fnend
8029bool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) {
8030  // Check the ordering of unwind directives
8031  if (!FnStartLoc.isValid())
8032    return Error(L, ".fnstart must precede .fnend directive");
8033
8034  // Reset the unwind directives parser state
8035  resetUnwindDirectiveParserState();
8036
8037  getParser().getStreamer().EmitFnEnd();
8038  return false;
8039}
8040
8041/// parseDirectiveCantUnwind
8042///  ::= .cantunwind
8043bool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) {
8044  // Check the ordering of unwind directives
8045  CantUnwindLoc = L;
8046  if (!FnStartLoc.isValid())
8047    return Error(L, ".fnstart must precede .cantunwind directive");
8048  if (HandlerDataLoc.isValid()) {
8049    Error(L, ".cantunwind can't be used with .handlerdata directive");
8050    Error(HandlerDataLoc, ".handlerdata was specified here");
8051    return true;
8052  }
8053  if (PersonalityLoc.isValid()) {
8054    Error(L, ".cantunwind can't be used with .personality directive");
8055    Error(PersonalityLoc, ".personality was specified here");
8056    return true;
8057  }
8058
8059  getParser().getStreamer().EmitCantUnwind();
8060  return false;
8061}
8062
8063/// parseDirectivePersonality
8064///  ::= .personality name
8065bool ARMAsmParser::parseDirectivePersonality(SMLoc L) {
8066  // Check the ordering of unwind directives
8067  PersonalityLoc = L;
8068  if (!FnStartLoc.isValid())
8069    return Error(L, ".fnstart must precede .personality directive");
8070  if (CantUnwindLoc.isValid()) {
8071    Error(L, ".personality can't be used with .cantunwind directive");
8072    Error(CantUnwindLoc, ".cantunwind was specified here");
8073    return true;
8074  }
8075  if (HandlerDataLoc.isValid()) {
8076    Error(L, ".personality must precede .handlerdata directive");
8077    Error(HandlerDataLoc, ".handlerdata was specified here");
8078    return true;
8079  }
8080
8081  // Parse the name of the personality routine
8082  if (Parser.getTok().isNot(AsmToken::Identifier)) {
8083    Parser.eatToEndOfStatement();
8084    return Error(L, "unexpected input in .personality directive.");
8085  }
8086  StringRef Name(Parser.getTok().getIdentifier());
8087  Parser.Lex();
8088
8089  MCSymbol *PR = getParser().getContext().GetOrCreateSymbol(Name);
8090  getParser().getStreamer().EmitPersonality(PR);
8091  return false;
8092}
8093
8094/// parseDirectiveHandlerData
8095///  ::= .handlerdata
8096bool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) {
8097  // Check the ordering of unwind directives
8098  HandlerDataLoc = L;
8099  if (!FnStartLoc.isValid())
8100    return Error(L, ".fnstart must precede .personality directive");
8101  if (CantUnwindLoc.isValid()) {
8102    Error(L, ".handlerdata can't be used with .cantunwind directive");
8103    Error(CantUnwindLoc, ".cantunwind was specified here");
8104    return true;
8105  }
8106
8107  getParser().getStreamer().EmitHandlerData();
8108  return false;
8109}
8110
8111/// parseDirectiveSetFP
8112///  ::= .setfp fpreg, spreg [, offset]
8113bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) {
8114  // Check the ordering of unwind directives
8115  if (!FnStartLoc.isValid())
8116    return Error(L, ".fnstart must precede .setfp directive");
8117  if (HandlerDataLoc.isValid())
8118    return Error(L, ".setfp must precede .handlerdata directive");
8119
8120  // Parse fpreg
8121  SMLoc NewFPRegLoc = Parser.getTok().getLoc();
8122  int NewFPReg = tryParseRegister();
8123  if (NewFPReg == -1)
8124    return Error(NewFPRegLoc, "frame pointer register expected");
8125
8126  // Consume comma
8127  if (!Parser.getTok().is(AsmToken::Comma))
8128    return Error(Parser.getTok().getLoc(), "comma expected");
8129  Parser.Lex(); // skip comma
8130
8131  // Parse spreg
8132  SMLoc NewSPRegLoc = Parser.getTok().getLoc();
8133  int NewSPReg = tryParseRegister();
8134  if (NewSPReg == -1)
8135    return Error(NewSPRegLoc, "stack pointer register expected");
8136
8137  if (NewSPReg != ARM::SP && NewSPReg != FPReg)
8138    return Error(NewSPRegLoc,
8139                 "register should be either $sp or the latest fp register");
8140
8141  // Update the frame pointer register
8142  FPReg = NewFPReg;
8143
8144  // Parse offset
8145  int64_t Offset = 0;
8146  if (Parser.getTok().is(AsmToken::Comma)) {
8147    Parser.Lex(); // skip comma
8148
8149    if (Parser.getTok().isNot(AsmToken::Hash) &&
8150        Parser.getTok().isNot(AsmToken::Dollar)) {
8151      return Error(Parser.getTok().getLoc(), "'#' expected");
8152    }
8153    Parser.Lex(); // skip hash token.
8154
8155    const MCExpr *OffsetExpr;
8156    SMLoc ExLoc = Parser.getTok().getLoc();
8157    SMLoc EndLoc;
8158    if (getParser().parseExpression(OffsetExpr, EndLoc))
8159      return Error(ExLoc, "malformed setfp offset");
8160    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
8161    if (!CE)
8162      return Error(ExLoc, "setfp offset must be an immediate");
8163
8164    Offset = CE->getValue();
8165  }
8166
8167  getParser().getStreamer().EmitSetFP(static_cast<unsigned>(NewFPReg),
8168                                      static_cast<unsigned>(NewSPReg),
8169                                      Offset);
8170  return false;
8171}
8172
8173/// parseDirective
8174///  ::= .pad offset
8175bool ARMAsmParser::parseDirectivePad(SMLoc L) {
8176  // Check the ordering of unwind directives
8177  if (!FnStartLoc.isValid())
8178    return Error(L, ".fnstart must precede .pad directive");
8179  if (HandlerDataLoc.isValid())
8180    return Error(L, ".pad must precede .handlerdata directive");
8181
8182  // Parse the offset
8183  if (Parser.getTok().isNot(AsmToken::Hash) &&
8184      Parser.getTok().isNot(AsmToken::Dollar)) {
8185    return Error(Parser.getTok().getLoc(), "'#' expected");
8186  }
8187  Parser.Lex(); // skip hash token.
8188
8189  const MCExpr *OffsetExpr;
8190  SMLoc ExLoc = Parser.getTok().getLoc();
8191  SMLoc EndLoc;
8192  if (getParser().parseExpression(OffsetExpr, EndLoc))
8193    return Error(ExLoc, "malformed pad offset");
8194  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
8195  if (!CE)
8196    return Error(ExLoc, "pad offset must be an immediate");
8197
8198  getParser().getStreamer().EmitPad(CE->getValue());
8199  return false;
8200}
8201
8202/// parseDirectiveRegSave
8203///  ::= .save  { registers }
8204///  ::= .vsave { registers }
8205bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) {
8206  // Check the ordering of unwind directives
8207  if (!FnStartLoc.isValid())
8208    return Error(L, ".fnstart must precede .save or .vsave directives");
8209  if (HandlerDataLoc.isValid())
8210    return Error(L, ".save or .vsave must precede .handlerdata directive");
8211
8212  // Parse the register list
8213  SmallVector<MCParsedAsmOperand*, 1> Operands;
8214  if (parseRegisterList(Operands))
8215    return true;
8216  ARMOperand *Op = (ARMOperand*)Operands[0];
8217  if (!IsVector && !Op->isRegList())
8218    return Error(L, ".save expects GPR registers");
8219  if (IsVector && !Op->isDPRRegList())
8220    return Error(L, ".vsave expects DPR registers");
8221
8222  getParser().getStreamer().EmitRegSave(Op->getRegList(), IsVector);
8223  return false;
8224}
8225
8226/// Force static initialization.
8227extern "C" void LLVMInitializeARMAsmParser() {
8228  RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
8229  RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
8230}
8231
8232#define GET_REGISTER_MATCHER
8233#define GET_SUBTARGET_FEATURE_NAME
8234#define GET_MATCHER_IMPLEMENTATION
8235#include "ARMGenAsmMatcher.inc"
8236
8237// Define this matcher function after the auto-generated include so we
8238// have the match class enum definitions.
8239unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand *AsmOp,
8240                                                  unsigned Kind) {
8241  ARMOperand *Op = static_cast<ARMOperand*>(AsmOp);
8242  // If the kind is a token for a literal immediate, check if our asm
8243  // operand matches. This is for InstAliases which have a fixed-value
8244  // immediate in the syntax.
8245  if (Kind == MCK__35_0 && Op->isImm()) {
8246    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
8247    if (!CE)
8248      return Match_InvalidOperand;
8249    if (CE->getValue() == 0)
8250      return Match_Success;
8251  }
8252  return Match_InvalidOperand;
8253}
8254