ARMAsmParser.cpp revision d0132ba7225883b2f7b828561d46fa6e203db6bb 
1//===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "llvm/MC/MCTargetAsmParser.h"
11#include "MCTargetDesc/ARMAddressingModes.h"
12#include "MCTargetDesc/ARMBaseInfo.h"
13#include "MCTargetDesc/ARMMCExpr.h"
14#include "llvm/ADT/BitVector.h"
15#include "llvm/ADT/OwningPtr.h"
16#include "llvm/ADT/STLExtras.h"
17#include "llvm/ADT/SmallVector.h"
18#include "llvm/ADT/StringSwitch.h"
19#include "llvm/ADT/Twine.h"
20#include "llvm/MC/MCAsmInfo.h"
21#include "llvm/MC/MCAssembler.h"
22#include "llvm/MC/MCContext.h"
23#include "llvm/MC/MCELFStreamer.h"
24#include "llvm/MC/MCExpr.h"
25#include "llvm/MC/MCInst.h"
26#include "llvm/MC/MCInstrDesc.h"
27#include "llvm/MC/MCParser/MCAsmLexer.h"
28#include "llvm/MC/MCParser/MCAsmParser.h"
29#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
30#include "llvm/MC/MCRegisterInfo.h"
31#include "llvm/MC/MCStreamer.h"
32#include "llvm/MC/MCSubtargetInfo.h"
33#include "llvm/Support/ELF.h"
34#include "llvm/Support/MathExtras.h"
35#include "llvm/Support/SourceMgr.h"
36#include "llvm/Support/TargetRegistry.h"
37#include "llvm/Support/raw_ostream.h"
38
39using namespace llvm;
40
41namespace {
42
43class ARMOperand;
44
45enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
46
47class ARMAsmParser : public MCTargetAsmParser {
48  MCSubtargetInfo &STI;
49  MCAsmParser &Parser;
50  const MCRegisterInfo *MRI;
51
52  // Map of register aliases registers via the .req directive.
53  StringMap<unsigned> RegisterReqs;
54
55  struct {
56    ARMCC::CondCodes Cond;    // Condition for IT block.
57    unsigned Mask:4;          // Condition mask for instructions.
58                              // Starting at first 1 (from lsb).
59                              //   '1'  condition as indicated in IT.
60                              //   '0'  inverse of condition (else).
61                              // Count of instructions in IT block is
62                              // 4 - trailingzeroes(mask)
63
64    bool FirstCond;           // Explicit flag for when we're parsing the
65                              // First instruction in the IT block. It's
66                              // implied in the mask, so needs special
67                              // handling.
68
69    unsigned CurPosition;     // Current position in parsing of IT
70                              // block. In range [0,3]. Initialized
71                              // according to count of instructions in block.
72                              // ~0U if no active IT block.
73  } ITState;
74  bool inITBlock() { return ITState.CurPosition != ~0U;}
75  void forwardITPosition() {
76    if (!inITBlock()) return;
77    // Move to the next instruction in the IT block, if there is one. If not,
78    // mark the block as done.
79    unsigned TZ = CountTrailingZeros_32(ITState.Mask);
80    if (++ITState.CurPosition == 5 - TZ)
81      ITState.CurPosition = ~0U; // Done with the IT block after this.
82  }
83
84
85  MCAsmParser &getParser() const { return Parser; }
86  MCAsmLexer &getLexer() const { return Parser.getLexer(); }
87
88  bool Warning(SMLoc L, const Twine &Msg,
89               ArrayRef<SMRange> Ranges = ArrayRef<SMRange>()) {
90    return Parser.Warning(L, Msg, Ranges);
91  }
92  bool Error(SMLoc L, const Twine &Msg,
93             ArrayRef<SMRange> Ranges = ArrayRef<SMRange>()) {
94    return Parser.Error(L, Msg, Ranges);
95  }
96
97  int tryParseRegister();
98  bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
99  int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
100  bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
101  bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
102  bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
103  bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
104  bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
105                              unsigned &ShiftAmount);
106  bool parseDirectiveWord(unsigned Size, SMLoc L);
107  bool parseDirectiveThumb(SMLoc L);
108  bool parseDirectiveARM(SMLoc L);
109  bool parseDirectiveThumbFunc(SMLoc L);
110  bool parseDirectiveCode(SMLoc L);
111  bool parseDirectiveSyntax(SMLoc L);
112  bool parseDirectiveReq(StringRef Name, SMLoc L);
113  bool parseDirectiveUnreq(SMLoc L);
114  bool parseDirectiveArch(SMLoc L);
115  bool parseDirectiveEabiAttr(SMLoc L);
116
117  StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
118                          bool &CarrySetting, unsigned &ProcessorIMod,
119                          StringRef &ITMask);
120  void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
121                             bool &CanAcceptPredicationCode);
122
123  bool isThumb() const {
124    // FIXME: Can tablegen auto-generate this?
125    return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
126  }
127  bool isThumbOne() const {
128    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
129  }
130  bool isThumbTwo() const {
131    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
132  }
133  bool hasV6Ops() const {
134    return STI.getFeatureBits() & ARM::HasV6Ops;
135  }
136  bool hasV7Ops() const {
137    return STI.getFeatureBits() & ARM::HasV7Ops;
138  }
139  void SwitchMode() {
140    unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
141    setAvailableFeatures(FB);
142  }
143  bool isMClass() const {
144    return STI.getFeatureBits() & ARM::FeatureMClass;
145  }
146
147  /// @name Auto-generated Match Functions
148  /// {
149
150#define GET_ASSEMBLER_HEADER
151#include "ARMGenAsmMatcher.inc"
152
153  /// }
154
155  OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
156  OperandMatchResultTy parseCoprocNumOperand(
157    SmallVectorImpl<MCParsedAsmOperand*>&);
158  OperandMatchResultTy parseCoprocRegOperand(
159    SmallVectorImpl<MCParsedAsmOperand*>&);
160  OperandMatchResultTy parseCoprocOptionOperand(
161    SmallVectorImpl<MCParsedAsmOperand*>&);
162  OperandMatchResultTy parseMemBarrierOptOperand(
163    SmallVectorImpl<MCParsedAsmOperand*>&);
164  OperandMatchResultTy parseProcIFlagsOperand(
165    SmallVectorImpl<MCParsedAsmOperand*>&);
166  OperandMatchResultTy parseMSRMaskOperand(
167    SmallVectorImpl<MCParsedAsmOperand*>&);
168  OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
169                                   StringRef Op, int Low, int High);
170  OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
171    return parsePKHImm(O, "lsl", 0, 31);
172  }
173  OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
174    return parsePKHImm(O, "asr", 1, 32);
175  }
176  OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
177  OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
178  OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
179  OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
180  OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
181  OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
182  OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&);
183  OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&);
184  OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
185                                       SMLoc &EndLoc);
186
187  // Asm Match Converter Methods
188  void cvtT2LdrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &);
189  void cvtT2StrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &);
190  void cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst,
191                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
192  void cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst,
193                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
194  void cvtLdWriteBackRegAddrMode2(MCInst &Inst,
195                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
196  void cvtLdWriteBackRegAddrModeImm12(MCInst &Inst,
197                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
198  void cvtStWriteBackRegAddrModeImm12(MCInst &Inst,
199                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
200  void cvtStWriteBackRegAddrMode2(MCInst &Inst,
201                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
202  void cvtStWriteBackRegAddrMode3(MCInst &Inst,
203                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
204  void cvtLdExtTWriteBackImm(MCInst &Inst,
205                             const SmallVectorImpl<MCParsedAsmOperand*> &);
206  void cvtLdExtTWriteBackReg(MCInst &Inst,
207                             const SmallVectorImpl<MCParsedAsmOperand*> &);
208  void cvtStExtTWriteBackImm(MCInst &Inst,
209                             const SmallVectorImpl<MCParsedAsmOperand*> &);
210  void cvtStExtTWriteBackReg(MCInst &Inst,
211                             const SmallVectorImpl<MCParsedAsmOperand*> &);
212  void cvtLdrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &);
213  void cvtStrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &);
214  void cvtLdWriteBackRegAddrMode3(MCInst &Inst,
215                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
216  void cvtThumbMultiply(MCInst &Inst,
217                        const SmallVectorImpl<MCParsedAsmOperand*> &);
218  void cvtVLDwbFixed(MCInst &Inst,
219                     const SmallVectorImpl<MCParsedAsmOperand*> &);
220  void cvtVLDwbRegister(MCInst &Inst,
221                        const SmallVectorImpl<MCParsedAsmOperand*> &);
222  void cvtVSTwbFixed(MCInst &Inst,
223                     const SmallVectorImpl<MCParsedAsmOperand*> &);
224  void cvtVSTwbRegister(MCInst &Inst,
225                        const SmallVectorImpl<MCParsedAsmOperand*> &);
226  bool validateInstruction(MCInst &Inst,
227                           const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
228  bool processInstruction(MCInst &Inst,
229                          const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
230  bool shouldOmitCCOutOperand(StringRef Mnemonic,
231                              SmallVectorImpl<MCParsedAsmOperand*> &Operands);
232
233public:
234  enum ARMMatchResultTy {
235    Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
236    Match_RequiresNotITBlock,
237    Match_RequiresV6,
238    Match_RequiresThumb2,
239#define GET_OPERAND_DIAGNOSTIC_TYPES
240#include "ARMGenAsmMatcher.inc"
241
242  };
243
244  ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
245    : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
246    MCAsmParserExtension::Initialize(_Parser);
247
248    // Cache the MCRegisterInfo.
249    MRI = &getContext().getRegisterInfo();
250
251    // Initialize the set of available features.
252    setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
253
254    // Not in an ITBlock to start with.
255    ITState.CurPosition = ~0U;
256
257    // Set ELF header flags.
258    // FIXME: This should eventually end up somewhere else where more
259    // intelligent flag decisions can be made. For now we are just maintaining
260    // the statu/parseDirects quo for ARM and setting EF_ARM_EABI_VER5 as the default.
261    if (MCELFStreamer *MES = dyn_cast<MCELFStreamer>(&Parser.getStreamer()))
262      MES->getAssembler().setELFHeaderEFlags(ELF::EF_ARM_EABI_VER5);
263  }
264
265  // Implementation of the MCTargetAsmParser interface:
266  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
267  bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
268                        SMLoc NameLoc,
269                        SmallVectorImpl<MCParsedAsmOperand*> &Operands);
270  bool ParseDirective(AsmToken DirectiveID);
271
272  unsigned validateTargetOperandClass(MCParsedAsmOperand *Op, unsigned Kind);
273  unsigned checkTargetMatchPredicate(MCInst &Inst);
274
275  bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
276                               SmallVectorImpl<MCParsedAsmOperand*> &Operands,
277                               MCStreamer &Out, unsigned &ErrorInfo,
278                               bool MatchingInlineAsm);
279};
280} // end anonymous namespace
281
282namespace {
283
284/// ARMOperand - Instances of this class represent a parsed ARM machine
285/// operand.
286class ARMOperand : public MCParsedAsmOperand {
287  enum KindTy {
288    k_CondCode,
289    k_CCOut,
290    k_ITCondMask,
291    k_CoprocNum,
292    k_CoprocReg,
293    k_CoprocOption,
294    k_Immediate,
295    k_MemBarrierOpt,
296    k_Memory,
297    k_PostIndexRegister,
298    k_MSRMask,
299    k_ProcIFlags,
300    k_VectorIndex,
301    k_Register,
302    k_RegisterList,
303    k_DPRRegisterList,
304    k_SPRRegisterList,
305    k_VectorList,
306    k_VectorListAllLanes,
307    k_VectorListIndexed,
308    k_ShiftedRegister,
309    k_ShiftedImmediate,
310    k_ShifterImmediate,
311    k_RotateImmediate,
312    k_BitfieldDescriptor,
313    k_Token
314  } Kind;
315
316  SMLoc StartLoc, EndLoc;
317  SmallVector<unsigned, 8> Registers;
318
319  struct CCOp {
320    ARMCC::CondCodes Val;
321  };
322
323  struct CopOp {
324    unsigned Val;
325  };
326
327  struct CoprocOptionOp {
328    unsigned Val;
329  };
330
331  struct ITMaskOp {
332    unsigned Mask:4;
333  };
334
335  struct MBOptOp {
336    ARM_MB::MemBOpt Val;
337  };
338
339  struct IFlagsOp {
340    ARM_PROC::IFlags Val;
341  };
342
343  struct MMaskOp {
344    unsigned Val;
345  };
346
347  struct TokOp {
348    const char *Data;
349    unsigned Length;
350  };
351
352  struct RegOp {
353    unsigned RegNum;
354  };
355
356  // A vector register list is a sequential list of 1 to 4 registers.
357  struct VectorListOp {
358    unsigned RegNum;
359    unsigned Count;
360    unsigned LaneIndex;
361    bool isDoubleSpaced;
362  };
363
364  struct VectorIndexOp {
365    unsigned Val;
366  };
367
368  struct ImmOp {
369    const MCExpr *Val;
370  };
371
372  /// Combined record for all forms of ARM address expressions.
373  struct MemoryOp {
374    unsigned BaseRegNum;
375    // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
376    // was specified.
377    const MCConstantExpr *OffsetImm;  // Offset immediate value
378    unsigned OffsetRegNum;    // Offset register num, when OffsetImm == NULL
379    ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
380    unsigned ShiftImm;        // shift for OffsetReg.
381    unsigned Alignment;       // 0 = no alignment specified
382    // n = alignment in bytes (2, 4, 8, 16, or 32)
383    unsigned isNegative : 1;  // Negated OffsetReg? (~'U' bit)
384  };
385
386  struct PostIdxRegOp {
387    unsigned RegNum;
388    bool isAdd;
389    ARM_AM::ShiftOpc ShiftTy;
390    unsigned ShiftImm;
391  };
392
393  struct ShifterImmOp {
394    bool isASR;
395    unsigned Imm;
396  };
397
398  struct RegShiftedRegOp {
399    ARM_AM::ShiftOpc ShiftTy;
400    unsigned SrcReg;
401    unsigned ShiftReg;
402    unsigned ShiftImm;
403  };
404
405  struct RegShiftedImmOp {
406    ARM_AM::ShiftOpc ShiftTy;
407    unsigned SrcReg;
408    unsigned ShiftImm;
409  };
410
411  struct RotImmOp {
412    unsigned Imm;
413  };
414
415  struct BitfieldOp {
416    unsigned LSB;
417    unsigned Width;
418  };
419
420  union {
421    struct CCOp CC;
422    struct CopOp Cop;
423    struct CoprocOptionOp CoprocOption;
424    struct MBOptOp MBOpt;
425    struct ITMaskOp ITMask;
426    struct IFlagsOp IFlags;
427    struct MMaskOp MMask;
428    struct TokOp Tok;
429    struct RegOp Reg;
430    struct VectorListOp VectorList;
431    struct VectorIndexOp VectorIndex;
432    struct ImmOp Imm;
433    struct MemoryOp Memory;
434    struct PostIdxRegOp PostIdxReg;
435    struct ShifterImmOp ShifterImm;
436    struct RegShiftedRegOp RegShiftedReg;
437    struct RegShiftedImmOp RegShiftedImm;
438    struct RotImmOp RotImm;
439    struct BitfieldOp Bitfield;
440  };
441
442  ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
443public:
444  ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
445    Kind = o.Kind;
446    StartLoc = o.StartLoc;
447    EndLoc = o.EndLoc;
448    switch (Kind) {
449    case k_CondCode:
450      CC = o.CC;
451      break;
452    case k_ITCondMask:
453      ITMask = o.ITMask;
454      break;
455    case k_Token:
456      Tok = o.Tok;
457      break;
458    case k_CCOut:
459    case k_Register:
460      Reg = o.Reg;
461      break;
462    case k_RegisterList:
463    case k_DPRRegisterList:
464    case k_SPRRegisterList:
465      Registers = o.Registers;
466      break;
467    case k_VectorList:
468    case k_VectorListAllLanes:
469    case k_VectorListIndexed:
470      VectorList = o.VectorList;
471      break;
472    case k_CoprocNum:
473    case k_CoprocReg:
474      Cop = o.Cop;
475      break;
476    case k_CoprocOption:
477      CoprocOption = o.CoprocOption;
478      break;
479    case k_Immediate:
480      Imm = o.Imm;
481      break;
482    case k_MemBarrierOpt:
483      MBOpt = o.MBOpt;
484      break;
485    case k_Memory:
486      Memory = o.Memory;
487      break;
488    case k_PostIndexRegister:
489      PostIdxReg = o.PostIdxReg;
490      break;
491    case k_MSRMask:
492      MMask = o.MMask;
493      break;
494    case k_ProcIFlags:
495      IFlags = o.IFlags;
496      break;
497    case k_ShifterImmediate:
498      ShifterImm = o.ShifterImm;
499      break;
500    case k_ShiftedRegister:
501      RegShiftedReg = o.RegShiftedReg;
502      break;
503    case k_ShiftedImmediate:
504      RegShiftedImm = o.RegShiftedImm;
505      break;
506    case k_RotateImmediate:
507      RotImm = o.RotImm;
508      break;
509    case k_BitfieldDescriptor:
510      Bitfield = o.Bitfield;
511      break;
512    case k_VectorIndex:
513      VectorIndex = o.VectorIndex;
514      break;
515    }
516  }
517
518  /// getStartLoc - Get the location of the first token of this operand.
519  SMLoc getStartLoc() const { return StartLoc; }
520  /// getEndLoc - Get the location of the last token of this operand.
521  SMLoc getEndLoc() const { return EndLoc; }
522  /// getLocRange - Get the range between the first and last token of this
523  /// operand.
524  SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
525
526  ARMCC::CondCodes getCondCode() const {
527    assert(Kind == k_CondCode && "Invalid access!");
528    return CC.Val;
529  }
530
531  unsigned getCoproc() const {
532    assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
533    return Cop.Val;
534  }
535
536  StringRef getToken() const {
537    assert(Kind == k_Token && "Invalid access!");
538    return StringRef(Tok.Data, Tok.Length);
539  }
540
541  unsigned getReg() const {
542    assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
543    return Reg.RegNum;
544  }
545
546  const SmallVectorImpl<unsigned> &getRegList() const {
547    assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
548            Kind == k_SPRRegisterList) && "Invalid access!");
549    return Registers;
550  }
551
552  const MCExpr *getImm() const {
553    assert(isImm() && "Invalid access!");
554    return Imm.Val;
555  }
556
557  unsigned getVectorIndex() const {
558    assert(Kind == k_VectorIndex && "Invalid access!");
559    return VectorIndex.Val;
560  }
561
562  ARM_MB::MemBOpt getMemBarrierOpt() const {
563    assert(Kind == k_MemBarrierOpt && "Invalid access!");
564    return MBOpt.Val;
565  }
566
567  ARM_PROC::IFlags getProcIFlags() const {
568    assert(Kind == k_ProcIFlags && "Invalid access!");
569    return IFlags.Val;
570  }
571
572  unsigned getMSRMask() const {
573    assert(Kind == k_MSRMask && "Invalid access!");
574    return MMask.Val;
575  }
576
577  bool isCoprocNum() const { return Kind == k_CoprocNum; }
578  bool isCoprocReg() const { return Kind == k_CoprocReg; }
579  bool isCoprocOption() const { return Kind == k_CoprocOption; }
580  bool isCondCode() const { return Kind == k_CondCode; }
581  bool isCCOut() const { return Kind == k_CCOut; }
582  bool isITMask() const { return Kind == k_ITCondMask; }
583  bool isITCondCode() const { return Kind == k_CondCode; }
584  bool isImm() const { return Kind == k_Immediate; }
585  bool isFPImm() const {
586    if (!isImm()) return false;
587    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
588    if (!CE) return false;
589    int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
590    return Val != -1;
591  }
592  bool isFBits16() const {
593    if (!isImm()) return false;
594    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
595    if (!CE) return false;
596    int64_t Value = CE->getValue();
597    return Value >= 0 && Value <= 16;
598  }
599  bool isFBits32() const {
600    if (!isImm()) return false;
601    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
602    if (!CE) return false;
603    int64_t Value = CE->getValue();
604    return Value >= 1 && Value <= 32;
605  }
606  bool isImm8s4() const {
607    if (!isImm()) return false;
608    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
609    if (!CE) return false;
610    int64_t Value = CE->getValue();
611    return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
612  }
613  bool isImm0_1020s4() const {
614    if (!isImm()) return false;
615    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
616    if (!CE) return false;
617    int64_t Value = CE->getValue();
618    return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
619  }
620  bool isImm0_508s4() const {
621    if (!isImm()) return false;
622    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
623    if (!CE) return false;
624    int64_t Value = CE->getValue();
625    return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
626  }
627  bool isImm0_508s4Neg() const {
628    if (!isImm()) return false;
629    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
630    if (!CE) return false;
631    int64_t Value = -CE->getValue();
632    // explicitly exclude zero. we want that to use the normal 0_508 version.
633    return ((Value & 3) == 0) && Value > 0 && Value <= 508;
634  }
635  bool isImm0_255() const {
636    if (!isImm()) return false;
637    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
638    if (!CE) return false;
639    int64_t Value = CE->getValue();
640    return Value >= 0 && Value < 256;
641  }
642  bool isImm0_4095() const {
643    if (!isImm()) return false;
644    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
645    if (!CE) return false;
646    int64_t Value = CE->getValue();
647    return Value >= 0 && Value < 4096;
648  }
649  bool isImm0_4095Neg() const {
650    if (!isImm()) return false;
651    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
652    if (!CE) return false;
653    int64_t Value = -CE->getValue();
654    return Value > 0 && Value < 4096;
655  }
656  bool isImm0_1() const {
657    if (!isImm()) return false;
658    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
659    if (!CE) return false;
660    int64_t Value = CE->getValue();
661    return Value >= 0 && Value < 2;
662  }
663  bool isImm0_3() const {
664    if (!isImm()) return false;
665    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
666    if (!CE) return false;
667    int64_t Value = CE->getValue();
668    return Value >= 0 && Value < 4;
669  }
670  bool isImm0_7() const {
671    if (!isImm()) return false;
672    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
673    if (!CE) return false;
674    int64_t Value = CE->getValue();
675    return Value >= 0 && Value < 8;
676  }
677  bool isImm0_15() const {
678    if (!isImm()) return false;
679    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
680    if (!CE) return false;
681    int64_t Value = CE->getValue();
682    return Value >= 0 && Value < 16;
683  }
684  bool isImm0_31() const {
685    if (!isImm()) return false;
686    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
687    if (!CE) return false;
688    int64_t Value = CE->getValue();
689    return Value >= 0 && Value < 32;
690  }
691  bool isImm0_63() const {
692    if (!isImm()) return false;
693    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
694    if (!CE) return false;
695    int64_t Value = CE->getValue();
696    return Value >= 0 && Value < 64;
697  }
698  bool isImm8() const {
699    if (!isImm()) return false;
700    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
701    if (!CE) return false;
702    int64_t Value = CE->getValue();
703    return Value == 8;
704  }
705  bool isImm16() const {
706    if (!isImm()) return false;
707    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
708    if (!CE) return false;
709    int64_t Value = CE->getValue();
710    return Value == 16;
711  }
712  bool isImm32() const {
713    if (!isImm()) return false;
714    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
715    if (!CE) return false;
716    int64_t Value = CE->getValue();
717    return Value == 32;
718  }
719  bool isShrImm8() const {
720    if (!isImm()) return false;
721    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
722    if (!CE) return false;
723    int64_t Value = CE->getValue();
724    return Value > 0 && Value <= 8;
725  }
726  bool isShrImm16() const {
727    if (!isImm()) return false;
728    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
729    if (!CE) return false;
730    int64_t Value = CE->getValue();
731    return Value > 0 && Value <= 16;
732  }
733  bool isShrImm32() const {
734    if (!isImm()) return false;
735    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
736    if (!CE) return false;
737    int64_t Value = CE->getValue();
738    return Value > 0 && Value <= 32;
739  }
740  bool isShrImm64() const {
741    if (!isImm()) return false;
742    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
743    if (!CE) return false;
744    int64_t Value = CE->getValue();
745    return Value > 0 && Value <= 64;
746  }
747  bool isImm1_7() const {
748    if (!isImm()) return false;
749    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
750    if (!CE) return false;
751    int64_t Value = CE->getValue();
752    return Value > 0 && Value < 8;
753  }
754  bool isImm1_15() const {
755    if (!isImm()) return false;
756    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
757    if (!CE) return false;
758    int64_t Value = CE->getValue();
759    return Value > 0 && Value < 16;
760  }
761  bool isImm1_31() const {
762    if (!isImm()) return false;
763    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
764    if (!CE) return false;
765    int64_t Value = CE->getValue();
766    return Value > 0 && Value < 32;
767  }
768  bool isImm1_16() const {
769    if (!isImm()) return false;
770    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
771    if (!CE) return false;
772    int64_t Value = CE->getValue();
773    return Value > 0 && Value < 17;
774  }
775  bool isImm1_32() const {
776    if (!isImm()) return false;
777    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
778    if (!CE) return false;
779    int64_t Value = CE->getValue();
780    return Value > 0 && Value < 33;
781  }
782  bool isImm0_32() const {
783    if (!isImm()) return false;
784    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
785    if (!CE) return false;
786    int64_t Value = CE->getValue();
787    return Value >= 0 && Value < 33;
788  }
789  bool isImm0_65535() const {
790    if (!isImm()) return false;
791    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
792    if (!CE) return false;
793    int64_t Value = CE->getValue();
794    return Value >= 0 && Value < 65536;
795  }
796  bool isImm0_65535Expr() const {
797    if (!isImm()) return false;
798    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
799    // If it's not a constant expression, it'll generate a fixup and be
800    // handled later.
801    if (!CE) return true;
802    int64_t Value = CE->getValue();
803    return Value >= 0 && Value < 65536;
804  }
805  bool isImm24bit() const {
806    if (!isImm()) return false;
807    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
808    if (!CE) return false;
809    int64_t Value = CE->getValue();
810    return Value >= 0 && Value <= 0xffffff;
811  }
812  bool isImmThumbSR() const {
813    if (!isImm()) return false;
814    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
815    if (!CE) return false;
816    int64_t Value = CE->getValue();
817    return Value > 0 && Value < 33;
818  }
819  bool isPKHLSLImm() const {
820    if (!isImm()) return false;
821    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
822    if (!CE) return false;
823    int64_t Value = CE->getValue();
824    return Value >= 0 && Value < 32;
825  }
826  bool isPKHASRImm() const {
827    if (!isImm()) return false;
828    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
829    if (!CE) return false;
830    int64_t Value = CE->getValue();
831    return Value > 0 && Value <= 32;
832  }
833  bool isAdrLabel() const {
834    // If we have an immediate that's not a constant, treat it as a label
835    // reference needing a fixup. If it is a constant, but it can't fit
836    // into shift immediate encoding, we reject it.
837    if (isImm() && !isa<MCConstantExpr>(getImm())) return true;
838    else return (isARMSOImm() || isARMSOImmNeg());
839  }
840  bool isARMSOImm() const {
841    if (!isImm()) return false;
842    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
843    if (!CE) return false;
844    int64_t Value = CE->getValue();
845    return ARM_AM::getSOImmVal(Value) != -1;
846  }
847  bool isARMSOImmNot() const {
848    if (!isImm()) return false;
849    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
850    if (!CE) return false;
851    int64_t Value = CE->getValue();
852    return ARM_AM::getSOImmVal(~Value) != -1;
853  }
854  bool isARMSOImmNeg() const {
855    if (!isImm()) return false;
856    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
857    if (!CE) return false;
858    int64_t Value = CE->getValue();
859    // Only use this when not representable as a plain so_imm.
860    return ARM_AM::getSOImmVal(Value) == -1 &&
861      ARM_AM::getSOImmVal(-Value) != -1;
862  }
863  bool isT2SOImm() const {
864    if (!isImm()) return false;
865    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
866    if (!CE) return false;
867    int64_t Value = CE->getValue();
868    return ARM_AM::getT2SOImmVal(Value) != -1;
869  }
870  bool isT2SOImmNot() const {
871    if (!isImm()) return false;
872    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
873    if (!CE) return false;
874    int64_t Value = CE->getValue();
875    return ARM_AM::getT2SOImmVal(~Value) != -1;
876  }
877  bool isT2SOImmNeg() const {
878    if (!isImm()) return false;
879    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
880    if (!CE) return false;
881    int64_t Value = CE->getValue();
882    // Only use this when not representable as a plain so_imm.
883    return ARM_AM::getT2SOImmVal(Value) == -1 &&
884      ARM_AM::getT2SOImmVal(-Value) != -1;
885  }
886  bool isSetEndImm() const {
887    if (!isImm()) return false;
888    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
889    if (!CE) return false;
890    int64_t Value = CE->getValue();
891    return Value == 1 || Value == 0;
892  }
893  bool isReg() const { return Kind == k_Register; }
894  bool isRegList() const { return Kind == k_RegisterList; }
895  bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
896  bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
897  bool isToken() const { return Kind == k_Token; }
898  bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
899  bool isMem() const { return Kind == k_Memory; }
900  bool isShifterImm() const { return Kind == k_ShifterImmediate; }
901  bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
902  bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
903  bool isRotImm() const { return Kind == k_RotateImmediate; }
904  bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
905  bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
906  bool isPostIdxReg() const {
907    return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
908  }
909  bool isMemNoOffset(bool alignOK = false) const {
910    if (!isMem())
911      return false;
912    // No offset of any kind.
913    return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 &&
914     (alignOK || Memory.Alignment == 0);
915  }
916  bool isMemPCRelImm12() const {
917    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
918      return false;
919    // Base register must be PC.
920    if (Memory.BaseRegNum != ARM::PC)
921      return false;
922    // Immediate offset in range [-4095, 4095].
923    if (!Memory.OffsetImm) return true;
924    int64_t Val = Memory.OffsetImm->getValue();
925    return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
926  }
927  bool isAlignedMemory() const {
928    return isMemNoOffset(true);
929  }
930  bool isAddrMode2() const {
931    if (!isMem() || Memory.Alignment != 0) return false;
932    // Check for register offset.
933    if (Memory.OffsetRegNum) return true;
934    // Immediate offset in range [-4095, 4095].
935    if (!Memory.OffsetImm) return true;
936    int64_t Val = Memory.OffsetImm->getValue();
937    return Val > -4096 && Val < 4096;
938  }
939  bool isAM2OffsetImm() const {
940    if (!isImm()) return false;
941    // Immediate offset in range [-4095, 4095].
942    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
943    if (!CE) return false;
944    int64_t Val = CE->getValue();
945    return Val > -4096 && Val < 4096;
946  }
947  bool isAddrMode3() const {
948    // If we have an immediate that's not a constant, treat it as a label
949    // reference needing a fixup. If it is a constant, it's something else
950    // and we reject it.
951    if (isImm() && !isa<MCConstantExpr>(getImm()))
952      return true;
953    if (!isMem() || Memory.Alignment != 0) return false;
954    // No shifts are legal for AM3.
955    if (Memory.ShiftType != ARM_AM::no_shift) return false;
956    // Check for register offset.
957    if (Memory.OffsetRegNum) return true;
958    // Immediate offset in range [-255, 255].
959    if (!Memory.OffsetImm) return true;
960    int64_t Val = Memory.OffsetImm->getValue();
961    // The #-0 offset is encoded as INT32_MIN, and we have to check
962    // for this too.
963    return (Val > -256 && Val < 256) || Val == INT32_MIN;
964  }
965  bool isAM3Offset() const {
966    if (Kind != k_Immediate && Kind != k_PostIndexRegister)
967      return false;
968    if (Kind == k_PostIndexRegister)
969      return PostIdxReg.ShiftTy == ARM_AM::no_shift;
970    // Immediate offset in range [-255, 255].
971    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
972    if (!CE) return false;
973    int64_t Val = CE->getValue();
974    // Special case, #-0 is INT32_MIN.
975    return (Val > -256 && Val < 256) || Val == INT32_MIN;
976  }
977  bool isAddrMode5() const {
978    // If we have an immediate that's not a constant, treat it as a label
979    // reference needing a fixup. If it is a constant, it's something else
980    // and we reject it.
981    if (isImm() && !isa<MCConstantExpr>(getImm()))
982      return true;
983    if (!isMem() || Memory.Alignment != 0) return false;
984    // Check for register offset.
985    if (Memory.OffsetRegNum) return false;
986    // Immediate offset in range [-1020, 1020] and a multiple of 4.
987    if (!Memory.OffsetImm) return true;
988    int64_t Val = Memory.OffsetImm->getValue();
989    return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
990      Val == INT32_MIN;
991  }
992  bool isMemTBB() const {
993    if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
994        Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
995      return false;
996    return true;
997  }
998  bool isMemTBH() const {
999    if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1000        Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1001        Memory.Alignment != 0 )
1002      return false;
1003    return true;
1004  }
1005  bool isMemRegOffset() const {
1006    if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
1007      return false;
1008    return true;
1009  }
1010  bool isT2MemRegOffset() const {
1011    if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1012        Memory.Alignment != 0)
1013      return false;
1014    // Only lsl #{0, 1, 2, 3} allowed.
1015    if (Memory.ShiftType == ARM_AM::no_shift)
1016      return true;
1017    if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1018      return false;
1019    return true;
1020  }
1021  bool isMemThumbRR() const {
1022    // Thumb reg+reg addressing is simple. Just two registers, a base and
1023    // an offset. No shifts, negations or any other complicating factors.
1024    if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1025        Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1026      return false;
1027    return isARMLowRegister(Memory.BaseRegNum) &&
1028      (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
1029  }
1030  bool isMemThumbRIs4() const {
1031    if (!isMem() || Memory.OffsetRegNum != 0 ||
1032        !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1033      return false;
1034    // Immediate offset, multiple of 4 in range [0, 124].
1035    if (!Memory.OffsetImm) return true;
1036    int64_t Val = Memory.OffsetImm->getValue();
1037    return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1038  }
1039  bool isMemThumbRIs2() const {
1040    if (!isMem() || Memory.OffsetRegNum != 0 ||
1041        !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1042      return false;
1043    // Immediate offset, multiple of 4 in range [0, 62].
1044    if (!Memory.OffsetImm) return true;
1045    int64_t Val = Memory.OffsetImm->getValue();
1046    return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1047  }
1048  bool isMemThumbRIs1() const {
1049    if (!isMem() || Memory.OffsetRegNum != 0 ||
1050        !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1051      return false;
1052    // Immediate offset in range [0, 31].
1053    if (!Memory.OffsetImm) return true;
1054    int64_t Val = Memory.OffsetImm->getValue();
1055    return Val >= 0 && Val <= 31;
1056  }
1057  bool isMemThumbSPI() const {
1058    if (!isMem() || Memory.OffsetRegNum != 0 ||
1059        Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1060      return false;
1061    // Immediate offset, multiple of 4 in range [0, 1020].
1062    if (!Memory.OffsetImm) return true;
1063    int64_t Val = Memory.OffsetImm->getValue();
1064    return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1065  }
1066  bool isMemImm8s4Offset() const {
1067    // If we have an immediate that's not a constant, treat it as a label
1068    // reference needing a fixup. If it is a constant, it's something else
1069    // and we reject it.
1070    if (isImm() && !isa<MCConstantExpr>(getImm()))
1071      return true;
1072    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1073      return false;
1074    // Immediate offset a multiple of 4 in range [-1020, 1020].
1075    if (!Memory.OffsetImm) return true;
1076    int64_t Val = Memory.OffsetImm->getValue();
1077    // Special case, #-0 is INT32_MIN.
1078    return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN;
1079  }
1080  bool isMemImm0_1020s4Offset() const {
1081    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1082      return false;
1083    // Immediate offset a multiple of 4 in range [0, 1020].
1084    if (!Memory.OffsetImm) return true;
1085    int64_t Val = Memory.OffsetImm->getValue();
1086    return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1087  }
1088  bool isMemImm8Offset() const {
1089    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1090      return false;
1091    // Base reg of PC isn't allowed for these encodings.
1092    if (Memory.BaseRegNum == ARM::PC) return false;
1093    // Immediate offset in range [-255, 255].
1094    if (!Memory.OffsetImm) return true;
1095    int64_t Val = Memory.OffsetImm->getValue();
1096    return (Val == INT32_MIN) || (Val > -256 && Val < 256);
1097  }
1098  bool isMemPosImm8Offset() const {
1099    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1100      return false;
1101    // Immediate offset in range [0, 255].
1102    if (!Memory.OffsetImm) return true;
1103    int64_t Val = Memory.OffsetImm->getValue();
1104    return Val >= 0 && Val < 256;
1105  }
1106  bool isMemNegImm8Offset() const {
1107    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1108      return false;
1109    // Base reg of PC isn't allowed for these encodings.
1110    if (Memory.BaseRegNum == ARM::PC) return false;
1111    // Immediate offset in range [-255, -1].
1112    if (!Memory.OffsetImm) return false;
1113    int64_t Val = Memory.OffsetImm->getValue();
1114    return (Val == INT32_MIN) || (Val > -256 && Val < 0);
1115  }
1116  bool isMemUImm12Offset() const {
1117    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1118      return false;
1119    // Immediate offset in range [0, 4095].
1120    if (!Memory.OffsetImm) return true;
1121    int64_t Val = Memory.OffsetImm->getValue();
1122    return (Val >= 0 && Val < 4096);
1123  }
1124  bool isMemImm12Offset() const {
1125    // If we have an immediate that's not a constant, treat it as a label
1126    // reference needing a fixup. If it is a constant, it's something else
1127    // and we reject it.
1128    if (isImm() && !isa<MCConstantExpr>(getImm()))
1129      return true;
1130
1131    if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1132      return false;
1133    // Immediate offset in range [-4095, 4095].
1134    if (!Memory.OffsetImm) return true;
1135    int64_t Val = Memory.OffsetImm->getValue();
1136    return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1137  }
1138  bool isPostIdxImm8() const {
1139    if (!isImm()) return false;
1140    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1141    if (!CE) return false;
1142    int64_t Val = CE->getValue();
1143    return (Val > -256 && Val < 256) || (Val == INT32_MIN);
1144  }
1145  bool isPostIdxImm8s4() const {
1146    if (!isImm()) return false;
1147    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1148    if (!CE) return false;
1149    int64_t Val = CE->getValue();
1150    return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1151      (Val == INT32_MIN);
1152  }
1153
1154  bool isMSRMask() const { return Kind == k_MSRMask; }
1155  bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1156
1157  // NEON operands.
1158  bool isSingleSpacedVectorList() const {
1159    return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1160  }
1161  bool isDoubleSpacedVectorList() const {
1162    return Kind == k_VectorList && VectorList.isDoubleSpaced;
1163  }
1164  bool isVecListOneD() const {
1165    if (!isSingleSpacedVectorList()) return false;
1166    return VectorList.Count == 1;
1167  }
1168
1169  bool isVecListDPair() const {
1170    if (!isSingleSpacedVectorList()) return false;
1171    return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1172              .contains(VectorList.RegNum));
1173  }
1174
1175  bool isVecListThreeD() const {
1176    if (!isSingleSpacedVectorList()) return false;
1177    return VectorList.Count == 3;
1178  }
1179
1180  bool isVecListFourD() const {
1181    if (!isSingleSpacedVectorList()) return false;
1182    return VectorList.Count == 4;
1183  }
1184
1185  bool isVecListDPairSpaced() const {
1186    if (isSingleSpacedVectorList()) return false;
1187    return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1188              .contains(VectorList.RegNum));
1189  }
1190
1191  bool isVecListThreeQ() const {
1192    if (!isDoubleSpacedVectorList()) return false;
1193    return VectorList.Count == 3;
1194  }
1195
1196  bool isVecListFourQ() const {
1197    if (!isDoubleSpacedVectorList()) return false;
1198    return VectorList.Count == 4;
1199  }
1200
1201  bool isSingleSpacedVectorAllLanes() const {
1202    return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1203  }
1204  bool isDoubleSpacedVectorAllLanes() const {
1205    return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1206  }
1207  bool isVecListOneDAllLanes() const {
1208    if (!isSingleSpacedVectorAllLanes()) return false;
1209    return VectorList.Count == 1;
1210  }
1211
1212  bool isVecListDPairAllLanes() const {
1213    if (!isSingleSpacedVectorAllLanes()) return false;
1214    return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1215              .contains(VectorList.RegNum));
1216  }
1217
1218  bool isVecListDPairSpacedAllLanes() const {
1219    if (!isDoubleSpacedVectorAllLanes()) return false;
1220    return VectorList.Count == 2;
1221  }
1222
1223  bool isVecListThreeDAllLanes() const {
1224    if (!isSingleSpacedVectorAllLanes()) return false;
1225    return VectorList.Count == 3;
1226  }
1227
1228  bool isVecListThreeQAllLanes() const {
1229    if (!isDoubleSpacedVectorAllLanes()) return false;
1230    return VectorList.Count == 3;
1231  }
1232
1233  bool isVecListFourDAllLanes() const {
1234    if (!isSingleSpacedVectorAllLanes()) return false;
1235    return VectorList.Count == 4;
1236  }
1237
1238  bool isVecListFourQAllLanes() const {
1239    if (!isDoubleSpacedVectorAllLanes()) return false;
1240    return VectorList.Count == 4;
1241  }
1242
1243  bool isSingleSpacedVectorIndexed() const {
1244    return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1245  }
1246  bool isDoubleSpacedVectorIndexed() const {
1247    return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1248  }
1249  bool isVecListOneDByteIndexed() const {
1250    if (!isSingleSpacedVectorIndexed()) return false;
1251    return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1252  }
1253
1254  bool isVecListOneDHWordIndexed() const {
1255    if (!isSingleSpacedVectorIndexed()) return false;
1256    return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1257  }
1258
1259  bool isVecListOneDWordIndexed() const {
1260    if (!isSingleSpacedVectorIndexed()) return false;
1261    return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1262  }
1263
1264  bool isVecListTwoDByteIndexed() const {
1265    if (!isSingleSpacedVectorIndexed()) return false;
1266    return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1267  }
1268
1269  bool isVecListTwoDHWordIndexed() const {
1270    if (!isSingleSpacedVectorIndexed()) return false;
1271    return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1272  }
1273
1274  bool isVecListTwoQWordIndexed() const {
1275    if (!isDoubleSpacedVectorIndexed()) return false;
1276    return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1277  }
1278
1279  bool isVecListTwoQHWordIndexed() const {
1280    if (!isDoubleSpacedVectorIndexed()) return false;
1281    return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1282  }
1283
1284  bool isVecListTwoDWordIndexed() const {
1285    if (!isSingleSpacedVectorIndexed()) return false;
1286    return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1287  }
1288
1289  bool isVecListThreeDByteIndexed() const {
1290    if (!isSingleSpacedVectorIndexed()) return false;
1291    return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
1292  }
1293
1294  bool isVecListThreeDHWordIndexed() const {
1295    if (!isSingleSpacedVectorIndexed()) return false;
1296    return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1297  }
1298
1299  bool isVecListThreeQWordIndexed() const {
1300    if (!isDoubleSpacedVectorIndexed()) return false;
1301    return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1302  }
1303
1304  bool isVecListThreeQHWordIndexed() const {
1305    if (!isDoubleSpacedVectorIndexed()) return false;
1306    return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1307  }
1308
1309  bool isVecListThreeDWordIndexed() const {
1310    if (!isSingleSpacedVectorIndexed()) return false;
1311    return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1312  }
1313
1314  bool isVecListFourDByteIndexed() const {
1315    if (!isSingleSpacedVectorIndexed()) return false;
1316    return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
1317  }
1318
1319  bool isVecListFourDHWordIndexed() const {
1320    if (!isSingleSpacedVectorIndexed()) return false;
1321    return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1322  }
1323
1324  bool isVecListFourQWordIndexed() const {
1325    if (!isDoubleSpacedVectorIndexed()) return false;
1326    return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1327  }
1328
1329  bool isVecListFourQHWordIndexed() const {
1330    if (!isDoubleSpacedVectorIndexed()) return false;
1331    return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1332  }
1333
1334  bool isVecListFourDWordIndexed() const {
1335    if (!isSingleSpacedVectorIndexed()) return false;
1336    return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1337  }
1338
1339  bool isVectorIndex8() const {
1340    if (Kind != k_VectorIndex) return false;
1341    return VectorIndex.Val < 8;
1342  }
1343  bool isVectorIndex16() const {
1344    if (Kind != k_VectorIndex) return false;
1345    return VectorIndex.Val < 4;
1346  }
1347  bool isVectorIndex32() const {
1348    if (Kind != k_VectorIndex) return false;
1349    return VectorIndex.Val < 2;
1350  }
1351
1352  bool isNEONi8splat() const {
1353    if (!isImm()) return false;
1354    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1355    // Must be a constant.
1356    if (!CE) return false;
1357    int64_t Value = CE->getValue();
1358    // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1359    // value.
1360    return Value >= 0 && Value < 256;
1361  }
1362
1363  bool isNEONi16splat() const {
1364    if (!isImm()) return false;
1365    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1366    // Must be a constant.
1367    if (!CE) return false;
1368    int64_t Value = CE->getValue();
1369    // i16 value in the range [0,255] or [0x0100, 0xff00]
1370    return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00);
1371  }
1372
1373  bool isNEONi32splat() const {
1374    if (!isImm()) return false;
1375    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1376    // Must be a constant.
1377    if (!CE) return false;
1378    int64_t Value = CE->getValue();
1379    // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
1380    return (Value >= 0 && Value < 256) ||
1381      (Value >= 0x0100 && Value <= 0xff00) ||
1382      (Value >= 0x010000 && Value <= 0xff0000) ||
1383      (Value >= 0x01000000 && Value <= 0xff000000);
1384  }
1385
1386  bool isNEONi32vmov() const {
1387    if (!isImm()) return false;
1388    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1389    // Must be a constant.
1390    if (!CE) return false;
1391    int64_t Value = CE->getValue();
1392    // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1393    // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1394    return (Value >= 0 && Value < 256) ||
1395      (Value >= 0x0100 && Value <= 0xff00) ||
1396      (Value >= 0x010000 && Value <= 0xff0000) ||
1397      (Value >= 0x01000000 && Value <= 0xff000000) ||
1398      (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1399      (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1400  }
1401  bool isNEONi32vmovNeg() const {
1402    if (!isImm()) return false;
1403    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1404    // Must be a constant.
1405    if (!CE) return false;
1406    int64_t Value = ~CE->getValue();
1407    // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1408    // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1409    return (Value >= 0 && Value < 256) ||
1410      (Value >= 0x0100 && Value <= 0xff00) ||
1411      (Value >= 0x010000 && Value <= 0xff0000) ||
1412      (Value >= 0x01000000 && Value <= 0xff000000) ||
1413      (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1414      (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1415  }
1416
1417  bool isNEONi64splat() const {
1418    if (!isImm()) return false;
1419    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1420    // Must be a constant.
1421    if (!CE) return false;
1422    uint64_t Value = CE->getValue();
1423    // i64 value with each byte being either 0 or 0xff.
1424    for (unsigned i = 0; i < 8; ++i)
1425      if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1426    return true;
1427  }
1428
1429  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1430    // Add as immediates when possible.  Null MCExpr = 0.
1431    if (Expr == 0)
1432      Inst.addOperand(MCOperand::CreateImm(0));
1433    else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1434      Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1435    else
1436      Inst.addOperand(MCOperand::CreateExpr(Expr));
1437  }
1438
1439  void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1440    assert(N == 2 && "Invalid number of operands!");
1441    Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1442    unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1443    Inst.addOperand(MCOperand::CreateReg(RegNum));
1444  }
1445
1446  void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1447    assert(N == 1 && "Invalid number of operands!");
1448    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1449  }
1450
1451  void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1452    assert(N == 1 && "Invalid number of operands!");
1453    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1454  }
1455
1456  void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1457    assert(N == 1 && "Invalid number of operands!");
1458    Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1459  }
1460
1461  void addITMaskOperands(MCInst &Inst, unsigned N) const {
1462    assert(N == 1 && "Invalid number of operands!");
1463    Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1464  }
1465
1466  void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1467    assert(N == 1 && "Invalid number of operands!");
1468    Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1469  }
1470
1471  void addCCOutOperands(MCInst &Inst, unsigned N) const {
1472    assert(N == 1 && "Invalid number of operands!");
1473    Inst.addOperand(MCOperand::CreateReg(getReg()));
1474  }
1475
1476  void addRegOperands(MCInst &Inst, unsigned N) const {
1477    assert(N == 1 && "Invalid number of operands!");
1478    Inst.addOperand(MCOperand::CreateReg(getReg()));
1479  }
1480
1481  void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1482    assert(N == 3 && "Invalid number of operands!");
1483    assert(isRegShiftedReg() &&
1484           "addRegShiftedRegOperands() on non RegShiftedReg!");
1485    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1486    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1487    Inst.addOperand(MCOperand::CreateImm(
1488      ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1489  }
1490
1491  void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1492    assert(N == 2 && "Invalid number of operands!");
1493    assert(isRegShiftedImm() &&
1494           "addRegShiftedImmOperands() on non RegShiftedImm!");
1495    Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1496    // Shift of #32 is encoded as 0 where permitted
1497    unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
1498    Inst.addOperand(MCOperand::CreateImm(
1499      ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
1500  }
1501
1502  void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1503    assert(N == 1 && "Invalid number of operands!");
1504    Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1505                                         ShifterImm.Imm));
1506  }
1507
1508  void addRegListOperands(MCInst &Inst, unsigned N) const {
1509    assert(N == 1 && "Invalid number of operands!");
1510    const SmallVectorImpl<unsigned> &RegList = getRegList();
1511    for (SmallVectorImpl<unsigned>::const_iterator
1512           I = RegList.begin(), E = RegList.end(); I != E; ++I)
1513      Inst.addOperand(MCOperand::CreateReg(*I));
1514  }
1515
1516  void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1517    addRegListOperands(Inst, N);
1518  }
1519
1520  void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1521    addRegListOperands(Inst, N);
1522  }
1523
1524  void addRotImmOperands(MCInst &Inst, unsigned N) const {
1525    assert(N == 1 && "Invalid number of operands!");
1526    // Encoded as val>>3. The printer handles display as 8, 16, 24.
1527    Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1528  }
1529
1530  void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1531    assert(N == 1 && "Invalid number of operands!");
1532    // Munge the lsb/width into a bitfield mask.
1533    unsigned lsb = Bitfield.LSB;
1534    unsigned width = Bitfield.Width;
1535    // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1536    uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1537                      (32 - (lsb + width)));
1538    Inst.addOperand(MCOperand::CreateImm(Mask));
1539  }
1540
1541  void addImmOperands(MCInst &Inst, unsigned N) const {
1542    assert(N == 1 && "Invalid number of operands!");
1543    addExpr(Inst, getImm());
1544  }
1545
1546  void addFBits16Operands(MCInst &Inst, unsigned N) const {
1547    assert(N == 1 && "Invalid number of operands!");
1548    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1549    Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue()));
1550  }
1551
1552  void addFBits32Operands(MCInst &Inst, unsigned N) const {
1553    assert(N == 1 && "Invalid number of operands!");
1554    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1555    Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue()));
1556  }
1557
1558  void addFPImmOperands(MCInst &Inst, unsigned N) const {
1559    assert(N == 1 && "Invalid number of operands!");
1560    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1561    int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1562    Inst.addOperand(MCOperand::CreateImm(Val));
1563  }
1564
1565  void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1566    assert(N == 1 && "Invalid number of operands!");
1567    // FIXME: We really want to scale the value here, but the LDRD/STRD
1568    // instruction don't encode operands that way yet.
1569    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1570    Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1571  }
1572
1573  void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1574    assert(N == 1 && "Invalid number of operands!");
1575    // The immediate is scaled by four in the encoding and is stored
1576    // in the MCInst as such. Lop off the low two bits here.
1577    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1578    Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1579  }
1580
1581  void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
1582    assert(N == 1 && "Invalid number of operands!");
1583    // The immediate is scaled by four in the encoding and is stored
1584    // in the MCInst as such. Lop off the low two bits here.
1585    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1586    Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4)));
1587  }
1588
1589  void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1590    assert(N == 1 && "Invalid number of operands!");
1591    // The immediate is scaled by four in the encoding and is stored
1592    // in the MCInst as such. Lop off the low two bits here.
1593    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1594    Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1595  }
1596
1597  void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1598    assert(N == 1 && "Invalid number of operands!");
1599    // The constant encodes as the immediate-1, and we store in the instruction
1600    // the bits as encoded, so subtract off one here.
1601    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1602    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1603  }
1604
1605  void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1606    assert(N == 1 && "Invalid number of operands!");
1607    // The constant encodes as the immediate-1, and we store in the instruction
1608    // the bits as encoded, so subtract off one here.
1609    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1610    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1611  }
1612
1613  void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1614    assert(N == 1 && "Invalid number of operands!");
1615    // The constant encodes as the immediate, except for 32, which encodes as
1616    // zero.
1617    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1618    unsigned Imm = CE->getValue();
1619    Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1620  }
1621
1622  void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1623    assert(N == 1 && "Invalid number of operands!");
1624    // An ASR value of 32 encodes as 0, so that's how we want to add it to
1625    // the instruction as well.
1626    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1627    int Val = CE->getValue();
1628    Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1629  }
1630
1631  void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1632    assert(N == 1 && "Invalid number of operands!");
1633    // The operand is actually a t2_so_imm, but we have its bitwise
1634    // negation in the assembly source, so twiddle it here.
1635    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1636    Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1637  }
1638
1639  void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
1640    assert(N == 1 && "Invalid number of operands!");
1641    // The operand is actually a t2_so_imm, but we have its
1642    // negation in the assembly source, so twiddle it here.
1643    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1644    Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1645  }
1646
1647  void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
1648    assert(N == 1 && "Invalid number of operands!");
1649    // The operand is actually an imm0_4095, but we have its
1650    // negation in the assembly source, so twiddle it here.
1651    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1652    Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1653  }
1654
1655  void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
1656    assert(N == 1 && "Invalid number of operands!");
1657    // The operand is actually a so_imm, but we have its bitwise
1658    // negation in the assembly source, so twiddle it here.
1659    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1660    Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1661  }
1662
1663  void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const {
1664    assert(N == 1 && "Invalid number of operands!");
1665    // The operand is actually a so_imm, but we have its
1666    // negation in the assembly source, so twiddle it here.
1667    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1668    Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1669  }
1670
1671  void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1672    assert(N == 1 && "Invalid number of operands!");
1673    Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1674  }
1675
1676  void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1677    assert(N == 1 && "Invalid number of operands!");
1678    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1679  }
1680
1681  void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
1682    assert(N == 1 && "Invalid number of operands!");
1683    int32_t Imm = Memory.OffsetImm->getValue();
1684    // FIXME: Handle #-0
1685    if (Imm == INT32_MIN) Imm = 0;
1686    Inst.addOperand(MCOperand::CreateImm(Imm));
1687  }
1688
1689  void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
1690    assert(N == 1 && "Invalid number of operands!");
1691    assert(isImm() && "Not an immediate!");
1692
1693    // If we have an immediate that's not a constant, treat it as a label
1694    // reference needing a fixup.
1695    if (!isa<MCConstantExpr>(getImm())) {
1696      Inst.addOperand(MCOperand::CreateExpr(getImm()));
1697      return;
1698    }
1699
1700    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1701    int Val = CE->getValue();
1702    Inst.addOperand(MCOperand::CreateImm(Val));
1703  }
1704
1705  void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
1706    assert(N == 2 && "Invalid number of operands!");
1707    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1708    Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
1709  }
1710
1711  void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
1712    assert(N == 3 && "Invalid number of operands!");
1713    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1714    if (!Memory.OffsetRegNum) {
1715      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1716      // Special case for #-0
1717      if (Val == INT32_MIN) Val = 0;
1718      if (Val < 0) Val = -Val;
1719      Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1720    } else {
1721      // For register offset, we encode the shift type and negation flag
1722      // here.
1723      Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1724                              Memory.ShiftImm, Memory.ShiftType);
1725    }
1726    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1727    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1728    Inst.addOperand(MCOperand::CreateImm(Val));
1729  }
1730
1731  void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
1732    assert(N == 2 && "Invalid number of operands!");
1733    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1734    assert(CE && "non-constant AM2OffsetImm operand!");
1735    int32_t Val = CE->getValue();
1736    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1737    // Special case for #-0
1738    if (Val == INT32_MIN) Val = 0;
1739    if (Val < 0) Val = -Val;
1740    Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1741    Inst.addOperand(MCOperand::CreateReg(0));
1742    Inst.addOperand(MCOperand::CreateImm(Val));
1743  }
1744
1745  void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
1746    assert(N == 3 && "Invalid number of operands!");
1747    // If we have an immediate that's not a constant, treat it as a label
1748    // reference needing a fixup. If it is a constant, it's something else
1749    // and we reject it.
1750    if (isImm()) {
1751      Inst.addOperand(MCOperand::CreateExpr(getImm()));
1752      Inst.addOperand(MCOperand::CreateReg(0));
1753      Inst.addOperand(MCOperand::CreateImm(0));
1754      return;
1755    }
1756
1757    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1758    if (!Memory.OffsetRegNum) {
1759      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1760      // Special case for #-0
1761      if (Val == INT32_MIN) Val = 0;
1762      if (Val < 0) Val = -Val;
1763      Val = ARM_AM::getAM3Opc(AddSub, Val);
1764    } else {
1765      // For register offset, we encode the shift type and negation flag
1766      // here.
1767      Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
1768    }
1769    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1770    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1771    Inst.addOperand(MCOperand::CreateImm(Val));
1772  }
1773
1774  void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
1775    assert(N == 2 && "Invalid number of operands!");
1776    if (Kind == k_PostIndexRegister) {
1777      int32_t Val =
1778        ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
1779      Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1780      Inst.addOperand(MCOperand::CreateImm(Val));
1781      return;
1782    }
1783
1784    // Constant offset.
1785    const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
1786    int32_t Val = CE->getValue();
1787    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1788    // Special case for #-0
1789    if (Val == INT32_MIN) Val = 0;
1790    if (Val < 0) Val = -Val;
1791    Val = ARM_AM::getAM3Opc(AddSub, Val);
1792    Inst.addOperand(MCOperand::CreateReg(0));
1793    Inst.addOperand(MCOperand::CreateImm(Val));
1794  }
1795
1796  void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
1797    assert(N == 2 && "Invalid number of operands!");
1798    // If we have an immediate that's not a constant, treat it as a label
1799    // reference needing a fixup. If it is a constant, it's something else
1800    // and we reject it.
1801    if (isImm()) {
1802      Inst.addOperand(MCOperand::CreateExpr(getImm()));
1803      Inst.addOperand(MCOperand::CreateImm(0));
1804      return;
1805    }
1806
1807    // The lower two bits are always zero and as such are not encoded.
1808    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1809    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1810    // Special case for #-0
1811    if (Val == INT32_MIN) Val = 0;
1812    if (Val < 0) Val = -Val;
1813    Val = ARM_AM::getAM5Opc(AddSub, Val);
1814    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1815    Inst.addOperand(MCOperand::CreateImm(Val));
1816  }
1817
1818  void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
1819    assert(N == 2 && "Invalid number of operands!");
1820    // If we have an immediate that's not a constant, treat it as a label
1821    // reference needing a fixup. If it is a constant, it's something else
1822    // and we reject it.
1823    if (isImm()) {
1824      Inst.addOperand(MCOperand::CreateExpr(getImm()));
1825      Inst.addOperand(MCOperand::CreateImm(0));
1826      return;
1827    }
1828
1829    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1830    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1831    Inst.addOperand(MCOperand::CreateImm(Val));
1832  }
1833
1834  void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
1835    assert(N == 2 && "Invalid number of operands!");
1836    // The lower two bits are always zero and as such are not encoded.
1837    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1838    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1839    Inst.addOperand(MCOperand::CreateImm(Val));
1840  }
1841
1842  void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1843    assert(N == 2 && "Invalid number of operands!");
1844    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1845    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1846    Inst.addOperand(MCOperand::CreateImm(Val));
1847  }
1848
1849  void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1850    addMemImm8OffsetOperands(Inst, N);
1851  }
1852
1853  void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1854    addMemImm8OffsetOperands(Inst, N);
1855  }
1856
1857  void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1858    assert(N == 2 && "Invalid number of operands!");
1859    // If this is an immediate, it's a label reference.
1860    if (isImm()) {
1861      addExpr(Inst, getImm());
1862      Inst.addOperand(MCOperand::CreateImm(0));
1863      return;
1864    }
1865
1866    // Otherwise, it's a normal memory reg+offset.
1867    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1868    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1869    Inst.addOperand(MCOperand::CreateImm(Val));
1870  }
1871
1872  void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1873    assert(N == 2 && "Invalid number of operands!");
1874    // If this is an immediate, it's a label reference.
1875    if (isImm()) {
1876      addExpr(Inst, getImm());
1877      Inst.addOperand(MCOperand::CreateImm(0));
1878      return;
1879    }
1880
1881    // Otherwise, it's a normal memory reg+offset.
1882    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1883    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1884    Inst.addOperand(MCOperand::CreateImm(Val));
1885  }
1886
1887  void addMemTBBOperands(MCInst &Inst, unsigned N) const {
1888    assert(N == 2 && "Invalid number of operands!");
1889    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1890    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1891  }
1892
1893  void addMemTBHOperands(MCInst &Inst, unsigned N) const {
1894    assert(N == 2 && "Invalid number of operands!");
1895    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1896    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1897  }
1898
1899  void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1900    assert(N == 3 && "Invalid number of operands!");
1901    unsigned Val =
1902      ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1903                        Memory.ShiftImm, Memory.ShiftType);
1904    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1905    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1906    Inst.addOperand(MCOperand::CreateImm(Val));
1907  }
1908
1909  void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1910    assert(N == 3 && "Invalid number of operands!");
1911    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1912    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1913    Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
1914  }
1915
1916  void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
1917    assert(N == 2 && "Invalid number of operands!");
1918    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1919    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1920  }
1921
1922  void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
1923    assert(N == 2 && "Invalid number of operands!");
1924    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
1925    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1926    Inst.addOperand(MCOperand::CreateImm(Val));
1927  }
1928
1929  void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
1930    assert(N == 2 && "Invalid number of operands!");
1931    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
1932    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1933    Inst.addOperand(MCOperand::CreateImm(Val));
1934  }
1935
1936  void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
1937    assert(N == 2 && "Invalid number of operands!");
1938    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
1939    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1940    Inst.addOperand(MCOperand::CreateImm(Val));
1941  }
1942
1943  void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
1944    assert(N == 2 && "Invalid number of operands!");
1945    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
1946    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1947    Inst.addOperand(MCOperand::CreateImm(Val));
1948  }
1949
1950  void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
1951    assert(N == 1 && "Invalid number of operands!");
1952    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1953    assert(CE && "non-constant post-idx-imm8 operand!");
1954    int Imm = CE->getValue();
1955    bool isAdd = Imm >= 0;
1956    if (Imm == INT32_MIN) Imm = 0;
1957    Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
1958    Inst.addOperand(MCOperand::CreateImm(Imm));
1959  }
1960
1961  void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
1962    assert(N == 1 && "Invalid number of operands!");
1963    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1964    assert(CE && "non-constant post-idx-imm8s4 operand!");
1965    int Imm = CE->getValue();
1966    bool isAdd = Imm >= 0;
1967    if (Imm == INT32_MIN) Imm = 0;
1968    // Immediate is scaled by 4.
1969    Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
1970    Inst.addOperand(MCOperand::CreateImm(Imm));
1971  }
1972
1973  void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
1974    assert(N == 2 && "Invalid number of operands!");
1975    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1976    Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
1977  }
1978
1979  void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
1980    assert(N == 2 && "Invalid number of operands!");
1981    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1982    // The sign, shift type, and shift amount are encoded in a single operand
1983    // using the AM2 encoding helpers.
1984    ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
1985    unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
1986                                     PostIdxReg.ShiftTy);
1987    Inst.addOperand(MCOperand::CreateImm(Imm));
1988  }
1989
1990  void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
1991    assert(N == 1 && "Invalid number of operands!");
1992    Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
1993  }
1994
1995  void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
1996    assert(N == 1 && "Invalid number of operands!");
1997    Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
1998  }
1999
2000  void addVecListOperands(MCInst &Inst, unsigned N) const {
2001    assert(N == 1 && "Invalid number of operands!");
2002    Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2003  }
2004
2005  void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
2006    assert(N == 2 && "Invalid number of operands!");
2007    Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2008    Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex));
2009  }
2010
2011  void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
2012    assert(N == 1 && "Invalid number of operands!");
2013    Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2014  }
2015
2016  void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
2017    assert(N == 1 && "Invalid number of operands!");
2018    Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2019  }
2020
2021  void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
2022    assert(N == 1 && "Invalid number of operands!");
2023    Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2024  }
2025
2026  void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
2027    assert(N == 1 && "Invalid number of operands!");
2028    // The immediate encodes the type of constant as well as the value.
2029    // Mask in that this is an i8 splat.
2030    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2031    Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
2032  }
2033
2034  void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
2035    assert(N == 1 && "Invalid number of operands!");
2036    // The immediate encodes the type of constant as well as the value.
2037    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2038    unsigned Value = CE->getValue();
2039    if (Value >= 256)
2040      Value = (Value >> 8) | 0xa00;
2041    else
2042      Value |= 0x800;
2043    Inst.addOperand(MCOperand::CreateImm(Value));
2044  }
2045
2046  void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
2047    assert(N == 1 && "Invalid number of operands!");
2048    // The immediate encodes the type of constant as well as the value.
2049    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2050    unsigned Value = CE->getValue();
2051    if (Value >= 256 && Value <= 0xff00)
2052      Value = (Value >> 8) | 0x200;
2053    else if (Value > 0xffff && Value <= 0xff0000)
2054      Value = (Value >> 16) | 0x400;
2055    else if (Value > 0xffffff)
2056      Value = (Value >> 24) | 0x600;
2057    Inst.addOperand(MCOperand::CreateImm(Value));
2058  }
2059
2060  void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2061    assert(N == 1 && "Invalid number of operands!");
2062    // The immediate encodes the type of constant as well as the value.
2063    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2064    unsigned Value = CE->getValue();
2065    if (Value >= 256 && Value <= 0xffff)
2066      Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2067    else if (Value > 0xffff && Value <= 0xffffff)
2068      Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2069    else if (Value > 0xffffff)
2070      Value = (Value >> 24) | 0x600;
2071    Inst.addOperand(MCOperand::CreateImm(Value));
2072  }
2073
2074  void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2075    assert(N == 1 && "Invalid number of operands!");
2076    // The immediate encodes the type of constant as well as the value.
2077    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2078    unsigned Value = ~CE->getValue();
2079    if (Value >= 256 && Value <= 0xffff)
2080      Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2081    else if (Value > 0xffff && Value <= 0xffffff)
2082      Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2083    else if (Value > 0xffffff)
2084      Value = (Value >> 24) | 0x600;
2085    Inst.addOperand(MCOperand::CreateImm(Value));
2086  }
2087
2088  void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2089    assert(N == 1 && "Invalid number of operands!");
2090    // The immediate encodes the type of constant as well as the value.
2091    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2092    uint64_t Value = CE->getValue();
2093    unsigned Imm = 0;
2094    for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
2095      Imm |= (Value & 1) << i;
2096    }
2097    Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
2098  }
2099
2100  virtual void print(raw_ostream &OS) const;
2101
2102  static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
2103    ARMOperand *Op = new ARMOperand(k_ITCondMask);
2104    Op->ITMask.Mask = Mask;
2105    Op->StartLoc = S;
2106    Op->EndLoc = S;
2107    return Op;
2108  }
2109
2110  static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
2111    ARMOperand *Op = new ARMOperand(k_CondCode);
2112    Op->CC.Val = CC;
2113    Op->StartLoc = S;
2114    Op->EndLoc = S;
2115    return Op;
2116  }
2117
2118  static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
2119    ARMOperand *Op = new ARMOperand(k_CoprocNum);
2120    Op->Cop.Val = CopVal;
2121    Op->StartLoc = S;
2122    Op->EndLoc = S;
2123    return Op;
2124  }
2125
2126  static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
2127    ARMOperand *Op = new ARMOperand(k_CoprocReg);
2128    Op->Cop.Val = CopVal;
2129    Op->StartLoc = S;
2130    Op->EndLoc = S;
2131    return Op;
2132  }
2133
2134  static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) {
2135    ARMOperand *Op = new ARMOperand(k_CoprocOption);
2136    Op->Cop.Val = Val;
2137    Op->StartLoc = S;
2138    Op->EndLoc = E;
2139    return Op;
2140  }
2141
2142  static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
2143    ARMOperand *Op = new ARMOperand(k_CCOut);
2144    Op->Reg.RegNum = RegNum;
2145    Op->StartLoc = S;
2146    Op->EndLoc = S;
2147    return Op;
2148  }
2149
2150  static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
2151    ARMOperand *Op = new ARMOperand(k_Token);
2152    Op->Tok.Data = Str.data();
2153    Op->Tok.Length = Str.size();
2154    Op->StartLoc = S;
2155    Op->EndLoc = S;
2156    return Op;
2157  }
2158
2159  static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
2160    ARMOperand *Op = new ARMOperand(k_Register);
2161    Op->Reg.RegNum = RegNum;
2162    Op->StartLoc = S;
2163    Op->EndLoc = E;
2164    return Op;
2165  }
2166
2167  static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
2168                                           unsigned SrcReg,
2169                                           unsigned ShiftReg,
2170                                           unsigned ShiftImm,
2171                                           SMLoc S, SMLoc E) {
2172    ARMOperand *Op = new ARMOperand(k_ShiftedRegister);
2173    Op->RegShiftedReg.ShiftTy = ShTy;
2174    Op->RegShiftedReg.SrcReg = SrcReg;
2175    Op->RegShiftedReg.ShiftReg = ShiftReg;
2176    Op->RegShiftedReg.ShiftImm = ShiftImm;
2177    Op->StartLoc = S;
2178    Op->EndLoc = E;
2179    return Op;
2180  }
2181
2182  static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
2183                                            unsigned SrcReg,
2184                                            unsigned ShiftImm,
2185                                            SMLoc S, SMLoc E) {
2186    ARMOperand *Op = new ARMOperand(k_ShiftedImmediate);
2187    Op->RegShiftedImm.ShiftTy = ShTy;
2188    Op->RegShiftedImm.SrcReg = SrcReg;
2189    Op->RegShiftedImm.ShiftImm = ShiftImm;
2190    Op->StartLoc = S;
2191    Op->EndLoc = E;
2192    return Op;
2193  }
2194
2195  static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
2196                                   SMLoc S, SMLoc E) {
2197    ARMOperand *Op = new ARMOperand(k_ShifterImmediate);
2198    Op->ShifterImm.isASR = isASR;
2199    Op->ShifterImm.Imm = Imm;
2200    Op->StartLoc = S;
2201    Op->EndLoc = E;
2202    return Op;
2203  }
2204
2205  static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
2206    ARMOperand *Op = new ARMOperand(k_RotateImmediate);
2207    Op->RotImm.Imm = Imm;
2208    Op->StartLoc = S;
2209    Op->EndLoc = E;
2210    return Op;
2211  }
2212
2213  static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
2214                                    SMLoc S, SMLoc E) {
2215    ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor);
2216    Op->Bitfield.LSB = LSB;
2217    Op->Bitfield.Width = Width;
2218    Op->StartLoc = S;
2219    Op->EndLoc = E;
2220    return Op;
2221  }
2222
2223  static ARMOperand *
2224  CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
2225                SMLoc StartLoc, SMLoc EndLoc) {
2226    KindTy Kind = k_RegisterList;
2227
2228    if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().first))
2229      Kind = k_DPRRegisterList;
2230    else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
2231             contains(Regs.front().first))
2232      Kind = k_SPRRegisterList;
2233
2234    ARMOperand *Op = new ARMOperand(Kind);
2235    for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
2236           I = Regs.begin(), E = Regs.end(); I != E; ++I)
2237      Op->Registers.push_back(I->first);
2238    array_pod_sort(Op->Registers.begin(), Op->Registers.end());
2239    Op->StartLoc = StartLoc;
2240    Op->EndLoc = EndLoc;
2241    return Op;
2242  }
2243
2244  static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count,
2245                                      bool isDoubleSpaced, SMLoc S, SMLoc E) {
2246    ARMOperand *Op = new ARMOperand(k_VectorList);
2247    Op->VectorList.RegNum = RegNum;
2248    Op->VectorList.Count = Count;
2249    Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2250    Op->StartLoc = S;
2251    Op->EndLoc = E;
2252    return Op;
2253  }
2254
2255  static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count,
2256                                              bool isDoubleSpaced,
2257                                              SMLoc S, SMLoc E) {
2258    ARMOperand *Op = new ARMOperand(k_VectorListAllLanes);
2259    Op->VectorList.RegNum = RegNum;
2260    Op->VectorList.Count = Count;
2261    Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2262    Op->StartLoc = S;
2263    Op->EndLoc = E;
2264    return Op;
2265  }
2266
2267  static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count,
2268                                             unsigned Index,
2269                                             bool isDoubleSpaced,
2270                                             SMLoc S, SMLoc E) {
2271    ARMOperand *Op = new ARMOperand(k_VectorListIndexed);
2272    Op->VectorList.RegNum = RegNum;
2273    Op->VectorList.Count = Count;
2274    Op->VectorList.LaneIndex = Index;
2275    Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2276    Op->StartLoc = S;
2277    Op->EndLoc = E;
2278    return Op;
2279  }
2280
2281  static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E,
2282                                       MCContext &Ctx) {
2283    ARMOperand *Op = new ARMOperand(k_VectorIndex);
2284    Op->VectorIndex.Val = Idx;
2285    Op->StartLoc = S;
2286    Op->EndLoc = E;
2287    return Op;
2288  }
2289
2290  static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
2291    ARMOperand *Op = new ARMOperand(k_Immediate);
2292    Op->Imm.Val = Val;
2293    Op->StartLoc = S;
2294    Op->EndLoc = E;
2295    return Op;
2296  }
2297
2298  static ARMOperand *CreateMem(unsigned BaseRegNum,
2299                               const MCConstantExpr *OffsetImm,
2300                               unsigned OffsetRegNum,
2301                               ARM_AM::ShiftOpc ShiftType,
2302                               unsigned ShiftImm,
2303                               unsigned Alignment,
2304                               bool isNegative,
2305                               SMLoc S, SMLoc E) {
2306    ARMOperand *Op = new ARMOperand(k_Memory);
2307    Op->Memory.BaseRegNum = BaseRegNum;
2308    Op->Memory.OffsetImm = OffsetImm;
2309    Op->Memory.OffsetRegNum = OffsetRegNum;
2310    Op->Memory.ShiftType = ShiftType;
2311    Op->Memory.ShiftImm = ShiftImm;
2312    Op->Memory.Alignment = Alignment;
2313    Op->Memory.isNegative = isNegative;
2314    Op->StartLoc = S;
2315    Op->EndLoc = E;
2316    return Op;
2317  }
2318
2319  static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
2320                                      ARM_AM::ShiftOpc ShiftTy,
2321                                      unsigned ShiftImm,
2322                                      SMLoc S, SMLoc E) {
2323    ARMOperand *Op = new ARMOperand(k_PostIndexRegister);
2324    Op->PostIdxReg.RegNum = RegNum;
2325    Op->PostIdxReg.isAdd = isAdd;
2326    Op->PostIdxReg.ShiftTy = ShiftTy;
2327    Op->PostIdxReg.ShiftImm = ShiftImm;
2328    Op->StartLoc = S;
2329    Op->EndLoc = E;
2330    return Op;
2331  }
2332
2333  static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
2334    ARMOperand *Op = new ARMOperand(k_MemBarrierOpt);
2335    Op->MBOpt.Val = Opt;
2336    Op->StartLoc = S;
2337    Op->EndLoc = S;
2338    return Op;
2339  }
2340
2341  static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
2342    ARMOperand *Op = new ARMOperand(k_ProcIFlags);
2343    Op->IFlags.Val = IFlags;
2344    Op->StartLoc = S;
2345    Op->EndLoc = S;
2346    return Op;
2347  }
2348
2349  static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
2350    ARMOperand *Op = new ARMOperand(k_MSRMask);
2351    Op->MMask.Val = MMask;
2352    Op->StartLoc = S;
2353    Op->EndLoc = S;
2354    return Op;
2355  }
2356};
2357
2358} // end anonymous namespace.
2359
2360void ARMOperand::print(raw_ostream &OS) const {
2361  switch (Kind) {
2362  case k_CondCode:
2363    OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
2364    break;
2365  case k_CCOut:
2366    OS << "<ccout " << getReg() << ">";
2367    break;
2368  case k_ITCondMask: {
2369    static const char *const MaskStr[] = {
2370      "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
2371      "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
2372    };
2373    assert((ITMask.Mask & 0xf) == ITMask.Mask);
2374    OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
2375    break;
2376  }
2377  case k_CoprocNum:
2378    OS << "<coprocessor number: " << getCoproc() << ">";
2379    break;
2380  case k_CoprocReg:
2381    OS << "<coprocessor register: " << getCoproc() << ">";
2382    break;
2383  case k_CoprocOption:
2384    OS << "<coprocessor option: " << CoprocOption.Val << ">";
2385    break;
2386  case k_MSRMask:
2387    OS << "<mask: " << getMSRMask() << ">";
2388    break;
2389  case k_Immediate:
2390    getImm()->print(OS);
2391    break;
2392  case k_MemBarrierOpt:
2393    OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
2394    break;
2395  case k_Memory:
2396    OS << "<memory "
2397       << " base:" << Memory.BaseRegNum;
2398    OS << ">";
2399    break;
2400  case k_PostIndexRegister:
2401    OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
2402       << PostIdxReg.RegNum;
2403    if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
2404      OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
2405         << PostIdxReg.ShiftImm;
2406    OS << ">";
2407    break;
2408  case k_ProcIFlags: {
2409    OS << "<ARM_PROC::";
2410    unsigned IFlags = getProcIFlags();
2411    for (int i=2; i >= 0; --i)
2412      if (IFlags & (1 << i))
2413        OS << ARM_PROC::IFlagsToString(1 << i);
2414    OS << ">";
2415    break;
2416  }
2417  case k_Register:
2418    OS << "<register " << getReg() << ">";
2419    break;
2420  case k_ShifterImmediate:
2421    OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
2422       << " #" << ShifterImm.Imm << ">";
2423    break;
2424  case k_ShiftedRegister:
2425    OS << "<so_reg_reg "
2426       << RegShiftedReg.SrcReg << " "
2427       << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
2428       << " " << RegShiftedReg.ShiftReg << ">";
2429    break;
2430  case k_ShiftedImmediate:
2431    OS << "<so_reg_imm "
2432       << RegShiftedImm.SrcReg << " "
2433       << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
2434       << " #" << RegShiftedImm.ShiftImm << ">";
2435    break;
2436  case k_RotateImmediate:
2437    OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
2438    break;
2439  case k_BitfieldDescriptor:
2440    OS << "<bitfield " << "lsb: " << Bitfield.LSB
2441       << ", width: " << Bitfield.Width << ">";
2442    break;
2443  case k_RegisterList:
2444  case k_DPRRegisterList:
2445  case k_SPRRegisterList: {
2446    OS << "<register_list ";
2447
2448    const SmallVectorImpl<unsigned> &RegList = getRegList();
2449    for (SmallVectorImpl<unsigned>::const_iterator
2450           I = RegList.begin(), E = RegList.end(); I != E; ) {
2451      OS << *I;
2452      if (++I < E) OS << ", ";
2453    }
2454
2455    OS << ">";
2456    break;
2457  }
2458  case k_VectorList:
2459    OS << "<vector_list " << VectorList.Count << " * "
2460       << VectorList.RegNum << ">";
2461    break;
2462  case k_VectorListAllLanes:
2463    OS << "<vector_list(all lanes) " << VectorList.Count << " * "
2464       << VectorList.RegNum << ">";
2465    break;
2466  case k_VectorListIndexed:
2467    OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
2468       << VectorList.Count << " * " << VectorList.RegNum << ">";
2469    break;
2470  case k_Token:
2471    OS << "'" << getToken() << "'";
2472    break;
2473  case k_VectorIndex:
2474    OS << "<vectorindex " << getVectorIndex() << ">";
2475    break;
2476  }
2477}
2478
2479/// @name Auto-generated Match Functions
2480/// {
2481
2482static unsigned MatchRegisterName(StringRef Name);
2483
2484/// }
2485
2486bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2487                                 SMLoc &StartLoc, SMLoc &EndLoc) {
2488  StartLoc = Parser.getTok().getLoc();
2489  EndLoc = Parser.getTok().getEndLoc();
2490  RegNo = tryParseRegister();
2491
2492  return (RegNo == (unsigned)-1);
2493}
2494
2495/// Try to parse a register name.  The token must be an Identifier when called,
2496/// and if it is a register name the token is eaten and the register number is
2497/// returned.  Otherwise return -1.
2498///
2499int ARMAsmParser::tryParseRegister() {
2500  const AsmToken &Tok = Parser.getTok();
2501  if (Tok.isNot(AsmToken::Identifier)) return -1;
2502
2503  std::string lowerCase = Tok.getString().lower();
2504  unsigned RegNum = MatchRegisterName(lowerCase);
2505  if (!RegNum) {
2506    RegNum = StringSwitch<unsigned>(lowerCase)
2507      .Case("r13", ARM::SP)
2508      .Case("r14", ARM::LR)
2509      .Case("r15", ARM::PC)
2510      .Case("ip", ARM::R12)
2511      // Additional register name aliases for 'gas' compatibility.
2512      .Case("a1", ARM::R0)
2513      .Case("a2", ARM::R1)
2514      .Case("a3", ARM::R2)
2515      .Case("a4", ARM::R3)
2516      .Case("v1", ARM::R4)
2517      .Case("v2", ARM::R5)
2518      .Case("v3", ARM::R6)
2519      .Case("v4", ARM::R7)
2520      .Case("v5", ARM::R8)
2521      .Case("v6", ARM::R9)
2522      .Case("v7", ARM::R10)
2523      .Case("v8", ARM::R11)
2524      .Case("sb", ARM::R9)
2525      .Case("sl", ARM::R10)
2526      .Case("fp", ARM::R11)
2527      .Default(0);
2528  }
2529  if (!RegNum) {
2530    // Check for aliases registered via .req. Canonicalize to lower case.
2531    // That's more consistent since register names are case insensitive, and
2532    // it's how the original entry was passed in from MC/MCParser/AsmParser.
2533    StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
2534    // If no match, return failure.
2535    if (Entry == RegisterReqs.end())
2536      return -1;
2537    Parser.Lex(); // Eat identifier token.
2538    return Entry->getValue();
2539  }
2540
2541  Parser.Lex(); // Eat identifier token.
2542
2543  return RegNum;
2544}
2545
2546// Try to parse a shifter  (e.g., "lsl <amt>"). On success, return 0.
2547// If a recoverable error occurs, return 1. If an irrecoverable error
2548// occurs, return -1. An irrecoverable error is one where tokens have been
2549// consumed in the process of trying to parse the shifter (i.e., when it is
2550// indeed a shifter operand, but malformed).
2551int ARMAsmParser::tryParseShiftRegister(
2552                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2553  SMLoc S = Parser.getTok().getLoc();
2554  const AsmToken &Tok = Parser.getTok();
2555  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2556
2557  std::string lowerCase = Tok.getString().lower();
2558  ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
2559      .Case("asl", ARM_AM::lsl)
2560      .Case("lsl", ARM_AM::lsl)
2561      .Case("lsr", ARM_AM::lsr)
2562      .Case("asr", ARM_AM::asr)
2563      .Case("ror", ARM_AM::ror)
2564      .Case("rrx", ARM_AM::rrx)
2565      .Default(ARM_AM::no_shift);
2566
2567  if (ShiftTy == ARM_AM::no_shift)
2568    return 1;
2569
2570  Parser.Lex(); // Eat the operator.
2571
2572  // The source register for the shift has already been added to the
2573  // operand list, so we need to pop it off and combine it into the shifted
2574  // register operand instead.
2575  OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
2576  if (!PrevOp->isReg())
2577    return Error(PrevOp->getStartLoc(), "shift must be of a register");
2578  int SrcReg = PrevOp->getReg();
2579
2580  SMLoc EndLoc;
2581  int64_t Imm = 0;
2582  int ShiftReg = 0;
2583  if (ShiftTy == ARM_AM::rrx) {
2584    // RRX Doesn't have an explicit shift amount. The encoder expects
2585    // the shift register to be the same as the source register. Seems odd,
2586    // but OK.
2587    ShiftReg = SrcReg;
2588  } else {
2589    // Figure out if this is shifted by a constant or a register (for non-RRX).
2590    if (Parser.getTok().is(AsmToken::Hash) ||
2591        Parser.getTok().is(AsmToken::Dollar)) {
2592      Parser.Lex(); // Eat hash.
2593      SMLoc ImmLoc = Parser.getTok().getLoc();
2594      const MCExpr *ShiftExpr = 0;
2595      if (getParser().parseExpression(ShiftExpr, EndLoc)) {
2596        Error(ImmLoc, "invalid immediate shift value");
2597        return -1;
2598      }
2599      // The expression must be evaluatable as an immediate.
2600      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
2601      if (!CE) {
2602        Error(ImmLoc, "invalid immediate shift value");
2603        return -1;
2604      }
2605      // Range check the immediate.
2606      // lsl, ror: 0 <= imm <= 31
2607      // lsr, asr: 0 <= imm <= 32
2608      Imm = CE->getValue();
2609      if (Imm < 0 ||
2610          ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
2611          ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
2612        Error(ImmLoc, "immediate shift value out of range");
2613        return -1;
2614      }
2615      // shift by zero is a nop. Always send it through as lsl.
2616      // ('as' compatibility)
2617      if (Imm == 0)
2618        ShiftTy = ARM_AM::lsl;
2619    } else if (Parser.getTok().is(AsmToken::Identifier)) {
2620      SMLoc L = Parser.getTok().getLoc();
2621      EndLoc = Parser.getTok().getEndLoc();
2622      ShiftReg = tryParseRegister();
2623      if (ShiftReg == -1) {
2624        Error (L, "expected immediate or register in shift operand");
2625        return -1;
2626      }
2627    } else {
2628      Error (Parser.getTok().getLoc(),
2629                    "expected immediate or register in shift operand");
2630      return -1;
2631    }
2632  }
2633
2634  if (ShiftReg && ShiftTy != ARM_AM::rrx)
2635    Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
2636                                                         ShiftReg, Imm,
2637                                                         S, EndLoc));
2638  else
2639    Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
2640                                                          S, EndLoc));
2641
2642  return 0;
2643}
2644
2645
2646/// Try to parse a register name.  The token must be an Identifier when called.
2647/// If it's a register, an AsmOperand is created. Another AsmOperand is created
2648/// if there is a "writeback". 'true' if it's not a register.
2649///
2650/// TODO this is likely to change to allow different register types and or to
2651/// parse for a specific register type.
2652bool ARMAsmParser::
2653tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2654  const AsmToken &RegTok = Parser.getTok();
2655  int RegNo = tryParseRegister();
2656  if (RegNo == -1)
2657    return true;
2658
2659  Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(),
2660                                           RegTok.getEndLoc()));
2661
2662  const AsmToken &ExclaimTok = Parser.getTok();
2663  if (ExclaimTok.is(AsmToken::Exclaim)) {
2664    Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
2665                                               ExclaimTok.getLoc()));
2666    Parser.Lex(); // Eat exclaim token
2667    return false;
2668  }
2669
2670  // Also check for an index operand. This is only legal for vector registers,
2671  // but that'll get caught OK in operand matching, so we don't need to
2672  // explicitly filter everything else out here.
2673  if (Parser.getTok().is(AsmToken::LBrac)) {
2674    SMLoc SIdx = Parser.getTok().getLoc();
2675    Parser.Lex(); // Eat left bracket token.
2676
2677    const MCExpr *ImmVal;
2678    if (getParser().parseExpression(ImmVal))
2679      return true;
2680    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
2681    if (!MCE)
2682      return TokError("immediate value expected for vector index");
2683
2684    if (Parser.getTok().isNot(AsmToken::RBrac))
2685      return Error(Parser.getTok().getLoc(), "']' expected");
2686
2687    SMLoc E = Parser.getTok().getEndLoc();
2688    Parser.Lex(); // Eat right bracket token.
2689
2690    Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
2691                                                     SIdx, E,
2692                                                     getContext()));
2693  }
2694
2695  return false;
2696}
2697
2698/// MatchCoprocessorOperandName - Try to parse an coprocessor related
2699/// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
2700/// "c5", ...
2701static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
2702  // Use the same layout as the tablegen'erated register name matcher. Ugly,
2703  // but efficient.
2704  switch (Name.size()) {
2705  default: return -1;
2706  case 2:
2707    if (Name[0] != CoprocOp)
2708      return -1;
2709    switch (Name[1]) {
2710    default:  return -1;
2711    case '0': return 0;
2712    case '1': return 1;
2713    case '2': return 2;
2714    case '3': return 3;
2715    case '4': return 4;
2716    case '5': return 5;
2717    case '6': return 6;
2718    case '7': return 7;
2719    case '8': return 8;
2720    case '9': return 9;
2721    }
2722  case 3:
2723    if (Name[0] != CoprocOp || Name[1] != '1')
2724      return -1;
2725    switch (Name[2]) {
2726    default:  return -1;
2727    case '0': return 10;
2728    case '1': return 11;
2729    case '2': return 12;
2730    case '3': return 13;
2731    case '4': return 14;
2732    case '5': return 15;
2733    }
2734  }
2735}
2736
2737/// parseITCondCode - Try to parse a condition code for an IT instruction.
2738ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2739parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2740  SMLoc S = Parser.getTok().getLoc();
2741  const AsmToken &Tok = Parser.getTok();
2742  if (!Tok.is(AsmToken::Identifier))
2743    return MatchOperand_NoMatch;
2744  unsigned CC = StringSwitch<unsigned>(Tok.getString().lower())
2745    .Case("eq", ARMCC::EQ)
2746    .Case("ne", ARMCC::NE)
2747    .Case("hs", ARMCC::HS)
2748    .Case("cs", ARMCC::HS)
2749    .Case("lo", ARMCC::LO)
2750    .Case("cc", ARMCC::LO)
2751    .Case("mi", ARMCC::MI)
2752    .Case("pl", ARMCC::PL)
2753    .Case("vs", ARMCC::VS)
2754    .Case("vc", ARMCC::VC)
2755    .Case("hi", ARMCC::HI)
2756    .Case("ls", ARMCC::LS)
2757    .Case("ge", ARMCC::GE)
2758    .Case("lt", ARMCC::LT)
2759    .Case("gt", ARMCC::GT)
2760    .Case("le", ARMCC::LE)
2761    .Case("al", ARMCC::AL)
2762    .Default(~0U);
2763  if (CC == ~0U)
2764    return MatchOperand_NoMatch;
2765  Parser.Lex(); // Eat the token.
2766
2767  Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
2768
2769  return MatchOperand_Success;
2770}
2771
2772/// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
2773/// token must be an Identifier when called, and if it is a coprocessor
2774/// number, the token is eaten and the operand is added to the operand list.
2775ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2776parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2777  SMLoc S = Parser.getTok().getLoc();
2778  const AsmToken &Tok = Parser.getTok();
2779  if (Tok.isNot(AsmToken::Identifier))
2780    return MatchOperand_NoMatch;
2781
2782  int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
2783  if (Num == -1)
2784    return MatchOperand_NoMatch;
2785
2786  Parser.Lex(); // Eat identifier token.
2787  Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
2788  return MatchOperand_Success;
2789}
2790
2791/// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
2792/// token must be an Identifier when called, and if it is a coprocessor
2793/// number, the token is eaten and the operand is added to the operand list.
2794ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2795parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2796  SMLoc S = Parser.getTok().getLoc();
2797  const AsmToken &Tok = Parser.getTok();
2798  if (Tok.isNot(AsmToken::Identifier))
2799    return MatchOperand_NoMatch;
2800
2801  int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
2802  if (Reg == -1)
2803    return MatchOperand_NoMatch;
2804
2805  Parser.Lex(); // Eat identifier token.
2806  Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
2807  return MatchOperand_Success;
2808}
2809
2810/// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
2811/// coproc_option : '{' imm0_255 '}'
2812ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2813parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2814  SMLoc S = Parser.getTok().getLoc();
2815
2816  // If this isn't a '{', this isn't a coprocessor immediate operand.
2817  if (Parser.getTok().isNot(AsmToken::LCurly))
2818    return MatchOperand_NoMatch;
2819  Parser.Lex(); // Eat the '{'
2820
2821  const MCExpr *Expr;
2822  SMLoc Loc = Parser.getTok().getLoc();
2823  if (getParser().parseExpression(Expr)) {
2824    Error(Loc, "illegal expression");
2825    return MatchOperand_ParseFail;
2826  }
2827  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2828  if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
2829    Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
2830    return MatchOperand_ParseFail;
2831  }
2832  int Val = CE->getValue();
2833
2834  // Check for and consume the closing '}'
2835  if (Parser.getTok().isNot(AsmToken::RCurly))
2836    return MatchOperand_ParseFail;
2837  SMLoc E = Parser.getTok().getEndLoc();
2838  Parser.Lex(); // Eat the '}'
2839
2840  Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
2841  return MatchOperand_Success;
2842}
2843
2844// For register list parsing, we need to map from raw GPR register numbering
2845// to the enumeration values. The enumeration values aren't sorted by
2846// register number due to our using "sp", "lr" and "pc" as canonical names.
2847static unsigned getNextRegister(unsigned Reg) {
2848  // If this is a GPR, we need to do it manually, otherwise we can rely
2849  // on the sort ordering of the enumeration since the other reg-classes
2850  // are sane.
2851  if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2852    return Reg + 1;
2853  switch(Reg) {
2854  default: llvm_unreachable("Invalid GPR number!");
2855  case ARM::R0:  return ARM::R1;  case ARM::R1:  return ARM::R2;
2856  case ARM::R2:  return ARM::R3;  case ARM::R3:  return ARM::R4;
2857  case ARM::R4:  return ARM::R5;  case ARM::R5:  return ARM::R6;
2858  case ARM::R6:  return ARM::R7;  case ARM::R7:  return ARM::R8;
2859  case ARM::R8:  return ARM::R9;  case ARM::R9:  return ARM::R10;
2860  case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
2861  case ARM::R12: return ARM::SP;  case ARM::SP:  return ARM::LR;
2862  case ARM::LR:  return ARM::PC;  case ARM::PC:  return ARM::R0;
2863  }
2864}
2865
2866// Return the low-subreg of a given Q register.
2867static unsigned getDRegFromQReg(unsigned QReg) {
2868  switch (QReg) {
2869  default: llvm_unreachable("expected a Q register!");
2870  case ARM::Q0:  return ARM::D0;
2871  case ARM::Q1:  return ARM::D2;
2872  case ARM::Q2:  return ARM::D4;
2873  case ARM::Q3:  return ARM::D6;
2874  case ARM::Q4:  return ARM::D8;
2875  case ARM::Q5:  return ARM::D10;
2876  case ARM::Q6:  return ARM::D12;
2877  case ARM::Q7:  return ARM::D14;
2878  case ARM::Q8:  return ARM::D16;
2879  case ARM::Q9:  return ARM::D18;
2880  case ARM::Q10: return ARM::D20;
2881  case ARM::Q11: return ARM::D22;
2882  case ARM::Q12: return ARM::D24;
2883  case ARM::Q13: return ARM::D26;
2884  case ARM::Q14: return ARM::D28;
2885  case ARM::Q15: return ARM::D30;
2886  }
2887}
2888
2889/// Parse a register list.
2890bool ARMAsmParser::
2891parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2892  assert(Parser.getTok().is(AsmToken::LCurly) &&
2893         "Token is not a Left Curly Brace");
2894  SMLoc S = Parser.getTok().getLoc();
2895  Parser.Lex(); // Eat '{' token.
2896  SMLoc RegLoc = Parser.getTok().getLoc();
2897
2898  // Check the first register in the list to see what register class
2899  // this is a list of.
2900  int Reg = tryParseRegister();
2901  if (Reg == -1)
2902    return Error(RegLoc, "register expected");
2903
2904  // The reglist instructions have at most 16 registers, so reserve
2905  // space for that many.
2906  SmallVector<std::pair<unsigned, SMLoc>, 16> Registers;
2907
2908  // Allow Q regs and just interpret them as the two D sub-registers.
2909  if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2910    Reg = getDRegFromQReg(Reg);
2911    Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2912    ++Reg;
2913  }
2914  const MCRegisterClass *RC;
2915  if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2916    RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
2917  else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
2918    RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
2919  else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
2920    RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
2921  else
2922    return Error(RegLoc, "invalid register in register list");
2923
2924  // Store the register.
2925  Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2926
2927  // This starts immediately after the first register token in the list,
2928  // so we can see either a comma or a minus (range separator) as a legal
2929  // next token.
2930  while (Parser.getTok().is(AsmToken::Comma) ||
2931         Parser.getTok().is(AsmToken::Minus)) {
2932    if (Parser.getTok().is(AsmToken::Minus)) {
2933      Parser.Lex(); // Eat the minus.
2934      SMLoc AfterMinusLoc = Parser.getTok().getLoc();
2935      int EndReg = tryParseRegister();
2936      if (EndReg == -1)
2937        return Error(AfterMinusLoc, "register expected");
2938      // Allow Q regs and just interpret them as the two D sub-registers.
2939      if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
2940        EndReg = getDRegFromQReg(EndReg) + 1;
2941      // If the register is the same as the start reg, there's nothing
2942      // more to do.
2943      if (Reg == EndReg)
2944        continue;
2945      // The register must be in the same register class as the first.
2946      if (!RC->contains(EndReg))
2947        return Error(AfterMinusLoc, "invalid register in register list");
2948      // Ranges must go from low to high.
2949      if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
2950        return Error(AfterMinusLoc, "bad range in register list");
2951
2952      // Add all the registers in the range to the register list.
2953      while (Reg != EndReg) {
2954        Reg = getNextRegister(Reg);
2955        Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2956      }
2957      continue;
2958    }
2959    Parser.Lex(); // Eat the comma.
2960    RegLoc = Parser.getTok().getLoc();
2961    int OldReg = Reg;
2962    const AsmToken RegTok = Parser.getTok();
2963    Reg = tryParseRegister();
2964    if (Reg == -1)
2965      return Error(RegLoc, "register expected");
2966    // Allow Q regs and just interpret them as the two D sub-registers.
2967    bool isQReg = false;
2968    if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2969      Reg = getDRegFromQReg(Reg);
2970      isQReg = true;
2971    }
2972    // The register must be in the same register class as the first.
2973    if (!RC->contains(Reg))
2974      return Error(RegLoc, "invalid register in register list");
2975    // List must be monotonically increasing.
2976    if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
2977      if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2978        Warning(RegLoc, "register list not in ascending order");
2979      else
2980        return Error(RegLoc, "register list not in ascending order");
2981    }
2982    if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
2983      Warning(RegLoc, "duplicated register (" + RegTok.getString() +
2984              ") in register list");
2985      continue;
2986    }
2987    // VFP register lists must also be contiguous.
2988    // It's OK to use the enumeration values directly here rather, as the
2989    // VFP register classes have the enum sorted properly.
2990    if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
2991        Reg != OldReg + 1)
2992      return Error(RegLoc, "non-contiguous register range");
2993    Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2994    if (isQReg)
2995      Registers.push_back(std::pair<unsigned, SMLoc>(++Reg, RegLoc));
2996  }
2997
2998  if (Parser.getTok().isNot(AsmToken::RCurly))
2999    return Error(Parser.getTok().getLoc(), "'}' expected");
3000  SMLoc E = Parser.getTok().getEndLoc();
3001  Parser.Lex(); // Eat '}' token.
3002
3003  // Push the register list operand.
3004  Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
3005
3006  // The ARM system instruction variants for LDM/STM have a '^' token here.
3007  if (Parser.getTok().is(AsmToken::Caret)) {
3008    Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
3009    Parser.Lex(); // Eat '^' token.
3010  }
3011
3012  return false;
3013}
3014
3015// Helper function to parse the lane index for vector lists.
3016ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3017parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
3018  Index = 0; // Always return a defined index value.
3019  if (Parser.getTok().is(AsmToken::LBrac)) {
3020    Parser.Lex(); // Eat the '['.
3021    if (Parser.getTok().is(AsmToken::RBrac)) {
3022      // "Dn[]" is the 'all lanes' syntax.
3023      LaneKind = AllLanes;
3024      EndLoc = Parser.getTok().getEndLoc();
3025      Parser.Lex(); // Eat the ']'.
3026      return MatchOperand_Success;
3027    }
3028
3029    // There's an optional '#' token here. Normally there wouldn't be, but
3030    // inline assemble puts one in, and it's friendly to accept that.
3031    if (Parser.getTok().is(AsmToken::Hash))
3032      Parser.Lex(); // Eat the '#'
3033
3034    const MCExpr *LaneIndex;
3035    SMLoc Loc = Parser.getTok().getLoc();
3036    if (getParser().parseExpression(LaneIndex)) {
3037      Error(Loc, "illegal expression");
3038      return MatchOperand_ParseFail;
3039    }
3040    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
3041    if (!CE) {
3042      Error(Loc, "lane index must be empty or an integer");
3043      return MatchOperand_ParseFail;
3044    }
3045    if (Parser.getTok().isNot(AsmToken::RBrac)) {
3046      Error(Parser.getTok().getLoc(), "']' expected");
3047      return MatchOperand_ParseFail;
3048    }
3049    EndLoc = Parser.getTok().getEndLoc();
3050    Parser.Lex(); // Eat the ']'.
3051    int64_t Val = CE->getValue();
3052
3053    // FIXME: Make this range check context sensitive for .8, .16, .32.
3054    if (Val < 0 || Val > 7) {
3055      Error(Parser.getTok().getLoc(), "lane index out of range");
3056      return MatchOperand_ParseFail;
3057    }
3058    Index = Val;
3059    LaneKind = IndexedLane;
3060    return MatchOperand_Success;
3061  }
3062  LaneKind = NoLanes;
3063  return MatchOperand_Success;
3064}
3065
3066// parse a vector register list
3067ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3068parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3069  VectorLaneTy LaneKind;
3070  unsigned LaneIndex;
3071  SMLoc S = Parser.getTok().getLoc();
3072  // As an extension (to match gas), support a plain D register or Q register
3073  // (without encosing curly braces) as a single or double entry list,
3074  // respectively.
3075  if (Parser.getTok().is(AsmToken::Identifier)) {
3076    SMLoc E = Parser.getTok().getEndLoc();
3077    int Reg = tryParseRegister();
3078    if (Reg == -1)
3079      return MatchOperand_NoMatch;
3080    if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
3081      OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3082      if (Res != MatchOperand_Success)
3083        return Res;
3084      switch (LaneKind) {
3085      case NoLanes:
3086        Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
3087        break;
3088      case AllLanes:
3089        Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
3090                                                                S, E));
3091        break;
3092      case IndexedLane:
3093        Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
3094                                                               LaneIndex,
3095                                                               false, S, E));
3096        break;
3097      }
3098      return MatchOperand_Success;
3099    }
3100    if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3101      Reg = getDRegFromQReg(Reg);
3102      OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3103      if (Res != MatchOperand_Success)
3104        return Res;
3105      switch (LaneKind) {
3106      case NoLanes:
3107        Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3108                                   &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3109        Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
3110        break;
3111      case AllLanes:
3112        Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3113                                   &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3114        Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
3115                                                                S, E));
3116        break;
3117      case IndexedLane:
3118        Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
3119                                                               LaneIndex,
3120                                                               false, S, E));
3121        break;
3122      }
3123      return MatchOperand_Success;
3124    }
3125    Error(S, "vector register expected");
3126    return MatchOperand_ParseFail;
3127  }
3128
3129  if (Parser.getTok().isNot(AsmToken::LCurly))
3130    return MatchOperand_NoMatch;
3131
3132  Parser.Lex(); // Eat '{' token.
3133  SMLoc RegLoc = Parser.getTok().getLoc();
3134
3135  int Reg = tryParseRegister();
3136  if (Reg == -1) {
3137    Error(RegLoc, "register expected");
3138    return MatchOperand_ParseFail;
3139  }
3140  unsigned Count = 1;
3141  int Spacing = 0;
3142  unsigned FirstReg = Reg;
3143  // The list is of D registers, but we also allow Q regs and just interpret
3144  // them as the two D sub-registers.
3145  if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3146    FirstReg = Reg = getDRegFromQReg(Reg);
3147    Spacing = 1; // double-spacing requires explicit D registers, otherwise
3148                 // it's ambiguous with four-register single spaced.
3149    ++Reg;
3150    ++Count;
3151  }
3152
3153  SMLoc E;
3154  if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success)
3155    return MatchOperand_ParseFail;
3156
3157  while (Parser.getTok().is(AsmToken::Comma) ||
3158         Parser.getTok().is(AsmToken::Minus)) {
3159    if (Parser.getTok().is(AsmToken::Minus)) {
3160      if (!Spacing)
3161        Spacing = 1; // Register range implies a single spaced list.
3162      else if (Spacing == 2) {
3163        Error(Parser.getTok().getLoc(),
3164              "sequential registers in double spaced list");
3165        return MatchOperand_ParseFail;
3166      }
3167      Parser.Lex(); // Eat the minus.
3168      SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3169      int EndReg = tryParseRegister();
3170      if (EndReg == -1) {
3171        Error(AfterMinusLoc, "register expected");
3172        return MatchOperand_ParseFail;
3173      }
3174      // Allow Q regs and just interpret them as the two D sub-registers.
3175      if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3176        EndReg = getDRegFromQReg(EndReg) + 1;
3177      // If the register is the same as the start reg, there's nothing
3178      // more to do.
3179      if (Reg == EndReg)
3180        continue;
3181      // The register must be in the same register class as the first.
3182      if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
3183        Error(AfterMinusLoc, "invalid register in register list");
3184        return MatchOperand_ParseFail;
3185      }
3186      // Ranges must go from low to high.
3187      if (Reg > EndReg) {
3188        Error(AfterMinusLoc, "bad range in register list");
3189        return MatchOperand_ParseFail;
3190      }
3191      // Parse the lane specifier if present.
3192      VectorLaneTy NextLaneKind;
3193      unsigned NextLaneIndex;
3194      if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3195          MatchOperand_Success)
3196        return MatchOperand_ParseFail;
3197      if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3198        Error(AfterMinusLoc, "mismatched lane index in register list");
3199        return MatchOperand_ParseFail;
3200      }
3201
3202      // Add all the registers in the range to the register list.
3203      Count += EndReg - Reg;
3204      Reg = EndReg;
3205      continue;
3206    }
3207    Parser.Lex(); // Eat the comma.
3208    RegLoc = Parser.getTok().getLoc();
3209    int OldReg = Reg;
3210    Reg = tryParseRegister();
3211    if (Reg == -1) {
3212      Error(RegLoc, "register expected");
3213      return MatchOperand_ParseFail;
3214    }
3215    // vector register lists must be contiguous.
3216    // It's OK to use the enumeration values directly here rather, as the
3217    // VFP register classes have the enum sorted properly.
3218    //
3219    // The list is of D registers, but we also allow Q regs and just interpret
3220    // them as the two D sub-registers.
3221    if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3222      if (!Spacing)
3223        Spacing = 1; // Register range implies a single spaced list.
3224      else if (Spacing == 2) {
3225        Error(RegLoc,
3226              "invalid register in double-spaced list (must be 'D' register')");
3227        return MatchOperand_ParseFail;
3228      }
3229      Reg = getDRegFromQReg(Reg);
3230      if (Reg != OldReg + 1) {
3231        Error(RegLoc, "non-contiguous register range");
3232        return MatchOperand_ParseFail;
3233      }
3234      ++Reg;
3235      Count += 2;
3236      // Parse the lane specifier if present.
3237      VectorLaneTy NextLaneKind;
3238      unsigned NextLaneIndex;
3239      SMLoc LaneLoc = Parser.getTok().getLoc();
3240      if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3241          MatchOperand_Success)
3242        return MatchOperand_ParseFail;
3243      if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3244        Error(LaneLoc, "mismatched lane index in register list");
3245        return MatchOperand_ParseFail;
3246      }
3247      continue;
3248    }
3249    // Normal D register.
3250    // Figure out the register spacing (single or double) of the list if
3251    // we don't know it already.
3252    if (!Spacing)
3253      Spacing = 1 + (Reg == OldReg + 2);
3254
3255    // Just check that it's contiguous and keep going.
3256    if (Reg != OldReg + Spacing) {
3257      Error(RegLoc, "non-contiguous register range");
3258      return MatchOperand_ParseFail;
3259    }
3260    ++Count;
3261    // Parse the lane specifier if present.
3262    VectorLaneTy NextLaneKind;
3263    unsigned NextLaneIndex;
3264    SMLoc EndLoc = Parser.getTok().getLoc();
3265    if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success)
3266      return MatchOperand_ParseFail;
3267    if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3268      Error(EndLoc, "mismatched lane index in register list");
3269      return MatchOperand_ParseFail;
3270    }
3271  }
3272
3273  if (Parser.getTok().isNot(AsmToken::RCurly)) {
3274    Error(Parser.getTok().getLoc(), "'}' expected");
3275    return MatchOperand_ParseFail;
3276  }
3277  E = Parser.getTok().getEndLoc();
3278  Parser.Lex(); // Eat '}' token.
3279
3280  switch (LaneKind) {
3281  case NoLanes:
3282    // Two-register operands have been converted to the
3283    // composite register classes.
3284    if (Count == 2) {
3285      const MCRegisterClass *RC = (Spacing == 1) ?
3286        &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3287        &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3288      FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3289    }
3290
3291    Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
3292                                                    (Spacing == 2), S, E));
3293    break;
3294  case AllLanes:
3295    // Two-register operands have been converted to the
3296    // composite register classes.
3297    if (Count == 2) {
3298      const MCRegisterClass *RC = (Spacing == 1) ?
3299        &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3300        &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3301      FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3302    }
3303    Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
3304                                                            (Spacing == 2),
3305                                                            S, E));
3306    break;
3307  case IndexedLane:
3308    Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
3309                                                           LaneIndex,
3310                                                           (Spacing == 2),
3311                                                           S, E));
3312    break;
3313  }
3314  return MatchOperand_Success;
3315}
3316
3317/// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
3318ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3319parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3320  SMLoc S = Parser.getTok().getLoc();
3321  const AsmToken &Tok = Parser.getTok();
3322  unsigned Opt;
3323
3324  if (Tok.is(AsmToken::Identifier)) {
3325    StringRef OptStr = Tok.getString();
3326
3327    Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
3328      .Case("sy",    ARM_MB::SY)
3329      .Case("st",    ARM_MB::ST)
3330      .Case("sh",    ARM_MB::ISH)
3331      .Case("ish",   ARM_MB::ISH)
3332      .Case("shst",  ARM_MB::ISHST)
3333      .Case("ishst", ARM_MB::ISHST)
3334      .Case("nsh",   ARM_MB::NSH)
3335      .Case("un",    ARM_MB::NSH)
3336      .Case("nshst", ARM_MB::NSHST)
3337      .Case("unst",  ARM_MB::NSHST)
3338      .Case("osh",   ARM_MB::OSH)
3339      .Case("oshst", ARM_MB::OSHST)
3340      .Default(~0U);
3341
3342    if (Opt == ~0U)
3343      return MatchOperand_NoMatch;
3344
3345    Parser.Lex(); // Eat identifier token.
3346  } else if (Tok.is(AsmToken::Hash) ||
3347             Tok.is(AsmToken::Dollar) ||
3348             Tok.is(AsmToken::Integer)) {
3349    if (Parser.getTok().isNot(AsmToken::Integer))
3350      Parser.Lex(); // Eat the '#'.
3351    SMLoc Loc = Parser.getTok().getLoc();
3352
3353    const MCExpr *MemBarrierID;
3354    if (getParser().parseExpression(MemBarrierID)) {
3355      Error(Loc, "illegal expression");
3356      return MatchOperand_ParseFail;
3357    }
3358
3359    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
3360    if (!CE) {
3361      Error(Loc, "constant expression expected");
3362      return MatchOperand_ParseFail;
3363    }
3364
3365    int Val = CE->getValue();
3366    if (Val & ~0xf) {
3367      Error(Loc, "immediate value out of range");
3368      return MatchOperand_ParseFail;
3369    }
3370
3371    Opt = ARM_MB::RESERVED_0 + Val;
3372  } else
3373    return MatchOperand_ParseFail;
3374
3375  Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
3376  return MatchOperand_Success;
3377}
3378
3379/// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
3380ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3381parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3382  SMLoc S = Parser.getTok().getLoc();
3383  const AsmToken &Tok = Parser.getTok();
3384  if (!Tok.is(AsmToken::Identifier))
3385    return MatchOperand_NoMatch;
3386  StringRef IFlagsStr = Tok.getString();
3387
3388  // An iflags string of "none" is interpreted to mean that none of the AIF
3389  // bits are set.  Not a terribly useful instruction, but a valid encoding.
3390  unsigned IFlags = 0;
3391  if (IFlagsStr != "none") {
3392        for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
3393      unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
3394        .Case("a", ARM_PROC::A)
3395        .Case("i", ARM_PROC::I)
3396        .Case("f", ARM_PROC::F)
3397        .Default(~0U);
3398
3399      // If some specific iflag is already set, it means that some letter is
3400      // present more than once, this is not acceptable.
3401      if (Flag == ~0U || (IFlags & Flag))
3402        return MatchOperand_NoMatch;
3403
3404      IFlags |= Flag;
3405    }
3406  }
3407
3408  Parser.Lex(); // Eat identifier token.
3409  Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
3410  return MatchOperand_Success;
3411}
3412
3413/// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
3414ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3415parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3416  SMLoc S = Parser.getTok().getLoc();
3417  const AsmToken &Tok = Parser.getTok();
3418  if (!Tok.is(AsmToken::Identifier))
3419    return MatchOperand_NoMatch;
3420  StringRef Mask = Tok.getString();
3421
3422  if (isMClass()) {
3423    // See ARMv6-M 10.1.1
3424    std::string Name = Mask.lower();
3425    unsigned FlagsVal = StringSwitch<unsigned>(Name)
3426      // Note: in the documentation:
3427      //  ARM deprecates using MSR APSR without a _<bits> qualifier as an alias
3428      //  for MSR APSR_nzcvq.
3429      // but we do make it an alias here.  This is so to get the "mask encoding"
3430      // bits correct on MSR APSR writes.
3431      //
3432      // FIXME: Note the 0xc00 "mask encoding" bits version of the registers
3433      // should really only be allowed when writing a special register.  Note
3434      // they get dropped in the MRS instruction reading a special register as
3435      // the SYSm field is only 8 bits.
3436      //
3437      // FIXME: the _g and _nzcvqg versions are only allowed if the processor
3438      // includes the DSP extension but that is not checked.
3439      .Case("apsr", 0x800)
3440      .Case("apsr_nzcvq", 0x800)
3441      .Case("apsr_g", 0x400)
3442      .Case("apsr_nzcvqg", 0xc00)
3443      .Case("iapsr", 0x801)
3444      .Case("iapsr_nzcvq", 0x801)
3445      .Case("iapsr_g", 0x401)
3446      .Case("iapsr_nzcvqg", 0xc01)
3447      .Case("eapsr", 0x802)
3448      .Case("eapsr_nzcvq", 0x802)
3449      .Case("eapsr_g", 0x402)
3450      .Case("eapsr_nzcvqg", 0xc02)
3451      .Case("xpsr", 0x803)
3452      .Case("xpsr_nzcvq", 0x803)
3453      .Case("xpsr_g", 0x403)
3454      .Case("xpsr_nzcvqg", 0xc03)
3455      .Case("ipsr", 0x805)
3456      .Case("epsr", 0x806)
3457      .Case("iepsr", 0x807)
3458      .Case("msp", 0x808)
3459      .Case("psp", 0x809)
3460      .Case("primask", 0x810)
3461      .Case("basepri", 0x811)
3462      .Case("basepri_max", 0x812)
3463      .Case("faultmask", 0x813)
3464      .Case("control", 0x814)
3465      .Default(~0U);
3466
3467    if (FlagsVal == ~0U)
3468      return MatchOperand_NoMatch;
3469
3470    if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813)
3471      // basepri, basepri_max and faultmask only valid for V7m.
3472      return MatchOperand_NoMatch;
3473
3474    Parser.Lex(); // Eat identifier token.
3475    Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3476    return MatchOperand_Success;
3477  }
3478
3479  // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
3480  size_t Start = 0, Next = Mask.find('_');
3481  StringRef Flags = "";
3482  std::string SpecReg = Mask.slice(Start, Next).lower();
3483  if (Next != StringRef::npos)
3484    Flags = Mask.slice(Next+1, Mask.size());
3485
3486  // FlagsVal contains the complete mask:
3487  // 3-0: Mask
3488  // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3489  unsigned FlagsVal = 0;
3490
3491  if (SpecReg == "apsr") {
3492    FlagsVal = StringSwitch<unsigned>(Flags)
3493    .Case("nzcvq",  0x8) // same as CPSR_f
3494    .Case("g",      0x4) // same as CPSR_s
3495    .Case("nzcvqg", 0xc) // same as CPSR_fs
3496    .Default(~0U);
3497
3498    if (FlagsVal == ~0U) {
3499      if (!Flags.empty())
3500        return MatchOperand_NoMatch;
3501      else
3502        FlagsVal = 8; // No flag
3503    }
3504  } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
3505    // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
3506    if (Flags == "all" || Flags == "")
3507      Flags = "fc";
3508    for (int i = 0, e = Flags.size(); i != e; ++i) {
3509      unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
3510      .Case("c", 1)
3511      .Case("x", 2)
3512      .Case("s", 4)
3513      .Case("f", 8)
3514      .Default(~0U);
3515
3516      // If some specific flag is already set, it means that some letter is
3517      // present more than once, this is not acceptable.
3518      if (FlagsVal == ~0U || (FlagsVal & Flag))
3519        return MatchOperand_NoMatch;
3520      FlagsVal |= Flag;
3521    }
3522  } else // No match for special register.
3523    return MatchOperand_NoMatch;
3524
3525  // Special register without flags is NOT equivalent to "fc" flags.
3526  // NOTE: This is a divergence from gas' behavior.  Uncommenting the following
3527  // two lines would enable gas compatibility at the expense of breaking
3528  // round-tripping.
3529  //
3530  // if (!FlagsVal)
3531  //  FlagsVal = 0x9;
3532
3533  // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3534  if (SpecReg == "spsr")
3535    FlagsVal |= 16;
3536
3537  Parser.Lex(); // Eat identifier token.
3538  Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3539  return MatchOperand_Success;
3540}
3541
3542ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3543parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
3544            int Low, int High) {
3545  const AsmToken &Tok = Parser.getTok();
3546  if (Tok.isNot(AsmToken::Identifier)) {
3547    Error(Parser.getTok().getLoc(), Op + " operand expected.");
3548    return MatchOperand_ParseFail;
3549  }
3550  StringRef ShiftName = Tok.getString();
3551  std::string LowerOp = Op.lower();
3552  std::string UpperOp = Op.upper();
3553  if (ShiftName != LowerOp && ShiftName != UpperOp) {
3554    Error(Parser.getTok().getLoc(), Op + " operand expected.");
3555    return MatchOperand_ParseFail;
3556  }
3557  Parser.Lex(); // Eat shift type token.
3558
3559  // There must be a '#' and a shift amount.
3560  if (Parser.getTok().isNot(AsmToken::Hash) &&
3561      Parser.getTok().isNot(AsmToken::Dollar)) {
3562    Error(Parser.getTok().getLoc(), "'#' expected");
3563    return MatchOperand_ParseFail;
3564  }
3565  Parser.Lex(); // Eat hash token.
3566
3567  const MCExpr *ShiftAmount;
3568  SMLoc Loc = Parser.getTok().getLoc();
3569  SMLoc EndLoc;
3570  if (getParser().parseExpression(ShiftAmount, EndLoc)) {
3571    Error(Loc, "illegal expression");
3572    return MatchOperand_ParseFail;
3573  }
3574  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3575  if (!CE) {
3576    Error(Loc, "constant expression expected");
3577    return MatchOperand_ParseFail;
3578  }
3579  int Val = CE->getValue();
3580  if (Val < Low || Val > High) {
3581    Error(Loc, "immediate value out of range");
3582    return MatchOperand_ParseFail;
3583  }
3584
3585  Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc));
3586
3587  return MatchOperand_Success;
3588}
3589
3590ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3591parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3592  const AsmToken &Tok = Parser.getTok();
3593  SMLoc S = Tok.getLoc();
3594  if (Tok.isNot(AsmToken::Identifier)) {
3595    Error(S, "'be' or 'le' operand expected");
3596    return MatchOperand_ParseFail;
3597  }
3598  int Val = StringSwitch<int>(Tok.getString())
3599    .Case("be", 1)
3600    .Case("le", 0)
3601    .Default(-1);
3602  Parser.Lex(); // Eat the token.
3603
3604  if (Val == -1) {
3605    Error(S, "'be' or 'le' operand expected");
3606    return MatchOperand_ParseFail;
3607  }
3608  Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
3609                                                                  getContext()),
3610                                           S, Tok.getEndLoc()));
3611  return MatchOperand_Success;
3612}
3613
3614/// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
3615/// instructions. Legal values are:
3616///     lsl #n  'n' in [0,31]
3617///     asr #n  'n' in [1,32]
3618///             n == 32 encoded as n == 0.
3619ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3620parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3621  const AsmToken &Tok = Parser.getTok();
3622  SMLoc S = Tok.getLoc();
3623  if (Tok.isNot(AsmToken::Identifier)) {
3624    Error(S, "shift operator 'asr' or 'lsl' expected");
3625    return MatchOperand_ParseFail;
3626  }
3627  StringRef ShiftName = Tok.getString();
3628  bool isASR;
3629  if (ShiftName == "lsl" || ShiftName == "LSL")
3630    isASR = false;
3631  else if (ShiftName == "asr" || ShiftName == "ASR")
3632    isASR = true;
3633  else {
3634    Error(S, "shift operator 'asr' or 'lsl' expected");
3635    return MatchOperand_ParseFail;
3636  }
3637  Parser.Lex(); // Eat the operator.
3638
3639  // A '#' and a shift amount.
3640  if (Parser.getTok().isNot(AsmToken::Hash) &&
3641      Parser.getTok().isNot(AsmToken::Dollar)) {
3642    Error(Parser.getTok().getLoc(), "'#' expected");
3643    return MatchOperand_ParseFail;
3644  }
3645  Parser.Lex(); // Eat hash token.
3646  SMLoc ExLoc = Parser.getTok().getLoc();
3647
3648  const MCExpr *ShiftAmount;
3649  SMLoc EndLoc;
3650  if (getParser().parseExpression(ShiftAmount, EndLoc)) {
3651    Error(ExLoc, "malformed shift expression");
3652    return MatchOperand_ParseFail;
3653  }
3654  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3655  if (!CE) {
3656    Error(ExLoc, "shift amount must be an immediate");
3657    return MatchOperand_ParseFail;
3658  }
3659
3660  int64_t Val = CE->getValue();
3661  if (isASR) {
3662    // Shift amount must be in [1,32]
3663    if (Val < 1 || Val > 32) {
3664      Error(ExLoc, "'asr' shift amount must be in range [1,32]");
3665      return MatchOperand_ParseFail;
3666    }
3667    // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
3668    if (isThumb() && Val == 32) {
3669      Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode");
3670      return MatchOperand_ParseFail;
3671    }
3672    if (Val == 32) Val = 0;
3673  } else {
3674    // Shift amount must be in [1,32]
3675    if (Val < 0 || Val > 31) {
3676      Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
3677      return MatchOperand_ParseFail;
3678    }
3679  }
3680
3681  Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc));
3682
3683  return MatchOperand_Success;
3684}
3685
3686/// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
3687/// of instructions. Legal values are:
3688///     ror #n  'n' in {0, 8, 16, 24}
3689ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3690parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3691  const AsmToken &Tok = Parser.getTok();
3692  SMLoc S = Tok.getLoc();
3693  if (Tok.isNot(AsmToken::Identifier))
3694    return MatchOperand_NoMatch;
3695  StringRef ShiftName = Tok.getString();
3696  if (ShiftName != "ror" && ShiftName != "ROR")
3697    return MatchOperand_NoMatch;
3698  Parser.Lex(); // Eat the operator.
3699
3700  // A '#' and a rotate amount.
3701  if (Parser.getTok().isNot(AsmToken::Hash) &&
3702      Parser.getTok().isNot(AsmToken::Dollar)) {
3703    Error(Parser.getTok().getLoc(), "'#' expected");
3704    return MatchOperand_ParseFail;
3705  }
3706  Parser.Lex(); // Eat hash token.
3707  SMLoc ExLoc = Parser.getTok().getLoc();
3708
3709  const MCExpr *ShiftAmount;
3710  SMLoc EndLoc;
3711  if (getParser().parseExpression(ShiftAmount, EndLoc)) {
3712    Error(ExLoc, "malformed rotate expression");
3713    return MatchOperand_ParseFail;
3714  }
3715  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3716  if (!CE) {
3717    Error(ExLoc, "rotate amount must be an immediate");
3718    return MatchOperand_ParseFail;
3719  }
3720
3721  int64_t Val = CE->getValue();
3722  // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
3723  // normally, zero is represented in asm by omitting the rotate operand
3724  // entirely.
3725  if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
3726    Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24");
3727    return MatchOperand_ParseFail;
3728  }
3729
3730  Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc));
3731
3732  return MatchOperand_Success;
3733}
3734
3735ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3736parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3737  SMLoc S = Parser.getTok().getLoc();
3738  // The bitfield descriptor is really two operands, the LSB and the width.
3739  if (Parser.getTok().isNot(AsmToken::Hash) &&
3740      Parser.getTok().isNot(AsmToken::Dollar)) {
3741    Error(Parser.getTok().getLoc(), "'#' expected");
3742    return MatchOperand_ParseFail;
3743  }
3744  Parser.Lex(); // Eat hash token.
3745
3746  const MCExpr *LSBExpr;
3747  SMLoc E = Parser.getTok().getLoc();
3748  if (getParser().parseExpression(LSBExpr)) {
3749    Error(E, "malformed immediate expression");
3750    return MatchOperand_ParseFail;
3751  }
3752  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
3753  if (!CE) {
3754    Error(E, "'lsb' operand must be an immediate");
3755    return MatchOperand_ParseFail;
3756  }
3757
3758  int64_t LSB = CE->getValue();
3759  // The LSB must be in the range [0,31]
3760  if (LSB < 0 || LSB > 31) {
3761    Error(E, "'lsb' operand must be in the range [0,31]");
3762    return MatchOperand_ParseFail;
3763  }
3764  E = Parser.getTok().getLoc();
3765
3766  // Expect another immediate operand.
3767  if (Parser.getTok().isNot(AsmToken::Comma)) {
3768    Error(Parser.getTok().getLoc(), "too few operands");
3769    return MatchOperand_ParseFail;
3770  }
3771  Parser.Lex(); // Eat hash token.
3772  if (Parser.getTok().isNot(AsmToken::Hash) &&
3773      Parser.getTok().isNot(AsmToken::Dollar)) {
3774    Error(Parser.getTok().getLoc(), "'#' expected");
3775    return MatchOperand_ParseFail;
3776  }
3777  Parser.Lex(); // Eat hash token.
3778
3779  const MCExpr *WidthExpr;
3780  SMLoc EndLoc;
3781  if (getParser().parseExpression(WidthExpr, EndLoc)) {
3782    Error(E, "malformed immediate expression");
3783    return MatchOperand_ParseFail;
3784  }
3785  CE = dyn_cast<MCConstantExpr>(WidthExpr);
3786  if (!CE) {
3787    Error(E, "'width' operand must be an immediate");
3788    return MatchOperand_ParseFail;
3789  }
3790
3791  int64_t Width = CE->getValue();
3792  // The LSB must be in the range [1,32-lsb]
3793  if (Width < 1 || Width > 32 - LSB) {
3794    Error(E, "'width' operand must be in the range [1,32-lsb]");
3795    return MatchOperand_ParseFail;
3796  }
3797
3798  Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc));
3799
3800  return MatchOperand_Success;
3801}
3802
3803ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3804parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3805  // Check for a post-index addressing register operand. Specifically:
3806  // postidx_reg := '+' register {, shift}
3807  //              | '-' register {, shift}
3808  //              | register {, shift}
3809
3810  // This method must return MatchOperand_NoMatch without consuming any tokens
3811  // in the case where there is no match, as other alternatives take other
3812  // parse methods.
3813  AsmToken Tok = Parser.getTok();
3814  SMLoc S = Tok.getLoc();
3815  bool haveEaten = false;
3816  bool isAdd = true;
3817  if (Tok.is(AsmToken::Plus)) {
3818    Parser.Lex(); // Eat the '+' token.
3819    haveEaten = true;
3820  } else if (Tok.is(AsmToken::Minus)) {
3821    Parser.Lex(); // Eat the '-' token.
3822    isAdd = false;
3823    haveEaten = true;
3824  }
3825
3826  SMLoc E = Parser.getTok().getEndLoc();
3827  int Reg = tryParseRegister();
3828  if (Reg == -1) {
3829    if (!haveEaten)
3830      return MatchOperand_NoMatch;
3831    Error(Parser.getTok().getLoc(), "register expected");
3832    return MatchOperand_ParseFail;
3833  }
3834
3835  ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
3836  unsigned ShiftImm = 0;
3837  if (Parser.getTok().is(AsmToken::Comma)) {
3838    Parser.Lex(); // Eat the ','.
3839    if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
3840      return MatchOperand_ParseFail;
3841
3842    // FIXME: Only approximates end...may include intervening whitespace.
3843    E = Parser.getTok().getLoc();
3844  }
3845
3846  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
3847                                                  ShiftImm, S, E));
3848
3849  return MatchOperand_Success;
3850}
3851
3852ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3853parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3854  // Check for a post-index addressing register operand. Specifically:
3855  // am3offset := '+' register
3856  //              | '-' register
3857  //              | register
3858  //              | # imm
3859  //              | # + imm
3860  //              | # - imm
3861
3862  // This method must return MatchOperand_NoMatch without consuming any tokens
3863  // in the case where there is no match, as other alternatives take other
3864  // parse methods.
3865  AsmToken Tok = Parser.getTok();
3866  SMLoc S = Tok.getLoc();
3867
3868  // Do immediates first, as we always parse those if we have a '#'.
3869  if (Parser.getTok().is(AsmToken::Hash) ||
3870      Parser.getTok().is(AsmToken::Dollar)) {
3871    Parser.Lex(); // Eat the '#'.
3872    // Explicitly look for a '-', as we need to encode negative zero
3873    // differently.
3874    bool isNegative = Parser.getTok().is(AsmToken::Minus);
3875    const MCExpr *Offset;
3876    SMLoc E;
3877    if (getParser().parseExpression(Offset, E))
3878      return MatchOperand_ParseFail;
3879    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
3880    if (!CE) {
3881      Error(S, "constant expression expected");
3882      return MatchOperand_ParseFail;
3883    }
3884    // Negative zero is encoded as the flag value INT32_MIN.
3885    int32_t Val = CE->getValue();
3886    if (isNegative && Val == 0)
3887      Val = INT32_MIN;
3888
3889    Operands.push_back(
3890      ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
3891
3892    return MatchOperand_Success;
3893  }
3894
3895
3896  bool haveEaten = false;
3897  bool isAdd = true;
3898  if (Tok.is(AsmToken::Plus)) {
3899    Parser.Lex(); // Eat the '+' token.
3900    haveEaten = true;
3901  } else if (Tok.is(AsmToken::Minus)) {
3902    Parser.Lex(); // Eat the '-' token.
3903    isAdd = false;
3904    haveEaten = true;
3905  }
3906
3907  Tok = Parser.getTok();
3908  int Reg = tryParseRegister();
3909  if (Reg == -1) {
3910    if (!haveEaten)
3911      return MatchOperand_NoMatch;
3912    Error(Tok.getLoc(), "register expected");
3913    return MatchOperand_ParseFail;
3914  }
3915
3916  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
3917                                                  0, S, Tok.getEndLoc()));
3918
3919  return MatchOperand_Success;
3920}
3921
3922/// cvtT2LdrdPre - Convert parsed operands to MCInst.
3923/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3924/// when they refer multiple MIOperands inside a single one.
3925void ARMAsmParser::
3926cvtT2LdrdPre(MCInst &Inst,
3927             const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3928  // Rt, Rt2
3929  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3930  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3931  // Create a writeback register dummy placeholder.
3932  Inst.addOperand(MCOperand::CreateReg(0));
3933  // addr
3934  ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
3935  // pred
3936  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3937}
3938
3939/// cvtT2StrdPre - Convert parsed operands to MCInst.
3940/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3941/// when they refer multiple MIOperands inside a single one.
3942void ARMAsmParser::
3943cvtT2StrdPre(MCInst &Inst,
3944             const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3945  // Create a writeback register dummy placeholder.
3946  Inst.addOperand(MCOperand::CreateReg(0));
3947  // Rt, Rt2
3948  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3949  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3950  // addr
3951  ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
3952  // pred
3953  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3954}
3955
3956/// cvtLdWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
3957/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3958/// when they refer multiple MIOperands inside a single one.
3959void ARMAsmParser::
3960cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst,
3961                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3962  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3963
3964  // Create a writeback register dummy placeholder.
3965  Inst.addOperand(MCOperand::CreateImm(0));
3966
3967  ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
3968  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3969}
3970
3971/// cvtStWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
3972/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3973/// when they refer multiple MIOperands inside a single one.
3974void ARMAsmParser::
3975cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst,
3976                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3977  // Create a writeback register dummy placeholder.
3978  Inst.addOperand(MCOperand::CreateImm(0));
3979  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3980  ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
3981  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3982}
3983
3984/// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
3985/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3986/// when they refer multiple MIOperands inside a single one.
3987void ARMAsmParser::
3988cvtLdWriteBackRegAddrMode2(MCInst &Inst,
3989                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3990  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3991
3992  // Create a writeback register dummy placeholder.
3993  Inst.addOperand(MCOperand::CreateImm(0));
3994
3995  ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
3996  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3997}
3998
3999/// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
4000/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4001/// when they refer multiple MIOperands inside a single one.
4002void ARMAsmParser::
4003cvtLdWriteBackRegAddrModeImm12(MCInst &Inst,
4004                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4005  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4006
4007  // Create a writeback register dummy placeholder.
4008  Inst.addOperand(MCOperand::CreateImm(0));
4009
4010  ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
4011  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4012}
4013
4014
4015/// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
4016/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4017/// when they refer multiple MIOperands inside a single one.
4018void ARMAsmParser::
4019cvtStWriteBackRegAddrModeImm12(MCInst &Inst,
4020                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4021  // Create a writeback register dummy placeholder.
4022  Inst.addOperand(MCOperand::CreateImm(0));
4023  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4024  ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
4025  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4026}
4027
4028/// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
4029/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4030/// when they refer multiple MIOperands inside a single one.
4031void ARMAsmParser::
4032cvtStWriteBackRegAddrMode2(MCInst &Inst,
4033                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4034  // Create a writeback register dummy placeholder.
4035  Inst.addOperand(MCOperand::CreateImm(0));
4036  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4037  ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
4038  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4039}
4040
4041/// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
4042/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4043/// when they refer multiple MIOperands inside a single one.
4044void ARMAsmParser::
4045cvtStWriteBackRegAddrMode3(MCInst &Inst,
4046                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4047  // Create a writeback register dummy placeholder.
4048  Inst.addOperand(MCOperand::CreateImm(0));
4049  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4050  ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
4051  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4052}
4053
4054/// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst.
4055/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4056/// when they refer multiple MIOperands inside a single one.
4057void ARMAsmParser::
4058cvtLdExtTWriteBackImm(MCInst &Inst,
4059                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4060  // Rt
4061  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4062  // Create a writeback register dummy placeholder.
4063  Inst.addOperand(MCOperand::CreateImm(0));
4064  // addr
4065  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4066  // offset
4067  ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
4068  // pred
4069  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4070}
4071
4072/// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst.
4073/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4074/// when they refer multiple MIOperands inside a single one.
4075void ARMAsmParser::
4076cvtLdExtTWriteBackReg(MCInst &Inst,
4077                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4078  // Rt
4079  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4080  // Create a writeback register dummy placeholder.
4081  Inst.addOperand(MCOperand::CreateImm(0));
4082  // addr
4083  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4084  // offset
4085  ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
4086  // pred
4087  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4088}
4089
4090/// cvtStExtTWriteBackImm - Convert parsed operands to MCInst.
4091/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4092/// when they refer multiple MIOperands inside a single one.
4093void ARMAsmParser::
4094cvtStExtTWriteBackImm(MCInst &Inst,
4095                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4096  // Create a writeback register dummy placeholder.
4097  Inst.addOperand(MCOperand::CreateImm(0));
4098  // Rt
4099  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4100  // addr
4101  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4102  // offset
4103  ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
4104  // pred
4105  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4106}
4107
4108/// cvtStExtTWriteBackReg - Convert parsed operands to MCInst.
4109/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4110/// when they refer multiple MIOperands inside a single one.
4111void ARMAsmParser::
4112cvtStExtTWriteBackReg(MCInst &Inst,
4113                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4114  // Create a writeback register dummy placeholder.
4115  Inst.addOperand(MCOperand::CreateImm(0));
4116  // Rt
4117  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4118  // addr
4119  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4120  // offset
4121  ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
4122  // pred
4123  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4124}
4125
4126/// cvtLdrdPre - Convert parsed operands to MCInst.
4127/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4128/// when they refer multiple MIOperands inside a single one.
4129void ARMAsmParser::
4130cvtLdrdPre(MCInst &Inst,
4131           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4132  // Rt, Rt2
4133  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4134  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4135  // Create a writeback register dummy placeholder.
4136  Inst.addOperand(MCOperand::CreateImm(0));
4137  // addr
4138  ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
4139  // pred
4140  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4141}
4142
4143/// cvtStrdPre - Convert parsed operands to MCInst.
4144/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4145/// when they refer multiple MIOperands inside a single one.
4146void ARMAsmParser::
4147cvtStrdPre(MCInst &Inst,
4148           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4149  // Create a writeback register dummy placeholder.
4150  Inst.addOperand(MCOperand::CreateImm(0));
4151  // Rt, Rt2
4152  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4153  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4154  // addr
4155  ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
4156  // pred
4157  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4158}
4159
4160/// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
4161/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4162/// when they refer multiple MIOperands inside a single one.
4163void ARMAsmParser::
4164cvtLdWriteBackRegAddrMode3(MCInst &Inst,
4165                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4166  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4167  // Create a writeback register dummy placeholder.
4168  Inst.addOperand(MCOperand::CreateImm(0));
4169  ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
4170  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4171}
4172
4173/// cvtThumbMultiply - Convert parsed operands to MCInst.
4174/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4175/// when they refer multiple MIOperands inside a single one.
4176void ARMAsmParser::
4177cvtThumbMultiply(MCInst &Inst,
4178           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4179  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4180  ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
4181  // If we have a three-operand form, make sure to set Rn to be the operand
4182  // that isn't the same as Rd.
4183  unsigned RegOp = 4;
4184  if (Operands.size() == 6 &&
4185      ((ARMOperand*)Operands[4])->getReg() ==
4186        ((ARMOperand*)Operands[3])->getReg())
4187    RegOp = 5;
4188  ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1);
4189  Inst.addOperand(Inst.getOperand(0));
4190  ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
4191}
4192
4193void ARMAsmParser::
4194cvtVLDwbFixed(MCInst &Inst,
4195              const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4196  // Vd
4197  ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4198  // Create a writeback register dummy placeholder.
4199  Inst.addOperand(MCOperand::CreateImm(0));
4200  // Vn
4201  ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4202  // pred
4203  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4204}
4205
4206void ARMAsmParser::
4207cvtVLDwbRegister(MCInst &Inst,
4208                 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4209  // Vd
4210  ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4211  // Create a writeback register dummy placeholder.
4212  Inst.addOperand(MCOperand::CreateImm(0));
4213  // Vn
4214  ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4215  // Vm
4216  ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
4217  // pred
4218  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4219}
4220
4221void ARMAsmParser::
4222cvtVSTwbFixed(MCInst &Inst,
4223              const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4224  // Create a writeback register dummy placeholder.
4225  Inst.addOperand(MCOperand::CreateImm(0));
4226  // Vn
4227  ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4228  // Vt
4229  ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4230  // pred
4231  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4232}
4233
4234void ARMAsmParser::
4235cvtVSTwbRegister(MCInst &Inst,
4236                 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4237  // Create a writeback register dummy placeholder.
4238  Inst.addOperand(MCOperand::CreateImm(0));
4239  // Vn
4240  ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4241  // Vm
4242  ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
4243  // Vt
4244  ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4245  // pred
4246  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4247}
4248
4249/// Parse an ARM memory expression, return false if successful else return true
4250/// or an error.  The first token must be a '[' when called.
4251bool ARMAsmParser::
4252parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4253  SMLoc S, E;
4254  assert(Parser.getTok().is(AsmToken::LBrac) &&
4255         "Token is not a Left Bracket");
4256  S = Parser.getTok().getLoc();
4257  Parser.Lex(); // Eat left bracket token.
4258
4259  const AsmToken &BaseRegTok = Parser.getTok();
4260  int BaseRegNum = tryParseRegister();
4261  if (BaseRegNum == -1)
4262    return Error(BaseRegTok.getLoc(), "register expected");
4263
4264  // The next token must either be a comma, a colon or a closing bracket.
4265  const AsmToken &Tok = Parser.getTok();
4266  if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) &&
4267      !Tok.is(AsmToken::RBrac))
4268    return Error(Tok.getLoc(), "malformed memory operand");
4269
4270  if (Tok.is(AsmToken::RBrac)) {
4271    E = Tok.getEndLoc();
4272    Parser.Lex(); // Eat right bracket token.
4273
4274    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
4275                                             0, 0, false, S, E));
4276
4277    // If there's a pre-indexing writeback marker, '!', just add it as a token
4278    // operand. It's rather odd, but syntactically valid.
4279    if (Parser.getTok().is(AsmToken::Exclaim)) {
4280      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4281      Parser.Lex(); // Eat the '!'.
4282    }
4283
4284    return false;
4285  }
4286
4287  assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) &&
4288         "Lost colon or comma in memory operand?!");
4289  if (Tok.is(AsmToken::Comma)) {
4290    Parser.Lex(); // Eat the comma.
4291  }
4292
4293  // If we have a ':', it's an alignment specifier.
4294  if (Parser.getTok().is(AsmToken::Colon)) {
4295    Parser.Lex(); // Eat the ':'.
4296    E = Parser.getTok().getLoc();
4297
4298    const MCExpr *Expr;
4299    if (getParser().parseExpression(Expr))
4300     return true;
4301
4302    // The expression has to be a constant. Memory references with relocations
4303    // don't come through here, as they use the <label> forms of the relevant
4304    // instructions.
4305    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4306    if (!CE)
4307      return Error (E, "constant expression expected");
4308
4309    unsigned Align = 0;
4310    switch (CE->getValue()) {
4311    default:
4312      return Error(E,
4313                   "alignment specifier must be 16, 32, 64, 128, or 256 bits");
4314    case 16:  Align = 2; break;
4315    case 32:  Align = 4; break;
4316    case 64:  Align = 8; break;
4317    case 128: Align = 16; break;
4318    case 256: Align = 32; break;
4319    }
4320
4321    // Now we should have the closing ']'
4322    if (Parser.getTok().isNot(AsmToken::RBrac))
4323      return Error(Parser.getTok().getLoc(), "']' expected");
4324    E = Parser.getTok().getEndLoc();
4325    Parser.Lex(); // Eat right bracket token.
4326
4327    // Don't worry about range checking the value here. That's handled by
4328    // the is*() predicates.
4329    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0,
4330                                             ARM_AM::no_shift, 0, Align,
4331                                             false, S, E));
4332
4333    // If there's a pre-indexing writeback marker, '!', just add it as a token
4334    // operand.
4335    if (Parser.getTok().is(AsmToken::Exclaim)) {
4336      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4337      Parser.Lex(); // Eat the '!'.
4338    }
4339
4340    return false;
4341  }
4342
4343  // If we have a '#', it's an immediate offset, else assume it's a register
4344  // offset. Be friendly and also accept a plain integer (without a leading
4345  // hash) for gas compatibility.
4346  if (Parser.getTok().is(AsmToken::Hash) ||
4347      Parser.getTok().is(AsmToken::Dollar) ||
4348      Parser.getTok().is(AsmToken::Integer)) {
4349    if (Parser.getTok().isNot(AsmToken::Integer))
4350      Parser.Lex(); // Eat the '#'.
4351    E = Parser.getTok().getLoc();
4352
4353    bool isNegative = getParser().getTok().is(AsmToken::Minus);
4354    const MCExpr *Offset;
4355    if (getParser().parseExpression(Offset))
4356     return true;
4357
4358    // The expression has to be a constant. Memory references with relocations
4359    // don't come through here, as they use the <label> forms of the relevant
4360    // instructions.
4361    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4362    if (!CE)
4363      return Error (E, "constant expression expected");
4364
4365    // If the constant was #-0, represent it as INT32_MIN.
4366    int32_t Val = CE->getValue();
4367    if (isNegative && Val == 0)
4368      CE = MCConstantExpr::Create(INT32_MIN, getContext());
4369
4370    // Now we should have the closing ']'
4371    if (Parser.getTok().isNot(AsmToken::RBrac))
4372      return Error(Parser.getTok().getLoc(), "']' expected");
4373    E = Parser.getTok().getEndLoc();
4374    Parser.Lex(); // Eat right bracket token.
4375
4376    // Don't worry about range checking the value here. That's handled by
4377    // the is*() predicates.
4378    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
4379                                             ARM_AM::no_shift, 0, 0,
4380                                             false, S, E));
4381
4382    // If there's a pre-indexing writeback marker, '!', just add it as a token
4383    // operand.
4384    if (Parser.getTok().is(AsmToken::Exclaim)) {
4385      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4386      Parser.Lex(); // Eat the '!'.
4387    }
4388
4389    return false;
4390  }
4391
4392  // The register offset is optionally preceded by a '+' or '-'
4393  bool isNegative = false;
4394  if (Parser.getTok().is(AsmToken::Minus)) {
4395    isNegative = true;
4396    Parser.Lex(); // Eat the '-'.
4397  } else if (Parser.getTok().is(AsmToken::Plus)) {
4398    // Nothing to do.
4399    Parser.Lex(); // Eat the '+'.
4400  }
4401
4402  E = Parser.getTok().getLoc();
4403  int OffsetRegNum = tryParseRegister();
4404  if (OffsetRegNum == -1)
4405    return Error(E, "register expected");
4406
4407  // If there's a shift operator, handle it.
4408  ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
4409  unsigned ShiftImm = 0;
4410  if (Parser.getTok().is(AsmToken::Comma)) {
4411    Parser.Lex(); // Eat the ','.
4412    if (parseMemRegOffsetShift(ShiftType, ShiftImm))
4413      return true;
4414  }
4415
4416  // Now we should have the closing ']'
4417  if (Parser.getTok().isNot(AsmToken::RBrac))
4418    return Error(Parser.getTok().getLoc(), "']' expected");
4419  E = Parser.getTok().getEndLoc();
4420  Parser.Lex(); // Eat right bracket token.
4421
4422  Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
4423                                           ShiftType, ShiftImm, 0, isNegative,
4424                                           S, E));
4425
4426  // If there's a pre-indexing writeback marker, '!', just add it as a token
4427  // operand.
4428  if (Parser.getTok().is(AsmToken::Exclaim)) {
4429    Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4430    Parser.Lex(); // Eat the '!'.
4431  }
4432
4433  return false;
4434}
4435
4436/// parseMemRegOffsetShift - one of these two:
4437///   ( lsl | lsr | asr | ror ) , # shift_amount
4438///   rrx
4439/// return true if it parses a shift otherwise it returns false.
4440bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
4441                                          unsigned &Amount) {
4442  SMLoc Loc = Parser.getTok().getLoc();
4443  const AsmToken &Tok = Parser.getTok();
4444  if (Tok.isNot(AsmToken::Identifier))
4445    return true;
4446  StringRef ShiftName = Tok.getString();
4447  if (ShiftName == "lsl" || ShiftName == "LSL" ||
4448      ShiftName == "asl" || ShiftName == "ASL")
4449    St = ARM_AM::lsl;
4450  else if (ShiftName == "lsr" || ShiftName == "LSR")
4451    St = ARM_AM::lsr;
4452  else if (ShiftName == "asr" || ShiftName == "ASR")
4453    St = ARM_AM::asr;
4454  else if (ShiftName == "ror" || ShiftName == "ROR")
4455    St = ARM_AM::ror;
4456  else if (ShiftName == "rrx" || ShiftName == "RRX")
4457    St = ARM_AM::rrx;
4458  else
4459    return Error(Loc, "illegal shift operator");
4460  Parser.Lex(); // Eat shift type token.
4461
4462  // rrx stands alone.
4463  Amount = 0;
4464  if (St != ARM_AM::rrx) {
4465    Loc = Parser.getTok().getLoc();
4466    // A '#' and a shift amount.
4467    const AsmToken &HashTok = Parser.getTok();
4468    if (HashTok.isNot(AsmToken::Hash) &&
4469        HashTok.isNot(AsmToken::Dollar))
4470      return Error(HashTok.getLoc(), "'#' expected");
4471    Parser.Lex(); // Eat hash token.
4472
4473    const MCExpr *Expr;
4474    if (getParser().parseExpression(Expr))
4475      return true;
4476    // Range check the immediate.
4477    // lsl, ror: 0 <= imm <= 31
4478    // lsr, asr: 0 <= imm <= 32
4479    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4480    if (!CE)
4481      return Error(Loc, "shift amount must be an immediate");
4482    int64_t Imm = CE->getValue();
4483    if (Imm < 0 ||
4484        ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
4485        ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
4486      return Error(Loc, "immediate shift value out of range");
4487    // If <ShiftTy> #0, turn it into a no_shift.
4488    if (Imm == 0)
4489      St = ARM_AM::lsl;
4490    // For consistency, treat lsr #32 and asr #32 as having immediate value 0.
4491    if (Imm == 32)
4492      Imm = 0;
4493    Amount = Imm;
4494  }
4495
4496  return false;
4497}
4498
4499/// parseFPImm - A floating point immediate expression operand.
4500ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4501parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4502  // Anything that can accept a floating point constant as an operand
4503  // needs to go through here, as the regular parseExpression is
4504  // integer only.
4505  //
4506  // This routine still creates a generic Immediate operand, containing
4507  // a bitcast of the 64-bit floating point value. The various operands
4508  // that accept floats can check whether the value is valid for them
4509  // via the standard is*() predicates.
4510
4511  SMLoc S = Parser.getTok().getLoc();
4512
4513  if (Parser.getTok().isNot(AsmToken::Hash) &&
4514      Parser.getTok().isNot(AsmToken::Dollar))
4515    return MatchOperand_NoMatch;
4516
4517  // Disambiguate the VMOV forms that can accept an FP immediate.
4518  // vmov.f32 <sreg>, #imm
4519  // vmov.f64 <dreg>, #imm
4520  // vmov.f32 <dreg>, #imm  @ vector f32x2
4521  // vmov.f32 <qreg>, #imm  @ vector f32x4
4522  //
4523  // There are also the NEON VMOV instructions which expect an
4524  // integer constant. Make sure we don't try to parse an FPImm
4525  // for these:
4526  // vmov.i{8|16|32|64} <dreg|qreg>, #imm
4527  ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]);
4528  if (!TyOp->isToken() || (TyOp->getToken() != ".f32" &&
4529                           TyOp->getToken() != ".f64"))
4530    return MatchOperand_NoMatch;
4531
4532  Parser.Lex(); // Eat the '#'.
4533
4534  // Handle negation, as that still comes through as a separate token.
4535  bool isNegative = false;
4536  if (Parser.getTok().is(AsmToken::Minus)) {
4537    isNegative = true;
4538    Parser.Lex();
4539  }
4540  const AsmToken &Tok = Parser.getTok();
4541  SMLoc Loc = Tok.getLoc();
4542  if (Tok.is(AsmToken::Real)) {
4543    APFloat RealVal(APFloat::IEEEsingle, Tok.getString());
4544    uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
4545    // If we had a '-' in front, toggle the sign bit.
4546    IntVal ^= (uint64_t)isNegative << 31;
4547    Parser.Lex(); // Eat the token.
4548    Operands.push_back(ARMOperand::CreateImm(
4549          MCConstantExpr::Create(IntVal, getContext()),
4550          S, Parser.getTok().getLoc()));
4551    return MatchOperand_Success;
4552  }
4553  // Also handle plain integers. Instructions which allow floating point
4554  // immediates also allow a raw encoded 8-bit value.
4555  if (Tok.is(AsmToken::Integer)) {
4556    int64_t Val = Tok.getIntVal();
4557    Parser.Lex(); // Eat the token.
4558    if (Val > 255 || Val < 0) {
4559      Error(Loc, "encoded floating point value out of range");
4560      return MatchOperand_ParseFail;
4561    }
4562    double RealVal = ARM_AM::getFPImmFloat(Val);
4563    Val = APFloat(APFloat::IEEEdouble, RealVal).bitcastToAPInt().getZExtValue();
4564    Operands.push_back(ARMOperand::CreateImm(
4565        MCConstantExpr::Create(Val, getContext()), S,
4566        Parser.getTok().getLoc()));
4567    return MatchOperand_Success;
4568  }
4569
4570  Error(Loc, "invalid floating point immediate");
4571  return MatchOperand_ParseFail;
4572}
4573
4574/// Parse a arm instruction operand.  For now this parses the operand regardless
4575/// of the mnemonic.
4576bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
4577                                StringRef Mnemonic) {
4578  SMLoc S, E;
4579
4580  // Check if the current operand has a custom associated parser, if so, try to
4581  // custom parse the operand, or fallback to the general approach.
4582  OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
4583  if (ResTy == MatchOperand_Success)
4584    return false;
4585  // If there wasn't a custom match, try the generic matcher below. Otherwise,
4586  // there was a match, but an error occurred, in which case, just return that
4587  // the operand parsing failed.
4588  if (ResTy == MatchOperand_ParseFail)
4589    return true;
4590
4591  switch (getLexer().getKind()) {
4592  default:
4593    Error(Parser.getTok().getLoc(), "unexpected token in operand");
4594    return true;
4595  case AsmToken::Identifier: {
4596    // If we've seen a branch mnemonic, the next operand must be a label.  This
4597    // is true even if the label is a register name.  So "br r1" means branch to
4598    // label "r1".
4599    bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl";
4600    if (!ExpectLabel) {
4601      if (!tryParseRegisterWithWriteBack(Operands))
4602        return false;
4603      int Res = tryParseShiftRegister(Operands);
4604      if (Res == 0) // success
4605        return false;
4606      else if (Res == -1) // irrecoverable error
4607        return true;
4608      // If this is VMRS, check for the apsr_nzcv operand.
4609      if (Mnemonic == "vmrs" &&
4610          Parser.getTok().getString().equals_lower("apsr_nzcv")) {
4611        S = Parser.getTok().getLoc();
4612        Parser.Lex();
4613        Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
4614        return false;
4615      }
4616    }
4617
4618    // Fall though for the Identifier case that is not a register or a
4619    // special name.
4620  }
4621  case AsmToken::LParen:  // parenthesized expressions like (_strcmp-4)
4622  case AsmToken::Integer: // things like 1f and 2b as a branch targets
4623  case AsmToken::String:  // quoted label names.
4624  case AsmToken::Dot: {   // . as a branch target
4625    // This was not a register so parse other operands that start with an
4626    // identifier (like labels) as expressions and create them as immediates.
4627    const MCExpr *IdVal;
4628    S = Parser.getTok().getLoc();
4629    if (getParser().parseExpression(IdVal))
4630      return true;
4631    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4632    Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
4633    return false;
4634  }
4635  case AsmToken::LBrac:
4636    return parseMemory(Operands);
4637  case AsmToken::LCurly:
4638    return parseRegisterList(Operands);
4639  case AsmToken::Dollar:
4640  case AsmToken::Hash: {
4641    // #42 -> immediate.
4642    S = Parser.getTok().getLoc();
4643    Parser.Lex();
4644
4645    if (Parser.getTok().isNot(AsmToken::Colon)) {
4646      bool isNegative = Parser.getTok().is(AsmToken::Minus);
4647      const MCExpr *ImmVal;
4648      if (getParser().parseExpression(ImmVal))
4649        return true;
4650      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
4651      if (CE) {
4652        int32_t Val = CE->getValue();
4653        if (isNegative && Val == 0)
4654          ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
4655      }
4656      E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4657      Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
4658
4659      // There can be a trailing '!' on operands that we want as a separate
4660      // '!' Token operand. Handle that here. For example, the compatibilty
4661      // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'.
4662      if (Parser.getTok().is(AsmToken::Exclaim)) {
4663        Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(),
4664                                                   Parser.getTok().getLoc()));
4665        Parser.Lex(); // Eat exclaim token
4666      }
4667      return false;
4668    }
4669    // w/ a ':' after the '#', it's just like a plain ':'.
4670    // FALLTHROUGH
4671  }
4672  case AsmToken::Colon: {
4673    // ":lower16:" and ":upper16:" expression prefixes
4674    // FIXME: Check it's an expression prefix,
4675    // e.g. (FOO - :lower16:BAR) isn't legal.
4676    ARMMCExpr::VariantKind RefKind;
4677    if (parsePrefix(RefKind))
4678      return true;
4679
4680    const MCExpr *SubExprVal;
4681    if (getParser().parseExpression(SubExprVal))
4682      return true;
4683
4684    const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
4685                                              getContext());
4686    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4687    Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
4688    return false;
4689  }
4690  }
4691}
4692
4693// parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
4694//  :lower16: and :upper16:.
4695bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
4696  RefKind = ARMMCExpr::VK_ARM_None;
4697
4698  // :lower16: and :upper16: modifiers
4699  assert(getLexer().is(AsmToken::Colon) && "expected a :");
4700  Parser.Lex(); // Eat ':'
4701
4702  if (getLexer().isNot(AsmToken::Identifier)) {
4703    Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
4704    return true;
4705  }
4706
4707  StringRef IDVal = Parser.getTok().getIdentifier();
4708  if (IDVal == "lower16") {
4709    RefKind = ARMMCExpr::VK_ARM_LO16;
4710  } else if (IDVal == "upper16") {
4711    RefKind = ARMMCExpr::VK_ARM_HI16;
4712  } else {
4713    Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
4714    return true;
4715  }
4716  Parser.Lex();
4717
4718  if (getLexer().isNot(AsmToken::Colon)) {
4719    Error(Parser.getTok().getLoc(), "unexpected token after prefix");
4720    return true;
4721  }
4722  Parser.Lex(); // Eat the last ':'
4723  return false;
4724}
4725
4726/// \brief Given a mnemonic, split out possible predication code and carry
4727/// setting letters to form a canonical mnemonic and flags.
4728//
4729// FIXME: Would be nice to autogen this.
4730// FIXME: This is a bit of a maze of special cases.
4731StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
4732                                      unsigned &PredicationCode,
4733                                      bool &CarrySetting,
4734                                      unsigned &ProcessorIMod,
4735                                      StringRef &ITMask) {
4736  PredicationCode = ARMCC::AL;
4737  CarrySetting = false;
4738  ProcessorIMod = 0;
4739
4740  // Ignore some mnemonics we know aren't predicated forms.
4741  //
4742  // FIXME: Would be nice to autogen this.
4743  if ((Mnemonic == "movs" && isThumb()) ||
4744      Mnemonic == "teq"   || Mnemonic == "vceq"   || Mnemonic == "svc"   ||
4745      Mnemonic == "mls"   || Mnemonic == "smmls"  || Mnemonic == "vcls"  ||
4746      Mnemonic == "vmls"  || Mnemonic == "vnmls"  || Mnemonic == "vacge" ||
4747      Mnemonic == "vcge"  || Mnemonic == "vclt"   || Mnemonic == "vacgt" ||
4748      Mnemonic == "vaclt" || Mnemonic == "vacle"  ||
4749      Mnemonic == "vcgt"  || Mnemonic == "vcle"   || Mnemonic == "smlal" ||
4750      Mnemonic == "umaal" || Mnemonic == "umlal"  || Mnemonic == "vabal" ||
4751      Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
4752      Mnemonic == "fmuls")
4753    return Mnemonic;
4754
4755  // First, split out any predication code. Ignore mnemonics we know aren't
4756  // predicated but do have a carry-set and so weren't caught above.
4757  if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
4758      Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
4759      Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
4760      Mnemonic != "sbcs" && Mnemonic != "rscs") {
4761    unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
4762      .Case("eq", ARMCC::EQ)
4763      .Case("ne", ARMCC::NE)
4764      .Case("hs", ARMCC::HS)
4765      .Case("cs", ARMCC::HS)
4766      .Case("lo", ARMCC::LO)
4767      .Case("cc", ARMCC::LO)
4768      .Case("mi", ARMCC::MI)
4769      .Case("pl", ARMCC::PL)
4770      .Case("vs", ARMCC::VS)
4771      .Case("vc", ARMCC::VC)
4772      .Case("hi", ARMCC::HI)
4773      .Case("ls", ARMCC::LS)
4774      .Case("ge", ARMCC::GE)
4775      .Case("lt", ARMCC::LT)
4776      .Case("gt", ARMCC::GT)
4777      .Case("le", ARMCC::LE)
4778      .Case("al", ARMCC::AL)
4779      .Default(~0U);
4780    if (CC != ~0U) {
4781      Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
4782      PredicationCode = CC;
4783    }
4784  }
4785
4786  // Next, determine if we have a carry setting bit. We explicitly ignore all
4787  // the instructions we know end in 's'.
4788  if (Mnemonic.endswith("s") &&
4789      !(Mnemonic == "cps" || Mnemonic == "mls" ||
4790        Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
4791        Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
4792        Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
4793        Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
4794        Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
4795        Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
4796        Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
4797        Mnemonic == "vfms" || Mnemonic == "vfnms" ||
4798        (Mnemonic == "movs" && isThumb()))) {
4799    Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
4800    CarrySetting = true;
4801  }
4802
4803  // The "cps" instruction can have a interrupt mode operand which is glued into
4804  // the mnemonic. Check if this is the case, split it and parse the imod op
4805  if (Mnemonic.startswith("cps")) {
4806    // Split out any imod code.
4807    unsigned IMod =
4808      StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
4809      .Case("ie", ARM_PROC::IE)
4810      .Case("id", ARM_PROC::ID)
4811      .Default(~0U);
4812    if (IMod != ~0U) {
4813      Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
4814      ProcessorIMod = IMod;
4815    }
4816  }
4817
4818  // The "it" instruction has the condition mask on the end of the mnemonic.
4819  if (Mnemonic.startswith("it")) {
4820    ITMask = Mnemonic.slice(2, Mnemonic.size());
4821    Mnemonic = Mnemonic.slice(0, 2);
4822  }
4823
4824  return Mnemonic;
4825}
4826
4827/// \brief Given a canonical mnemonic, determine if the instruction ever allows
4828/// inclusion of carry set or predication code operands.
4829//
4830// FIXME: It would be nice to autogen this.
4831void ARMAsmParser::
4832getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
4833                      bool &CanAcceptPredicationCode) {
4834  if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
4835      Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
4836      Mnemonic == "add" || Mnemonic == "adc" ||
4837      Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
4838      Mnemonic == "orr" || Mnemonic == "mvn" ||
4839      Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
4840      Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
4841      Mnemonic == "vfm" || Mnemonic == "vfnm" ||
4842      (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
4843                      Mnemonic == "mla" || Mnemonic == "smlal" ||
4844                      Mnemonic == "umlal" || Mnemonic == "umull"))) {
4845    CanAcceptCarrySet = true;
4846  } else
4847    CanAcceptCarrySet = false;
4848
4849  if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
4850      Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
4851      Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
4852      Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
4853      Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "setend" ||
4854      (Mnemonic == "clrex" && !isThumb()) ||
4855      (Mnemonic == "nop" && isThumbOne()) ||
4856      ((Mnemonic == "pld" || Mnemonic == "pli" || Mnemonic == "pldw" ||
4857        Mnemonic == "ldc2" || Mnemonic == "ldc2l" ||
4858        Mnemonic == "stc2" || Mnemonic == "stc2l") && !isThumb()) ||
4859      ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs")) &&
4860       !isThumb()) ||
4861      Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumbOne())) {
4862    CanAcceptPredicationCode = false;
4863  } else
4864    CanAcceptPredicationCode = true;
4865
4866  if (isThumb()) {
4867    if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
4868        Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
4869      CanAcceptPredicationCode = false;
4870  }
4871}
4872
4873bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
4874                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4875  // FIXME: This is all horribly hacky. We really need a better way to deal
4876  // with optional operands like this in the matcher table.
4877
4878  // The 'mov' mnemonic is special. One variant has a cc_out operand, while
4879  // another does not. Specifically, the MOVW instruction does not. So we
4880  // special case it here and remove the defaulted (non-setting) cc_out
4881  // operand if that's the instruction we're trying to match.
4882  //
4883  // We do this as post-processing of the explicit operands rather than just
4884  // conditionally adding the cc_out in the first place because we need
4885  // to check the type of the parsed immediate operand.
4886  if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
4887      !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
4888      static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
4889      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4890    return true;
4891
4892  // Register-register 'add' for thumb does not have a cc_out operand
4893  // when there are only two register operands.
4894  if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
4895      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4896      static_cast<ARMOperand*>(Operands[4])->isReg() &&
4897      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4898    return true;
4899  // Register-register 'add' for thumb does not have a cc_out operand
4900  // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
4901  // have to check the immediate range here since Thumb2 has a variant
4902  // that can handle a different range and has a cc_out operand.
4903  if (((isThumb() && Mnemonic == "add") ||
4904       (isThumbTwo() && Mnemonic == "sub")) &&
4905      Operands.size() == 6 &&
4906      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4907      static_cast<ARMOperand*>(Operands[4])->isReg() &&
4908      static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
4909      static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4910      ((Mnemonic == "add" &&static_cast<ARMOperand*>(Operands[5])->isReg()) ||
4911       static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
4912    return true;
4913  // For Thumb2, add/sub immediate does not have a cc_out operand for the
4914  // imm0_4095 variant. That's the least-preferred variant when
4915  // selecting via the generic "add" mnemonic, so to know that we
4916  // should remove the cc_out operand, we have to explicitly check that
4917  // it's not one of the other variants. Ugh.
4918  if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
4919      Operands.size() == 6 &&
4920      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4921      static_cast<ARMOperand*>(Operands[4])->isReg() &&
4922      static_cast<ARMOperand*>(Operands[5])->isImm()) {
4923    // Nest conditions rather than one big 'if' statement for readability.
4924    //
4925    // If either register is a high reg, it's either one of the SP
4926    // variants (handled above) or a 32-bit encoding, so we just
4927    // check against T3. If the second register is the PC, this is an
4928    // alternate form of ADR, which uses encoding T4, so check for that too.
4929    if ((!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4930         !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg())) &&
4931        static_cast<ARMOperand*>(Operands[4])->getReg() != ARM::PC &&
4932        static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
4933      return false;
4934    // If both registers are low, we're in an IT block, and the immediate is
4935    // in range, we should use encoding T1 instead, which has a cc_out.
4936    if (inITBlock() &&
4937        isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
4938        isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
4939        static_cast<ARMOperand*>(Operands[5])->isImm0_7())
4940      return false;
4941
4942    // Otherwise, we use encoding T4, which does not have a cc_out
4943    // operand.
4944    return true;
4945  }
4946
4947  // The thumb2 multiply instruction doesn't have a CCOut register, so
4948  // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
4949  // use the 16-bit encoding or not.
4950  if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
4951      static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4952      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4953      static_cast<ARMOperand*>(Operands[4])->isReg() &&
4954      static_cast<ARMOperand*>(Operands[5])->isReg() &&
4955      // If the registers aren't low regs, the destination reg isn't the
4956      // same as one of the source regs, or the cc_out operand is zero
4957      // outside of an IT block, we have to use the 32-bit encoding, so
4958      // remove the cc_out operand.
4959      (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4960       !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4961       !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) ||
4962       !inITBlock() ||
4963       (static_cast<ARMOperand*>(Operands[3])->getReg() !=
4964        static_cast<ARMOperand*>(Operands[5])->getReg() &&
4965        static_cast<ARMOperand*>(Operands[3])->getReg() !=
4966        static_cast<ARMOperand*>(Operands[4])->getReg())))
4967    return true;
4968
4969  // Also check the 'mul' syntax variant that doesn't specify an explicit
4970  // destination register.
4971  if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
4972      static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4973      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4974      static_cast<ARMOperand*>(Operands[4])->isReg() &&
4975      // If the registers aren't low regs  or the cc_out operand is zero
4976      // outside of an IT block, we have to use the 32-bit encoding, so
4977      // remove the cc_out operand.
4978      (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4979       !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4980       !inITBlock()))
4981    return true;
4982
4983
4984
4985  // Register-register 'add/sub' for thumb does not have a cc_out operand
4986  // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
4987  // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
4988  // right, this will result in better diagnostics (which operand is off)
4989  // anyway.
4990  if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
4991      (Operands.size() == 5 || Operands.size() == 6) &&
4992      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4993      static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
4994      static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4995      (static_cast<ARMOperand*>(Operands[4])->isImm() ||
4996       (Operands.size() == 6 &&
4997        static_cast<ARMOperand*>(Operands[5])->isImm())))
4998    return true;
4999
5000  return false;
5001}
5002
5003static bool isDataTypeToken(StringRef Tok) {
5004  return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
5005    Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
5006    Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
5007    Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
5008    Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
5009    Tok == ".f" || Tok == ".d";
5010}
5011
5012// FIXME: This bit should probably be handled via an explicit match class
5013// in the .td files that matches the suffix instead of having it be
5014// a literal string token the way it is now.
5015static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
5016  return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
5017}
5018
5019static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features);
5020/// Parse an arm instruction mnemonic followed by its operands.
5021bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
5022                                    SMLoc NameLoc,
5023                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5024  // Apply mnemonic aliases before doing anything else, as the destination
5025  // mnemnonic may include suffices and we want to handle them normally.
5026  // The generic tblgen'erated code does this later, at the start of
5027  // MatchInstructionImpl(), but that's too late for aliases that include
5028  // any sort of suffix.
5029  unsigned AvailableFeatures = getAvailableFeatures();
5030  applyMnemonicAliases(Name, AvailableFeatures);
5031
5032  // First check for the ARM-specific .req directive.
5033  if (Parser.getTok().is(AsmToken::Identifier) &&
5034      Parser.getTok().getIdentifier() == ".req") {
5035    parseDirectiveReq(Name, NameLoc);
5036    // We always return 'error' for this, as we're done with this
5037    // statement and don't need to match the 'instruction."
5038    return true;
5039  }
5040
5041  // Create the leading tokens for the mnemonic, split by '.' characters.
5042  size_t Start = 0, Next = Name.find('.');
5043  StringRef Mnemonic = Name.slice(Start, Next);
5044
5045  // Split out the predication code and carry setting flag from the mnemonic.
5046  unsigned PredicationCode;
5047  unsigned ProcessorIMod;
5048  bool CarrySetting;
5049  StringRef ITMask;
5050  Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
5051                           ProcessorIMod, ITMask);
5052
5053  // In Thumb1, only the branch (B) instruction can be predicated.
5054  if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
5055    Parser.eatToEndOfStatement();
5056    return Error(NameLoc, "conditional execution not supported in Thumb1");
5057  }
5058
5059  Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
5060
5061  // Handle the IT instruction ITMask. Convert it to a bitmask. This
5062  // is the mask as it will be for the IT encoding if the conditional
5063  // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
5064  // where the conditional bit0 is zero, the instruction post-processing
5065  // will adjust the mask accordingly.
5066  if (Mnemonic == "it") {
5067    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
5068    if (ITMask.size() > 3) {
5069      Parser.eatToEndOfStatement();
5070      return Error(Loc, "too many conditions on IT instruction");
5071    }
5072    unsigned Mask = 8;
5073    for (unsigned i = ITMask.size(); i != 0; --i) {
5074      char pos = ITMask[i - 1];
5075      if (pos != 't' && pos != 'e') {
5076        Parser.eatToEndOfStatement();
5077        return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
5078      }
5079      Mask >>= 1;
5080      if (ITMask[i - 1] == 't')
5081        Mask |= 8;
5082    }
5083    Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
5084  }
5085
5086  // FIXME: This is all a pretty gross hack. We should automatically handle
5087  // optional operands like this via tblgen.
5088
5089  // Next, add the CCOut and ConditionCode operands, if needed.
5090  //
5091  // For mnemonics which can ever incorporate a carry setting bit or predication
5092  // code, our matching model involves us always generating CCOut and
5093  // ConditionCode operands to match the mnemonic "as written" and then we let
5094  // the matcher deal with finding the right instruction or generating an
5095  // appropriate error.
5096  bool CanAcceptCarrySet, CanAcceptPredicationCode;
5097  getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
5098
5099  // If we had a carry-set on an instruction that can't do that, issue an
5100  // error.
5101  if (!CanAcceptCarrySet && CarrySetting) {
5102    Parser.eatToEndOfStatement();
5103    return Error(NameLoc, "instruction '" + Mnemonic +
5104                 "' can not set flags, but 's' suffix specified");
5105  }
5106  // If we had a predication code on an instruction that can't do that, issue an
5107  // error.
5108  if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
5109    Parser.eatToEndOfStatement();
5110    return Error(NameLoc, "instruction '" + Mnemonic +
5111                 "' is not predicable, but condition code specified");
5112  }
5113
5114  // Add the carry setting operand, if necessary.
5115  if (CanAcceptCarrySet) {
5116    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
5117    Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
5118                                               Loc));
5119  }
5120
5121  // Add the predication code operand, if necessary.
5122  if (CanAcceptPredicationCode) {
5123    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
5124                                      CarrySetting);
5125    Operands.push_back(ARMOperand::CreateCondCode(
5126                         ARMCC::CondCodes(PredicationCode), Loc));
5127  }
5128
5129  // Add the processor imod operand, if necessary.
5130  if (ProcessorIMod) {
5131    Operands.push_back(ARMOperand::CreateImm(
5132          MCConstantExpr::Create(ProcessorIMod, getContext()),
5133                                 NameLoc, NameLoc));
5134  }
5135
5136  // Add the remaining tokens in the mnemonic.
5137  while (Next != StringRef::npos) {
5138    Start = Next;
5139    Next = Name.find('.', Start + 1);
5140    StringRef ExtraToken = Name.slice(Start, Next);
5141
5142    // Some NEON instructions have an optional datatype suffix that is
5143    // completely ignored. Check for that.
5144    if (isDataTypeToken(ExtraToken) &&
5145        doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
5146      continue;
5147
5148    if (ExtraToken != ".n") {
5149      SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5150      Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
5151    }
5152  }
5153
5154  // Read the remaining operands.
5155  if (getLexer().isNot(AsmToken::EndOfStatement)) {
5156    // Read the first operand.
5157    if (parseOperand(Operands, Mnemonic)) {
5158      Parser.eatToEndOfStatement();
5159      return true;
5160    }
5161
5162    while (getLexer().is(AsmToken::Comma)) {
5163      Parser.Lex();  // Eat the comma.
5164
5165      // Parse and remember the operand.
5166      if (parseOperand(Operands, Mnemonic)) {
5167        Parser.eatToEndOfStatement();
5168        return true;
5169      }
5170    }
5171  }
5172
5173  if (getLexer().isNot(AsmToken::EndOfStatement)) {
5174    SMLoc Loc = getLexer().getLoc();
5175    Parser.eatToEndOfStatement();
5176    return Error(Loc, "unexpected token in argument list");
5177  }
5178
5179  Parser.Lex(); // Consume the EndOfStatement
5180
5181  // Some instructions, mostly Thumb, have forms for the same mnemonic that
5182  // do and don't have a cc_out optional-def operand. With some spot-checks
5183  // of the operand list, we can figure out which variant we're trying to
5184  // parse and adjust accordingly before actually matching. We shouldn't ever
5185  // try to remove a cc_out operand that was explicitly set on the the
5186  // mnemonic, of course (CarrySetting == true). Reason number #317 the
5187  // table driven matcher doesn't fit well with the ARM instruction set.
5188  if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
5189    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5190    Operands.erase(Operands.begin() + 1);
5191    delete Op;
5192  }
5193
5194  // ARM mode 'blx' need special handling, as the register operand version
5195  // is predicable, but the label operand version is not. So, we can't rely
5196  // on the Mnemonic based checking to correctly figure out when to put
5197  // a k_CondCode operand in the list. If we're trying to match the label
5198  // version, remove the k_CondCode operand here.
5199  if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
5200      static_cast<ARMOperand*>(Operands[2])->isImm()) {
5201    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5202    Operands.erase(Operands.begin() + 1);
5203    delete Op;
5204  }
5205
5206  // Adjust operands of ldrexd/strexd to MCK_GPRPair.
5207  // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
5208  // a single GPRPair reg operand is used in the .td file to replace the two
5209  // GPRs. However, when parsing from asm, the two GRPs cannot be automatically
5210  // expressed as a GPRPair, so we have to manually merge them.
5211  // FIXME: We would really like to be able to tablegen'erate this.
5212  if (!isThumb() && Operands.size() > 4 &&
5213      (Mnemonic == "ldrexd" || Mnemonic == "strexd")) {
5214    bool isLoad = (Mnemonic == "ldrexd");
5215    unsigned Idx = isLoad ? 2 : 3;
5216    ARMOperand* Op1 = static_cast<ARMOperand*>(Operands[Idx]);
5217    ARMOperand* Op2 = static_cast<ARMOperand*>(Operands[Idx+1]);
5218
5219    const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID);
5220    // Adjust only if Op1 and Op2 are GPRs.
5221    if (Op1->isReg() && Op2->isReg() && MRC.contains(Op1->getReg()) &&
5222        MRC.contains(Op2->getReg())) {
5223      unsigned Reg1 = Op1->getReg();
5224      unsigned Reg2 = Op2->getReg();
5225      unsigned Rt = MRI->getEncodingValue(Reg1);
5226      unsigned Rt2 = MRI->getEncodingValue(Reg2);
5227
5228      // Rt2 must be Rt + 1 and Rt must be even.
5229      if (Rt + 1 != Rt2 || (Rt & 1)) {
5230        Error(Op2->getStartLoc(), isLoad ?
5231            "destination operands must be sequential" :
5232            "source operands must be sequential");
5233        return true;
5234      }
5235      unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0,
5236          &(MRI->getRegClass(ARM::GPRPairRegClassID)));
5237      Operands.erase(Operands.begin() + Idx, Operands.begin() + Idx + 2);
5238      Operands.insert(Operands.begin() + Idx, ARMOperand::CreateReg(
5239            NewReg, Op1->getStartLoc(), Op2->getEndLoc()));
5240      delete Op1;
5241      delete Op2;
5242    }
5243  }
5244
5245  return false;
5246}
5247
5248// Validate context-sensitive operand constraints.
5249
5250// return 'true' if register list contains non-low GPR registers,
5251// 'false' otherwise. If Reg is in the register list or is HiReg, set
5252// 'containsReg' to true.
5253static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
5254                                 unsigned HiReg, bool &containsReg) {
5255  containsReg = false;
5256  for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5257    unsigned OpReg = Inst.getOperand(i).getReg();
5258    if (OpReg == Reg)
5259      containsReg = true;
5260    // Anything other than a low register isn't legal here.
5261    if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
5262      return true;
5263  }
5264  return false;
5265}
5266
5267// Check if the specified regisgter is in the register list of the inst,
5268// starting at the indicated operand number.
5269static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
5270  for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5271    unsigned OpReg = Inst.getOperand(i).getReg();
5272    if (OpReg == Reg)
5273      return true;
5274  }
5275  return false;
5276}
5277
5278// FIXME: We would really prefer to have MCInstrInfo (the wrapper around
5279// the ARMInsts array) instead. Getting that here requires awkward
5280// API changes, though. Better way?
5281namespace llvm {
5282extern const MCInstrDesc ARMInsts[];
5283}
5284static const MCInstrDesc &getInstDesc(unsigned Opcode) {
5285  return ARMInsts[Opcode];
5286}
5287
5288// FIXME: We would really like to be able to tablegen'erate this.
5289bool ARMAsmParser::
5290validateInstruction(MCInst &Inst,
5291                    const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5292  const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
5293  SMLoc Loc = Operands[0]->getStartLoc();
5294  // Check the IT block state first.
5295  // NOTE: BKPT instruction has the interesting property of being
5296  // allowed in IT blocks, but not being predicable.  It just always
5297  // executes.
5298  if (inITBlock() && Inst.getOpcode() != ARM::tBKPT &&
5299      Inst.getOpcode() != ARM::BKPT) {
5300    unsigned bit = 1;
5301    if (ITState.FirstCond)
5302      ITState.FirstCond = false;
5303    else
5304      bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
5305    // The instruction must be predicable.
5306    if (!MCID.isPredicable())
5307      return Error(Loc, "instructions in IT block must be predicable");
5308    unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
5309    unsigned ITCond = bit ? ITState.Cond :
5310      ARMCC::getOppositeCondition(ITState.Cond);
5311    if (Cond != ITCond) {
5312      // Find the condition code Operand to get its SMLoc information.
5313      SMLoc CondLoc;
5314      for (unsigned i = 1; i < Operands.size(); ++i)
5315        if (static_cast<ARMOperand*>(Operands[i])->isCondCode())
5316          CondLoc = Operands[i]->getStartLoc();
5317      return Error(CondLoc, "incorrect condition in IT block; got '" +
5318                   StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
5319                   "', but expected '" +
5320                   ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
5321    }
5322  // Check for non-'al' condition codes outside of the IT block.
5323  } else if (isThumbTwo() && MCID.isPredicable() &&
5324             Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
5325             ARMCC::AL && Inst.getOpcode() != ARM::tB &&
5326             Inst.getOpcode() != ARM::t2B)
5327    return Error(Loc, "predicated instructions must be in IT block");
5328
5329  switch (Inst.getOpcode()) {
5330  case ARM::LDRD:
5331  case ARM::LDRD_PRE:
5332  case ARM::LDRD_POST: {
5333    // Rt2 must be Rt + 1.
5334    unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5335    unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5336    if (Rt2 != Rt + 1)
5337      return Error(Operands[3]->getStartLoc(),
5338                   "destination operands must be sequential");
5339    return false;
5340  }
5341  case ARM::STRD: {
5342    // Rt2 must be Rt + 1.
5343    unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5344    unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5345    if (Rt2 != Rt + 1)
5346      return Error(Operands[3]->getStartLoc(),
5347                   "source operands must be sequential");
5348    return false;
5349  }
5350  case ARM::STRD_PRE:
5351  case ARM::STRD_POST: {
5352    // Rt2 must be Rt + 1.
5353    unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5354    unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
5355    if (Rt2 != Rt + 1)
5356      return Error(Operands[3]->getStartLoc(),
5357                   "source operands must be sequential");
5358    return false;
5359  }
5360  case ARM::SBFX:
5361  case ARM::UBFX: {
5362    // width must be in range [1, 32-lsb]
5363    unsigned lsb = Inst.getOperand(2).getImm();
5364    unsigned widthm1 = Inst.getOperand(3).getImm();
5365    if (widthm1 >= 32 - lsb)
5366      return Error(Operands[5]->getStartLoc(),
5367                   "bitfield width must be in range [1,32-lsb]");
5368    return false;
5369  }
5370  case ARM::tLDMIA: {
5371    // If we're parsing Thumb2, the .w variant is available and handles
5372    // most cases that are normally illegal for a Thumb1 LDM
5373    // instruction. We'll make the transformation in processInstruction()
5374    // if necessary.
5375    //
5376    // Thumb LDM instructions are writeback iff the base register is not
5377    // in the register list.
5378    unsigned Rn = Inst.getOperand(0).getReg();
5379    bool hasWritebackToken =
5380      (static_cast<ARMOperand*>(Operands[3])->isToken() &&
5381       static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
5382    bool listContainsBase;
5383    if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo())
5384      return Error(Operands[3 + hasWritebackToken]->getStartLoc(),
5385                   "registers must be in range r0-r7");
5386    // If we should have writeback, then there should be a '!' token.
5387    if (!listContainsBase && !hasWritebackToken && !isThumbTwo())
5388      return Error(Operands[2]->getStartLoc(),
5389                   "writeback operator '!' expected");
5390    // If we should not have writeback, there must not be a '!'. This is
5391    // true even for the 32-bit wide encodings.
5392    if (listContainsBase && hasWritebackToken)
5393      return Error(Operands[3]->getStartLoc(),
5394                   "writeback operator '!' not allowed when base register "
5395                   "in register list");
5396
5397    break;
5398  }
5399  case ARM::t2LDMIA_UPD: {
5400    if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
5401      return Error(Operands[4]->getStartLoc(),
5402                   "writeback operator '!' not allowed when base register "
5403                   "in register list");
5404    break;
5405  }
5406  case ARM::tMUL: {
5407    // The second source operand must be the same register as the destination
5408    // operand.
5409    //
5410    // In this case, we must directly check the parsed operands because the
5411    // cvtThumbMultiply() function is written in such a way that it guarantees
5412    // this first statement is always true for the new Inst.  Essentially, the
5413    // destination is unconditionally copied into the second source operand
5414    // without checking to see if it matches what we actually parsed.
5415    if (Operands.size() == 6 &&
5416        (((ARMOperand*)Operands[3])->getReg() !=
5417         ((ARMOperand*)Operands[5])->getReg()) &&
5418        (((ARMOperand*)Operands[3])->getReg() !=
5419         ((ARMOperand*)Operands[4])->getReg())) {
5420      return Error(Operands[3]->getStartLoc(),
5421                   "destination register must match source register");
5422    }
5423    break;
5424  }
5425  // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
5426  // so only issue a diagnostic for thumb1. The instructions will be
5427  // switched to the t2 encodings in processInstruction() if necessary.
5428  case ARM::tPOP: {
5429    bool listContainsBase;
5430    if (checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase) &&
5431        !isThumbTwo())
5432      return Error(Operands[2]->getStartLoc(),
5433                   "registers must be in range r0-r7 or pc");
5434    break;
5435  }
5436  case ARM::tPUSH: {
5437    bool listContainsBase;
5438    if (checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase) &&
5439        !isThumbTwo())
5440      return Error(Operands[2]->getStartLoc(),
5441                   "registers must be in range r0-r7 or lr");
5442    break;
5443  }
5444  case ARM::tSTMIA_UPD: {
5445    bool listContainsBase;
5446    if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase) && !isThumbTwo())
5447      return Error(Operands[4]->getStartLoc(),
5448                   "registers must be in range r0-r7");
5449    break;
5450  }
5451  case ARM::tADDrSP: {
5452    // If the non-SP source operand and the destination operand are not the
5453    // same, we need thumb2 (for the wide encoding), or we have an error.
5454    if (!isThumbTwo() &&
5455        Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
5456      return Error(Operands[4]->getStartLoc(),
5457                   "source register must be the same as destination");
5458    }
5459    break;
5460  }
5461  }
5462
5463  return false;
5464}
5465
5466static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
5467  switch(Opc) {
5468  default: llvm_unreachable("unexpected opcode!");
5469  // VST1LN
5470  case ARM::VST1LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST1LNd8_UPD;
5471  case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5472  case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5473  case ARM::VST1LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST1LNd8_UPD;
5474  case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5475  case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5476  case ARM::VST1LNdAsm_8:  Spacing = 1; return ARM::VST1LNd8;
5477  case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
5478  case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
5479
5480  // VST2LN
5481  case ARM::VST2LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST2LNd8_UPD;
5482  case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5483  case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5484  case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5485  case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5486
5487  case ARM::VST2LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST2LNd8_UPD;
5488  case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5489  case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5490  case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5491  case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5492
5493  case ARM::VST2LNdAsm_8:  Spacing = 1; return ARM::VST2LNd8;
5494  case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
5495  case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
5496  case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
5497  case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
5498
5499  // VST3LN
5500  case ARM::VST3LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST3LNd8_UPD;
5501  case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5502  case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5503  case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
5504  case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5505  case ARM::VST3LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST3LNd8_UPD;
5506  case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5507  case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5508  case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
5509  case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5510  case ARM::VST3LNdAsm_8:  Spacing = 1; return ARM::VST3LNd8;
5511  case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
5512  case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
5513  case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
5514  case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
5515
5516  // VST3
5517  case ARM::VST3dWB_fixed_Asm_8:  Spacing = 1; return ARM::VST3d8_UPD;
5518  case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5519  case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5520  case ARM::VST3qWB_fixed_Asm_8:  Spacing = 2; return ARM::VST3q8_UPD;
5521  case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5522  case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5523  case ARM::VST3dWB_register_Asm_8:  Spacing = 1; return ARM::VST3d8_UPD;
5524  case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5525  case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5526  case ARM::VST3qWB_register_Asm_8:  Spacing = 2; return ARM::VST3q8_UPD;
5527  case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5528  case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5529  case ARM::VST3dAsm_8:  Spacing = 1; return ARM::VST3d8;
5530  case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
5531  case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
5532  case ARM::VST3qAsm_8:  Spacing = 2; return ARM::VST3q8;
5533  case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
5534  case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
5535
5536  // VST4LN
5537  case ARM::VST4LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST4LNd8_UPD;
5538  case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5539  case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5540  case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
5541  case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5542  case ARM::VST4LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST4LNd8_UPD;
5543  case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5544  case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5545  case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
5546  case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5547  case ARM::VST4LNdAsm_8:  Spacing = 1; return ARM::VST4LNd8;
5548  case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
5549  case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
5550  case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
5551  case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
5552
5553  // VST4
5554  case ARM::VST4dWB_fixed_Asm_8:  Spacing = 1; return ARM::VST4d8_UPD;
5555  case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5556  case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5557  case ARM::VST4qWB_fixed_Asm_8:  Spacing = 2; return ARM::VST4q8_UPD;
5558  case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5559  case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5560  case ARM::VST4dWB_register_Asm_8:  Spacing = 1; return ARM::VST4d8_UPD;
5561  case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5562  case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5563  case ARM::VST4qWB_register_Asm_8:  Spacing = 2; return ARM::VST4q8_UPD;
5564  case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5565  case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5566  case ARM::VST4dAsm_8:  Spacing = 1; return ARM::VST4d8;
5567  case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
5568  case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
5569  case ARM::VST4qAsm_8:  Spacing = 2; return ARM::VST4q8;
5570  case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
5571  case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
5572  }
5573}
5574
5575static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
5576  switch(Opc) {
5577  default: llvm_unreachable("unexpected opcode!");
5578  // VLD1LN
5579  case ARM::VLD1LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD1LNd8_UPD;
5580  case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5581  case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5582  case ARM::VLD1LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD1LNd8_UPD;
5583  case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5584  case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5585  case ARM::VLD1LNdAsm_8:  Spacing = 1; return ARM::VLD1LNd8;
5586  case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
5587  case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
5588
5589  // VLD2LN
5590  case ARM::VLD2LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD2LNd8_UPD;
5591  case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5592  case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5593  case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
5594  case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5595  case ARM::VLD2LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD2LNd8_UPD;
5596  case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5597  case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5598  case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
5599  case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5600  case ARM::VLD2LNdAsm_8:  Spacing = 1; return ARM::VLD2LNd8;
5601  case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
5602  case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
5603  case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
5604  case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
5605
5606  // VLD3DUP
5607  case ARM::VLD3DUPdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3DUPd8_UPD;
5608  case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5609  case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5610  case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
5611  case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPq16_UPD;
5612  case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5613  case ARM::VLD3DUPdWB_register_Asm_8:  Spacing = 1; return ARM::VLD3DUPd8_UPD;
5614  case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5615  case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5616  case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
5617  case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
5618  case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5619  case ARM::VLD3DUPdAsm_8:  Spacing = 1; return ARM::VLD3DUPd8;
5620  case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
5621  case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
5622  case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
5623  case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
5624  case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
5625
5626  // VLD3LN
5627  case ARM::VLD3LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3LNd8_UPD;
5628  case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5629  case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5630  case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
5631  case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5632  case ARM::VLD3LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD3LNd8_UPD;
5633  case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5634  case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5635  case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
5636  case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5637  case ARM::VLD3LNdAsm_8:  Spacing = 1; return ARM::VLD3LNd8;
5638  case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
5639  case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
5640  case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
5641  case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
5642
5643  // VLD3
5644  case ARM::VLD3dWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3d8_UPD;
5645  case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5646  case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5647  case ARM::VLD3qWB_fixed_Asm_8:  Spacing = 2; return ARM::VLD3q8_UPD;
5648  case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5649  case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5650  case ARM::VLD3dWB_register_Asm_8:  Spacing = 1; return ARM::VLD3d8_UPD;
5651  case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5652  case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5653  case ARM::VLD3qWB_register_Asm_8:  Spacing = 2; return ARM::VLD3q8_UPD;
5654  case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5655  case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5656  case ARM::VLD3dAsm_8:  Spacing = 1; return ARM::VLD3d8;
5657  case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
5658  case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
5659  case ARM::VLD3qAsm_8:  Spacing = 2; return ARM::VLD3q8;
5660  case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
5661  case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
5662
5663  // VLD4LN
5664  case ARM::VLD4LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4LNd8_UPD;
5665  case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5666  case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5667  case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNq16_UPD;
5668  case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5669  case ARM::VLD4LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD4LNd8_UPD;
5670  case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5671  case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5672  case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
5673  case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5674  case ARM::VLD4LNdAsm_8:  Spacing = 1; return ARM::VLD4LNd8;
5675  case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
5676  case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
5677  case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
5678  case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
5679
5680  // VLD4DUP
5681  case ARM::VLD4DUPdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4DUPd8_UPD;
5682  case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5683  case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5684  case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
5685  case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
5686  case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5687  case ARM::VLD4DUPdWB_register_Asm_8:  Spacing = 1; return ARM::VLD4DUPd8_UPD;
5688  case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5689  case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5690  case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
5691  case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
5692  case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5693  case ARM::VLD4DUPdAsm_8:  Spacing = 1; return ARM::VLD4DUPd8;
5694  case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
5695  case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
5696  case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
5697  case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
5698  case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
5699
5700  // VLD4
5701  case ARM::VLD4dWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4d8_UPD;
5702  case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5703  case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5704  case ARM::VLD4qWB_fixed_Asm_8:  Spacing = 2; return ARM::VLD4q8_UPD;
5705  case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5706  case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5707  case ARM::VLD4dWB_register_Asm_8:  Spacing = 1; return ARM::VLD4d8_UPD;
5708  case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5709  case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5710  case ARM::VLD4qWB_register_Asm_8:  Spacing = 2; return ARM::VLD4q8_UPD;
5711  case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5712  case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5713  case ARM::VLD4dAsm_8:  Spacing = 1; return ARM::VLD4d8;
5714  case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
5715  case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
5716  case ARM::VLD4qAsm_8:  Spacing = 2; return ARM::VLD4q8;
5717  case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
5718  case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
5719  }
5720}
5721
5722bool ARMAsmParser::
5723processInstruction(MCInst &Inst,
5724                   const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5725  switch (Inst.getOpcode()) {
5726  // Alias for alternate form of 'ADR Rd, #imm' instruction.
5727  case ARM::ADDri: {
5728    if (Inst.getOperand(1).getReg() != ARM::PC ||
5729        Inst.getOperand(5).getReg() != 0)
5730      return false;
5731    MCInst TmpInst;
5732    TmpInst.setOpcode(ARM::ADR);
5733    TmpInst.addOperand(Inst.getOperand(0));
5734    TmpInst.addOperand(Inst.getOperand(2));
5735    TmpInst.addOperand(Inst.getOperand(3));
5736    TmpInst.addOperand(Inst.getOperand(4));
5737    Inst = TmpInst;
5738    return true;
5739  }
5740  // Aliases for alternate PC+imm syntax of LDR instructions.
5741  case ARM::t2LDRpcrel:
5742    // Select the narrow version if the immediate will fit.
5743    if (Inst.getOperand(1).getImm() > 0 &&
5744        Inst.getOperand(1).getImm() <= 0xff)
5745      Inst.setOpcode(ARM::tLDRpci);
5746    else
5747      Inst.setOpcode(ARM::t2LDRpci);
5748    return true;
5749  case ARM::t2LDRBpcrel:
5750    Inst.setOpcode(ARM::t2LDRBpci);
5751    return true;
5752  case ARM::t2LDRHpcrel:
5753    Inst.setOpcode(ARM::t2LDRHpci);
5754    return true;
5755  case ARM::t2LDRSBpcrel:
5756    Inst.setOpcode(ARM::t2LDRSBpci);
5757    return true;
5758  case ARM::t2LDRSHpcrel:
5759    Inst.setOpcode(ARM::t2LDRSHpci);
5760    return true;
5761  // Handle NEON VST complex aliases.
5762  case ARM::VST1LNdWB_register_Asm_8:
5763  case ARM::VST1LNdWB_register_Asm_16:
5764  case ARM::VST1LNdWB_register_Asm_32: {
5765    MCInst TmpInst;
5766    // Shuffle the operands around so the lane index operand is in the
5767    // right place.
5768    unsigned Spacing;
5769    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5770    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5771    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5772    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5773    TmpInst.addOperand(Inst.getOperand(4)); // Rm
5774    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5775    TmpInst.addOperand(Inst.getOperand(1)); // lane
5776    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5777    TmpInst.addOperand(Inst.getOperand(6));
5778    Inst = TmpInst;
5779    return true;
5780  }
5781
5782  case ARM::VST2LNdWB_register_Asm_8:
5783  case ARM::VST2LNdWB_register_Asm_16:
5784  case ARM::VST2LNdWB_register_Asm_32:
5785  case ARM::VST2LNqWB_register_Asm_16:
5786  case ARM::VST2LNqWB_register_Asm_32: {
5787    MCInst TmpInst;
5788    // Shuffle the operands around so the lane index operand is in the
5789    // right place.
5790    unsigned Spacing;
5791    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5792    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5793    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5794    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5795    TmpInst.addOperand(Inst.getOperand(4)); // Rm
5796    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5797    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5798                                            Spacing));
5799    TmpInst.addOperand(Inst.getOperand(1)); // lane
5800    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5801    TmpInst.addOperand(Inst.getOperand(6));
5802    Inst = TmpInst;
5803    return true;
5804  }
5805
5806  case ARM::VST3LNdWB_register_Asm_8:
5807  case ARM::VST3LNdWB_register_Asm_16:
5808  case ARM::VST3LNdWB_register_Asm_32:
5809  case ARM::VST3LNqWB_register_Asm_16:
5810  case ARM::VST3LNqWB_register_Asm_32: {
5811    MCInst TmpInst;
5812    // Shuffle the operands around so the lane index operand is in the
5813    // right place.
5814    unsigned Spacing;
5815    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5816    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5817    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5818    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5819    TmpInst.addOperand(Inst.getOperand(4)); // Rm
5820    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5821    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5822                                            Spacing));
5823    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5824                                            Spacing * 2));
5825    TmpInst.addOperand(Inst.getOperand(1)); // lane
5826    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5827    TmpInst.addOperand(Inst.getOperand(6));
5828    Inst = TmpInst;
5829    return true;
5830  }
5831
5832  case ARM::VST4LNdWB_register_Asm_8:
5833  case ARM::VST4LNdWB_register_Asm_16:
5834  case ARM::VST4LNdWB_register_Asm_32:
5835  case ARM::VST4LNqWB_register_Asm_16:
5836  case ARM::VST4LNqWB_register_Asm_32: {
5837    MCInst TmpInst;
5838    // Shuffle the operands around so the lane index operand is in the
5839    // right place.
5840    unsigned Spacing;
5841    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5842    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5843    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5844    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5845    TmpInst.addOperand(Inst.getOperand(4)); // Rm
5846    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5847    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5848                                            Spacing));
5849    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5850                                            Spacing * 2));
5851    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5852                                            Spacing * 3));
5853    TmpInst.addOperand(Inst.getOperand(1)); // lane
5854    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5855    TmpInst.addOperand(Inst.getOperand(6));
5856    Inst = TmpInst;
5857    return true;
5858  }
5859
5860  case ARM::VST1LNdWB_fixed_Asm_8:
5861  case ARM::VST1LNdWB_fixed_Asm_16:
5862  case ARM::VST1LNdWB_fixed_Asm_32: {
5863    MCInst TmpInst;
5864    // Shuffle the operands around so the lane index operand is in the
5865    // right place.
5866    unsigned Spacing;
5867    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5868    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5869    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5870    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5871    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5872    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5873    TmpInst.addOperand(Inst.getOperand(1)); // lane
5874    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5875    TmpInst.addOperand(Inst.getOperand(5));
5876    Inst = TmpInst;
5877    return true;
5878  }
5879
5880  case ARM::VST2LNdWB_fixed_Asm_8:
5881  case ARM::VST2LNdWB_fixed_Asm_16:
5882  case ARM::VST2LNdWB_fixed_Asm_32:
5883  case ARM::VST2LNqWB_fixed_Asm_16:
5884  case ARM::VST2LNqWB_fixed_Asm_32: {
5885    MCInst TmpInst;
5886    // Shuffle the operands around so the lane index operand is in the
5887    // right place.
5888    unsigned Spacing;
5889    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5890    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5891    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5892    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5893    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5894    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5895    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5896                                            Spacing));
5897    TmpInst.addOperand(Inst.getOperand(1)); // lane
5898    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5899    TmpInst.addOperand(Inst.getOperand(5));
5900    Inst = TmpInst;
5901    return true;
5902  }
5903
5904  case ARM::VST3LNdWB_fixed_Asm_8:
5905  case ARM::VST3LNdWB_fixed_Asm_16:
5906  case ARM::VST3LNdWB_fixed_Asm_32:
5907  case ARM::VST3LNqWB_fixed_Asm_16:
5908  case ARM::VST3LNqWB_fixed_Asm_32: {
5909    MCInst TmpInst;
5910    // Shuffle the operands around so the lane index operand is in the
5911    // right place.
5912    unsigned Spacing;
5913    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5914    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5915    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5916    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5917    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5918    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5919    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5920                                            Spacing));
5921    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5922                                            Spacing * 2));
5923    TmpInst.addOperand(Inst.getOperand(1)); // lane
5924    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5925    TmpInst.addOperand(Inst.getOperand(5));
5926    Inst = TmpInst;
5927    return true;
5928  }
5929
5930  case ARM::VST4LNdWB_fixed_Asm_8:
5931  case ARM::VST4LNdWB_fixed_Asm_16:
5932  case ARM::VST4LNdWB_fixed_Asm_32:
5933  case ARM::VST4LNqWB_fixed_Asm_16:
5934  case ARM::VST4LNqWB_fixed_Asm_32: {
5935    MCInst TmpInst;
5936    // Shuffle the operands around so the lane index operand is in the
5937    // right place.
5938    unsigned Spacing;
5939    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5940    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5941    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5942    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5943    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5944    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5945    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5946                                            Spacing));
5947    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5948                                            Spacing * 2));
5949    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5950                                            Spacing * 3));
5951    TmpInst.addOperand(Inst.getOperand(1)); // lane
5952    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5953    TmpInst.addOperand(Inst.getOperand(5));
5954    Inst = TmpInst;
5955    return true;
5956  }
5957
5958  case ARM::VST1LNdAsm_8:
5959  case ARM::VST1LNdAsm_16:
5960  case ARM::VST1LNdAsm_32: {
5961    MCInst TmpInst;
5962    // Shuffle the operands around so the lane index operand is in the
5963    // right place.
5964    unsigned Spacing;
5965    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5966    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5967    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5968    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5969    TmpInst.addOperand(Inst.getOperand(1)); // lane
5970    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5971    TmpInst.addOperand(Inst.getOperand(5));
5972    Inst = TmpInst;
5973    return true;
5974  }
5975
5976  case ARM::VST2LNdAsm_8:
5977  case ARM::VST2LNdAsm_16:
5978  case ARM::VST2LNdAsm_32:
5979  case ARM::VST2LNqAsm_16:
5980  case ARM::VST2LNqAsm_32: {
5981    MCInst TmpInst;
5982    // Shuffle the operands around so the lane index operand is in the
5983    // right place.
5984    unsigned Spacing;
5985    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5986    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5987    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5988    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5989    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5990                                            Spacing));
5991    TmpInst.addOperand(Inst.getOperand(1)); // lane
5992    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5993    TmpInst.addOperand(Inst.getOperand(5));
5994    Inst = TmpInst;
5995    return true;
5996  }
5997
5998  case ARM::VST3LNdAsm_8:
5999  case ARM::VST3LNdAsm_16:
6000  case ARM::VST3LNdAsm_32:
6001  case ARM::VST3LNqAsm_16:
6002  case ARM::VST3LNqAsm_32: {
6003    MCInst TmpInst;
6004    // Shuffle the operands around so the lane index operand is in the
6005    // right place.
6006    unsigned Spacing;
6007    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6008    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6009    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6010    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6011    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6012                                            Spacing));
6013    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6014                                            Spacing * 2));
6015    TmpInst.addOperand(Inst.getOperand(1)); // lane
6016    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6017    TmpInst.addOperand(Inst.getOperand(5));
6018    Inst = TmpInst;
6019    return true;
6020  }
6021
6022  case ARM::VST4LNdAsm_8:
6023  case ARM::VST4LNdAsm_16:
6024  case ARM::VST4LNdAsm_32:
6025  case ARM::VST4LNqAsm_16:
6026  case ARM::VST4LNqAsm_32: {
6027    MCInst TmpInst;
6028    // Shuffle the operands around so the lane index operand is in the
6029    // right place.
6030    unsigned Spacing;
6031    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6032    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6033    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6034    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6035    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6036                                            Spacing));
6037    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6038                                            Spacing * 2));
6039    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6040                                            Spacing * 3));
6041    TmpInst.addOperand(Inst.getOperand(1)); // lane
6042    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6043    TmpInst.addOperand(Inst.getOperand(5));
6044    Inst = TmpInst;
6045    return true;
6046  }
6047
6048  // Handle NEON VLD complex aliases.
6049  case ARM::VLD1LNdWB_register_Asm_8:
6050  case ARM::VLD1LNdWB_register_Asm_16:
6051  case ARM::VLD1LNdWB_register_Asm_32: {
6052    MCInst TmpInst;
6053    // Shuffle the operands around so the lane index operand is in the
6054    // right place.
6055    unsigned Spacing;
6056    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6057    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6058    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6059    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6060    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6061    TmpInst.addOperand(Inst.getOperand(4)); // Rm
6062    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6063    TmpInst.addOperand(Inst.getOperand(1)); // lane
6064    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6065    TmpInst.addOperand(Inst.getOperand(6));
6066    Inst = TmpInst;
6067    return true;
6068  }
6069
6070  case ARM::VLD2LNdWB_register_Asm_8:
6071  case ARM::VLD2LNdWB_register_Asm_16:
6072  case ARM::VLD2LNdWB_register_Asm_32:
6073  case ARM::VLD2LNqWB_register_Asm_16:
6074  case ARM::VLD2LNqWB_register_Asm_32: {
6075    MCInst TmpInst;
6076    // Shuffle the operands around so the lane index operand is in the
6077    // right place.
6078    unsigned Spacing;
6079    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6080    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6081    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6082                                            Spacing));
6083    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6084    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6085    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6086    TmpInst.addOperand(Inst.getOperand(4)); // Rm
6087    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6088    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6089                                            Spacing));
6090    TmpInst.addOperand(Inst.getOperand(1)); // lane
6091    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6092    TmpInst.addOperand(Inst.getOperand(6));
6093    Inst = TmpInst;
6094    return true;
6095  }
6096
6097  case ARM::VLD3LNdWB_register_Asm_8:
6098  case ARM::VLD3LNdWB_register_Asm_16:
6099  case ARM::VLD3LNdWB_register_Asm_32:
6100  case ARM::VLD3LNqWB_register_Asm_16:
6101  case ARM::VLD3LNqWB_register_Asm_32: {
6102    MCInst TmpInst;
6103    // Shuffle the operands around so the lane index operand is in the
6104    // right place.
6105    unsigned Spacing;
6106    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6107    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6108    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6109                                            Spacing));
6110    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6111                                            Spacing * 2));
6112    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6113    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6114    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6115    TmpInst.addOperand(Inst.getOperand(4)); // Rm
6116    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6117    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6118                                            Spacing));
6119    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6120                                            Spacing * 2));
6121    TmpInst.addOperand(Inst.getOperand(1)); // lane
6122    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6123    TmpInst.addOperand(Inst.getOperand(6));
6124    Inst = TmpInst;
6125    return true;
6126  }
6127
6128  case ARM::VLD4LNdWB_register_Asm_8:
6129  case ARM::VLD4LNdWB_register_Asm_16:
6130  case ARM::VLD4LNdWB_register_Asm_32:
6131  case ARM::VLD4LNqWB_register_Asm_16:
6132  case ARM::VLD4LNqWB_register_Asm_32: {
6133    MCInst TmpInst;
6134    // Shuffle the operands around so the lane index operand is in the
6135    // right place.
6136    unsigned Spacing;
6137    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6138    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6139    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6140                                            Spacing));
6141    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6142                                            Spacing * 2));
6143    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6144                                            Spacing * 3));
6145    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6146    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6147    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6148    TmpInst.addOperand(Inst.getOperand(4)); // Rm
6149    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6150    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6151                                            Spacing));
6152    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6153                                            Spacing * 2));
6154    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6155                                            Spacing * 3));
6156    TmpInst.addOperand(Inst.getOperand(1)); // lane
6157    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6158    TmpInst.addOperand(Inst.getOperand(6));
6159    Inst = TmpInst;
6160    return true;
6161  }
6162
6163  case ARM::VLD1LNdWB_fixed_Asm_8:
6164  case ARM::VLD1LNdWB_fixed_Asm_16:
6165  case ARM::VLD1LNdWB_fixed_Asm_32: {
6166    MCInst TmpInst;
6167    // Shuffle the operands around so the lane index operand is in the
6168    // right place.
6169    unsigned Spacing;
6170    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6171    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6172    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6173    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6174    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6175    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6176    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6177    TmpInst.addOperand(Inst.getOperand(1)); // lane
6178    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6179    TmpInst.addOperand(Inst.getOperand(5));
6180    Inst = TmpInst;
6181    return true;
6182  }
6183
6184  case ARM::VLD2LNdWB_fixed_Asm_8:
6185  case ARM::VLD2LNdWB_fixed_Asm_16:
6186  case ARM::VLD2LNdWB_fixed_Asm_32:
6187  case ARM::VLD2LNqWB_fixed_Asm_16:
6188  case ARM::VLD2LNqWB_fixed_Asm_32: {
6189    MCInst TmpInst;
6190    // Shuffle the operands around so the lane index operand is in the
6191    // right place.
6192    unsigned Spacing;
6193    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6194    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6195    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6196                                            Spacing));
6197    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6198    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6199    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6200    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6201    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6202    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6203                                            Spacing));
6204    TmpInst.addOperand(Inst.getOperand(1)); // lane
6205    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6206    TmpInst.addOperand(Inst.getOperand(5));
6207    Inst = TmpInst;
6208    return true;
6209  }
6210
6211  case ARM::VLD3LNdWB_fixed_Asm_8:
6212  case ARM::VLD3LNdWB_fixed_Asm_16:
6213  case ARM::VLD3LNdWB_fixed_Asm_32:
6214  case ARM::VLD3LNqWB_fixed_Asm_16:
6215  case ARM::VLD3LNqWB_fixed_Asm_32: {
6216    MCInst TmpInst;
6217    // Shuffle the operands around so the lane index operand is in the
6218    // right place.
6219    unsigned Spacing;
6220    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6221    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6222    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6223                                            Spacing));
6224    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6225                                            Spacing * 2));
6226    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6227    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6228    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6229    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6230    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6231    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6232                                            Spacing));
6233    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6234                                            Spacing * 2));
6235    TmpInst.addOperand(Inst.getOperand(1)); // lane
6236    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6237    TmpInst.addOperand(Inst.getOperand(5));
6238    Inst = TmpInst;
6239    return true;
6240  }
6241
6242  case ARM::VLD4LNdWB_fixed_Asm_8:
6243  case ARM::VLD4LNdWB_fixed_Asm_16:
6244  case ARM::VLD4LNdWB_fixed_Asm_32:
6245  case ARM::VLD4LNqWB_fixed_Asm_16:
6246  case ARM::VLD4LNqWB_fixed_Asm_32: {
6247    MCInst TmpInst;
6248    // Shuffle the operands around so the lane index operand is in the
6249    // right place.
6250    unsigned Spacing;
6251    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6252    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6253    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6254                                            Spacing));
6255    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6256                                            Spacing * 2));
6257    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6258                                            Spacing * 3));
6259    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6260    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6261    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6262    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6263    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6264    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6265                                            Spacing));
6266    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6267                                            Spacing * 2));
6268    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6269                                            Spacing * 3));
6270    TmpInst.addOperand(Inst.getOperand(1)); // lane
6271    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6272    TmpInst.addOperand(Inst.getOperand(5));
6273    Inst = TmpInst;
6274    return true;
6275  }
6276
6277  case ARM::VLD1LNdAsm_8:
6278  case ARM::VLD1LNdAsm_16:
6279  case ARM::VLD1LNdAsm_32: {
6280    MCInst TmpInst;
6281    // Shuffle the operands around so the lane index operand is in the
6282    // right place.
6283    unsigned Spacing;
6284    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6285    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6286    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6287    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6288    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6289    TmpInst.addOperand(Inst.getOperand(1)); // lane
6290    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6291    TmpInst.addOperand(Inst.getOperand(5));
6292    Inst = TmpInst;
6293    return true;
6294  }
6295
6296  case ARM::VLD2LNdAsm_8:
6297  case ARM::VLD2LNdAsm_16:
6298  case ARM::VLD2LNdAsm_32:
6299  case ARM::VLD2LNqAsm_16:
6300  case ARM::VLD2LNqAsm_32: {
6301    MCInst TmpInst;
6302    // Shuffle the operands around so the lane index operand is in the
6303    // right place.
6304    unsigned Spacing;
6305    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6306    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6307    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6308                                            Spacing));
6309    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6310    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6311    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6312    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6313                                            Spacing));
6314    TmpInst.addOperand(Inst.getOperand(1)); // lane
6315    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6316    TmpInst.addOperand(Inst.getOperand(5));
6317    Inst = TmpInst;
6318    return true;
6319  }
6320
6321  case ARM::VLD3LNdAsm_8:
6322  case ARM::VLD3LNdAsm_16:
6323  case ARM::VLD3LNdAsm_32:
6324  case ARM::VLD3LNqAsm_16:
6325  case ARM::VLD3LNqAsm_32: {
6326    MCInst TmpInst;
6327    // Shuffle the operands around so the lane index operand is in the
6328    // right place.
6329    unsigned Spacing;
6330    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6331    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6332    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6333                                            Spacing));
6334    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6335                                            Spacing * 2));
6336    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6337    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6338    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6339    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6340                                            Spacing));
6341    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6342                                            Spacing * 2));
6343    TmpInst.addOperand(Inst.getOperand(1)); // lane
6344    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6345    TmpInst.addOperand(Inst.getOperand(5));
6346    Inst = TmpInst;
6347    return true;
6348  }
6349
6350  case ARM::VLD4LNdAsm_8:
6351  case ARM::VLD4LNdAsm_16:
6352  case ARM::VLD4LNdAsm_32:
6353  case ARM::VLD4LNqAsm_16:
6354  case ARM::VLD4LNqAsm_32: {
6355    MCInst TmpInst;
6356    // Shuffle the operands around so the lane index operand is in the
6357    // right place.
6358    unsigned Spacing;
6359    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6360    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6361    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6362                                            Spacing));
6363    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6364                                            Spacing * 2));
6365    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6366                                            Spacing * 3));
6367    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6368    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6369    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6370    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6371                                            Spacing));
6372    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6373                                            Spacing * 2));
6374    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6375                                            Spacing * 3));
6376    TmpInst.addOperand(Inst.getOperand(1)); // lane
6377    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6378    TmpInst.addOperand(Inst.getOperand(5));
6379    Inst = TmpInst;
6380    return true;
6381  }
6382
6383  // VLD3DUP single 3-element structure to all lanes instructions.
6384  case ARM::VLD3DUPdAsm_8:
6385  case ARM::VLD3DUPdAsm_16:
6386  case ARM::VLD3DUPdAsm_32:
6387  case ARM::VLD3DUPqAsm_8:
6388  case ARM::VLD3DUPqAsm_16:
6389  case ARM::VLD3DUPqAsm_32: {
6390    MCInst TmpInst;
6391    unsigned Spacing;
6392    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6393    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6394    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6395                                            Spacing));
6396    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6397                                            Spacing * 2));
6398    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6399    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6400    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6401    TmpInst.addOperand(Inst.getOperand(4));
6402    Inst = TmpInst;
6403    return true;
6404  }
6405
6406  case ARM::VLD3DUPdWB_fixed_Asm_8:
6407  case ARM::VLD3DUPdWB_fixed_Asm_16:
6408  case ARM::VLD3DUPdWB_fixed_Asm_32:
6409  case ARM::VLD3DUPqWB_fixed_Asm_8:
6410  case ARM::VLD3DUPqWB_fixed_Asm_16:
6411  case ARM::VLD3DUPqWB_fixed_Asm_32: {
6412    MCInst TmpInst;
6413    unsigned Spacing;
6414    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6415    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6416    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6417                                            Spacing));
6418    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6419                                            Spacing * 2));
6420    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6421    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6422    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6423    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6424    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6425    TmpInst.addOperand(Inst.getOperand(4));
6426    Inst = TmpInst;
6427    return true;
6428  }
6429
6430  case ARM::VLD3DUPdWB_register_Asm_8:
6431  case ARM::VLD3DUPdWB_register_Asm_16:
6432  case ARM::VLD3DUPdWB_register_Asm_32:
6433  case ARM::VLD3DUPqWB_register_Asm_8:
6434  case ARM::VLD3DUPqWB_register_Asm_16:
6435  case ARM::VLD3DUPqWB_register_Asm_32: {
6436    MCInst TmpInst;
6437    unsigned Spacing;
6438    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6439    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6440    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6441                                            Spacing));
6442    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6443                                            Spacing * 2));
6444    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6445    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6446    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6447    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6448    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6449    TmpInst.addOperand(Inst.getOperand(5));
6450    Inst = TmpInst;
6451    return true;
6452  }
6453
6454  // VLD3 multiple 3-element structure instructions.
6455  case ARM::VLD3dAsm_8:
6456  case ARM::VLD3dAsm_16:
6457  case ARM::VLD3dAsm_32:
6458  case ARM::VLD3qAsm_8:
6459  case ARM::VLD3qAsm_16:
6460  case ARM::VLD3qAsm_32: {
6461    MCInst TmpInst;
6462    unsigned Spacing;
6463    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6464    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6465    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6466                                            Spacing));
6467    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6468                                            Spacing * 2));
6469    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6470    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6471    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6472    TmpInst.addOperand(Inst.getOperand(4));
6473    Inst = TmpInst;
6474    return true;
6475  }
6476
6477  case ARM::VLD3dWB_fixed_Asm_8:
6478  case ARM::VLD3dWB_fixed_Asm_16:
6479  case ARM::VLD3dWB_fixed_Asm_32:
6480  case ARM::VLD3qWB_fixed_Asm_8:
6481  case ARM::VLD3qWB_fixed_Asm_16:
6482  case ARM::VLD3qWB_fixed_Asm_32: {
6483    MCInst TmpInst;
6484    unsigned Spacing;
6485    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6486    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6487    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6488                                            Spacing));
6489    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6490                                            Spacing * 2));
6491    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6492    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6493    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6494    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6495    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6496    TmpInst.addOperand(Inst.getOperand(4));
6497    Inst = TmpInst;
6498    return true;
6499  }
6500
6501  case ARM::VLD3dWB_register_Asm_8:
6502  case ARM::VLD3dWB_register_Asm_16:
6503  case ARM::VLD3dWB_register_Asm_32:
6504  case ARM::VLD3qWB_register_Asm_8:
6505  case ARM::VLD3qWB_register_Asm_16:
6506  case ARM::VLD3qWB_register_Asm_32: {
6507    MCInst TmpInst;
6508    unsigned Spacing;
6509    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6510    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6511    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6512                                            Spacing));
6513    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6514                                            Spacing * 2));
6515    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6516    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6517    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6518    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6519    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6520    TmpInst.addOperand(Inst.getOperand(5));
6521    Inst = TmpInst;
6522    return true;
6523  }
6524
6525  // VLD4DUP single 3-element structure to all lanes instructions.
6526  case ARM::VLD4DUPdAsm_8:
6527  case ARM::VLD4DUPdAsm_16:
6528  case ARM::VLD4DUPdAsm_32:
6529  case ARM::VLD4DUPqAsm_8:
6530  case ARM::VLD4DUPqAsm_16:
6531  case ARM::VLD4DUPqAsm_32: {
6532    MCInst TmpInst;
6533    unsigned Spacing;
6534    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6535    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6536    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6537                                            Spacing));
6538    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6539                                            Spacing * 2));
6540    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6541                                            Spacing * 3));
6542    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6543    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6544    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6545    TmpInst.addOperand(Inst.getOperand(4));
6546    Inst = TmpInst;
6547    return true;
6548  }
6549
6550  case ARM::VLD4DUPdWB_fixed_Asm_8:
6551  case ARM::VLD4DUPdWB_fixed_Asm_16:
6552  case ARM::VLD4DUPdWB_fixed_Asm_32:
6553  case ARM::VLD4DUPqWB_fixed_Asm_8:
6554  case ARM::VLD4DUPqWB_fixed_Asm_16:
6555  case ARM::VLD4DUPqWB_fixed_Asm_32: {
6556    MCInst TmpInst;
6557    unsigned Spacing;
6558    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6559    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6560    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6561                                            Spacing));
6562    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6563                                            Spacing * 2));
6564    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6565                                            Spacing * 3));
6566    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6567    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6568    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6569    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6570    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6571    TmpInst.addOperand(Inst.getOperand(4));
6572    Inst = TmpInst;
6573    return true;
6574  }
6575
6576  case ARM::VLD4DUPdWB_register_Asm_8:
6577  case ARM::VLD4DUPdWB_register_Asm_16:
6578  case ARM::VLD4DUPdWB_register_Asm_32:
6579  case ARM::VLD4DUPqWB_register_Asm_8:
6580  case ARM::VLD4DUPqWB_register_Asm_16:
6581  case ARM::VLD4DUPqWB_register_Asm_32: {
6582    MCInst TmpInst;
6583    unsigned Spacing;
6584    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6585    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6586    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6587                                            Spacing));
6588    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6589                                            Spacing * 2));
6590    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6591                                            Spacing * 3));
6592    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6593    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6594    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6595    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6596    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6597    TmpInst.addOperand(Inst.getOperand(5));
6598    Inst = TmpInst;
6599    return true;
6600  }
6601
6602  // VLD4 multiple 4-element structure instructions.
6603  case ARM::VLD4dAsm_8:
6604  case ARM::VLD4dAsm_16:
6605  case ARM::VLD4dAsm_32:
6606  case ARM::VLD4qAsm_8:
6607  case ARM::VLD4qAsm_16:
6608  case ARM::VLD4qAsm_32: {
6609    MCInst TmpInst;
6610    unsigned Spacing;
6611    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6612    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6613    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6614                                            Spacing));
6615    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6616                                            Spacing * 2));
6617    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6618                                            Spacing * 3));
6619    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6620    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6621    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6622    TmpInst.addOperand(Inst.getOperand(4));
6623    Inst = TmpInst;
6624    return true;
6625  }
6626
6627  case ARM::VLD4dWB_fixed_Asm_8:
6628  case ARM::VLD4dWB_fixed_Asm_16:
6629  case ARM::VLD4dWB_fixed_Asm_32:
6630  case ARM::VLD4qWB_fixed_Asm_8:
6631  case ARM::VLD4qWB_fixed_Asm_16:
6632  case ARM::VLD4qWB_fixed_Asm_32: {
6633    MCInst TmpInst;
6634    unsigned Spacing;
6635    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6636    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6637    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6638                                            Spacing));
6639    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6640                                            Spacing * 2));
6641    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6642                                            Spacing * 3));
6643    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6644    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6645    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6646    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6647    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6648    TmpInst.addOperand(Inst.getOperand(4));
6649    Inst = TmpInst;
6650    return true;
6651  }
6652
6653  case ARM::VLD4dWB_register_Asm_8:
6654  case ARM::VLD4dWB_register_Asm_16:
6655  case ARM::VLD4dWB_register_Asm_32:
6656  case ARM::VLD4qWB_register_Asm_8:
6657  case ARM::VLD4qWB_register_Asm_16:
6658  case ARM::VLD4qWB_register_Asm_32: {
6659    MCInst TmpInst;
6660    unsigned Spacing;
6661    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6662    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6663    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6664                                            Spacing));
6665    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6666                                            Spacing * 2));
6667    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6668                                            Spacing * 3));
6669    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6670    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6671    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6672    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6673    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6674    TmpInst.addOperand(Inst.getOperand(5));
6675    Inst = TmpInst;
6676    return true;
6677  }
6678
6679  // VST3 multiple 3-element structure instructions.
6680  case ARM::VST3dAsm_8:
6681  case ARM::VST3dAsm_16:
6682  case ARM::VST3dAsm_32:
6683  case ARM::VST3qAsm_8:
6684  case ARM::VST3qAsm_16:
6685  case ARM::VST3qAsm_32: {
6686    MCInst TmpInst;
6687    unsigned Spacing;
6688    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6689    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6690    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6691    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6692    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6693                                            Spacing));
6694    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6695                                            Spacing * 2));
6696    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6697    TmpInst.addOperand(Inst.getOperand(4));
6698    Inst = TmpInst;
6699    return true;
6700  }
6701
6702  case ARM::VST3dWB_fixed_Asm_8:
6703  case ARM::VST3dWB_fixed_Asm_16:
6704  case ARM::VST3dWB_fixed_Asm_32:
6705  case ARM::VST3qWB_fixed_Asm_8:
6706  case ARM::VST3qWB_fixed_Asm_16:
6707  case ARM::VST3qWB_fixed_Asm_32: {
6708    MCInst TmpInst;
6709    unsigned Spacing;
6710    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6711    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6712    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6713    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6714    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6715    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6716    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6717                                            Spacing));
6718    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6719                                            Spacing * 2));
6720    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6721    TmpInst.addOperand(Inst.getOperand(4));
6722    Inst = TmpInst;
6723    return true;
6724  }
6725
6726  case ARM::VST3dWB_register_Asm_8:
6727  case ARM::VST3dWB_register_Asm_16:
6728  case ARM::VST3dWB_register_Asm_32:
6729  case ARM::VST3qWB_register_Asm_8:
6730  case ARM::VST3qWB_register_Asm_16:
6731  case ARM::VST3qWB_register_Asm_32: {
6732    MCInst TmpInst;
6733    unsigned Spacing;
6734    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6735    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6736    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6737    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6738    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6739    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6740    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6741                                            Spacing));
6742    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6743                                            Spacing * 2));
6744    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6745    TmpInst.addOperand(Inst.getOperand(5));
6746    Inst = TmpInst;
6747    return true;
6748  }
6749
6750  // VST4 multiple 3-element structure instructions.
6751  case ARM::VST4dAsm_8:
6752  case ARM::VST4dAsm_16:
6753  case ARM::VST4dAsm_32:
6754  case ARM::VST4qAsm_8:
6755  case ARM::VST4qAsm_16:
6756  case ARM::VST4qAsm_32: {
6757    MCInst TmpInst;
6758    unsigned Spacing;
6759    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6760    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6761    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6762    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6763    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6764                                            Spacing));
6765    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6766                                            Spacing * 2));
6767    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6768                                            Spacing * 3));
6769    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6770    TmpInst.addOperand(Inst.getOperand(4));
6771    Inst = TmpInst;
6772    return true;
6773  }
6774
6775  case ARM::VST4dWB_fixed_Asm_8:
6776  case ARM::VST4dWB_fixed_Asm_16:
6777  case ARM::VST4dWB_fixed_Asm_32:
6778  case ARM::VST4qWB_fixed_Asm_8:
6779  case ARM::VST4qWB_fixed_Asm_16:
6780  case ARM::VST4qWB_fixed_Asm_32: {
6781    MCInst TmpInst;
6782    unsigned Spacing;
6783    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6784    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6785    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6786    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6787    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6788    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6789    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6790                                            Spacing));
6791    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6792                                            Spacing * 2));
6793    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6794                                            Spacing * 3));
6795    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6796    TmpInst.addOperand(Inst.getOperand(4));
6797    Inst = TmpInst;
6798    return true;
6799  }
6800
6801  case ARM::VST4dWB_register_Asm_8:
6802  case ARM::VST4dWB_register_Asm_16:
6803  case ARM::VST4dWB_register_Asm_32:
6804  case ARM::VST4qWB_register_Asm_8:
6805  case ARM::VST4qWB_register_Asm_16:
6806  case ARM::VST4qWB_register_Asm_32: {
6807    MCInst TmpInst;
6808    unsigned Spacing;
6809    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6810    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6811    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6812    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6813    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6814    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6815    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6816                                            Spacing));
6817    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6818                                            Spacing * 2));
6819    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6820                                            Spacing * 3));
6821    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6822    TmpInst.addOperand(Inst.getOperand(5));
6823    Inst = TmpInst;
6824    return true;
6825  }
6826
6827  // Handle encoding choice for the shift-immediate instructions.
6828  case ARM::t2LSLri:
6829  case ARM::t2LSRri:
6830  case ARM::t2ASRri: {
6831    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6832        Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
6833        Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
6834        !(static_cast<ARMOperand*>(Operands[3])->isToken() &&
6835         static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) {
6836      unsigned NewOpc;
6837      switch (Inst.getOpcode()) {
6838      default: llvm_unreachable("unexpected opcode");
6839      case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
6840      case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
6841      case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
6842      }
6843      // The Thumb1 operands aren't in the same order. Awesome, eh?
6844      MCInst TmpInst;
6845      TmpInst.setOpcode(NewOpc);
6846      TmpInst.addOperand(Inst.getOperand(0));
6847      TmpInst.addOperand(Inst.getOperand(5));
6848      TmpInst.addOperand(Inst.getOperand(1));
6849      TmpInst.addOperand(Inst.getOperand(2));
6850      TmpInst.addOperand(Inst.getOperand(3));
6851      TmpInst.addOperand(Inst.getOperand(4));
6852      Inst = TmpInst;
6853      return true;
6854    }
6855    return false;
6856  }
6857
6858  // Handle the Thumb2 mode MOV complex aliases.
6859  case ARM::t2MOVsr:
6860  case ARM::t2MOVSsr: {
6861    // Which instruction to expand to depends on the CCOut operand and
6862    // whether we're in an IT block if the register operands are low
6863    // registers.
6864    bool isNarrow = false;
6865    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6866        isARMLowRegister(Inst.getOperand(1).getReg()) &&
6867        isARMLowRegister(Inst.getOperand(2).getReg()) &&
6868        Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
6869        inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
6870      isNarrow = true;
6871    MCInst TmpInst;
6872    unsigned newOpc;
6873    switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
6874    default: llvm_unreachable("unexpected opcode!");
6875    case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
6876    case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
6877    case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
6878    case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR   : ARM::t2RORrr; break;
6879    }
6880    TmpInst.setOpcode(newOpc);
6881    TmpInst.addOperand(Inst.getOperand(0)); // Rd
6882    if (isNarrow)
6883      TmpInst.addOperand(MCOperand::CreateReg(
6884          Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
6885    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6886    TmpInst.addOperand(Inst.getOperand(2)); // Rm
6887    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6888    TmpInst.addOperand(Inst.getOperand(5));
6889    if (!isNarrow)
6890      TmpInst.addOperand(MCOperand::CreateReg(
6891          Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
6892    Inst = TmpInst;
6893    return true;
6894  }
6895  case ARM::t2MOVsi:
6896  case ARM::t2MOVSsi: {
6897    // Which instruction to expand to depends on the CCOut operand and
6898    // whether we're in an IT block if the register operands are low
6899    // registers.
6900    bool isNarrow = false;
6901    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6902        isARMLowRegister(Inst.getOperand(1).getReg()) &&
6903        inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
6904      isNarrow = true;
6905    MCInst TmpInst;
6906    unsigned newOpc;
6907    switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
6908    default: llvm_unreachable("unexpected opcode!");
6909    case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
6910    case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
6911    case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
6912    case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
6913    case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
6914    }
6915    unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
6916    if (Amount == 32) Amount = 0;
6917    TmpInst.setOpcode(newOpc);
6918    TmpInst.addOperand(Inst.getOperand(0)); // Rd
6919    if (isNarrow)
6920      TmpInst.addOperand(MCOperand::CreateReg(
6921          Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
6922    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6923    if (newOpc != ARM::t2RRX)
6924      TmpInst.addOperand(MCOperand::CreateImm(Amount));
6925    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6926    TmpInst.addOperand(Inst.getOperand(4));
6927    if (!isNarrow)
6928      TmpInst.addOperand(MCOperand::CreateReg(
6929          Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
6930    Inst = TmpInst;
6931    return true;
6932  }
6933  // Handle the ARM mode MOV complex aliases.
6934  case ARM::ASRr:
6935  case ARM::LSRr:
6936  case ARM::LSLr:
6937  case ARM::RORr: {
6938    ARM_AM::ShiftOpc ShiftTy;
6939    switch(Inst.getOpcode()) {
6940    default: llvm_unreachable("unexpected opcode!");
6941    case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
6942    case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
6943    case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
6944    case ARM::RORr: ShiftTy = ARM_AM::ror; break;
6945    }
6946    unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
6947    MCInst TmpInst;
6948    TmpInst.setOpcode(ARM::MOVsr);
6949    TmpInst.addOperand(Inst.getOperand(0)); // Rd
6950    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6951    TmpInst.addOperand(Inst.getOperand(2)); // Rm
6952    TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
6953    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6954    TmpInst.addOperand(Inst.getOperand(4));
6955    TmpInst.addOperand(Inst.getOperand(5)); // cc_out
6956    Inst = TmpInst;
6957    return true;
6958  }
6959  case ARM::ASRi:
6960  case ARM::LSRi:
6961  case ARM::LSLi:
6962  case ARM::RORi: {
6963    ARM_AM::ShiftOpc ShiftTy;
6964    switch(Inst.getOpcode()) {
6965    default: llvm_unreachable("unexpected opcode!");
6966    case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
6967    case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
6968    case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
6969    case ARM::RORi: ShiftTy = ARM_AM::ror; break;
6970    }
6971    // A shift by zero is a plain MOVr, not a MOVsi.
6972    unsigned Amt = Inst.getOperand(2).getImm();
6973    unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
6974    // A shift by 32 should be encoded as 0 when permitted
6975    if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
6976      Amt = 0;
6977    unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
6978    MCInst TmpInst;
6979    TmpInst.setOpcode(Opc);
6980    TmpInst.addOperand(Inst.getOperand(0)); // Rd
6981    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6982    if (Opc == ARM::MOVsi)
6983      TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
6984    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6985    TmpInst.addOperand(Inst.getOperand(4));
6986    TmpInst.addOperand(Inst.getOperand(5)); // cc_out
6987    Inst = TmpInst;
6988    return true;
6989  }
6990  case ARM::RRXi: {
6991    unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
6992    MCInst TmpInst;
6993    TmpInst.setOpcode(ARM::MOVsi);
6994    TmpInst.addOperand(Inst.getOperand(0)); // Rd
6995    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6996    TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
6997    TmpInst.addOperand(Inst.getOperand(2)); // CondCode
6998    TmpInst.addOperand(Inst.getOperand(3));
6999    TmpInst.addOperand(Inst.getOperand(4)); // cc_out
7000    Inst = TmpInst;
7001    return true;
7002  }
7003  case ARM::t2LDMIA_UPD: {
7004    // If this is a load of a single register, then we should use
7005    // a post-indexed LDR instruction instead, per the ARM ARM.
7006    if (Inst.getNumOperands() != 5)
7007      return false;
7008    MCInst TmpInst;
7009    TmpInst.setOpcode(ARM::t2LDR_POST);
7010    TmpInst.addOperand(Inst.getOperand(4)); // Rt
7011    TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7012    TmpInst.addOperand(Inst.getOperand(1)); // Rn
7013    TmpInst.addOperand(MCOperand::CreateImm(4));
7014    TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7015    TmpInst.addOperand(Inst.getOperand(3));
7016    Inst = TmpInst;
7017    return true;
7018  }
7019  case ARM::t2STMDB_UPD: {
7020    // If this is a store of a single register, then we should use
7021    // a pre-indexed STR instruction instead, per the ARM ARM.
7022    if (Inst.getNumOperands() != 5)
7023      return false;
7024    MCInst TmpInst;
7025    TmpInst.setOpcode(ARM::t2STR_PRE);
7026    TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7027    TmpInst.addOperand(Inst.getOperand(4)); // Rt
7028    TmpInst.addOperand(Inst.getOperand(1)); // Rn
7029    TmpInst.addOperand(MCOperand::CreateImm(-4));
7030    TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7031    TmpInst.addOperand(Inst.getOperand(3));
7032    Inst = TmpInst;
7033    return true;
7034  }
7035  case ARM::LDMIA_UPD:
7036    // If this is a load of a single register via a 'pop', then we should use
7037    // a post-indexed LDR instruction instead, per the ARM ARM.
7038    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
7039        Inst.getNumOperands() == 5) {
7040      MCInst TmpInst;
7041      TmpInst.setOpcode(ARM::LDR_POST_IMM);
7042      TmpInst.addOperand(Inst.getOperand(4)); // Rt
7043      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7044      TmpInst.addOperand(Inst.getOperand(1)); // Rn
7045      TmpInst.addOperand(MCOperand::CreateReg(0));  // am2offset
7046      TmpInst.addOperand(MCOperand::CreateImm(4));
7047      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7048      TmpInst.addOperand(Inst.getOperand(3));
7049      Inst = TmpInst;
7050      return true;
7051    }
7052    break;
7053  case ARM::STMDB_UPD:
7054    // If this is a store of a single register via a 'push', then we should use
7055    // a pre-indexed STR instruction instead, per the ARM ARM.
7056    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
7057        Inst.getNumOperands() == 5) {
7058      MCInst TmpInst;
7059      TmpInst.setOpcode(ARM::STR_PRE_IMM);
7060      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7061      TmpInst.addOperand(Inst.getOperand(4)); // Rt
7062      TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
7063      TmpInst.addOperand(MCOperand::CreateImm(-4));
7064      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7065      TmpInst.addOperand(Inst.getOperand(3));
7066      Inst = TmpInst;
7067    }
7068    break;
7069  case ARM::t2ADDri12:
7070    // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
7071    // mnemonic was used (not "addw"), encoding T3 is preferred.
7072    if (static_cast<ARMOperand*>(Operands[0])->getToken() != "add" ||
7073        ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7074      break;
7075    Inst.setOpcode(ARM::t2ADDri);
7076    Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7077    break;
7078  case ARM::t2SUBri12:
7079    // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
7080    // mnemonic was used (not "subw"), encoding T3 is preferred.
7081    if (static_cast<ARMOperand*>(Operands[0])->getToken() != "sub" ||
7082        ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7083      break;
7084    Inst.setOpcode(ARM::t2SUBri);
7085    Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7086    break;
7087  case ARM::tADDi8:
7088    // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7089    // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7090    // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7091    // to encoding T1 if <Rd> is omitted."
7092    if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7093      Inst.setOpcode(ARM::tADDi3);
7094      return true;
7095    }
7096    break;
7097  case ARM::tSUBi8:
7098    // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7099    // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7100    // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7101    // to encoding T1 if <Rd> is omitted."
7102    if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7103      Inst.setOpcode(ARM::tSUBi3);
7104      return true;
7105    }
7106    break;
7107  case ARM::t2ADDri:
7108  case ARM::t2SUBri: {
7109    // If the destination and first source operand are the same, and
7110    // the flags are compatible with the current IT status, use encoding T2
7111    // instead of T3. For compatibility with the system 'as'. Make sure the
7112    // wide encoding wasn't explicit.
7113    if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7114        !isARMLowRegister(Inst.getOperand(0).getReg()) ||
7115        (unsigned)Inst.getOperand(2).getImm() > 255 ||
7116        ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
7117        (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
7118        (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7119         static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7120      break;
7121    MCInst TmpInst;
7122    TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
7123                      ARM::tADDi8 : ARM::tSUBi8);
7124    TmpInst.addOperand(Inst.getOperand(0));
7125    TmpInst.addOperand(Inst.getOperand(5));
7126    TmpInst.addOperand(Inst.getOperand(0));
7127    TmpInst.addOperand(Inst.getOperand(2));
7128    TmpInst.addOperand(Inst.getOperand(3));
7129    TmpInst.addOperand(Inst.getOperand(4));
7130    Inst = TmpInst;
7131    return true;
7132  }
7133  case ARM::t2ADDrr: {
7134    // If the destination and first source operand are the same, and
7135    // there's no setting of the flags, use encoding T2 instead of T3.
7136    // Note that this is only for ADD, not SUB. This mirrors the system
7137    // 'as' behaviour. Make sure the wide encoding wasn't explicit.
7138    if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7139        Inst.getOperand(5).getReg() != 0 ||
7140        (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7141         static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7142      break;
7143    MCInst TmpInst;
7144    TmpInst.setOpcode(ARM::tADDhirr);
7145    TmpInst.addOperand(Inst.getOperand(0));
7146    TmpInst.addOperand(Inst.getOperand(0));
7147    TmpInst.addOperand(Inst.getOperand(2));
7148    TmpInst.addOperand(Inst.getOperand(3));
7149    TmpInst.addOperand(Inst.getOperand(4));
7150    Inst = TmpInst;
7151    return true;
7152  }
7153  case ARM::tADDrSP: {
7154    // If the non-SP source operand and the destination operand are not the
7155    // same, we need to use the 32-bit encoding if it's available.
7156    if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
7157      Inst.setOpcode(ARM::t2ADDrr);
7158      Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7159      return true;
7160    }
7161    break;
7162  }
7163  case ARM::tB:
7164    // A Thumb conditional branch outside of an IT block is a tBcc.
7165    if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
7166      Inst.setOpcode(ARM::tBcc);
7167      return true;
7168    }
7169    break;
7170  case ARM::t2B:
7171    // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
7172    if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
7173      Inst.setOpcode(ARM::t2Bcc);
7174      return true;
7175    }
7176    break;
7177  case ARM::t2Bcc:
7178    // If the conditional is AL or we're in an IT block, we really want t2B.
7179    if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
7180      Inst.setOpcode(ARM::t2B);
7181      return true;
7182    }
7183    break;
7184  case ARM::tBcc:
7185    // If the conditional is AL, we really want tB.
7186    if (Inst.getOperand(1).getImm() == ARMCC::AL) {
7187      Inst.setOpcode(ARM::tB);
7188      return true;
7189    }
7190    break;
7191  case ARM::tLDMIA: {
7192    // If the register list contains any high registers, or if the writeback
7193    // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
7194    // instead if we're in Thumb2. Otherwise, this should have generated
7195    // an error in validateInstruction().
7196    unsigned Rn = Inst.getOperand(0).getReg();
7197    bool hasWritebackToken =
7198      (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7199       static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
7200    bool listContainsBase;
7201    if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
7202        (!listContainsBase && !hasWritebackToken) ||
7203        (listContainsBase && hasWritebackToken)) {
7204      // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7205      assert (isThumbTwo());
7206      Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
7207      // If we're switching to the updating version, we need to insert
7208      // the writeback tied operand.
7209      if (hasWritebackToken)
7210        Inst.insert(Inst.begin(),
7211                    MCOperand::CreateReg(Inst.getOperand(0).getReg()));
7212      return true;
7213    }
7214    break;
7215  }
7216  case ARM::tSTMIA_UPD: {
7217    // If the register list contains any high registers, we need to use
7218    // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7219    // should have generated an error in validateInstruction().
7220    unsigned Rn = Inst.getOperand(0).getReg();
7221    bool listContainsBase;
7222    if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
7223      // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7224      assert (isThumbTwo());
7225      Inst.setOpcode(ARM::t2STMIA_UPD);
7226      return true;
7227    }
7228    break;
7229  }
7230  case ARM::tPOP: {
7231    bool listContainsBase;
7232    // If the register list contains any high registers, we need to use
7233    // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7234    // should have generated an error in validateInstruction().
7235    if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
7236      return false;
7237    assert (isThumbTwo());
7238    Inst.setOpcode(ARM::t2LDMIA_UPD);
7239    // Add the base register and writeback operands.
7240    Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7241    Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7242    return true;
7243  }
7244  case ARM::tPUSH: {
7245    bool listContainsBase;
7246    if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
7247      return false;
7248    assert (isThumbTwo());
7249    Inst.setOpcode(ARM::t2STMDB_UPD);
7250    // Add the base register and writeback operands.
7251    Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7252    Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7253    return true;
7254  }
7255  case ARM::t2MOVi: {
7256    // If we can use the 16-bit encoding and the user didn't explicitly
7257    // request the 32-bit variant, transform it here.
7258    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7259        (unsigned)Inst.getOperand(1).getImm() <= 255 &&
7260        ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
7261         Inst.getOperand(4).getReg() == ARM::CPSR) ||
7262        (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
7263        (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7264         static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7265      // The operands aren't in the same order for tMOVi8...
7266      MCInst TmpInst;
7267      TmpInst.setOpcode(ARM::tMOVi8);
7268      TmpInst.addOperand(Inst.getOperand(0));
7269      TmpInst.addOperand(Inst.getOperand(4));
7270      TmpInst.addOperand(Inst.getOperand(1));
7271      TmpInst.addOperand(Inst.getOperand(2));
7272      TmpInst.addOperand(Inst.getOperand(3));
7273      Inst = TmpInst;
7274      return true;
7275    }
7276    break;
7277  }
7278  case ARM::t2MOVr: {
7279    // If we can use the 16-bit encoding and the user didn't explicitly
7280    // request the 32-bit variant, transform it here.
7281    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7282        isARMLowRegister(Inst.getOperand(1).getReg()) &&
7283        Inst.getOperand(2).getImm() == ARMCC::AL &&
7284        Inst.getOperand(4).getReg() == ARM::CPSR &&
7285        (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7286         static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7287      // The operands aren't the same for tMOV[S]r... (no cc_out)
7288      MCInst TmpInst;
7289      TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
7290      TmpInst.addOperand(Inst.getOperand(0));
7291      TmpInst.addOperand(Inst.getOperand(1));
7292      TmpInst.addOperand(Inst.getOperand(2));
7293      TmpInst.addOperand(Inst.getOperand(3));
7294      Inst = TmpInst;
7295      return true;
7296    }
7297    break;
7298  }
7299  case ARM::t2SXTH:
7300  case ARM::t2SXTB:
7301  case ARM::t2UXTH:
7302  case ARM::t2UXTB: {
7303    // If we can use the 16-bit encoding and the user didn't explicitly
7304    // request the 32-bit variant, transform it here.
7305    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7306        isARMLowRegister(Inst.getOperand(1).getReg()) &&
7307        Inst.getOperand(2).getImm() == 0 &&
7308        (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7309         static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7310      unsigned NewOpc;
7311      switch (Inst.getOpcode()) {
7312      default: llvm_unreachable("Illegal opcode!");
7313      case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
7314      case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
7315      case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
7316      case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
7317      }
7318      // The operands aren't the same for thumb1 (no rotate operand).
7319      MCInst TmpInst;
7320      TmpInst.setOpcode(NewOpc);
7321      TmpInst.addOperand(Inst.getOperand(0));
7322      TmpInst.addOperand(Inst.getOperand(1));
7323      TmpInst.addOperand(Inst.getOperand(3));
7324      TmpInst.addOperand(Inst.getOperand(4));
7325      Inst = TmpInst;
7326      return true;
7327    }
7328    break;
7329  }
7330  case ARM::MOVsi: {
7331    ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
7332    // rrx shifts and asr/lsr of #32 is encoded as 0
7333    if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
7334      return false;
7335    if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
7336      // Shifting by zero is accepted as a vanilla 'MOVr'
7337      MCInst TmpInst;
7338      TmpInst.setOpcode(ARM::MOVr);
7339      TmpInst.addOperand(Inst.getOperand(0));
7340      TmpInst.addOperand(Inst.getOperand(1));
7341      TmpInst.addOperand(Inst.getOperand(3));
7342      TmpInst.addOperand(Inst.getOperand(4));
7343      TmpInst.addOperand(Inst.getOperand(5));
7344      Inst = TmpInst;
7345      return true;
7346    }
7347    return false;
7348  }
7349  case ARM::ANDrsi:
7350  case ARM::ORRrsi:
7351  case ARM::EORrsi:
7352  case ARM::BICrsi:
7353  case ARM::SUBrsi:
7354  case ARM::ADDrsi: {
7355    unsigned newOpc;
7356    ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
7357    if (SOpc == ARM_AM::rrx) return false;
7358    switch (Inst.getOpcode()) {
7359    default: llvm_unreachable("unexpected opcode!");
7360    case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
7361    case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
7362    case ARM::EORrsi: newOpc = ARM::EORrr; break;
7363    case ARM::BICrsi: newOpc = ARM::BICrr; break;
7364    case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
7365    case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
7366    }
7367    // If the shift is by zero, use the non-shifted instruction definition.
7368    // The exception is for right shifts, where 0 == 32
7369    if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
7370        !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
7371      MCInst TmpInst;
7372      TmpInst.setOpcode(newOpc);
7373      TmpInst.addOperand(Inst.getOperand(0));
7374      TmpInst.addOperand(Inst.getOperand(1));
7375      TmpInst.addOperand(Inst.getOperand(2));
7376      TmpInst.addOperand(Inst.getOperand(4));
7377      TmpInst.addOperand(Inst.getOperand(5));
7378      TmpInst.addOperand(Inst.getOperand(6));
7379      Inst = TmpInst;
7380      return true;
7381    }
7382    return false;
7383  }
7384  case ARM::ITasm:
7385  case ARM::t2IT: {
7386    // The mask bits for all but the first condition are represented as
7387    // the low bit of the condition code value implies 't'. We currently
7388    // always have 1 implies 't', so XOR toggle the bits if the low bit
7389    // of the condition code is zero.
7390    MCOperand &MO = Inst.getOperand(1);
7391    unsigned Mask = MO.getImm();
7392    unsigned OrigMask = Mask;
7393    unsigned TZ = CountTrailingZeros_32(Mask);
7394    if ((Inst.getOperand(0).getImm() & 1) == 0) {
7395      assert(Mask && TZ <= 3 && "illegal IT mask value!");
7396      for (unsigned i = 3; i != TZ; --i)
7397        Mask ^= 1 << i;
7398    }
7399    MO.setImm(Mask);
7400
7401    // Set up the IT block state according to the IT instruction we just
7402    // matched.
7403    assert(!inITBlock() && "nested IT blocks?!");
7404    ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
7405    ITState.Mask = OrigMask; // Use the original mask, not the updated one.
7406    ITState.CurPosition = 0;
7407    ITState.FirstCond = true;
7408    break;
7409  }
7410  case ARM::t2LSLrr:
7411  case ARM::t2LSRrr:
7412  case ARM::t2ASRrr:
7413  case ARM::t2SBCrr:
7414  case ARM::t2RORrr:
7415  case ARM::t2BICrr:
7416  {
7417    // Assemblers should use the narrow encodings of these instructions when permissible.
7418    if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7419         isARMLowRegister(Inst.getOperand(2).getReg())) &&
7420        Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7421        ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7422         (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7423        (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7424         !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7425      unsigned NewOpc;
7426      switch (Inst.getOpcode()) {
7427        default: llvm_unreachable("unexpected opcode");
7428        case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
7429        case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
7430        case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
7431        case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
7432        case ARM::t2RORrr: NewOpc = ARM::tROR; break;
7433        case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
7434      }
7435      MCInst TmpInst;
7436      TmpInst.setOpcode(NewOpc);
7437      TmpInst.addOperand(Inst.getOperand(0));
7438      TmpInst.addOperand(Inst.getOperand(5));
7439      TmpInst.addOperand(Inst.getOperand(1));
7440      TmpInst.addOperand(Inst.getOperand(2));
7441      TmpInst.addOperand(Inst.getOperand(3));
7442      TmpInst.addOperand(Inst.getOperand(4));
7443      Inst = TmpInst;
7444      return true;
7445    }
7446    return false;
7447  }
7448  case ARM::t2ANDrr:
7449  case ARM::t2EORrr:
7450  case ARM::t2ADCrr:
7451  case ARM::t2ORRrr:
7452  {
7453    // Assemblers should use the narrow encodings of these instructions when permissible.
7454    // These instructions are special in that they are commutable, so shorter encodings
7455    // are available more often.
7456    if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7457         isARMLowRegister(Inst.getOperand(2).getReg())) &&
7458        (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
7459         Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
7460        ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7461         (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7462        (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7463         !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7464      unsigned NewOpc;
7465      switch (Inst.getOpcode()) {
7466        default: llvm_unreachable("unexpected opcode");
7467        case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
7468        case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
7469        case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
7470        case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
7471      }
7472      MCInst TmpInst;
7473      TmpInst.setOpcode(NewOpc);
7474      TmpInst.addOperand(Inst.getOperand(0));
7475      TmpInst.addOperand(Inst.getOperand(5));
7476      if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
7477        TmpInst.addOperand(Inst.getOperand(1));
7478        TmpInst.addOperand(Inst.getOperand(2));
7479      } else {
7480        TmpInst.addOperand(Inst.getOperand(2));
7481        TmpInst.addOperand(Inst.getOperand(1));
7482      }
7483      TmpInst.addOperand(Inst.getOperand(3));
7484      TmpInst.addOperand(Inst.getOperand(4));
7485      Inst = TmpInst;
7486      return true;
7487    }
7488    return false;
7489  }
7490  }
7491  return false;
7492}
7493
7494unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
7495  // 16-bit thumb arithmetic instructions either require or preclude the 'S'
7496  // suffix depending on whether they're in an IT block or not.
7497  unsigned Opc = Inst.getOpcode();
7498  const MCInstrDesc &MCID = getInstDesc(Opc);
7499  if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
7500    assert(MCID.hasOptionalDef() &&
7501           "optionally flag setting instruction missing optional def operand");
7502    assert(MCID.NumOperands == Inst.getNumOperands() &&
7503           "operand count mismatch!");
7504    // Find the optional-def operand (cc_out).
7505    unsigned OpNo;
7506    for (OpNo = 0;
7507         !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
7508         ++OpNo)
7509      ;
7510    // If we're parsing Thumb1, reject it completely.
7511    if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
7512      return Match_MnemonicFail;
7513    // If we're parsing Thumb2, which form is legal depends on whether we're
7514    // in an IT block.
7515    if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
7516        !inITBlock())
7517      return Match_RequiresITBlock;
7518    if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
7519        inITBlock())
7520      return Match_RequiresNotITBlock;
7521  }
7522  // Some high-register supporting Thumb1 encodings only allow both registers
7523  // to be from r0-r7 when in Thumb2.
7524  else if (Opc == ARM::tADDhirr && isThumbOne() &&
7525           isARMLowRegister(Inst.getOperand(1).getReg()) &&
7526           isARMLowRegister(Inst.getOperand(2).getReg()))
7527    return Match_RequiresThumb2;
7528  // Others only require ARMv6 or later.
7529  else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
7530           isARMLowRegister(Inst.getOperand(0).getReg()) &&
7531           isARMLowRegister(Inst.getOperand(1).getReg()))
7532    return Match_RequiresV6;
7533  return Match_Success;
7534}
7535
7536static const char *getSubtargetFeatureName(unsigned Val);
7537bool ARMAsmParser::
7538MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
7539                        SmallVectorImpl<MCParsedAsmOperand*> &Operands,
7540                        MCStreamer &Out, unsigned &ErrorInfo,
7541                        bool MatchingInlineAsm) {
7542  MCInst Inst;
7543  unsigned MatchResult;
7544
7545  MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
7546                                     MatchingInlineAsm);
7547  switch (MatchResult) {
7548  default: break;
7549  case Match_Success:
7550    // Context sensitive operand constraints aren't handled by the matcher,
7551    // so check them here.
7552    if (validateInstruction(Inst, Operands)) {
7553      // Still progress the IT block, otherwise one wrong condition causes
7554      // nasty cascading errors.
7555      forwardITPosition();
7556      return true;
7557    }
7558
7559    // Some instructions need post-processing to, for example, tweak which
7560    // encoding is selected. Loop on it while changes happen so the
7561    // individual transformations can chain off each other. E.g.,
7562    // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
7563    while (processInstruction(Inst, Operands))
7564      ;
7565
7566    // Only move forward at the very end so that everything in validate
7567    // and process gets a consistent answer about whether we're in an IT
7568    // block.
7569    forwardITPosition();
7570
7571    // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
7572    // doesn't actually encode.
7573    if (Inst.getOpcode() == ARM::ITasm)
7574      return false;
7575
7576    Inst.setLoc(IDLoc);
7577    Out.EmitInstruction(Inst);
7578    return false;
7579  case Match_MissingFeature: {
7580    assert(ErrorInfo && "Unknown missing feature!");
7581    // Special case the error message for the very common case where only
7582    // a single subtarget feature is missing (Thumb vs. ARM, e.g.).
7583    std::string Msg = "instruction requires:";
7584    unsigned Mask = 1;
7585    for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
7586      if (ErrorInfo & Mask) {
7587        Msg += " ";
7588        Msg += getSubtargetFeatureName(ErrorInfo & Mask);
7589      }
7590      Mask <<= 1;
7591    }
7592    return Error(IDLoc, Msg);
7593  }
7594  case Match_InvalidOperand: {
7595    SMLoc ErrorLoc = IDLoc;
7596    if (ErrorInfo != ~0U) {
7597      if (ErrorInfo >= Operands.size())
7598        return Error(IDLoc, "too few operands for instruction");
7599
7600      ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7601      if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7602    }
7603
7604    return Error(ErrorLoc, "invalid operand for instruction");
7605  }
7606  case Match_MnemonicFail:
7607    return Error(IDLoc, "invalid instruction",
7608                 ((ARMOperand*)Operands[0])->getLocRange());
7609  case Match_RequiresNotITBlock:
7610    return Error(IDLoc, "flag setting instruction only valid outside IT block");
7611  case Match_RequiresITBlock:
7612    return Error(IDLoc, "instruction only valid inside IT block");
7613  case Match_RequiresV6:
7614    return Error(IDLoc, "instruction variant requires ARMv6 or later");
7615  case Match_RequiresThumb2:
7616    return Error(IDLoc, "instruction variant requires Thumb2");
7617  case Match_ImmRange0_15: {
7618    SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7619    if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7620    return Error(ErrorLoc, "immediate operand must be in the range [0,15]");
7621  }
7622  }
7623
7624  llvm_unreachable("Implement any new match types added!");
7625}
7626
7627/// parseDirective parses the arm specific directives
7628bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
7629  StringRef IDVal = DirectiveID.getIdentifier();
7630  if (IDVal == ".word")
7631    return parseDirectiveWord(4, DirectiveID.getLoc());
7632  else if (IDVal == ".thumb")
7633    return parseDirectiveThumb(DirectiveID.getLoc());
7634  else if (IDVal == ".arm")
7635    return parseDirectiveARM(DirectiveID.getLoc());
7636  else if (IDVal == ".thumb_func")
7637    return parseDirectiveThumbFunc(DirectiveID.getLoc());
7638  else if (IDVal == ".code")
7639    return parseDirectiveCode(DirectiveID.getLoc());
7640  else if (IDVal == ".syntax")
7641    return parseDirectiveSyntax(DirectiveID.getLoc());
7642  else if (IDVal == ".unreq")
7643    return parseDirectiveUnreq(DirectiveID.getLoc());
7644  else if (IDVal == ".arch")
7645    return parseDirectiveArch(DirectiveID.getLoc());
7646  else if (IDVal == ".eabi_attribute")
7647    return parseDirectiveEabiAttr(DirectiveID.getLoc());
7648  return true;
7649}
7650
7651/// parseDirectiveWord
7652///  ::= .word [ expression (, expression)* ]
7653bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
7654  if (getLexer().isNot(AsmToken::EndOfStatement)) {
7655    for (;;) {
7656      const MCExpr *Value;
7657      if (getParser().parseExpression(Value))
7658        return true;
7659
7660      getParser().getStreamer().EmitValue(Value, Size);
7661
7662      if (getLexer().is(AsmToken::EndOfStatement))
7663        break;
7664
7665      // FIXME: Improve diagnostic.
7666      if (getLexer().isNot(AsmToken::Comma))
7667        return Error(L, "unexpected token in directive");
7668      Parser.Lex();
7669    }
7670  }
7671
7672  Parser.Lex();
7673  return false;
7674}
7675
7676/// parseDirectiveThumb
7677///  ::= .thumb
7678bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
7679  if (getLexer().isNot(AsmToken::EndOfStatement))
7680    return Error(L, "unexpected token in directive");
7681  Parser.Lex();
7682
7683  if (!isThumb())
7684    SwitchMode();
7685  getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
7686  return false;
7687}
7688
7689/// parseDirectiveARM
7690///  ::= .arm
7691bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
7692  if (getLexer().isNot(AsmToken::EndOfStatement))
7693    return Error(L, "unexpected token in directive");
7694  Parser.Lex();
7695
7696  if (isThumb())
7697    SwitchMode();
7698  getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
7699  return false;
7700}
7701
7702/// parseDirectiveThumbFunc
7703///  ::= .thumbfunc symbol_name
7704bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
7705  const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
7706  bool isMachO = MAI.hasSubsectionsViaSymbols();
7707  StringRef Name;
7708  bool needFuncName = true;
7709
7710  // Darwin asm has (optionally) function name after .thumb_func direction
7711  // ELF doesn't
7712  if (isMachO) {
7713    const AsmToken &Tok = Parser.getTok();
7714    if (Tok.isNot(AsmToken::EndOfStatement)) {
7715      if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
7716        return Error(L, "unexpected token in .thumb_func directive");
7717      Name = Tok.getIdentifier();
7718      Parser.Lex(); // Consume the identifier token.
7719      needFuncName = false;
7720    }
7721  }
7722
7723  if (getLexer().isNot(AsmToken::EndOfStatement))
7724    return Error(L, "unexpected token in directive");
7725
7726  // Eat the end of statement and any blank lines that follow.
7727  while (getLexer().is(AsmToken::EndOfStatement))
7728    Parser.Lex();
7729
7730  // FIXME: assuming function name will be the line following .thumb_func
7731  // We really should be checking the next symbol definition even if there's
7732  // stuff in between.
7733  if (needFuncName) {
7734    Name = Parser.getTok().getIdentifier();
7735  }
7736
7737  // Mark symbol as a thumb symbol.
7738  MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
7739  getParser().getStreamer().EmitThumbFunc(Func);
7740  return false;
7741}
7742
7743/// parseDirectiveSyntax
7744///  ::= .syntax unified | divided
7745bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
7746  const AsmToken &Tok = Parser.getTok();
7747  if (Tok.isNot(AsmToken::Identifier))
7748    return Error(L, "unexpected token in .syntax directive");
7749  StringRef Mode = Tok.getString();
7750  if (Mode == "unified" || Mode == "UNIFIED")
7751    Parser.Lex();
7752  else if (Mode == "divided" || Mode == "DIVIDED")
7753    return Error(L, "'.syntax divided' arm asssembly not supported");
7754  else
7755    return Error(L, "unrecognized syntax mode in .syntax directive");
7756
7757  if (getLexer().isNot(AsmToken::EndOfStatement))
7758    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
7759  Parser.Lex();
7760
7761  // TODO tell the MC streamer the mode
7762  // getParser().getStreamer().Emit???();
7763  return false;
7764}
7765
7766/// parseDirectiveCode
7767///  ::= .code 16 | 32
7768bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
7769  const AsmToken &Tok = Parser.getTok();
7770  if (Tok.isNot(AsmToken::Integer))
7771    return Error(L, "unexpected token in .code directive");
7772  int64_t Val = Parser.getTok().getIntVal();
7773  if (Val == 16)
7774    Parser.Lex();
7775  else if (Val == 32)
7776    Parser.Lex();
7777  else
7778    return Error(L, "invalid operand to .code directive");
7779
7780  if (getLexer().isNot(AsmToken::EndOfStatement))
7781    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
7782  Parser.Lex();
7783
7784  if (Val == 16) {
7785    if (!isThumb())
7786      SwitchMode();
7787    getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
7788  } else {
7789    if (isThumb())
7790      SwitchMode();
7791    getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
7792  }
7793
7794  return false;
7795}
7796
7797/// parseDirectiveReq
7798///  ::= name .req registername
7799bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
7800  Parser.Lex(); // Eat the '.req' token.
7801  unsigned Reg;
7802  SMLoc SRegLoc, ERegLoc;
7803  if (ParseRegister(Reg, SRegLoc, ERegLoc)) {
7804    Parser.eatToEndOfStatement();
7805    return Error(SRegLoc, "register name expected");
7806  }
7807
7808  // Shouldn't be anything else.
7809  if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
7810    Parser.eatToEndOfStatement();
7811    return Error(Parser.getTok().getLoc(),
7812                 "unexpected input in .req directive.");
7813  }
7814
7815  Parser.Lex(); // Consume the EndOfStatement
7816
7817  if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg)
7818    return Error(SRegLoc, "redefinition of '" + Name +
7819                          "' does not match original.");
7820
7821  return false;
7822}
7823
7824/// parseDirectiveUneq
7825///  ::= .unreq registername
7826bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
7827  if (Parser.getTok().isNot(AsmToken::Identifier)) {
7828    Parser.eatToEndOfStatement();
7829    return Error(L, "unexpected input in .unreq directive.");
7830  }
7831  RegisterReqs.erase(Parser.getTok().getIdentifier());
7832  Parser.Lex(); // Eat the identifier.
7833  return false;
7834}
7835
7836/// parseDirectiveArch
7837///  ::= .arch token
7838bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
7839  return true;
7840}
7841
7842/// parseDirectiveEabiAttr
7843///  ::= .eabi_attribute int, int
7844bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
7845  return true;
7846}
7847
7848/// Force static initialization.
7849extern "C" void LLVMInitializeARMAsmParser() {
7850  RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
7851  RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
7852}
7853
7854#define GET_REGISTER_MATCHER
7855#define GET_SUBTARGET_FEATURE_NAME
7856#define GET_MATCHER_IMPLEMENTATION
7857#include "ARMGenAsmMatcher.inc"
7858
7859// Define this matcher function after the auto-generated include so we
7860// have the match class enum definitions.
7861unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand *AsmOp,
7862                                                  unsigned Kind) {
7863  ARMOperand *Op = static_cast<ARMOperand*>(AsmOp);
7864  // If the kind is a token for a literal immediate, check if our asm
7865  // operand matches. This is for InstAliases which have a fixed-value
7866  // immediate in the syntax.
7867  if (Kind == MCK__35_0 && Op->isImm()) {
7868    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
7869    if (!CE)
7870      return Match_InvalidOperand;
7871    if (CE->getValue() == 0)
7872      return Match_Success;
7873  }
7874  return Match_InvalidOperand;
7875}
7876