ARMAsmParser.cpp revision d0588e2a2ed1f7570f13b78c2042855dc4afae10
1//===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10#include "MCTargetDesc/ARMBaseInfo.h" 11#include "MCTargetDesc/ARMAddressingModes.h" 12#include "MCTargetDesc/ARMMCExpr.h" 13#include "llvm/MC/MCParser/MCAsmLexer.h" 14#include "llvm/MC/MCParser/MCAsmParser.h" 15#include "llvm/MC/MCParser/MCParsedAsmOperand.h" 16#include "llvm/MC/MCAsmInfo.h" 17#include "llvm/MC/MCContext.h" 18#include "llvm/MC/MCStreamer.h" 19#include "llvm/MC/MCExpr.h" 20#include "llvm/MC/MCInst.h" 21#include "llvm/MC/MCInstrDesc.h" 22#include "llvm/MC/MCRegisterInfo.h" 23#include "llvm/MC/MCSubtargetInfo.h" 24#include "llvm/MC/MCTargetAsmParser.h" 25#include "llvm/Support/MathExtras.h" 26#include "llvm/Support/SourceMgr.h" 27#include "llvm/Support/TargetRegistry.h" 28#include "llvm/Support/raw_ostream.h" 29#include "llvm/ADT/BitVector.h" 30#include "llvm/ADT/OwningPtr.h" 31#include "llvm/ADT/STLExtras.h" 32#include "llvm/ADT/SmallVector.h" 33#include "llvm/ADT/StringExtras.h" 34#include "llvm/ADT/StringSwitch.h" 35#include "llvm/ADT/Twine.h" 36 37using namespace llvm; 38 39namespace { 40 41class ARMOperand; 42 43class ARMAsmParser : public MCTargetAsmParser { 44 MCSubtargetInfo &STI; 45 MCAsmParser &Parser; 46 47 struct { 48 ARMCC::CondCodes Cond; // Condition for IT block. 49 unsigned Mask:4; // Condition mask for instructions. 50 // Starting at first 1 (from lsb). 51 // '1' condition as indicated in IT. 52 // '0' inverse of condition (else). 53 // Count of instructions in IT block is 54 // 4 - trailingzeroes(mask) 55 56 bool FirstCond; // Explicit flag for when we're parsing the 57 // First instruction in the IT block. It's 58 // implied in the mask, so needs special 59 // handling. 60 61 unsigned CurPosition; // Current position in parsing of IT 62 // block. In range [0,3]. Initialized 63 // according to count of instructions in block. 64 // ~0U if no active IT block. 65 } ITState; 66 bool inITBlock() { return ITState.CurPosition != ~0U;} 67 void forwardITPosition() { 68 if (!inITBlock()) return; 69 // Move to the next instruction in the IT block, if there is one. If not, 70 // mark the block as done. 71 unsigned TZ = CountTrailingZeros_32(ITState.Mask); 72 if (++ITState.CurPosition == 5 - TZ) 73 ITState.CurPosition = ~0U; // Done with the IT block after this. 74 } 75 76 77 MCAsmParser &getParser() const { return Parser; } 78 MCAsmLexer &getLexer() const { return Parser.getLexer(); } 79 80 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); } 81 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); } 82 83 int tryParseRegister(); 84 bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &); 85 int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &); 86 bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &); 87 bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &); 88 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic); 89 bool parsePrefix(ARMMCExpr::VariantKind &RefKind); 90 const MCExpr *applyPrefixToExpr(const MCExpr *E, 91 MCSymbolRefExpr::VariantKind Variant); 92 93 94 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType, 95 unsigned &ShiftAmount); 96 bool parseDirectiveWord(unsigned Size, SMLoc L); 97 bool parseDirectiveThumb(SMLoc L); 98 bool parseDirectiveThumbFunc(SMLoc L); 99 bool parseDirectiveCode(SMLoc L); 100 bool parseDirectiveSyntax(SMLoc L); 101 102 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode, 103 bool &CarrySetting, unsigned &ProcessorIMod, 104 StringRef &ITMask); 105 void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet, 106 bool &CanAcceptPredicationCode); 107 108 bool isThumb() const { 109 // FIXME: Can tablegen auto-generate this? 110 return (STI.getFeatureBits() & ARM::ModeThumb) != 0; 111 } 112 bool isThumbOne() const { 113 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0; 114 } 115 bool isThumbTwo() const { 116 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2); 117 } 118 bool hasV6Ops() const { 119 return STI.getFeatureBits() & ARM::HasV6Ops; 120 } 121 void SwitchMode() { 122 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb)); 123 setAvailableFeatures(FB); 124 } 125 126 /// @name Auto-generated Match Functions 127 /// { 128 129#define GET_ASSEMBLER_HEADER 130#include "ARMGenAsmMatcher.inc" 131 132 /// } 133 134 OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&); 135 OperandMatchResultTy parseCoprocNumOperand( 136 SmallVectorImpl<MCParsedAsmOperand*>&); 137 OperandMatchResultTy parseCoprocRegOperand( 138 SmallVectorImpl<MCParsedAsmOperand*>&); 139 OperandMatchResultTy parseMemBarrierOptOperand( 140 SmallVectorImpl<MCParsedAsmOperand*>&); 141 OperandMatchResultTy parseProcIFlagsOperand( 142 SmallVectorImpl<MCParsedAsmOperand*>&); 143 OperandMatchResultTy parseMSRMaskOperand( 144 SmallVectorImpl<MCParsedAsmOperand*>&); 145 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O, 146 StringRef Op, int Low, int High); 147 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) { 148 return parsePKHImm(O, "lsl", 0, 31); 149 } 150 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) { 151 return parsePKHImm(O, "asr", 1, 32); 152 } 153 OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&); 154 OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&); 155 OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&); 156 OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&); 157 OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&); 158 OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&); 159 160 // Asm Match Converter Methods 161 bool cvtT2LdrdPre(MCInst &Inst, unsigned Opcode, 162 const SmallVectorImpl<MCParsedAsmOperand*> &); 163 bool cvtT2StrdPre(MCInst &Inst, unsigned Opcode, 164 const SmallVectorImpl<MCParsedAsmOperand*> &); 165 bool cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode, 166 const SmallVectorImpl<MCParsedAsmOperand*> &); 167 bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, 168 const SmallVectorImpl<MCParsedAsmOperand*> &); 169 bool cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode, 170 const SmallVectorImpl<MCParsedAsmOperand*> &); 171 bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode, 172 const SmallVectorImpl<MCParsedAsmOperand*> &); 173 bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, 174 const SmallVectorImpl<MCParsedAsmOperand*> &); 175 bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, 176 const SmallVectorImpl<MCParsedAsmOperand*> &); 177 bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode, 178 const SmallVectorImpl<MCParsedAsmOperand*> &); 179 bool cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode, 180 const SmallVectorImpl<MCParsedAsmOperand*> &); 181 bool cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode, 182 const SmallVectorImpl<MCParsedAsmOperand*> &); 183 bool cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode, 184 const SmallVectorImpl<MCParsedAsmOperand*> &); 185 bool cvtLdrdPre(MCInst &Inst, unsigned Opcode, 186 const SmallVectorImpl<MCParsedAsmOperand*> &); 187 bool cvtStrdPre(MCInst &Inst, unsigned Opcode, 188 const SmallVectorImpl<MCParsedAsmOperand*> &); 189 bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, 190 const SmallVectorImpl<MCParsedAsmOperand*> &); 191 bool cvtThumbMultiply(MCInst &Inst, unsigned Opcode, 192 const SmallVectorImpl<MCParsedAsmOperand*> &); 193 194 bool validateInstruction(MCInst &Inst, 195 const SmallVectorImpl<MCParsedAsmOperand*> &Ops); 196 void processInstruction(MCInst &Inst, 197 const SmallVectorImpl<MCParsedAsmOperand*> &Ops); 198 bool shouldOmitCCOutOperand(StringRef Mnemonic, 199 SmallVectorImpl<MCParsedAsmOperand*> &Operands); 200 201public: 202 enum ARMMatchResultTy { 203 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY, 204 Match_RequiresNotITBlock, 205 Match_RequiresV6, 206 Match_RequiresThumb2 207 }; 208 209 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser) 210 : MCTargetAsmParser(), STI(_STI), Parser(_Parser) { 211 MCAsmParserExtension::Initialize(_Parser); 212 213 // Initialize the set of available features. 214 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); 215 216 // Not in an ITBlock to start with. 217 ITState.CurPosition = ~0U; 218 } 219 220 // Implementation of the MCTargetAsmParser interface: 221 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc); 222 bool ParseInstruction(StringRef Name, SMLoc NameLoc, 223 SmallVectorImpl<MCParsedAsmOperand*> &Operands); 224 bool ParseDirective(AsmToken DirectiveID); 225 226 unsigned checkTargetMatchPredicate(MCInst &Inst); 227 228 bool MatchAndEmitInstruction(SMLoc IDLoc, 229 SmallVectorImpl<MCParsedAsmOperand*> &Operands, 230 MCStreamer &Out); 231}; 232} // end anonymous namespace 233 234namespace { 235 236/// ARMOperand - Instances of this class represent a parsed ARM machine 237/// instruction. 238class ARMOperand : public MCParsedAsmOperand { 239 enum KindTy { 240 CondCode, 241 CCOut, 242 ITCondMask, 243 CoprocNum, 244 CoprocReg, 245 Immediate, 246 MemBarrierOpt, 247 Memory, 248 PostIndexRegister, 249 MSRMask, 250 ProcIFlags, 251 Register, 252 RegisterList, 253 DPRRegisterList, 254 SPRRegisterList, 255 ShiftedRegister, 256 ShiftedImmediate, 257 ShifterImmediate, 258 RotateImmediate, 259 BitfieldDescriptor, 260 Token 261 } Kind; 262 263 SMLoc StartLoc, EndLoc; 264 SmallVector<unsigned, 8> Registers; 265 266 union { 267 struct { 268 ARMCC::CondCodes Val; 269 } CC; 270 271 struct { 272 unsigned Val; 273 } Cop; 274 275 struct { 276 unsigned Mask:4; 277 } ITMask; 278 279 struct { 280 ARM_MB::MemBOpt Val; 281 } MBOpt; 282 283 struct { 284 ARM_PROC::IFlags Val; 285 } IFlags; 286 287 struct { 288 unsigned Val; 289 } MMask; 290 291 struct { 292 const char *Data; 293 unsigned Length; 294 } Tok; 295 296 struct { 297 unsigned RegNum; 298 } Reg; 299 300 struct { 301 const MCExpr *Val; 302 } Imm; 303 304 /// Combined record for all forms of ARM address expressions. 305 struct { 306 unsigned BaseRegNum; 307 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset 308 // was specified. 309 const MCConstantExpr *OffsetImm; // Offset immediate value 310 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL 311 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg 312 unsigned ShiftImm; // shift for OffsetReg. 313 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit) 314 } Mem; 315 316 struct { 317 unsigned RegNum; 318 bool isAdd; 319 ARM_AM::ShiftOpc ShiftTy; 320 unsigned ShiftImm; 321 } PostIdxReg; 322 323 struct { 324 bool isASR; 325 unsigned Imm; 326 } ShifterImm; 327 struct { 328 ARM_AM::ShiftOpc ShiftTy; 329 unsigned SrcReg; 330 unsigned ShiftReg; 331 unsigned ShiftImm; 332 } RegShiftedReg; 333 struct { 334 ARM_AM::ShiftOpc ShiftTy; 335 unsigned SrcReg; 336 unsigned ShiftImm; 337 } RegShiftedImm; 338 struct { 339 unsigned Imm; 340 } RotImm; 341 struct { 342 unsigned LSB; 343 unsigned Width; 344 } Bitfield; 345 }; 346 347 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {} 348public: 349 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() { 350 Kind = o.Kind; 351 StartLoc = o.StartLoc; 352 EndLoc = o.EndLoc; 353 switch (Kind) { 354 case CondCode: 355 CC = o.CC; 356 break; 357 case ITCondMask: 358 ITMask = o.ITMask; 359 break; 360 case Token: 361 Tok = o.Tok; 362 break; 363 case CCOut: 364 case Register: 365 Reg = o.Reg; 366 break; 367 case RegisterList: 368 case DPRRegisterList: 369 case SPRRegisterList: 370 Registers = o.Registers; 371 break; 372 case CoprocNum: 373 case CoprocReg: 374 Cop = o.Cop; 375 break; 376 case Immediate: 377 Imm = o.Imm; 378 break; 379 case MemBarrierOpt: 380 MBOpt = o.MBOpt; 381 break; 382 case Memory: 383 Mem = o.Mem; 384 break; 385 case PostIndexRegister: 386 PostIdxReg = o.PostIdxReg; 387 break; 388 case MSRMask: 389 MMask = o.MMask; 390 break; 391 case ProcIFlags: 392 IFlags = o.IFlags; 393 break; 394 case ShifterImmediate: 395 ShifterImm = o.ShifterImm; 396 break; 397 case ShiftedRegister: 398 RegShiftedReg = o.RegShiftedReg; 399 break; 400 case ShiftedImmediate: 401 RegShiftedImm = o.RegShiftedImm; 402 break; 403 case RotateImmediate: 404 RotImm = o.RotImm; 405 break; 406 case BitfieldDescriptor: 407 Bitfield = o.Bitfield; 408 break; 409 } 410 } 411 412 /// getStartLoc - Get the location of the first token of this operand. 413 SMLoc getStartLoc() const { return StartLoc; } 414 /// getEndLoc - Get the location of the last token of this operand. 415 SMLoc getEndLoc() const { return EndLoc; } 416 417 ARMCC::CondCodes getCondCode() const { 418 assert(Kind == CondCode && "Invalid access!"); 419 return CC.Val; 420 } 421 422 unsigned getCoproc() const { 423 assert((Kind == CoprocNum || Kind == CoprocReg) && "Invalid access!"); 424 return Cop.Val; 425 } 426 427 StringRef getToken() const { 428 assert(Kind == Token && "Invalid access!"); 429 return StringRef(Tok.Data, Tok.Length); 430 } 431 432 unsigned getReg() const { 433 assert((Kind == Register || Kind == CCOut) && "Invalid access!"); 434 return Reg.RegNum; 435 } 436 437 const SmallVectorImpl<unsigned> &getRegList() const { 438 assert((Kind == RegisterList || Kind == DPRRegisterList || 439 Kind == SPRRegisterList) && "Invalid access!"); 440 return Registers; 441 } 442 443 const MCExpr *getImm() const { 444 assert(Kind == Immediate && "Invalid access!"); 445 return Imm.Val; 446 } 447 448 ARM_MB::MemBOpt getMemBarrierOpt() const { 449 assert(Kind == MemBarrierOpt && "Invalid access!"); 450 return MBOpt.Val; 451 } 452 453 ARM_PROC::IFlags getProcIFlags() const { 454 assert(Kind == ProcIFlags && "Invalid access!"); 455 return IFlags.Val; 456 } 457 458 unsigned getMSRMask() const { 459 assert(Kind == MSRMask && "Invalid access!"); 460 return MMask.Val; 461 } 462 463 bool isCoprocNum() const { return Kind == CoprocNum; } 464 bool isCoprocReg() const { return Kind == CoprocReg; } 465 bool isCondCode() const { return Kind == CondCode; } 466 bool isCCOut() const { return Kind == CCOut; } 467 bool isITMask() const { return Kind == ITCondMask; } 468 bool isITCondCode() const { return Kind == CondCode; } 469 bool isImm() const { return Kind == Immediate; } 470 bool isImm8s4() const { 471 if (Kind != Immediate) 472 return false; 473 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 474 if (!CE) return false; 475 int64_t Value = CE->getValue(); 476 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020; 477 } 478 bool isImm0_1020s4() const { 479 if (Kind != Immediate) 480 return false; 481 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 482 if (!CE) return false; 483 int64_t Value = CE->getValue(); 484 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020; 485 } 486 bool isImm0_508s4() const { 487 if (Kind != Immediate) 488 return false; 489 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 490 if (!CE) return false; 491 int64_t Value = CE->getValue(); 492 return ((Value & 3) == 0) && Value >= 0 && Value <= 508; 493 } 494 bool isImm0_255() const { 495 if (Kind != Immediate) 496 return false; 497 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 498 if (!CE) return false; 499 int64_t Value = CE->getValue(); 500 return Value >= 0 && Value < 256; 501 } 502 bool isImm0_7() const { 503 if (Kind != Immediate) 504 return false; 505 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 506 if (!CE) return false; 507 int64_t Value = CE->getValue(); 508 return Value >= 0 && Value < 8; 509 } 510 bool isImm0_15() const { 511 if (Kind != Immediate) 512 return false; 513 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 514 if (!CE) return false; 515 int64_t Value = CE->getValue(); 516 return Value >= 0 && Value < 16; 517 } 518 bool isImm0_31() const { 519 if (Kind != Immediate) 520 return false; 521 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 522 if (!CE) return false; 523 int64_t Value = CE->getValue(); 524 return Value >= 0 && Value < 32; 525 } 526 bool isImm1_16() const { 527 if (Kind != Immediate) 528 return false; 529 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 530 if (!CE) return false; 531 int64_t Value = CE->getValue(); 532 return Value > 0 && Value < 17; 533 } 534 bool isImm1_32() const { 535 if (Kind != Immediate) 536 return false; 537 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 538 if (!CE) return false; 539 int64_t Value = CE->getValue(); 540 return Value > 0 && Value < 33; 541 } 542 bool isImm0_65535() const { 543 if (Kind != Immediate) 544 return false; 545 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 546 if (!CE) return false; 547 int64_t Value = CE->getValue(); 548 return Value >= 0 && Value < 65536; 549 } 550 bool isImm0_65535Expr() const { 551 if (Kind != Immediate) 552 return false; 553 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 554 // If it's not a constant expression, it'll generate a fixup and be 555 // handled later. 556 if (!CE) return true; 557 int64_t Value = CE->getValue(); 558 return Value >= 0 && Value < 65536; 559 } 560 bool isImm24bit() const { 561 if (Kind != Immediate) 562 return false; 563 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 564 if (!CE) return false; 565 int64_t Value = CE->getValue(); 566 return Value >= 0 && Value <= 0xffffff; 567 } 568 bool isImmThumbSR() const { 569 if (Kind != Immediate) 570 return false; 571 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 572 if (!CE) return false; 573 int64_t Value = CE->getValue(); 574 return Value > 0 && Value < 33; 575 } 576 bool isPKHLSLImm() const { 577 if (Kind != Immediate) 578 return false; 579 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 580 if (!CE) return false; 581 int64_t Value = CE->getValue(); 582 return Value >= 0 && Value < 32; 583 } 584 bool isPKHASRImm() const { 585 if (Kind != Immediate) 586 return false; 587 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 588 if (!CE) return false; 589 int64_t Value = CE->getValue(); 590 return Value > 0 && Value <= 32; 591 } 592 bool isARMSOImm() const { 593 if (Kind != Immediate) 594 return false; 595 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 596 if (!CE) return false; 597 int64_t Value = CE->getValue(); 598 return ARM_AM::getSOImmVal(Value) != -1; 599 } 600 bool isT2SOImm() const { 601 if (Kind != Immediate) 602 return false; 603 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 604 if (!CE) return false; 605 int64_t Value = CE->getValue(); 606 return ARM_AM::getT2SOImmVal(Value) != -1; 607 } 608 bool isSetEndImm() const { 609 if (Kind != Immediate) 610 return false; 611 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 612 if (!CE) return false; 613 int64_t Value = CE->getValue(); 614 return Value == 1 || Value == 0; 615 } 616 bool isReg() const { return Kind == Register; } 617 bool isRegList() const { return Kind == RegisterList; } 618 bool isDPRRegList() const { return Kind == DPRRegisterList; } 619 bool isSPRRegList() const { return Kind == SPRRegisterList; } 620 bool isToken() const { return Kind == Token; } 621 bool isMemBarrierOpt() const { return Kind == MemBarrierOpt; } 622 bool isMemory() const { return Kind == Memory; } 623 bool isShifterImm() const { return Kind == ShifterImmediate; } 624 bool isRegShiftedReg() const { return Kind == ShiftedRegister; } 625 bool isRegShiftedImm() const { return Kind == ShiftedImmediate; } 626 bool isRotImm() const { return Kind == RotateImmediate; } 627 bool isBitfield() const { return Kind == BitfieldDescriptor; } 628 bool isPostIdxRegShifted() const { return Kind == PostIndexRegister; } 629 bool isPostIdxReg() const { 630 return Kind == PostIndexRegister && PostIdxReg.ShiftTy == ARM_AM::no_shift; 631 } 632 bool isMemNoOffset() const { 633 if (Kind != Memory) 634 return false; 635 // No offset of any kind. 636 return Mem.OffsetRegNum == 0 && Mem.OffsetImm == 0; 637 } 638 bool isAddrMode2() const { 639 if (Kind != Memory) 640 return false; 641 // Check for register offset. 642 if (Mem.OffsetRegNum) return true; 643 // Immediate offset in range [-4095, 4095]. 644 if (!Mem.OffsetImm) return true; 645 int64_t Val = Mem.OffsetImm->getValue(); 646 return Val > -4096 && Val < 4096; 647 } 648 bool isAM2OffsetImm() const { 649 if (Kind != Immediate) 650 return false; 651 // Immediate offset in range [-4095, 4095]. 652 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 653 if (!CE) return false; 654 int64_t Val = CE->getValue(); 655 return Val > -4096 && Val < 4096; 656 } 657 bool isAddrMode3() const { 658 if (Kind != Memory) 659 return false; 660 // No shifts are legal for AM3. 661 if (Mem.ShiftType != ARM_AM::no_shift) return false; 662 // Check for register offset. 663 if (Mem.OffsetRegNum) return true; 664 // Immediate offset in range [-255, 255]. 665 if (!Mem.OffsetImm) return true; 666 int64_t Val = Mem.OffsetImm->getValue(); 667 return Val > -256 && Val < 256; 668 } 669 bool isAM3Offset() const { 670 if (Kind != Immediate && Kind != PostIndexRegister) 671 return false; 672 if (Kind == PostIndexRegister) 673 return PostIdxReg.ShiftTy == ARM_AM::no_shift; 674 // Immediate offset in range [-255, 255]. 675 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 676 if (!CE) return false; 677 int64_t Val = CE->getValue(); 678 // Special case, #-0 is INT32_MIN. 679 return (Val > -256 && Val < 256) || Val == INT32_MIN; 680 } 681 bool isAddrMode5() const { 682 if (Kind != Memory) 683 return false; 684 // Check for register offset. 685 if (Mem.OffsetRegNum) return false; 686 // Immediate offset in range [-1020, 1020] and a multiple of 4. 687 if (!Mem.OffsetImm) return true; 688 int64_t Val = Mem.OffsetImm->getValue(); 689 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) || 690 Val == INT32_MIN; 691 } 692 bool isMemRegOffset() const { 693 if (Kind != Memory || !Mem.OffsetRegNum) 694 return false; 695 return true; 696 } 697 bool isT2MemRegOffset() const { 698 if (Kind != Memory || !Mem.OffsetRegNum || Mem.isNegative) 699 return false; 700 // Only lsl #{0, 1, 2, 3} allowed. 701 if (Mem.ShiftType == ARM_AM::no_shift) 702 return true; 703 if (Mem.ShiftType != ARM_AM::lsl || Mem.ShiftImm > 3) 704 return false; 705 return true; 706 } 707 bool isMemThumbRR() const { 708 // Thumb reg+reg addressing is simple. Just two registers, a base and 709 // an offset. No shifts, negations or any other complicating factors. 710 if (Kind != Memory || !Mem.OffsetRegNum || Mem.isNegative || 711 Mem.ShiftType != ARM_AM::no_shift) 712 return false; 713 return isARMLowRegister(Mem.BaseRegNum) && 714 (!Mem.OffsetRegNum || isARMLowRegister(Mem.OffsetRegNum)); 715 } 716 bool isMemThumbRIs4() const { 717 if (Kind != Memory || Mem.OffsetRegNum != 0 || 718 !isARMLowRegister(Mem.BaseRegNum)) 719 return false; 720 // Immediate offset, multiple of 4 in range [0, 124]. 721 if (!Mem.OffsetImm) return true; 722 int64_t Val = Mem.OffsetImm->getValue(); 723 return Val >= 0 && Val <= 124 && (Val % 4) == 0; 724 } 725 bool isMemThumbRIs2() const { 726 if (Kind != Memory || Mem.OffsetRegNum != 0 || 727 !isARMLowRegister(Mem.BaseRegNum)) 728 return false; 729 // Immediate offset, multiple of 4 in range [0, 62]. 730 if (!Mem.OffsetImm) return true; 731 int64_t Val = Mem.OffsetImm->getValue(); 732 return Val >= 0 && Val <= 62 && (Val % 2) == 0; 733 } 734 bool isMemThumbRIs1() const { 735 if (Kind != Memory || Mem.OffsetRegNum != 0 || 736 !isARMLowRegister(Mem.BaseRegNum)) 737 return false; 738 // Immediate offset in range [0, 31]. 739 if (!Mem.OffsetImm) return true; 740 int64_t Val = Mem.OffsetImm->getValue(); 741 return Val >= 0 && Val <= 31; 742 } 743 bool isMemThumbSPI() const { 744 if (Kind != Memory || Mem.OffsetRegNum != 0 || Mem.BaseRegNum != ARM::SP) 745 return false; 746 // Immediate offset, multiple of 4 in range [0, 1020]. 747 if (!Mem.OffsetImm) return true; 748 int64_t Val = Mem.OffsetImm->getValue(); 749 return Val >= 0 && Val <= 1020 && (Val % 4) == 0; 750 } 751 bool isMemImm8s4Offset() const { 752 if (Kind != Memory || Mem.OffsetRegNum != 0) 753 return false; 754 // Immediate offset a multiple of 4 in range [-1020, 1020]. 755 if (!Mem.OffsetImm) return true; 756 int64_t Val = Mem.OffsetImm->getValue(); 757 return Val >= -1020 && Val <= 1020 && (Val & 3) == 0; 758 } 759 bool isMemImm0_1020s4Offset() const { 760 if (Kind != Memory || Mem.OffsetRegNum != 0) 761 return false; 762 // Immediate offset a multiple of 4 in range [0, 1020]. 763 if (!Mem.OffsetImm) return true; 764 int64_t Val = Mem.OffsetImm->getValue(); 765 return Val >= 0 && Val <= 1020 && (Val & 3) == 0; 766 } 767 bool isMemImm8Offset() const { 768 if (Kind != Memory || Mem.OffsetRegNum != 0) 769 return false; 770 // Immediate offset in range [-255, 255]. 771 if (!Mem.OffsetImm) return true; 772 int64_t Val = Mem.OffsetImm->getValue(); 773 return Val > -256 && Val < 256; 774 } 775 bool isMemPosImm8Offset() const { 776 if (Kind != Memory || Mem.OffsetRegNum != 0) 777 return false; 778 // Immediate offset in range [0, 255]. 779 if (!Mem.OffsetImm) return true; 780 int64_t Val = Mem.OffsetImm->getValue(); 781 return Val >= 0 && Val < 256; 782 } 783 bool isMemNegImm8Offset() const { 784 if (Kind != Memory || Mem.OffsetRegNum != 0) 785 return false; 786 // Immediate offset in range [-255, -1]. 787 if (!Mem.OffsetImm) return true; 788 int64_t Val = Mem.OffsetImm->getValue(); 789 return Val > -256 && Val < 0; 790 } 791 bool isMemUImm12Offset() const { 792 // If we have an immediate that's not a constant, treat it as a label 793 // reference needing a fixup. If it is a constant, it's something else 794 // and we reject it. 795 if (Kind == Immediate && !isa<MCConstantExpr>(getImm())) 796 return true; 797 798 if (Kind != Memory || Mem.OffsetRegNum != 0) 799 return false; 800 // Immediate offset in range [0, 4095]. 801 if (!Mem.OffsetImm) return true; 802 int64_t Val = Mem.OffsetImm->getValue(); 803 return (Val >= 0 && Val < 4096); 804 } 805 bool isMemImm12Offset() const { 806 // If we have an immediate that's not a constant, treat it as a label 807 // reference needing a fixup. If it is a constant, it's something else 808 // and we reject it. 809 if (Kind == Immediate && !isa<MCConstantExpr>(getImm())) 810 return true; 811 812 if (Kind != Memory || Mem.OffsetRegNum != 0) 813 return false; 814 // Immediate offset in range [-4095, 4095]. 815 if (!Mem.OffsetImm) return true; 816 int64_t Val = Mem.OffsetImm->getValue(); 817 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN); 818 } 819 bool isPostIdxImm8() const { 820 if (Kind != Immediate) 821 return false; 822 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 823 if (!CE) return false; 824 int64_t Val = CE->getValue(); 825 return (Val > -256 && Val < 256) || (Val == INT32_MIN); 826 } 827 828 bool isMSRMask() const { return Kind == MSRMask; } 829 bool isProcIFlags() const { return Kind == ProcIFlags; } 830 831 void addExpr(MCInst &Inst, const MCExpr *Expr) const { 832 // Add as immediates when possible. Null MCExpr = 0. 833 if (Expr == 0) 834 Inst.addOperand(MCOperand::CreateImm(0)); 835 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr)) 836 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 837 else 838 Inst.addOperand(MCOperand::CreateExpr(Expr)); 839 } 840 841 void addCondCodeOperands(MCInst &Inst, unsigned N) const { 842 assert(N == 2 && "Invalid number of operands!"); 843 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); 844 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; 845 Inst.addOperand(MCOperand::CreateReg(RegNum)); 846 } 847 848 void addCoprocNumOperands(MCInst &Inst, unsigned N) const { 849 assert(N == 1 && "Invalid number of operands!"); 850 Inst.addOperand(MCOperand::CreateImm(getCoproc())); 851 } 852 853 void addITMaskOperands(MCInst &Inst, unsigned N) const { 854 assert(N == 1 && "Invalid number of operands!"); 855 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask)); 856 } 857 858 void addITCondCodeOperands(MCInst &Inst, unsigned N) const { 859 assert(N == 1 && "Invalid number of operands!"); 860 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); 861 } 862 863 void addCoprocRegOperands(MCInst &Inst, unsigned N) const { 864 assert(N == 1 && "Invalid number of operands!"); 865 Inst.addOperand(MCOperand::CreateImm(getCoproc())); 866 } 867 868 void addCCOutOperands(MCInst &Inst, unsigned N) const { 869 assert(N == 1 && "Invalid number of operands!"); 870 Inst.addOperand(MCOperand::CreateReg(getReg())); 871 } 872 873 void addRegOperands(MCInst &Inst, unsigned N) const { 874 assert(N == 1 && "Invalid number of operands!"); 875 Inst.addOperand(MCOperand::CreateReg(getReg())); 876 } 877 878 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const { 879 assert(N == 3 && "Invalid number of operands!"); 880 assert(isRegShiftedReg() && "addRegShiftedRegOperands() on non RegShiftedReg!"); 881 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg)); 882 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg)); 883 Inst.addOperand(MCOperand::CreateImm( 884 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm))); 885 } 886 887 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const { 888 assert(N == 2 && "Invalid number of operands!"); 889 assert(isRegShiftedImm() && "addRegShiftedImmOperands() on non RegShiftedImm!"); 890 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg)); 891 Inst.addOperand(MCOperand::CreateImm( 892 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm))); 893 } 894 895 void addShifterImmOperands(MCInst &Inst, unsigned N) const { 896 assert(N == 1 && "Invalid number of operands!"); 897 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) | 898 ShifterImm.Imm)); 899 } 900 901 void addRegListOperands(MCInst &Inst, unsigned N) const { 902 assert(N == 1 && "Invalid number of operands!"); 903 const SmallVectorImpl<unsigned> &RegList = getRegList(); 904 for (SmallVectorImpl<unsigned>::const_iterator 905 I = RegList.begin(), E = RegList.end(); I != E; ++I) 906 Inst.addOperand(MCOperand::CreateReg(*I)); 907 } 908 909 void addDPRRegListOperands(MCInst &Inst, unsigned N) const { 910 addRegListOperands(Inst, N); 911 } 912 913 void addSPRRegListOperands(MCInst &Inst, unsigned N) const { 914 addRegListOperands(Inst, N); 915 } 916 917 void addRotImmOperands(MCInst &Inst, unsigned N) const { 918 assert(N == 1 && "Invalid number of operands!"); 919 // Encoded as val>>3. The printer handles display as 8, 16, 24. 920 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3)); 921 } 922 923 void addBitfieldOperands(MCInst &Inst, unsigned N) const { 924 assert(N == 1 && "Invalid number of operands!"); 925 // Munge the lsb/width into a bitfield mask. 926 unsigned lsb = Bitfield.LSB; 927 unsigned width = Bitfield.Width; 928 // Make a 32-bit mask w/ the referenced bits clear and all other bits set. 929 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >> 930 (32 - (lsb + width))); 931 Inst.addOperand(MCOperand::CreateImm(Mask)); 932 } 933 934 void addImmOperands(MCInst &Inst, unsigned N) const { 935 assert(N == 1 && "Invalid number of operands!"); 936 addExpr(Inst, getImm()); 937 } 938 939 void addImm8s4Operands(MCInst &Inst, unsigned N) const { 940 assert(N == 1 && "Invalid number of operands!"); 941 // FIXME: We really want to scale the value here, but the LDRD/STRD 942 // instruction don't encode operands that way yet. 943 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 944 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 945 } 946 947 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const { 948 assert(N == 1 && "Invalid number of operands!"); 949 // The immediate is scaled by four in the encoding and is stored 950 // in the MCInst as such. Lop off the low two bits here. 951 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 952 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4)); 953 } 954 955 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const { 956 assert(N == 1 && "Invalid number of operands!"); 957 // The immediate is scaled by four in the encoding and is stored 958 // in the MCInst as such. Lop off the low two bits here. 959 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 960 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4)); 961 } 962 963 void addImm0_255Operands(MCInst &Inst, unsigned N) const { 964 assert(N == 1 && "Invalid number of operands!"); 965 addExpr(Inst, getImm()); 966 } 967 968 void addImm0_7Operands(MCInst &Inst, unsigned N) const { 969 assert(N == 1 && "Invalid number of operands!"); 970 addExpr(Inst, getImm()); 971 } 972 973 void addImm0_15Operands(MCInst &Inst, unsigned N) const { 974 assert(N == 1 && "Invalid number of operands!"); 975 addExpr(Inst, getImm()); 976 } 977 978 void addImm0_31Operands(MCInst &Inst, unsigned N) const { 979 assert(N == 1 && "Invalid number of operands!"); 980 addExpr(Inst, getImm()); 981 } 982 983 void addImm1_16Operands(MCInst &Inst, unsigned N) const { 984 assert(N == 1 && "Invalid number of operands!"); 985 // The constant encodes as the immediate-1, and we store in the instruction 986 // the bits as encoded, so subtract off one here. 987 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 988 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1)); 989 } 990 991 void addImm1_32Operands(MCInst &Inst, unsigned N) const { 992 assert(N == 1 && "Invalid number of operands!"); 993 // The constant encodes as the immediate-1, and we store in the instruction 994 // the bits as encoded, so subtract off one here. 995 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 996 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1)); 997 } 998 999 void addImm0_65535Operands(MCInst &Inst, unsigned N) const { 1000 assert(N == 1 && "Invalid number of operands!"); 1001 addExpr(Inst, getImm()); 1002 } 1003 1004 void addImm0_65535ExprOperands(MCInst &Inst, unsigned N) const { 1005 assert(N == 1 && "Invalid number of operands!"); 1006 addExpr(Inst, getImm()); 1007 } 1008 1009 void addImm24bitOperands(MCInst &Inst, unsigned N) const { 1010 assert(N == 1 && "Invalid number of operands!"); 1011 addExpr(Inst, getImm()); 1012 } 1013 1014 void addImmThumbSROperands(MCInst &Inst, unsigned N) const { 1015 assert(N == 1 && "Invalid number of operands!"); 1016 // The constant encodes as the immediate, except for 32, which encodes as 1017 // zero. 1018 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1019 unsigned Imm = CE->getValue(); 1020 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm))); 1021 } 1022 1023 void addPKHLSLImmOperands(MCInst &Inst, unsigned N) const { 1024 assert(N == 1 && "Invalid number of operands!"); 1025 addExpr(Inst, getImm()); 1026 } 1027 1028 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const { 1029 assert(N == 1 && "Invalid number of operands!"); 1030 // An ASR value of 32 encodes as 0, so that's how we want to add it to 1031 // the instruction as well. 1032 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1033 int Val = CE->getValue(); 1034 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val)); 1035 } 1036 1037 void addARMSOImmOperands(MCInst &Inst, unsigned N) const { 1038 assert(N == 1 && "Invalid number of operands!"); 1039 addExpr(Inst, getImm()); 1040 } 1041 1042 void addT2SOImmOperands(MCInst &Inst, unsigned N) const { 1043 assert(N == 1 && "Invalid number of operands!"); 1044 addExpr(Inst, getImm()); 1045 } 1046 1047 void addSetEndImmOperands(MCInst &Inst, unsigned N) const { 1048 assert(N == 1 && "Invalid number of operands!"); 1049 addExpr(Inst, getImm()); 1050 } 1051 1052 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const { 1053 assert(N == 1 && "Invalid number of operands!"); 1054 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt()))); 1055 } 1056 1057 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const { 1058 assert(N == 1 && "Invalid number of operands!"); 1059 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum)); 1060 } 1061 1062 void addAddrMode2Operands(MCInst &Inst, unsigned N) const { 1063 assert(N == 3 && "Invalid number of operands!"); 1064 int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0; 1065 if (!Mem.OffsetRegNum) { 1066 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1067 // Special case for #-0 1068 if (Val == INT32_MIN) Val = 0; 1069 if (Val < 0) Val = -Val; 1070 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); 1071 } else { 1072 // For register offset, we encode the shift type and negation flag 1073 // here. 1074 Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add, 1075 Mem.ShiftImm, Mem.ShiftType); 1076 } 1077 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum)); 1078 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum)); 1079 Inst.addOperand(MCOperand::CreateImm(Val)); 1080 } 1081 1082 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const { 1083 assert(N == 2 && "Invalid number of operands!"); 1084 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1085 assert(CE && "non-constant AM2OffsetImm operand!"); 1086 int32_t Val = CE->getValue(); 1087 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1088 // Special case for #-0 1089 if (Val == INT32_MIN) Val = 0; 1090 if (Val < 0) Val = -Val; 1091 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); 1092 Inst.addOperand(MCOperand::CreateReg(0)); 1093 Inst.addOperand(MCOperand::CreateImm(Val)); 1094 } 1095 1096 void addAddrMode3Operands(MCInst &Inst, unsigned N) const { 1097 assert(N == 3 && "Invalid number of operands!"); 1098 int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0; 1099 if (!Mem.OffsetRegNum) { 1100 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1101 // Special case for #-0 1102 if (Val == INT32_MIN) Val = 0; 1103 if (Val < 0) Val = -Val; 1104 Val = ARM_AM::getAM3Opc(AddSub, Val); 1105 } else { 1106 // For register offset, we encode the shift type and negation flag 1107 // here. 1108 Val = ARM_AM::getAM3Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add, 0); 1109 } 1110 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum)); 1111 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum)); 1112 Inst.addOperand(MCOperand::CreateImm(Val)); 1113 } 1114 1115 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const { 1116 assert(N == 2 && "Invalid number of operands!"); 1117 if (Kind == PostIndexRegister) { 1118 int32_t Val = 1119 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0); 1120 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 1121 Inst.addOperand(MCOperand::CreateImm(Val)); 1122 return; 1123 } 1124 1125 // Constant offset. 1126 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm()); 1127 int32_t Val = CE->getValue(); 1128 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1129 // Special case for #-0 1130 if (Val == INT32_MIN) Val = 0; 1131 if (Val < 0) Val = -Val; 1132 Val = ARM_AM::getAM3Opc(AddSub, Val); 1133 Inst.addOperand(MCOperand::CreateReg(0)); 1134 Inst.addOperand(MCOperand::CreateImm(Val)); 1135 } 1136 1137 void addAddrMode5Operands(MCInst &Inst, unsigned N) const { 1138 assert(N == 2 && "Invalid number of operands!"); 1139 // The lower two bits are always zero and as such are not encoded. 1140 int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() / 4 : 0; 1141 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1142 // Special case for #-0 1143 if (Val == INT32_MIN) Val = 0; 1144 if (Val < 0) Val = -Val; 1145 Val = ARM_AM::getAM5Opc(AddSub, Val); 1146 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum)); 1147 Inst.addOperand(MCOperand::CreateImm(Val)); 1148 } 1149 1150 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const { 1151 assert(N == 2 && "Invalid number of operands!"); 1152 int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0; 1153 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum)); 1154 Inst.addOperand(MCOperand::CreateImm(Val)); 1155 } 1156 1157 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const { 1158 assert(N == 2 && "Invalid number of operands!"); 1159 // The lower two bits are always zero and as such are not encoded. 1160 int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() / 4 : 0; 1161 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum)); 1162 Inst.addOperand(MCOperand::CreateImm(Val)); 1163 } 1164 1165 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const { 1166 assert(N == 2 && "Invalid number of operands!"); 1167 int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0; 1168 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum)); 1169 Inst.addOperand(MCOperand::CreateImm(Val)); 1170 } 1171 1172 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const { 1173 addMemImm8OffsetOperands(Inst, N); 1174 } 1175 1176 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const { 1177 addMemImm8OffsetOperands(Inst, N); 1178 } 1179 1180 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const { 1181 assert(N == 2 && "Invalid number of operands!"); 1182 // If this is an immediate, it's a label reference. 1183 if (Kind == Immediate) { 1184 addExpr(Inst, getImm()); 1185 Inst.addOperand(MCOperand::CreateImm(0)); 1186 return; 1187 } 1188 1189 // Otherwise, it's a normal memory reg+offset. 1190 int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0; 1191 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum)); 1192 Inst.addOperand(MCOperand::CreateImm(Val)); 1193 } 1194 1195 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const { 1196 assert(N == 2 && "Invalid number of operands!"); 1197 // If this is an immediate, it's a label reference. 1198 if (Kind == Immediate) { 1199 addExpr(Inst, getImm()); 1200 Inst.addOperand(MCOperand::CreateImm(0)); 1201 return; 1202 } 1203 1204 // Otherwise, it's a normal memory reg+offset. 1205 int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0; 1206 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum)); 1207 Inst.addOperand(MCOperand::CreateImm(Val)); 1208 } 1209 1210 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const { 1211 assert(N == 3 && "Invalid number of operands!"); 1212 unsigned Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add, 1213 Mem.ShiftImm, Mem.ShiftType); 1214 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum)); 1215 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum)); 1216 Inst.addOperand(MCOperand::CreateImm(Val)); 1217 } 1218 1219 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const { 1220 assert(N == 3 && "Invalid number of operands!"); 1221 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum)); 1222 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum)); 1223 Inst.addOperand(MCOperand::CreateImm(Mem.ShiftImm)); 1224 } 1225 1226 void addMemThumbRROperands(MCInst &Inst, unsigned N) const { 1227 assert(N == 2 && "Invalid number of operands!"); 1228 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum)); 1229 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum)); 1230 } 1231 1232 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const { 1233 assert(N == 2 && "Invalid number of operands!"); 1234 int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 4) : 0; 1235 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum)); 1236 Inst.addOperand(MCOperand::CreateImm(Val)); 1237 } 1238 1239 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const { 1240 assert(N == 2 && "Invalid number of operands!"); 1241 int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 2) : 0; 1242 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum)); 1243 Inst.addOperand(MCOperand::CreateImm(Val)); 1244 } 1245 1246 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const { 1247 assert(N == 2 && "Invalid number of operands!"); 1248 int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue()) : 0; 1249 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum)); 1250 Inst.addOperand(MCOperand::CreateImm(Val)); 1251 } 1252 1253 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const { 1254 assert(N == 2 && "Invalid number of operands!"); 1255 int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 4) : 0; 1256 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum)); 1257 Inst.addOperand(MCOperand::CreateImm(Val)); 1258 } 1259 1260 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const { 1261 assert(N == 1 && "Invalid number of operands!"); 1262 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1263 assert(CE && "non-constant post-idx-imm8 operand!"); 1264 int Imm = CE->getValue(); 1265 bool isAdd = Imm >= 0; 1266 if (Imm == INT32_MIN) Imm = 0; 1267 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8; 1268 Inst.addOperand(MCOperand::CreateImm(Imm)); 1269 } 1270 1271 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const { 1272 assert(N == 2 && "Invalid number of operands!"); 1273 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 1274 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd)); 1275 } 1276 1277 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const { 1278 assert(N == 2 && "Invalid number of operands!"); 1279 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 1280 // The sign, shift type, and shift amount are encoded in a single operand 1281 // using the AM2 encoding helpers. 1282 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub; 1283 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm, 1284 PostIdxReg.ShiftTy); 1285 Inst.addOperand(MCOperand::CreateImm(Imm)); 1286 } 1287 1288 void addMSRMaskOperands(MCInst &Inst, unsigned N) const { 1289 assert(N == 1 && "Invalid number of operands!"); 1290 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask()))); 1291 } 1292 1293 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const { 1294 assert(N == 1 && "Invalid number of operands!"); 1295 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags()))); 1296 } 1297 1298 virtual void print(raw_ostream &OS) const; 1299 1300 static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) { 1301 ARMOperand *Op = new ARMOperand(ITCondMask); 1302 Op->ITMask.Mask = Mask; 1303 Op->StartLoc = S; 1304 Op->EndLoc = S; 1305 return Op; 1306 } 1307 1308 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) { 1309 ARMOperand *Op = new ARMOperand(CondCode); 1310 Op->CC.Val = CC; 1311 Op->StartLoc = S; 1312 Op->EndLoc = S; 1313 return Op; 1314 } 1315 1316 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) { 1317 ARMOperand *Op = new ARMOperand(CoprocNum); 1318 Op->Cop.Val = CopVal; 1319 Op->StartLoc = S; 1320 Op->EndLoc = S; 1321 return Op; 1322 } 1323 1324 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) { 1325 ARMOperand *Op = new ARMOperand(CoprocReg); 1326 Op->Cop.Val = CopVal; 1327 Op->StartLoc = S; 1328 Op->EndLoc = S; 1329 return Op; 1330 } 1331 1332 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) { 1333 ARMOperand *Op = new ARMOperand(CCOut); 1334 Op->Reg.RegNum = RegNum; 1335 Op->StartLoc = S; 1336 Op->EndLoc = S; 1337 return Op; 1338 } 1339 1340 static ARMOperand *CreateToken(StringRef Str, SMLoc S) { 1341 ARMOperand *Op = new ARMOperand(Token); 1342 Op->Tok.Data = Str.data(); 1343 Op->Tok.Length = Str.size(); 1344 Op->StartLoc = S; 1345 Op->EndLoc = S; 1346 return Op; 1347 } 1348 1349 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) { 1350 ARMOperand *Op = new ARMOperand(Register); 1351 Op->Reg.RegNum = RegNum; 1352 Op->StartLoc = S; 1353 Op->EndLoc = E; 1354 return Op; 1355 } 1356 1357 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, 1358 unsigned SrcReg, 1359 unsigned ShiftReg, 1360 unsigned ShiftImm, 1361 SMLoc S, SMLoc E) { 1362 ARMOperand *Op = new ARMOperand(ShiftedRegister); 1363 Op->RegShiftedReg.ShiftTy = ShTy; 1364 Op->RegShiftedReg.SrcReg = SrcReg; 1365 Op->RegShiftedReg.ShiftReg = ShiftReg; 1366 Op->RegShiftedReg.ShiftImm = ShiftImm; 1367 Op->StartLoc = S; 1368 Op->EndLoc = E; 1369 return Op; 1370 } 1371 1372 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, 1373 unsigned SrcReg, 1374 unsigned ShiftImm, 1375 SMLoc S, SMLoc E) { 1376 ARMOperand *Op = new ARMOperand(ShiftedImmediate); 1377 Op->RegShiftedImm.ShiftTy = ShTy; 1378 Op->RegShiftedImm.SrcReg = SrcReg; 1379 Op->RegShiftedImm.ShiftImm = ShiftImm; 1380 Op->StartLoc = S; 1381 Op->EndLoc = E; 1382 return Op; 1383 } 1384 1385 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm, 1386 SMLoc S, SMLoc E) { 1387 ARMOperand *Op = new ARMOperand(ShifterImmediate); 1388 Op->ShifterImm.isASR = isASR; 1389 Op->ShifterImm.Imm = Imm; 1390 Op->StartLoc = S; 1391 Op->EndLoc = E; 1392 return Op; 1393 } 1394 1395 static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) { 1396 ARMOperand *Op = new ARMOperand(RotateImmediate); 1397 Op->RotImm.Imm = Imm; 1398 Op->StartLoc = S; 1399 Op->EndLoc = E; 1400 return Op; 1401 } 1402 1403 static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width, 1404 SMLoc S, SMLoc E) { 1405 ARMOperand *Op = new ARMOperand(BitfieldDescriptor); 1406 Op->Bitfield.LSB = LSB; 1407 Op->Bitfield.Width = Width; 1408 Op->StartLoc = S; 1409 Op->EndLoc = E; 1410 return Op; 1411 } 1412 1413 static ARMOperand * 1414 CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs, 1415 SMLoc StartLoc, SMLoc EndLoc) { 1416 KindTy Kind = RegisterList; 1417 1418 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().first)) 1419 Kind = DPRRegisterList; 1420 else if (ARMMCRegisterClasses[ARM::SPRRegClassID]. 1421 contains(Regs.front().first)) 1422 Kind = SPRRegisterList; 1423 1424 ARMOperand *Op = new ARMOperand(Kind); 1425 for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator 1426 I = Regs.begin(), E = Regs.end(); I != E; ++I) 1427 Op->Registers.push_back(I->first); 1428 array_pod_sort(Op->Registers.begin(), Op->Registers.end()); 1429 Op->StartLoc = StartLoc; 1430 Op->EndLoc = EndLoc; 1431 return Op; 1432 } 1433 1434 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) { 1435 ARMOperand *Op = new ARMOperand(Immediate); 1436 Op->Imm.Val = Val; 1437 Op->StartLoc = S; 1438 Op->EndLoc = E; 1439 return Op; 1440 } 1441 1442 static ARMOperand *CreateMem(unsigned BaseRegNum, 1443 const MCConstantExpr *OffsetImm, 1444 unsigned OffsetRegNum, 1445 ARM_AM::ShiftOpc ShiftType, 1446 unsigned ShiftImm, 1447 bool isNegative, 1448 SMLoc S, SMLoc E) { 1449 ARMOperand *Op = new ARMOperand(Memory); 1450 Op->Mem.BaseRegNum = BaseRegNum; 1451 Op->Mem.OffsetImm = OffsetImm; 1452 Op->Mem.OffsetRegNum = OffsetRegNum; 1453 Op->Mem.ShiftType = ShiftType; 1454 Op->Mem.ShiftImm = ShiftImm; 1455 Op->Mem.isNegative = isNegative; 1456 Op->StartLoc = S; 1457 Op->EndLoc = E; 1458 return Op; 1459 } 1460 1461 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd, 1462 ARM_AM::ShiftOpc ShiftTy, 1463 unsigned ShiftImm, 1464 SMLoc S, SMLoc E) { 1465 ARMOperand *Op = new ARMOperand(PostIndexRegister); 1466 Op->PostIdxReg.RegNum = RegNum; 1467 Op->PostIdxReg.isAdd = isAdd; 1468 Op->PostIdxReg.ShiftTy = ShiftTy; 1469 Op->PostIdxReg.ShiftImm = ShiftImm; 1470 Op->StartLoc = S; 1471 Op->EndLoc = E; 1472 return Op; 1473 } 1474 1475 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) { 1476 ARMOperand *Op = new ARMOperand(MemBarrierOpt); 1477 Op->MBOpt.Val = Opt; 1478 Op->StartLoc = S; 1479 Op->EndLoc = S; 1480 return Op; 1481 } 1482 1483 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) { 1484 ARMOperand *Op = new ARMOperand(ProcIFlags); 1485 Op->IFlags.Val = IFlags; 1486 Op->StartLoc = S; 1487 Op->EndLoc = S; 1488 return Op; 1489 } 1490 1491 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) { 1492 ARMOperand *Op = new ARMOperand(MSRMask); 1493 Op->MMask.Val = MMask; 1494 Op->StartLoc = S; 1495 Op->EndLoc = S; 1496 return Op; 1497 } 1498}; 1499 1500} // end anonymous namespace. 1501 1502void ARMOperand::print(raw_ostream &OS) const { 1503 switch (Kind) { 1504 case CondCode: 1505 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">"; 1506 break; 1507 case CCOut: 1508 OS << "<ccout " << getReg() << ">"; 1509 break; 1510 case ITCondMask: { 1511 static char MaskStr[][6] = { "()", "(t)", "(e)", "(tt)", "(et)", "(te)", 1512 "(ee)", "(ttt)", "(ett)", "(tet)", "(eet)", "(tte)", "(ete)", 1513 "(tee)", "(eee)" }; 1514 assert((ITMask.Mask & 0xf) == ITMask.Mask); 1515 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">"; 1516 break; 1517 } 1518 case CoprocNum: 1519 OS << "<coprocessor number: " << getCoproc() << ">"; 1520 break; 1521 case CoprocReg: 1522 OS << "<coprocessor register: " << getCoproc() << ">"; 1523 break; 1524 case MSRMask: 1525 OS << "<mask: " << getMSRMask() << ">"; 1526 break; 1527 case Immediate: 1528 getImm()->print(OS); 1529 break; 1530 case MemBarrierOpt: 1531 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">"; 1532 break; 1533 case Memory: 1534 OS << "<memory " 1535 << " base:" << Mem.BaseRegNum; 1536 OS << ">"; 1537 break; 1538 case PostIndexRegister: 1539 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-") 1540 << PostIdxReg.RegNum; 1541 if (PostIdxReg.ShiftTy != ARM_AM::no_shift) 1542 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " " 1543 << PostIdxReg.ShiftImm; 1544 OS << ">"; 1545 break; 1546 case ProcIFlags: { 1547 OS << "<ARM_PROC::"; 1548 unsigned IFlags = getProcIFlags(); 1549 for (int i=2; i >= 0; --i) 1550 if (IFlags & (1 << i)) 1551 OS << ARM_PROC::IFlagsToString(1 << i); 1552 OS << ">"; 1553 break; 1554 } 1555 case Register: 1556 OS << "<register " << getReg() << ">"; 1557 break; 1558 case ShifterImmediate: 1559 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl") 1560 << " #" << ShifterImm.Imm << ">"; 1561 break; 1562 case ShiftedRegister: 1563 OS << "<so_reg_reg " 1564 << RegShiftedReg.SrcReg 1565 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedReg.ShiftImm)) 1566 << ", " << RegShiftedReg.ShiftReg << ", " 1567 << ARM_AM::getSORegOffset(RegShiftedReg.ShiftImm) 1568 << ">"; 1569 break; 1570 case ShiftedImmediate: 1571 OS << "<so_reg_imm " 1572 << RegShiftedImm.SrcReg 1573 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedImm.ShiftImm)) 1574 << ", " << ARM_AM::getSORegOffset(RegShiftedImm.ShiftImm) 1575 << ">"; 1576 break; 1577 case RotateImmediate: 1578 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">"; 1579 break; 1580 case BitfieldDescriptor: 1581 OS << "<bitfield " << "lsb: " << Bitfield.LSB 1582 << ", width: " << Bitfield.Width << ">"; 1583 break; 1584 case RegisterList: 1585 case DPRRegisterList: 1586 case SPRRegisterList: { 1587 OS << "<register_list "; 1588 1589 const SmallVectorImpl<unsigned> &RegList = getRegList(); 1590 for (SmallVectorImpl<unsigned>::const_iterator 1591 I = RegList.begin(), E = RegList.end(); I != E; ) { 1592 OS << *I; 1593 if (++I < E) OS << ", "; 1594 } 1595 1596 OS << ">"; 1597 break; 1598 } 1599 case Token: 1600 OS << "'" << getToken() << "'"; 1601 break; 1602 } 1603} 1604 1605/// @name Auto-generated Match Functions 1606/// { 1607 1608static unsigned MatchRegisterName(StringRef Name); 1609 1610/// } 1611 1612bool ARMAsmParser::ParseRegister(unsigned &RegNo, 1613 SMLoc &StartLoc, SMLoc &EndLoc) { 1614 RegNo = tryParseRegister(); 1615 1616 return (RegNo == (unsigned)-1); 1617} 1618 1619/// Try to parse a register name. The token must be an Identifier when called, 1620/// and if it is a register name the token is eaten and the register number is 1621/// returned. Otherwise return -1. 1622/// 1623int ARMAsmParser::tryParseRegister() { 1624 const AsmToken &Tok = Parser.getTok(); 1625 if (Tok.isNot(AsmToken::Identifier)) return -1; 1626 1627 // FIXME: Validate register for the current architecture; we have to do 1628 // validation later, so maybe there is no need for this here. 1629 std::string upperCase = Tok.getString().str(); 1630 std::string lowerCase = LowercaseString(upperCase); 1631 unsigned RegNum = MatchRegisterName(lowerCase); 1632 if (!RegNum) { 1633 RegNum = StringSwitch<unsigned>(lowerCase) 1634 .Case("r13", ARM::SP) 1635 .Case("r14", ARM::LR) 1636 .Case("r15", ARM::PC) 1637 .Case("ip", ARM::R12) 1638 .Default(0); 1639 } 1640 if (!RegNum) return -1; 1641 1642 Parser.Lex(); // Eat identifier token. 1643 return RegNum; 1644} 1645 1646// Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0. 1647// If a recoverable error occurs, return 1. If an irrecoverable error 1648// occurs, return -1. An irrecoverable error is one where tokens have been 1649// consumed in the process of trying to parse the shifter (i.e., when it is 1650// indeed a shifter operand, but malformed). 1651int ARMAsmParser::tryParseShiftRegister( 1652 SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1653 SMLoc S = Parser.getTok().getLoc(); 1654 const AsmToken &Tok = Parser.getTok(); 1655 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 1656 1657 std::string upperCase = Tok.getString().str(); 1658 std::string lowerCase = LowercaseString(upperCase); 1659 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase) 1660 .Case("lsl", ARM_AM::lsl) 1661 .Case("lsr", ARM_AM::lsr) 1662 .Case("asr", ARM_AM::asr) 1663 .Case("ror", ARM_AM::ror) 1664 .Case("rrx", ARM_AM::rrx) 1665 .Default(ARM_AM::no_shift); 1666 1667 if (ShiftTy == ARM_AM::no_shift) 1668 return 1; 1669 1670 Parser.Lex(); // Eat the operator. 1671 1672 // The source register for the shift has already been added to the 1673 // operand list, so we need to pop it off and combine it into the shifted 1674 // register operand instead. 1675 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val()); 1676 if (!PrevOp->isReg()) 1677 return Error(PrevOp->getStartLoc(), "shift must be of a register"); 1678 int SrcReg = PrevOp->getReg(); 1679 int64_t Imm = 0; 1680 int ShiftReg = 0; 1681 if (ShiftTy == ARM_AM::rrx) { 1682 // RRX Doesn't have an explicit shift amount. The encoder expects 1683 // the shift register to be the same as the source register. Seems odd, 1684 // but OK. 1685 ShiftReg = SrcReg; 1686 } else { 1687 // Figure out if this is shifted by a constant or a register (for non-RRX). 1688 if (Parser.getTok().is(AsmToken::Hash)) { 1689 Parser.Lex(); // Eat hash. 1690 SMLoc ImmLoc = Parser.getTok().getLoc(); 1691 const MCExpr *ShiftExpr = 0; 1692 if (getParser().ParseExpression(ShiftExpr)) { 1693 Error(ImmLoc, "invalid immediate shift value"); 1694 return -1; 1695 } 1696 // The expression must be evaluatable as an immediate. 1697 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr); 1698 if (!CE) { 1699 Error(ImmLoc, "invalid immediate shift value"); 1700 return -1; 1701 } 1702 // Range check the immediate. 1703 // lsl, ror: 0 <= imm <= 31 1704 // lsr, asr: 0 <= imm <= 32 1705 Imm = CE->getValue(); 1706 if (Imm < 0 || 1707 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) || 1708 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) { 1709 Error(ImmLoc, "immediate shift value out of range"); 1710 return -1; 1711 } 1712 } else if (Parser.getTok().is(AsmToken::Identifier)) { 1713 ShiftReg = tryParseRegister(); 1714 SMLoc L = Parser.getTok().getLoc(); 1715 if (ShiftReg == -1) { 1716 Error (L, "expected immediate or register in shift operand"); 1717 return -1; 1718 } 1719 } else { 1720 Error (Parser.getTok().getLoc(), 1721 "expected immediate or register in shift operand"); 1722 return -1; 1723 } 1724 } 1725 1726 if (ShiftReg && ShiftTy != ARM_AM::rrx) 1727 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg, 1728 ShiftReg, Imm, 1729 S, Parser.getTok().getLoc())); 1730 else 1731 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm, 1732 S, Parser.getTok().getLoc())); 1733 1734 return 0; 1735} 1736 1737 1738/// Try to parse a register name. The token must be an Identifier when called. 1739/// If it's a register, an AsmOperand is created. Another AsmOperand is created 1740/// if there is a "writeback". 'true' if it's not a register. 1741/// 1742/// TODO this is likely to change to allow different register types and or to 1743/// parse for a specific register type. 1744bool ARMAsmParser:: 1745tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1746 SMLoc S = Parser.getTok().getLoc(); 1747 int RegNo = tryParseRegister(); 1748 if (RegNo == -1) 1749 return true; 1750 1751 Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc())); 1752 1753 const AsmToken &ExclaimTok = Parser.getTok(); 1754 if (ExclaimTok.is(AsmToken::Exclaim)) { 1755 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(), 1756 ExclaimTok.getLoc())); 1757 Parser.Lex(); // Eat exclaim token 1758 } 1759 1760 return false; 1761} 1762 1763/// MatchCoprocessorOperandName - Try to parse an coprocessor related 1764/// instruction with a symbolic operand name. Example: "p1", "p7", "c3", 1765/// "c5", ... 1766static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) { 1767 // Use the same layout as the tablegen'erated register name matcher. Ugly, 1768 // but efficient. 1769 switch (Name.size()) { 1770 default: break; 1771 case 2: 1772 if (Name[0] != CoprocOp) 1773 return -1; 1774 switch (Name[1]) { 1775 default: return -1; 1776 case '0': return 0; 1777 case '1': return 1; 1778 case '2': return 2; 1779 case '3': return 3; 1780 case '4': return 4; 1781 case '5': return 5; 1782 case '6': return 6; 1783 case '7': return 7; 1784 case '8': return 8; 1785 case '9': return 9; 1786 } 1787 break; 1788 case 3: 1789 if (Name[0] != CoprocOp || Name[1] != '1') 1790 return -1; 1791 switch (Name[2]) { 1792 default: return -1; 1793 case '0': return 10; 1794 case '1': return 11; 1795 case '2': return 12; 1796 case '3': return 13; 1797 case '4': return 14; 1798 case '5': return 15; 1799 } 1800 break; 1801 } 1802 1803 return -1; 1804} 1805 1806/// parseITCondCode - Try to parse a condition code for an IT instruction. 1807ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 1808parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1809 SMLoc S = Parser.getTok().getLoc(); 1810 const AsmToken &Tok = Parser.getTok(); 1811 if (!Tok.is(AsmToken::Identifier)) 1812 return MatchOperand_NoMatch; 1813 unsigned CC = StringSwitch<unsigned>(Tok.getString()) 1814 .Case("eq", ARMCC::EQ) 1815 .Case("ne", ARMCC::NE) 1816 .Case("hs", ARMCC::HS) 1817 .Case("cs", ARMCC::HS) 1818 .Case("lo", ARMCC::LO) 1819 .Case("cc", ARMCC::LO) 1820 .Case("mi", ARMCC::MI) 1821 .Case("pl", ARMCC::PL) 1822 .Case("vs", ARMCC::VS) 1823 .Case("vc", ARMCC::VC) 1824 .Case("hi", ARMCC::HI) 1825 .Case("ls", ARMCC::LS) 1826 .Case("ge", ARMCC::GE) 1827 .Case("lt", ARMCC::LT) 1828 .Case("gt", ARMCC::GT) 1829 .Case("le", ARMCC::LE) 1830 .Case("al", ARMCC::AL) 1831 .Default(~0U); 1832 if (CC == ~0U) 1833 return MatchOperand_NoMatch; 1834 Parser.Lex(); // Eat the token. 1835 1836 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S)); 1837 1838 return MatchOperand_Success; 1839} 1840 1841/// parseCoprocNumOperand - Try to parse an coprocessor number operand. The 1842/// token must be an Identifier when called, and if it is a coprocessor 1843/// number, the token is eaten and the operand is added to the operand list. 1844ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 1845parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1846 SMLoc S = Parser.getTok().getLoc(); 1847 const AsmToken &Tok = Parser.getTok(); 1848 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 1849 1850 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p'); 1851 if (Num == -1) 1852 return MatchOperand_NoMatch; 1853 1854 Parser.Lex(); // Eat identifier token. 1855 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S)); 1856 return MatchOperand_Success; 1857} 1858 1859/// parseCoprocRegOperand - Try to parse an coprocessor register operand. The 1860/// token must be an Identifier when called, and if it is a coprocessor 1861/// number, the token is eaten and the operand is added to the operand list. 1862ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 1863parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1864 SMLoc S = Parser.getTok().getLoc(); 1865 const AsmToken &Tok = Parser.getTok(); 1866 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 1867 1868 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c'); 1869 if (Reg == -1) 1870 return MatchOperand_NoMatch; 1871 1872 Parser.Lex(); // Eat identifier token. 1873 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S)); 1874 return MatchOperand_Success; 1875} 1876 1877// For register list parsing, we need to map from raw GPR register numbering 1878// to the enumeration values. The enumeration values aren't sorted by 1879// register number due to our using "sp", "lr" and "pc" as canonical names. 1880static unsigned getNextRegister(unsigned Reg) { 1881 // If this is a GPR, we need to do it manually, otherwise we can rely 1882 // on the sort ordering of the enumeration since the other reg-classes 1883 // are sane. 1884 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 1885 return Reg + 1; 1886 switch(Reg) { 1887 default: assert(0 && "Invalid GPR number!"); 1888 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2; 1889 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4; 1890 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6; 1891 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8; 1892 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10; 1893 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12; 1894 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR; 1895 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0; 1896 } 1897} 1898 1899/// Parse a register list. 1900bool ARMAsmParser:: 1901parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1902 assert(Parser.getTok().is(AsmToken::LCurly) && 1903 "Token is not a Left Curly Brace"); 1904 SMLoc S = Parser.getTok().getLoc(); 1905 Parser.Lex(); // Eat '{' token. 1906 SMLoc RegLoc = Parser.getTok().getLoc(); 1907 1908 // Check the first register in the list to see what register class 1909 // this is a list of. 1910 int Reg = tryParseRegister(); 1911 if (Reg == -1) 1912 return Error(RegLoc, "register expected"); 1913 1914 MCRegisterClass *RC; 1915 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 1916 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID]; 1917 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) 1918 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID]; 1919 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg)) 1920 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID]; 1921 else 1922 return Error(RegLoc, "invalid register in register list"); 1923 1924 // The reglist instructions have at most 16 registers, so reserve 1925 // space for that many. 1926 SmallVector<std::pair<unsigned, SMLoc>, 16> Registers; 1927 // Store the first register. 1928 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc)); 1929 1930 // This starts immediately after the first register token in the list, 1931 // so we can see either a comma or a minus (range separator) as a legal 1932 // next token. 1933 while (Parser.getTok().is(AsmToken::Comma) || 1934 Parser.getTok().is(AsmToken::Minus)) { 1935 if (Parser.getTok().is(AsmToken::Minus)) { 1936 Parser.Lex(); // Eat the comma. 1937 SMLoc EndLoc = Parser.getTok().getLoc(); 1938 int EndReg = tryParseRegister(); 1939 if (EndReg == -1) 1940 return Error(EndLoc, "register expected"); 1941 // If the register is the same as the start reg, there's nothing 1942 // more to do. 1943 if (Reg == EndReg) 1944 continue; 1945 // The register must be in the same register class as the first. 1946 if (!RC->contains(EndReg)) 1947 return Error(EndLoc, "invalid register in register list"); 1948 // Ranges must go from low to high. 1949 if (getARMRegisterNumbering(Reg) > getARMRegisterNumbering(EndReg)) 1950 return Error(EndLoc, "bad range in register list"); 1951 1952 // Add all the registers in the range to the register list. 1953 while (Reg != EndReg) { 1954 Reg = getNextRegister(Reg); 1955 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc)); 1956 } 1957 continue; 1958 } 1959 Parser.Lex(); // Eat the comma. 1960 RegLoc = Parser.getTok().getLoc(); 1961 int OldReg = Reg; 1962 Reg = tryParseRegister(); 1963 if (Reg == -1) 1964 return Error(RegLoc, "register expected"); 1965 // The register must be in the same register class as the first. 1966 if (!RC->contains(Reg)) 1967 return Error(RegLoc, "invalid register in register list"); 1968 // List must be monotonically increasing. 1969 if (getARMRegisterNumbering(Reg) <= getARMRegisterNumbering(OldReg)) 1970 return Error(RegLoc, "register list not in ascending order"); 1971 // VFP register lists must also be contiguous. 1972 // It's OK to use the enumeration values directly here rather, as the 1973 // VFP register classes have the enum sorted properly. 1974 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] && 1975 Reg != OldReg + 1) 1976 return Error(RegLoc, "non-contiguous register range"); 1977 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc)); 1978 } 1979 1980 SMLoc E = Parser.getTok().getLoc(); 1981 if (Parser.getTok().isNot(AsmToken::RCurly)) 1982 return Error(E, "'}' expected"); 1983 Parser.Lex(); // Eat '}' token. 1984 1985 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E)); 1986 return false; 1987} 1988 1989/// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options. 1990ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 1991parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1992 SMLoc S = Parser.getTok().getLoc(); 1993 const AsmToken &Tok = Parser.getTok(); 1994 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 1995 StringRef OptStr = Tok.getString(); 1996 1997 unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size())) 1998 .Case("sy", ARM_MB::SY) 1999 .Case("st", ARM_MB::ST) 2000 .Case("sh", ARM_MB::ISH) 2001 .Case("ish", ARM_MB::ISH) 2002 .Case("shst", ARM_MB::ISHST) 2003 .Case("ishst", ARM_MB::ISHST) 2004 .Case("nsh", ARM_MB::NSH) 2005 .Case("un", ARM_MB::NSH) 2006 .Case("nshst", ARM_MB::NSHST) 2007 .Case("unst", ARM_MB::NSHST) 2008 .Case("osh", ARM_MB::OSH) 2009 .Case("oshst", ARM_MB::OSHST) 2010 .Default(~0U); 2011 2012 if (Opt == ~0U) 2013 return MatchOperand_NoMatch; 2014 2015 Parser.Lex(); // Eat identifier token. 2016 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S)); 2017 return MatchOperand_Success; 2018} 2019 2020/// parseProcIFlagsOperand - Try to parse iflags from CPS instruction. 2021ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2022parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2023 SMLoc S = Parser.getTok().getLoc(); 2024 const AsmToken &Tok = Parser.getTok(); 2025 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 2026 StringRef IFlagsStr = Tok.getString(); 2027 2028 unsigned IFlags = 0; 2029 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) { 2030 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1)) 2031 .Case("a", ARM_PROC::A) 2032 .Case("i", ARM_PROC::I) 2033 .Case("f", ARM_PROC::F) 2034 .Default(~0U); 2035 2036 // If some specific iflag is already set, it means that some letter is 2037 // present more than once, this is not acceptable. 2038 if (Flag == ~0U || (IFlags & Flag)) 2039 return MatchOperand_NoMatch; 2040 2041 IFlags |= Flag; 2042 } 2043 2044 Parser.Lex(); // Eat identifier token. 2045 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S)); 2046 return MatchOperand_Success; 2047} 2048 2049/// parseMSRMaskOperand - Try to parse mask flags from MSR instruction. 2050ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2051parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2052 SMLoc S = Parser.getTok().getLoc(); 2053 const AsmToken &Tok = Parser.getTok(); 2054 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 2055 StringRef Mask = Tok.getString(); 2056 2057 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf" 2058 size_t Start = 0, Next = Mask.find('_'); 2059 StringRef Flags = ""; 2060 std::string SpecReg = LowercaseString(Mask.slice(Start, Next)); 2061 if (Next != StringRef::npos) 2062 Flags = Mask.slice(Next+1, Mask.size()); 2063 2064 // FlagsVal contains the complete mask: 2065 // 3-0: Mask 2066 // 4: Special Reg (cpsr, apsr => 0; spsr => 1) 2067 unsigned FlagsVal = 0; 2068 2069 if (SpecReg == "apsr") { 2070 FlagsVal = StringSwitch<unsigned>(Flags) 2071 .Case("nzcvq", 0x8) // same as CPSR_f 2072 .Case("g", 0x4) // same as CPSR_s 2073 .Case("nzcvqg", 0xc) // same as CPSR_fs 2074 .Default(~0U); 2075 2076 if (FlagsVal == ~0U) { 2077 if (!Flags.empty()) 2078 return MatchOperand_NoMatch; 2079 else 2080 FlagsVal = 0; // No flag 2081 } 2082 } else if (SpecReg == "cpsr" || SpecReg == "spsr") { 2083 if (Flags == "all") // cpsr_all is an alias for cpsr_fc 2084 Flags = "fc"; 2085 for (int i = 0, e = Flags.size(); i != e; ++i) { 2086 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1)) 2087 .Case("c", 1) 2088 .Case("x", 2) 2089 .Case("s", 4) 2090 .Case("f", 8) 2091 .Default(~0U); 2092 2093 // If some specific flag is already set, it means that some letter is 2094 // present more than once, this is not acceptable. 2095 if (FlagsVal == ~0U || (FlagsVal & Flag)) 2096 return MatchOperand_NoMatch; 2097 FlagsVal |= Flag; 2098 } 2099 } else // No match for special register. 2100 return MatchOperand_NoMatch; 2101 2102 // Special register without flags are equivalent to "fc" flags. 2103 if (!FlagsVal) 2104 FlagsVal = 0x9; 2105 2106 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1) 2107 if (SpecReg == "spsr") 2108 FlagsVal |= 16; 2109 2110 Parser.Lex(); // Eat identifier token. 2111 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); 2112 return MatchOperand_Success; 2113} 2114 2115ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2116parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op, 2117 int Low, int High) { 2118 const AsmToken &Tok = Parser.getTok(); 2119 if (Tok.isNot(AsmToken::Identifier)) { 2120 Error(Parser.getTok().getLoc(), Op + " operand expected."); 2121 return MatchOperand_ParseFail; 2122 } 2123 StringRef ShiftName = Tok.getString(); 2124 std::string LowerOp = LowercaseString(Op); 2125 std::string UpperOp = UppercaseString(Op); 2126 if (ShiftName != LowerOp && ShiftName != UpperOp) { 2127 Error(Parser.getTok().getLoc(), Op + " operand expected."); 2128 return MatchOperand_ParseFail; 2129 } 2130 Parser.Lex(); // Eat shift type token. 2131 2132 // There must be a '#' and a shift amount. 2133 if (Parser.getTok().isNot(AsmToken::Hash)) { 2134 Error(Parser.getTok().getLoc(), "'#' expected"); 2135 return MatchOperand_ParseFail; 2136 } 2137 Parser.Lex(); // Eat hash token. 2138 2139 const MCExpr *ShiftAmount; 2140 SMLoc Loc = Parser.getTok().getLoc(); 2141 if (getParser().ParseExpression(ShiftAmount)) { 2142 Error(Loc, "illegal expression"); 2143 return MatchOperand_ParseFail; 2144 } 2145 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 2146 if (!CE) { 2147 Error(Loc, "constant expression expected"); 2148 return MatchOperand_ParseFail; 2149 } 2150 int Val = CE->getValue(); 2151 if (Val < Low || Val > High) { 2152 Error(Loc, "immediate value out of range"); 2153 return MatchOperand_ParseFail; 2154 } 2155 2156 Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc())); 2157 2158 return MatchOperand_Success; 2159} 2160 2161ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2162parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2163 const AsmToken &Tok = Parser.getTok(); 2164 SMLoc S = Tok.getLoc(); 2165 if (Tok.isNot(AsmToken::Identifier)) { 2166 Error(Tok.getLoc(), "'be' or 'le' operand expected"); 2167 return MatchOperand_ParseFail; 2168 } 2169 int Val = StringSwitch<int>(Tok.getString()) 2170 .Case("be", 1) 2171 .Case("le", 0) 2172 .Default(-1); 2173 Parser.Lex(); // Eat the token. 2174 2175 if (Val == -1) { 2176 Error(Tok.getLoc(), "'be' or 'le' operand expected"); 2177 return MatchOperand_ParseFail; 2178 } 2179 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val, 2180 getContext()), 2181 S, Parser.getTok().getLoc())); 2182 return MatchOperand_Success; 2183} 2184 2185/// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT 2186/// instructions. Legal values are: 2187/// lsl #n 'n' in [0,31] 2188/// asr #n 'n' in [1,32] 2189/// n == 32 encoded as n == 0. 2190ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2191parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2192 const AsmToken &Tok = Parser.getTok(); 2193 SMLoc S = Tok.getLoc(); 2194 if (Tok.isNot(AsmToken::Identifier)) { 2195 Error(S, "shift operator 'asr' or 'lsl' expected"); 2196 return MatchOperand_ParseFail; 2197 } 2198 StringRef ShiftName = Tok.getString(); 2199 bool isASR; 2200 if (ShiftName == "lsl" || ShiftName == "LSL") 2201 isASR = false; 2202 else if (ShiftName == "asr" || ShiftName == "ASR") 2203 isASR = true; 2204 else { 2205 Error(S, "shift operator 'asr' or 'lsl' expected"); 2206 return MatchOperand_ParseFail; 2207 } 2208 Parser.Lex(); // Eat the operator. 2209 2210 // A '#' and a shift amount. 2211 if (Parser.getTok().isNot(AsmToken::Hash)) { 2212 Error(Parser.getTok().getLoc(), "'#' expected"); 2213 return MatchOperand_ParseFail; 2214 } 2215 Parser.Lex(); // Eat hash token. 2216 2217 const MCExpr *ShiftAmount; 2218 SMLoc E = Parser.getTok().getLoc(); 2219 if (getParser().ParseExpression(ShiftAmount)) { 2220 Error(E, "malformed shift expression"); 2221 return MatchOperand_ParseFail; 2222 } 2223 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 2224 if (!CE) { 2225 Error(E, "shift amount must be an immediate"); 2226 return MatchOperand_ParseFail; 2227 } 2228 2229 int64_t Val = CE->getValue(); 2230 if (isASR) { 2231 // Shift amount must be in [1,32] 2232 if (Val < 1 || Val > 32) { 2233 Error(E, "'asr' shift amount must be in range [1,32]"); 2234 return MatchOperand_ParseFail; 2235 } 2236 // asr #32 encoded as asr #0. 2237 if (Val == 32) Val = 0; 2238 } else { 2239 // Shift amount must be in [1,32] 2240 if (Val < 0 || Val > 31) { 2241 Error(E, "'lsr' shift amount must be in range [0,31]"); 2242 return MatchOperand_ParseFail; 2243 } 2244 } 2245 2246 E = Parser.getTok().getLoc(); 2247 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E)); 2248 2249 return MatchOperand_Success; 2250} 2251 2252/// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family 2253/// of instructions. Legal values are: 2254/// ror #n 'n' in {0, 8, 16, 24} 2255ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2256parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2257 const AsmToken &Tok = Parser.getTok(); 2258 SMLoc S = Tok.getLoc(); 2259 if (Tok.isNot(AsmToken::Identifier)) { 2260 Error(S, "rotate operator 'ror' expected"); 2261 return MatchOperand_ParseFail; 2262 } 2263 StringRef ShiftName = Tok.getString(); 2264 if (ShiftName != "ror" && ShiftName != "ROR") { 2265 Error(S, "rotate operator 'ror' expected"); 2266 return MatchOperand_ParseFail; 2267 } 2268 Parser.Lex(); // Eat the operator. 2269 2270 // A '#' and a rotate amount. 2271 if (Parser.getTok().isNot(AsmToken::Hash)) { 2272 Error(Parser.getTok().getLoc(), "'#' expected"); 2273 return MatchOperand_ParseFail; 2274 } 2275 Parser.Lex(); // Eat hash token. 2276 2277 const MCExpr *ShiftAmount; 2278 SMLoc E = Parser.getTok().getLoc(); 2279 if (getParser().ParseExpression(ShiftAmount)) { 2280 Error(E, "malformed rotate expression"); 2281 return MatchOperand_ParseFail; 2282 } 2283 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 2284 if (!CE) { 2285 Error(E, "rotate amount must be an immediate"); 2286 return MatchOperand_ParseFail; 2287 } 2288 2289 int64_t Val = CE->getValue(); 2290 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension) 2291 // normally, zero is represented in asm by omitting the rotate operand 2292 // entirely. 2293 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) { 2294 Error(E, "'ror' rotate amount must be 8, 16, or 24"); 2295 return MatchOperand_ParseFail; 2296 } 2297 2298 E = Parser.getTok().getLoc(); 2299 Operands.push_back(ARMOperand::CreateRotImm(Val, S, E)); 2300 2301 return MatchOperand_Success; 2302} 2303 2304ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2305parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2306 SMLoc S = Parser.getTok().getLoc(); 2307 // The bitfield descriptor is really two operands, the LSB and the width. 2308 if (Parser.getTok().isNot(AsmToken::Hash)) { 2309 Error(Parser.getTok().getLoc(), "'#' expected"); 2310 return MatchOperand_ParseFail; 2311 } 2312 Parser.Lex(); // Eat hash token. 2313 2314 const MCExpr *LSBExpr; 2315 SMLoc E = Parser.getTok().getLoc(); 2316 if (getParser().ParseExpression(LSBExpr)) { 2317 Error(E, "malformed immediate expression"); 2318 return MatchOperand_ParseFail; 2319 } 2320 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr); 2321 if (!CE) { 2322 Error(E, "'lsb' operand must be an immediate"); 2323 return MatchOperand_ParseFail; 2324 } 2325 2326 int64_t LSB = CE->getValue(); 2327 // The LSB must be in the range [0,31] 2328 if (LSB < 0 || LSB > 31) { 2329 Error(E, "'lsb' operand must be in the range [0,31]"); 2330 return MatchOperand_ParseFail; 2331 } 2332 E = Parser.getTok().getLoc(); 2333 2334 // Expect another immediate operand. 2335 if (Parser.getTok().isNot(AsmToken::Comma)) { 2336 Error(Parser.getTok().getLoc(), "too few operands"); 2337 return MatchOperand_ParseFail; 2338 } 2339 Parser.Lex(); // Eat hash token. 2340 if (Parser.getTok().isNot(AsmToken::Hash)) { 2341 Error(Parser.getTok().getLoc(), "'#' expected"); 2342 return MatchOperand_ParseFail; 2343 } 2344 Parser.Lex(); // Eat hash token. 2345 2346 const MCExpr *WidthExpr; 2347 if (getParser().ParseExpression(WidthExpr)) { 2348 Error(E, "malformed immediate expression"); 2349 return MatchOperand_ParseFail; 2350 } 2351 CE = dyn_cast<MCConstantExpr>(WidthExpr); 2352 if (!CE) { 2353 Error(E, "'width' operand must be an immediate"); 2354 return MatchOperand_ParseFail; 2355 } 2356 2357 int64_t Width = CE->getValue(); 2358 // The LSB must be in the range [1,32-lsb] 2359 if (Width < 1 || Width > 32 - LSB) { 2360 Error(E, "'width' operand must be in the range [1,32-lsb]"); 2361 return MatchOperand_ParseFail; 2362 } 2363 E = Parser.getTok().getLoc(); 2364 2365 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E)); 2366 2367 return MatchOperand_Success; 2368} 2369 2370ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2371parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2372 // Check for a post-index addressing register operand. Specifically: 2373 // postidx_reg := '+' register {, shift} 2374 // | '-' register {, shift} 2375 // | register {, shift} 2376 2377 // This method must return MatchOperand_NoMatch without consuming any tokens 2378 // in the case where there is no match, as other alternatives take other 2379 // parse methods. 2380 AsmToken Tok = Parser.getTok(); 2381 SMLoc S = Tok.getLoc(); 2382 bool haveEaten = false; 2383 bool isAdd = true; 2384 int Reg = -1; 2385 if (Tok.is(AsmToken::Plus)) { 2386 Parser.Lex(); // Eat the '+' token. 2387 haveEaten = true; 2388 } else if (Tok.is(AsmToken::Minus)) { 2389 Parser.Lex(); // Eat the '-' token. 2390 isAdd = false; 2391 haveEaten = true; 2392 } 2393 if (Parser.getTok().is(AsmToken::Identifier)) 2394 Reg = tryParseRegister(); 2395 if (Reg == -1) { 2396 if (!haveEaten) 2397 return MatchOperand_NoMatch; 2398 Error(Parser.getTok().getLoc(), "register expected"); 2399 return MatchOperand_ParseFail; 2400 } 2401 SMLoc E = Parser.getTok().getLoc(); 2402 2403 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift; 2404 unsigned ShiftImm = 0; 2405 if (Parser.getTok().is(AsmToken::Comma)) { 2406 Parser.Lex(); // Eat the ','. 2407 if (parseMemRegOffsetShift(ShiftTy, ShiftImm)) 2408 return MatchOperand_ParseFail; 2409 } 2410 2411 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy, 2412 ShiftImm, S, E)); 2413 2414 return MatchOperand_Success; 2415} 2416 2417ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2418parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2419 // Check for a post-index addressing register operand. Specifically: 2420 // am3offset := '+' register 2421 // | '-' register 2422 // | register 2423 // | # imm 2424 // | # + imm 2425 // | # - imm 2426 2427 // This method must return MatchOperand_NoMatch without consuming any tokens 2428 // in the case where there is no match, as other alternatives take other 2429 // parse methods. 2430 AsmToken Tok = Parser.getTok(); 2431 SMLoc S = Tok.getLoc(); 2432 2433 // Do immediates first, as we always parse those if we have a '#'. 2434 if (Parser.getTok().is(AsmToken::Hash)) { 2435 Parser.Lex(); // Eat the '#'. 2436 // Explicitly look for a '-', as we need to encode negative zero 2437 // differently. 2438 bool isNegative = Parser.getTok().is(AsmToken::Minus); 2439 const MCExpr *Offset; 2440 if (getParser().ParseExpression(Offset)) 2441 return MatchOperand_ParseFail; 2442 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset); 2443 if (!CE) { 2444 Error(S, "constant expression expected"); 2445 return MatchOperand_ParseFail; 2446 } 2447 SMLoc E = Tok.getLoc(); 2448 // Negative zero is encoded as the flag value INT32_MIN. 2449 int32_t Val = CE->getValue(); 2450 if (isNegative && Val == 0) 2451 Val = INT32_MIN; 2452 2453 Operands.push_back( 2454 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E)); 2455 2456 return MatchOperand_Success; 2457 } 2458 2459 2460 bool haveEaten = false; 2461 bool isAdd = true; 2462 int Reg = -1; 2463 if (Tok.is(AsmToken::Plus)) { 2464 Parser.Lex(); // Eat the '+' token. 2465 haveEaten = true; 2466 } else if (Tok.is(AsmToken::Minus)) { 2467 Parser.Lex(); // Eat the '-' token. 2468 isAdd = false; 2469 haveEaten = true; 2470 } 2471 if (Parser.getTok().is(AsmToken::Identifier)) 2472 Reg = tryParseRegister(); 2473 if (Reg == -1) { 2474 if (!haveEaten) 2475 return MatchOperand_NoMatch; 2476 Error(Parser.getTok().getLoc(), "register expected"); 2477 return MatchOperand_ParseFail; 2478 } 2479 SMLoc E = Parser.getTok().getLoc(); 2480 2481 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift, 2482 0, S, E)); 2483 2484 return MatchOperand_Success; 2485} 2486 2487/// cvtT2LdrdPre - Convert parsed operands to MCInst. 2488/// Needed here because the Asm Gen Matcher can't handle properly tied operands 2489/// when they refer multiple MIOperands inside a single one. 2490bool ARMAsmParser:: 2491cvtT2LdrdPre(MCInst &Inst, unsigned Opcode, 2492 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2493 // Rt, Rt2 2494 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 2495 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 2496 // Create a writeback register dummy placeholder. 2497 Inst.addOperand(MCOperand::CreateReg(0)); 2498 // addr 2499 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2); 2500 // pred 2501 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 2502 return true; 2503} 2504 2505/// cvtT2StrdPre - Convert parsed operands to MCInst. 2506/// Needed here because the Asm Gen Matcher can't handle properly tied operands 2507/// when they refer multiple MIOperands inside a single one. 2508bool ARMAsmParser:: 2509cvtT2StrdPre(MCInst &Inst, unsigned Opcode, 2510 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2511 // Create a writeback register dummy placeholder. 2512 Inst.addOperand(MCOperand::CreateReg(0)); 2513 // Rt, Rt2 2514 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 2515 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 2516 // addr 2517 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2); 2518 // pred 2519 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 2520 return true; 2521} 2522 2523/// cvtLdWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst. 2524/// Needed here because the Asm Gen Matcher can't handle properly tied operands 2525/// when they refer multiple MIOperands inside a single one. 2526bool ARMAsmParser:: 2527cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode, 2528 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2529 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 2530 2531 // Create a writeback register dummy placeholder. 2532 Inst.addOperand(MCOperand::CreateImm(0)); 2533 2534 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2); 2535 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 2536 return true; 2537} 2538 2539/// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst. 2540/// Needed here because the Asm Gen Matcher can't handle properly tied operands 2541/// when they refer multiple MIOperands inside a single one. 2542bool ARMAsmParser:: 2543cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, 2544 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2545 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 2546 2547 // Create a writeback register dummy placeholder. 2548 Inst.addOperand(MCOperand::CreateImm(0)); 2549 2550 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3); 2551 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 2552 return true; 2553} 2554 2555/// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst. 2556/// Needed here because the Asm Gen Matcher can't handle properly tied operands 2557/// when they refer multiple MIOperands inside a single one. 2558bool ARMAsmParser:: 2559cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode, 2560 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2561 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 2562 2563 // Create a writeback register dummy placeholder. 2564 Inst.addOperand(MCOperand::CreateImm(0)); 2565 2566 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2); 2567 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 2568 return true; 2569} 2570 2571 2572/// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst. 2573/// Needed here because the Asm Gen Matcher can't handle properly tied operands 2574/// when they refer multiple MIOperands inside a single one. 2575bool ARMAsmParser:: 2576cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode, 2577 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2578 // Create a writeback register dummy placeholder. 2579 Inst.addOperand(MCOperand::CreateImm(0)); 2580 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 2581 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2); 2582 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 2583 return true; 2584} 2585 2586/// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst. 2587/// Needed here because the Asm Gen Matcher can't handle properly tied operands 2588/// when they refer multiple MIOperands inside a single one. 2589bool ARMAsmParser:: 2590cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, 2591 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2592 // Create a writeback register dummy placeholder. 2593 Inst.addOperand(MCOperand::CreateImm(0)); 2594 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 2595 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3); 2596 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 2597 return true; 2598} 2599 2600/// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst. 2601/// Needed here because the Asm Gen Matcher can't handle properly tied operands 2602/// when they refer multiple MIOperands inside a single one. 2603bool ARMAsmParser:: 2604cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, 2605 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2606 // Create a writeback register dummy placeholder. 2607 Inst.addOperand(MCOperand::CreateImm(0)); 2608 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 2609 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3); 2610 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 2611 return true; 2612} 2613 2614/// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst. 2615/// Needed here because the Asm Gen Matcher can't handle properly tied operands 2616/// when they refer multiple MIOperands inside a single one. 2617bool ARMAsmParser:: 2618cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode, 2619 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2620 // Rt 2621 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 2622 // Create a writeback register dummy placeholder. 2623 Inst.addOperand(MCOperand::CreateImm(0)); 2624 // addr 2625 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 2626 // offset 2627 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1); 2628 // pred 2629 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 2630 return true; 2631} 2632 2633/// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst. 2634/// Needed here because the Asm Gen Matcher can't handle properly tied operands 2635/// when they refer multiple MIOperands inside a single one. 2636bool ARMAsmParser:: 2637cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode, 2638 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2639 // Rt 2640 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 2641 // Create a writeback register dummy placeholder. 2642 Inst.addOperand(MCOperand::CreateImm(0)); 2643 // addr 2644 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 2645 // offset 2646 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2); 2647 // pred 2648 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 2649 return true; 2650} 2651 2652/// cvtStExtTWriteBackImm - Convert parsed operands to MCInst. 2653/// Needed here because the Asm Gen Matcher can't handle properly tied operands 2654/// when they refer multiple MIOperands inside a single one. 2655bool ARMAsmParser:: 2656cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode, 2657 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2658 // Create a writeback register dummy placeholder. 2659 Inst.addOperand(MCOperand::CreateImm(0)); 2660 // Rt 2661 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 2662 // addr 2663 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 2664 // offset 2665 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1); 2666 // pred 2667 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 2668 return true; 2669} 2670 2671/// cvtStExtTWriteBackReg - Convert parsed operands to MCInst. 2672/// Needed here because the Asm Gen Matcher can't handle properly tied operands 2673/// when they refer multiple MIOperands inside a single one. 2674bool ARMAsmParser:: 2675cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode, 2676 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2677 // Create a writeback register dummy placeholder. 2678 Inst.addOperand(MCOperand::CreateImm(0)); 2679 // Rt 2680 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 2681 // addr 2682 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 2683 // offset 2684 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2); 2685 // pred 2686 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 2687 return true; 2688} 2689 2690/// cvtLdrdPre - Convert parsed operands to MCInst. 2691/// Needed here because the Asm Gen Matcher can't handle properly tied operands 2692/// when they refer multiple MIOperands inside a single one. 2693bool ARMAsmParser:: 2694cvtLdrdPre(MCInst &Inst, unsigned Opcode, 2695 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2696 // Rt, Rt2 2697 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 2698 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 2699 // Create a writeback register dummy placeholder. 2700 Inst.addOperand(MCOperand::CreateImm(0)); 2701 // addr 2702 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3); 2703 // pred 2704 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 2705 return true; 2706} 2707 2708/// cvtStrdPre - Convert parsed operands to MCInst. 2709/// Needed here because the Asm Gen Matcher can't handle properly tied operands 2710/// when they refer multiple MIOperands inside a single one. 2711bool ARMAsmParser:: 2712cvtStrdPre(MCInst &Inst, unsigned Opcode, 2713 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2714 // Create a writeback register dummy placeholder. 2715 Inst.addOperand(MCOperand::CreateImm(0)); 2716 // Rt, Rt2 2717 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 2718 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 2719 // addr 2720 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3); 2721 // pred 2722 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 2723 return true; 2724} 2725 2726/// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst. 2727/// Needed here because the Asm Gen Matcher can't handle properly tied operands 2728/// when they refer multiple MIOperands inside a single one. 2729bool ARMAsmParser:: 2730cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, 2731 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2732 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 2733 // Create a writeback register dummy placeholder. 2734 Inst.addOperand(MCOperand::CreateImm(0)); 2735 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3); 2736 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 2737 return true; 2738} 2739 2740/// cvtThumbMultiple- Convert parsed operands to MCInst. 2741/// Needed here because the Asm Gen Matcher can't handle properly tied operands 2742/// when they refer multiple MIOperands inside a single one. 2743bool ARMAsmParser:: 2744cvtThumbMultiply(MCInst &Inst, unsigned Opcode, 2745 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2746 // The second source operand must be the same register as the destination 2747 // operand. 2748 if (Operands.size() == 6 && 2749 (((ARMOperand*)Operands[3])->getReg() != 2750 ((ARMOperand*)Operands[5])->getReg()) && 2751 (((ARMOperand*)Operands[3])->getReg() != 2752 ((ARMOperand*)Operands[4])->getReg())) { 2753 Error(Operands[3]->getStartLoc(), 2754 "destination register must match source register"); 2755 return false; 2756 } 2757 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 2758 ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1); 2759 ((ARMOperand*)Operands[4])->addRegOperands(Inst, 1); 2760 // If we have a three-operand form, use that, else the second source operand 2761 // is just the destination operand again. 2762 if (Operands.size() == 6) 2763 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1); 2764 else 2765 Inst.addOperand(Inst.getOperand(0)); 2766 ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2); 2767 2768 return true; 2769} 2770 2771/// Parse an ARM memory expression, return false if successful else return true 2772/// or an error. The first token must be a '[' when called. 2773bool ARMAsmParser:: 2774parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2775 SMLoc S, E; 2776 assert(Parser.getTok().is(AsmToken::LBrac) && 2777 "Token is not a Left Bracket"); 2778 S = Parser.getTok().getLoc(); 2779 Parser.Lex(); // Eat left bracket token. 2780 2781 const AsmToken &BaseRegTok = Parser.getTok(); 2782 int BaseRegNum = tryParseRegister(); 2783 if (BaseRegNum == -1) 2784 return Error(BaseRegTok.getLoc(), "register expected"); 2785 2786 // The next token must either be a comma or a closing bracket. 2787 const AsmToken &Tok = Parser.getTok(); 2788 if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac)) 2789 return Error(Tok.getLoc(), "malformed memory operand"); 2790 2791 if (Tok.is(AsmToken::RBrac)) { 2792 E = Tok.getLoc(); 2793 Parser.Lex(); // Eat right bracket token. 2794 2795 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift, 2796 0, false, S, E)); 2797 2798 return false; 2799 } 2800 2801 assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!"); 2802 Parser.Lex(); // Eat the comma. 2803 2804 // If we have a '#' it's an immediate offset, else assume it's a register 2805 // offset. 2806 if (Parser.getTok().is(AsmToken::Hash)) { 2807 Parser.Lex(); // Eat the '#'. 2808 E = Parser.getTok().getLoc(); 2809 2810 bool isNegative = getParser().getTok().is(AsmToken::Minus); 2811 const MCExpr *Offset; 2812 if (getParser().ParseExpression(Offset)) 2813 return true; 2814 2815 // The expression has to be a constant. Memory references with relocations 2816 // don't come through here, as they use the <label> forms of the relevant 2817 // instructions. 2818 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset); 2819 if (!CE) 2820 return Error (E, "constant expression expected"); 2821 2822 // If the constant was #-0, represent it as INT32_MIN. 2823 int32_t Val = CE->getValue(); 2824 if (isNegative && Val == 0) 2825 CE = MCConstantExpr::Create(INT32_MIN, getContext()); 2826 2827 // Now we should have the closing ']' 2828 E = Parser.getTok().getLoc(); 2829 if (Parser.getTok().isNot(AsmToken::RBrac)) 2830 return Error(E, "']' expected"); 2831 Parser.Lex(); // Eat right bracket token. 2832 2833 // Don't worry about range checking the value here. That's handled by 2834 // the is*() predicates. 2835 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0, 2836 ARM_AM::no_shift, 0, false, S,E)); 2837 2838 // If there's a pre-indexing writeback marker, '!', just add it as a token 2839 // operand. 2840 if (Parser.getTok().is(AsmToken::Exclaim)) { 2841 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 2842 Parser.Lex(); // Eat the '!'. 2843 } 2844 2845 return false; 2846 } 2847 2848 // The register offset is optionally preceded by a '+' or '-' 2849 bool isNegative = false; 2850 if (Parser.getTok().is(AsmToken::Minus)) { 2851 isNegative = true; 2852 Parser.Lex(); // Eat the '-'. 2853 } else if (Parser.getTok().is(AsmToken::Plus)) { 2854 // Nothing to do. 2855 Parser.Lex(); // Eat the '+'. 2856 } 2857 2858 E = Parser.getTok().getLoc(); 2859 int OffsetRegNum = tryParseRegister(); 2860 if (OffsetRegNum == -1) 2861 return Error(E, "register expected"); 2862 2863 // If there's a shift operator, handle it. 2864 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift; 2865 unsigned ShiftImm = 0; 2866 if (Parser.getTok().is(AsmToken::Comma)) { 2867 Parser.Lex(); // Eat the ','. 2868 if (parseMemRegOffsetShift(ShiftType, ShiftImm)) 2869 return true; 2870 } 2871 2872 // Now we should have the closing ']' 2873 E = Parser.getTok().getLoc(); 2874 if (Parser.getTok().isNot(AsmToken::RBrac)) 2875 return Error(E, "']' expected"); 2876 Parser.Lex(); // Eat right bracket token. 2877 2878 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum, 2879 ShiftType, ShiftImm, isNegative, 2880 S, E)); 2881 2882 // If there's a pre-indexing writeback marker, '!', just add it as a token 2883 // operand. 2884 if (Parser.getTok().is(AsmToken::Exclaim)) { 2885 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 2886 Parser.Lex(); // Eat the '!'. 2887 } 2888 2889 return false; 2890} 2891 2892/// parseMemRegOffsetShift - one of these two: 2893/// ( lsl | lsr | asr | ror ) , # shift_amount 2894/// rrx 2895/// return true if it parses a shift otherwise it returns false. 2896bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St, 2897 unsigned &Amount) { 2898 SMLoc Loc = Parser.getTok().getLoc(); 2899 const AsmToken &Tok = Parser.getTok(); 2900 if (Tok.isNot(AsmToken::Identifier)) 2901 return true; 2902 StringRef ShiftName = Tok.getString(); 2903 if (ShiftName == "lsl" || ShiftName == "LSL") 2904 St = ARM_AM::lsl; 2905 else if (ShiftName == "lsr" || ShiftName == "LSR") 2906 St = ARM_AM::lsr; 2907 else if (ShiftName == "asr" || ShiftName == "ASR") 2908 St = ARM_AM::asr; 2909 else if (ShiftName == "ror" || ShiftName == "ROR") 2910 St = ARM_AM::ror; 2911 else if (ShiftName == "rrx" || ShiftName == "RRX") 2912 St = ARM_AM::rrx; 2913 else 2914 return Error(Loc, "illegal shift operator"); 2915 Parser.Lex(); // Eat shift type token. 2916 2917 // rrx stands alone. 2918 Amount = 0; 2919 if (St != ARM_AM::rrx) { 2920 Loc = Parser.getTok().getLoc(); 2921 // A '#' and a shift amount. 2922 const AsmToken &HashTok = Parser.getTok(); 2923 if (HashTok.isNot(AsmToken::Hash)) 2924 return Error(HashTok.getLoc(), "'#' expected"); 2925 Parser.Lex(); // Eat hash token. 2926 2927 const MCExpr *Expr; 2928 if (getParser().ParseExpression(Expr)) 2929 return true; 2930 // Range check the immediate. 2931 // lsl, ror: 0 <= imm <= 31 2932 // lsr, asr: 0 <= imm <= 32 2933 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 2934 if (!CE) 2935 return Error(Loc, "shift amount must be an immediate"); 2936 int64_t Imm = CE->getValue(); 2937 if (Imm < 0 || 2938 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) || 2939 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32)) 2940 return Error(Loc, "immediate shift value out of range"); 2941 Amount = Imm; 2942 } 2943 2944 return false; 2945} 2946 2947/// Parse a arm instruction operand. For now this parses the operand regardless 2948/// of the mnemonic. 2949bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands, 2950 StringRef Mnemonic) { 2951 SMLoc S, E; 2952 2953 // Check if the current operand has a custom associated parser, if so, try to 2954 // custom parse the operand, or fallback to the general approach. 2955 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic); 2956 if (ResTy == MatchOperand_Success) 2957 return false; 2958 // If there wasn't a custom match, try the generic matcher below. Otherwise, 2959 // there was a match, but an error occurred, in which case, just return that 2960 // the operand parsing failed. 2961 if (ResTy == MatchOperand_ParseFail) 2962 return true; 2963 2964 switch (getLexer().getKind()) { 2965 default: 2966 Error(Parser.getTok().getLoc(), "unexpected token in operand"); 2967 return true; 2968 case AsmToken::Identifier: { 2969 if (!tryParseRegisterWithWriteBack(Operands)) 2970 return false; 2971 int Res = tryParseShiftRegister(Operands); 2972 if (Res == 0) // success 2973 return false; 2974 else if (Res == -1) // irrecoverable error 2975 return true; 2976 2977 // Fall though for the Identifier case that is not a register or a 2978 // special name. 2979 } 2980 case AsmToken::Integer: // things like 1f and 2b as a branch targets 2981 case AsmToken::Dot: { // . as a branch target 2982 // This was not a register so parse other operands that start with an 2983 // identifier (like labels) as expressions and create them as immediates. 2984 const MCExpr *IdVal; 2985 S = Parser.getTok().getLoc(); 2986 if (getParser().ParseExpression(IdVal)) 2987 return true; 2988 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 2989 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E)); 2990 return false; 2991 } 2992 case AsmToken::LBrac: 2993 return parseMemory(Operands); 2994 case AsmToken::LCurly: 2995 return parseRegisterList(Operands); 2996 case AsmToken::Hash: { 2997 // #42 -> immediate. 2998 // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate 2999 S = Parser.getTok().getLoc(); 3000 Parser.Lex(); 3001 bool isNegative = Parser.getTok().is(AsmToken::Minus); 3002 const MCExpr *ImmVal; 3003 if (getParser().ParseExpression(ImmVal)) 3004 return true; 3005 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal); 3006 if (!CE) { 3007 Error(S, "constant expression expected"); 3008 return MatchOperand_ParseFail; 3009 } 3010 int32_t Val = CE->getValue(); 3011 if (isNegative && Val == 0) 3012 ImmVal = MCConstantExpr::Create(INT32_MIN, getContext()); 3013 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 3014 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E)); 3015 return false; 3016 } 3017 case AsmToken::Colon: { 3018 // ":lower16:" and ":upper16:" expression prefixes 3019 // FIXME: Check it's an expression prefix, 3020 // e.g. (FOO - :lower16:BAR) isn't legal. 3021 ARMMCExpr::VariantKind RefKind; 3022 if (parsePrefix(RefKind)) 3023 return true; 3024 3025 const MCExpr *SubExprVal; 3026 if (getParser().ParseExpression(SubExprVal)) 3027 return true; 3028 3029 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal, 3030 getContext()); 3031 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 3032 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E)); 3033 return false; 3034 } 3035 } 3036} 3037 3038// parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e. 3039// :lower16: and :upper16:. 3040bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) { 3041 RefKind = ARMMCExpr::VK_ARM_None; 3042 3043 // :lower16: and :upper16: modifiers 3044 assert(getLexer().is(AsmToken::Colon) && "expected a :"); 3045 Parser.Lex(); // Eat ':' 3046 3047 if (getLexer().isNot(AsmToken::Identifier)) { 3048 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand"); 3049 return true; 3050 } 3051 3052 StringRef IDVal = Parser.getTok().getIdentifier(); 3053 if (IDVal == "lower16") { 3054 RefKind = ARMMCExpr::VK_ARM_LO16; 3055 } else if (IDVal == "upper16") { 3056 RefKind = ARMMCExpr::VK_ARM_HI16; 3057 } else { 3058 Error(Parser.getTok().getLoc(), "unexpected prefix in operand"); 3059 return true; 3060 } 3061 Parser.Lex(); 3062 3063 if (getLexer().isNot(AsmToken::Colon)) { 3064 Error(Parser.getTok().getLoc(), "unexpected token after prefix"); 3065 return true; 3066 } 3067 Parser.Lex(); // Eat the last ':' 3068 return false; 3069} 3070 3071const MCExpr * 3072ARMAsmParser::applyPrefixToExpr(const MCExpr *E, 3073 MCSymbolRefExpr::VariantKind Variant) { 3074 // Recurse over the given expression, rebuilding it to apply the given variant 3075 // to the leftmost symbol. 3076 if (Variant == MCSymbolRefExpr::VK_None) 3077 return E; 3078 3079 switch (E->getKind()) { 3080 case MCExpr::Target: 3081 llvm_unreachable("Can't handle target expr yet"); 3082 case MCExpr::Constant: 3083 llvm_unreachable("Can't handle lower16/upper16 of constant yet"); 3084 3085 case MCExpr::SymbolRef: { 3086 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E); 3087 3088 if (SRE->getKind() != MCSymbolRefExpr::VK_None) 3089 return 0; 3090 3091 return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, getContext()); 3092 } 3093 3094 case MCExpr::Unary: 3095 llvm_unreachable("Can't handle unary expressions yet"); 3096 3097 case MCExpr::Binary: { 3098 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E); 3099 const MCExpr *LHS = applyPrefixToExpr(BE->getLHS(), Variant); 3100 const MCExpr *RHS = BE->getRHS(); 3101 if (!LHS) 3102 return 0; 3103 3104 return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, getContext()); 3105 } 3106 } 3107 3108 assert(0 && "Invalid expression kind!"); 3109 return 0; 3110} 3111 3112/// \brief Given a mnemonic, split out possible predication code and carry 3113/// setting letters to form a canonical mnemonic and flags. 3114// 3115// FIXME: Would be nice to autogen this. 3116// FIXME: This is a bit of a maze of special cases. 3117StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic, 3118 unsigned &PredicationCode, 3119 bool &CarrySetting, 3120 unsigned &ProcessorIMod, 3121 StringRef &ITMask) { 3122 PredicationCode = ARMCC::AL; 3123 CarrySetting = false; 3124 ProcessorIMod = 0; 3125 3126 // Ignore some mnemonics we know aren't predicated forms. 3127 // 3128 // FIXME: Would be nice to autogen this. 3129 if ((Mnemonic == "movs" && isThumb()) || 3130 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" || 3131 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" || 3132 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" || 3133 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" || 3134 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" || 3135 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" || 3136 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal") 3137 return Mnemonic; 3138 3139 // First, split out any predication code. Ignore mnemonics we know aren't 3140 // predicated but do have a carry-set and so weren't caught above. 3141 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" && 3142 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" && 3143 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" && 3144 Mnemonic != "sbcs" && Mnemonic != "rscs") { 3145 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2)) 3146 .Case("eq", ARMCC::EQ) 3147 .Case("ne", ARMCC::NE) 3148 .Case("hs", ARMCC::HS) 3149 .Case("cs", ARMCC::HS) 3150 .Case("lo", ARMCC::LO) 3151 .Case("cc", ARMCC::LO) 3152 .Case("mi", ARMCC::MI) 3153 .Case("pl", ARMCC::PL) 3154 .Case("vs", ARMCC::VS) 3155 .Case("vc", ARMCC::VC) 3156 .Case("hi", ARMCC::HI) 3157 .Case("ls", ARMCC::LS) 3158 .Case("ge", ARMCC::GE) 3159 .Case("lt", ARMCC::LT) 3160 .Case("gt", ARMCC::GT) 3161 .Case("le", ARMCC::LE) 3162 .Case("al", ARMCC::AL) 3163 .Default(~0U); 3164 if (CC != ~0U) { 3165 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2); 3166 PredicationCode = CC; 3167 } 3168 } 3169 3170 // Next, determine if we have a carry setting bit. We explicitly ignore all 3171 // the instructions we know end in 's'. 3172 if (Mnemonic.endswith("s") && 3173 !(Mnemonic == "cps" || Mnemonic == "mls" || 3174 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" || 3175 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" || 3176 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" || 3177 Mnemonic == "vrsqrts" || Mnemonic == "srs" || 3178 (Mnemonic == "movs" && isThumb()))) { 3179 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1); 3180 CarrySetting = true; 3181 } 3182 3183 // The "cps" instruction can have a interrupt mode operand which is glued into 3184 // the mnemonic. Check if this is the case, split it and parse the imod op 3185 if (Mnemonic.startswith("cps")) { 3186 // Split out any imod code. 3187 unsigned IMod = 3188 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2)) 3189 .Case("ie", ARM_PROC::IE) 3190 .Case("id", ARM_PROC::ID) 3191 .Default(~0U); 3192 if (IMod != ~0U) { 3193 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2); 3194 ProcessorIMod = IMod; 3195 } 3196 } 3197 3198 // The "it" instruction has the condition mask on the end of the mnemonic. 3199 if (Mnemonic.startswith("it")) { 3200 ITMask = Mnemonic.slice(2, Mnemonic.size()); 3201 Mnemonic = Mnemonic.slice(0, 2); 3202 } 3203 3204 return Mnemonic; 3205} 3206 3207/// \brief Given a canonical mnemonic, determine if the instruction ever allows 3208/// inclusion of carry set or predication code operands. 3209// 3210// FIXME: It would be nice to autogen this. 3211void ARMAsmParser:: 3212getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet, 3213 bool &CanAcceptPredicationCode) { 3214 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" || 3215 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" || 3216 Mnemonic == "smull" || Mnemonic == "add" || Mnemonic == "adc" || 3217 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" || 3218 Mnemonic == "umlal" || Mnemonic == "orr" || Mnemonic == "mvn" || 3219 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" || 3220 Mnemonic == "sbc" || Mnemonic == "umull" || 3221 Mnemonic == "eor" || Mnemonic == "smlal" || Mnemonic == "neg" || 3222 ((Mnemonic == "mov" || Mnemonic == "mla") && !isThumb())) { 3223 CanAcceptCarrySet = true; 3224 } else { 3225 CanAcceptCarrySet = false; 3226 } 3227 3228 if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" || 3229 Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" || 3230 Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" || 3231 Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" || 3232 Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "setend" || 3233 (Mnemonic == "clrex" && !isThumb()) || 3234 (Mnemonic == "nop" && isThumbOne()) || 3235 ((Mnemonic == "pld" || Mnemonic == "pli" || Mnemonic == "pldw") && 3236 !isThumb()) || 3237 ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs")) && 3238 !isThumb()) || 3239 Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumbOne())) { 3240 CanAcceptPredicationCode = false; 3241 } else { 3242 CanAcceptPredicationCode = true; 3243 } 3244 3245 if (isThumb()) 3246 if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" || 3247 Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp") 3248 CanAcceptPredicationCode = false; 3249} 3250 3251bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic, 3252 SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3253 // FIXME: This is all horribly hacky. We really need a better way to deal 3254 // with optional operands like this in the matcher table. 3255 3256 // The 'mov' mnemonic is special. One variant has a cc_out operand, while 3257 // another does not. Specifically, the MOVW instruction does not. So we 3258 // special case it here and remove the defaulted (non-setting) cc_out 3259 // operand if that's the instruction we're trying to match. 3260 // 3261 // We do this as post-processing of the explicit operands rather than just 3262 // conditionally adding the cc_out in the first place because we need 3263 // to check the type of the parsed immediate operand. 3264 if (Mnemonic == "mov" && Operands.size() > 4 && 3265 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() && 3266 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() && 3267 static_cast<ARMOperand*>(Operands[1])->getReg() == 0) 3268 return true; 3269 3270 // Register-register 'add' for thumb does not have a cc_out operand 3271 // when there are only two register operands. 3272 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 && 3273 static_cast<ARMOperand*>(Operands[3])->isReg() && 3274 static_cast<ARMOperand*>(Operands[4])->isReg() && 3275 static_cast<ARMOperand*>(Operands[1])->getReg() == 0) 3276 return true; 3277 // Register-register 'add' for thumb does not have a cc_out operand 3278 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do 3279 // have to check the immediate range here since Thumb2 has a variant 3280 // that can handle a different range and has a cc_out operand. 3281 if (isThumb() && Mnemonic == "add" && Operands.size() == 6 && 3282 static_cast<ARMOperand*>(Operands[3])->isReg() && 3283 static_cast<ARMOperand*>(Operands[4])->isReg() && 3284 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP && 3285 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 3286 (static_cast<ARMOperand*>(Operands[5])->isReg() || 3287 static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4())) 3288 return true; 3289 // For Thumb2, add immediate does not have a cc_out operand for the 3290 // imm0_4096 variant. That's the least-preferred variant when 3291 // selecting via the generic "add" mnemonic, so to know that we 3292 // should remove the cc_out operand, we have to explicitly check that 3293 // it's not one of the other variants. Ugh. 3294 if (isThumbTwo() && Mnemonic == "add" && Operands.size() == 6 && 3295 static_cast<ARMOperand*>(Operands[3])->isReg() && 3296 static_cast<ARMOperand*>(Operands[4])->isReg() && 3297 static_cast<ARMOperand*>(Operands[5])->isImm()) { 3298 // Nest conditions rather than one big 'if' statement for readability. 3299 // 3300 // If either register is a high reg, it's either one of the SP 3301 // variants (handled above) or a 32-bit encoding, so we just 3302 // check against T3. 3303 if ((!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) || 3304 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg())) && 3305 static_cast<ARMOperand*>(Operands[5])->isT2SOImm()) 3306 return false; 3307 // If both registers are low, we're in an IT block, and the immediate is 3308 // in range, we should use encoding T1 instead, which has a cc_out. 3309 if (inITBlock() && 3310 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) && 3311 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) && 3312 static_cast<ARMOperand*>(Operands[5])->isImm0_7()) 3313 return false; 3314 3315 // Otherwise, we use encoding T4, which does not have a cc_out 3316 // operand. 3317 return true; 3318 } 3319 3320 3321 // Register-register 'add/sub' for thumb does not have a cc_out operand 3322 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also 3323 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't 3324 // right, this will result in better diagnostics (which operand is off) 3325 // anyway. 3326 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") && 3327 (Operands.size() == 5 || Operands.size() == 6) && 3328 static_cast<ARMOperand*>(Operands[3])->isReg() && 3329 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP && 3330 static_cast<ARMOperand*>(Operands[1])->getReg() == 0) 3331 return true; 3332 3333 return false; 3334} 3335 3336/// Parse an arm instruction mnemonic followed by its operands. 3337bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc, 3338 SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3339 // Create the leading tokens for the mnemonic, split by '.' characters. 3340 size_t Start = 0, Next = Name.find('.'); 3341 StringRef Mnemonic = Name.slice(Start, Next); 3342 3343 // Split out the predication code and carry setting flag from the mnemonic. 3344 unsigned PredicationCode; 3345 unsigned ProcessorIMod; 3346 bool CarrySetting; 3347 StringRef ITMask; 3348 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting, 3349 ProcessorIMod, ITMask); 3350 3351 // In Thumb1, only the branch (B) instruction can be predicated. 3352 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") { 3353 Parser.EatToEndOfStatement(); 3354 return Error(NameLoc, "conditional execution not supported in Thumb1"); 3355 } 3356 3357 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc)); 3358 3359 // Handle the IT instruction ITMask. Convert it to a bitmask. This 3360 // is the mask as it will be for the IT encoding if the conditional 3361 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case 3362 // where the conditional bit0 is zero, the instruction post-processing 3363 // will adjust the mask accordingly. 3364 if (Mnemonic == "it") { 3365 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2); 3366 if (ITMask.size() > 3) { 3367 Parser.EatToEndOfStatement(); 3368 return Error(Loc, "too many conditions on IT instruction"); 3369 } 3370 unsigned Mask = 8; 3371 for (unsigned i = ITMask.size(); i != 0; --i) { 3372 char pos = ITMask[i - 1]; 3373 if (pos != 't' && pos != 'e') { 3374 Parser.EatToEndOfStatement(); 3375 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'"); 3376 } 3377 Mask >>= 1; 3378 if (ITMask[i - 1] == 't') 3379 Mask |= 8; 3380 } 3381 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc)); 3382 } 3383 3384 // FIXME: This is all a pretty gross hack. We should automatically handle 3385 // optional operands like this via tblgen. 3386 3387 // Next, add the CCOut and ConditionCode operands, if needed. 3388 // 3389 // For mnemonics which can ever incorporate a carry setting bit or predication 3390 // code, our matching model involves us always generating CCOut and 3391 // ConditionCode operands to match the mnemonic "as written" and then we let 3392 // the matcher deal with finding the right instruction or generating an 3393 // appropriate error. 3394 bool CanAcceptCarrySet, CanAcceptPredicationCode; 3395 getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode); 3396 3397 // If we had a carry-set on an instruction that can't do that, issue an 3398 // error. 3399 if (!CanAcceptCarrySet && CarrySetting) { 3400 Parser.EatToEndOfStatement(); 3401 return Error(NameLoc, "instruction '" + Mnemonic + 3402 "' can not set flags, but 's' suffix specified"); 3403 } 3404 // If we had a predication code on an instruction that can't do that, issue an 3405 // error. 3406 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) { 3407 Parser.EatToEndOfStatement(); 3408 return Error(NameLoc, "instruction '" + Mnemonic + 3409 "' is not predicable, but condition code specified"); 3410 } 3411 3412 // Add the carry setting operand, if necessary. 3413 if (CanAcceptCarrySet) { 3414 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size()); 3415 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0, 3416 Loc)); 3417 } 3418 3419 // Add the predication code operand, if necessary. 3420 if (CanAcceptPredicationCode) { 3421 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() + 3422 CarrySetting); 3423 Operands.push_back(ARMOperand::CreateCondCode( 3424 ARMCC::CondCodes(PredicationCode), Loc)); 3425 } 3426 3427 // Add the processor imod operand, if necessary. 3428 if (ProcessorIMod) { 3429 Operands.push_back(ARMOperand::CreateImm( 3430 MCConstantExpr::Create(ProcessorIMod, getContext()), 3431 NameLoc, NameLoc)); 3432 } 3433 3434 // Add the remaining tokens in the mnemonic. 3435 while (Next != StringRef::npos) { 3436 Start = Next; 3437 Next = Name.find('.', Start + 1); 3438 StringRef ExtraToken = Name.slice(Start, Next); 3439 3440 // For now, we're only parsing Thumb1 (for the most part), so 3441 // just ignore ".n" qualifiers. We'll use them to restrict 3442 // matching when we do Thumb2. 3443 if (ExtraToken != ".n") { 3444 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start); 3445 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc)); 3446 } 3447 } 3448 3449 // Read the remaining operands. 3450 if (getLexer().isNot(AsmToken::EndOfStatement)) { 3451 // Read the first operand. 3452 if (parseOperand(Operands, Mnemonic)) { 3453 Parser.EatToEndOfStatement(); 3454 return true; 3455 } 3456 3457 while (getLexer().is(AsmToken::Comma)) { 3458 Parser.Lex(); // Eat the comma. 3459 3460 // Parse and remember the operand. 3461 if (parseOperand(Operands, Mnemonic)) { 3462 Parser.EatToEndOfStatement(); 3463 return true; 3464 } 3465 } 3466 } 3467 3468 if (getLexer().isNot(AsmToken::EndOfStatement)) { 3469 Parser.EatToEndOfStatement(); 3470 return TokError("unexpected token in argument list"); 3471 } 3472 3473 Parser.Lex(); // Consume the EndOfStatement 3474 3475 // Some instructions, mostly Thumb, have forms for the same mnemonic that 3476 // do and don't have a cc_out optional-def operand. With some spot-checks 3477 // of the operand list, we can figure out which variant we're trying to 3478 // parse and adjust accordingly before actually matching. We shouldn't ever 3479 // try to remove a cc_out operand that was explicitly set on the the 3480 // mnemonic, of course (CarrySetting == true). Reason number #317 the 3481 // table driven matcher doesn't fit well with the ARM instruction set. 3482 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) { 3483 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]); 3484 Operands.erase(Operands.begin() + 1); 3485 delete Op; 3486 } 3487 3488 // ARM mode 'blx' need special handling, as the register operand version 3489 // is predicable, but the label operand version is not. So, we can't rely 3490 // on the Mnemonic based checking to correctly figure out when to put 3491 // a CondCode operand in the list. If we're trying to match the label 3492 // version, remove the CondCode operand here. 3493 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 && 3494 static_cast<ARMOperand*>(Operands[2])->isImm()) { 3495 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]); 3496 Operands.erase(Operands.begin() + 1); 3497 delete Op; 3498 } 3499 3500 // The vector-compare-to-zero instructions have a literal token "#0" at 3501 // the end that comes to here as an immediate operand. Convert it to a 3502 // token to play nicely with the matcher. 3503 if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" || 3504 Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 && 3505 static_cast<ARMOperand*>(Operands[5])->isImm()) { 3506 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]); 3507 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm()); 3508 if (CE && CE->getValue() == 0) { 3509 Operands.erase(Operands.begin() + 5); 3510 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc())); 3511 delete Op; 3512 } 3513 } 3514 // Similarly, the Thumb1 "RSB" instruction has a literal "#0" on the 3515 // end. Convert it to a token here. 3516 if (Mnemonic == "rsb" && isThumb() && Operands.size() == 6 && 3517 static_cast<ARMOperand*>(Operands[5])->isImm()) { 3518 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]); 3519 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm()); 3520 if (CE && CE->getValue() == 0) { 3521 Operands.erase(Operands.begin() + 5); 3522 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc())); 3523 delete Op; 3524 } 3525 } 3526 3527 return false; 3528} 3529 3530// Validate context-sensitive operand constraints. 3531 3532// return 'true' if register list contains non-low GPR registers, 3533// 'false' otherwise. If Reg is in the register list or is HiReg, set 3534// 'containsReg' to true. 3535static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg, 3536 unsigned HiReg, bool &containsReg) { 3537 containsReg = false; 3538 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) { 3539 unsigned OpReg = Inst.getOperand(i).getReg(); 3540 if (OpReg == Reg) 3541 containsReg = true; 3542 // Anything other than a low register isn't legal here. 3543 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg)) 3544 return true; 3545 } 3546 return false; 3547} 3548 3549// Check if the specified regisgter is in the register list of the inst, 3550// starting at the indicated operand number. 3551static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) { 3552 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) { 3553 unsigned OpReg = Inst.getOperand(i).getReg(); 3554 if (OpReg == Reg) 3555 return true; 3556 } 3557 return false; 3558} 3559 3560// FIXME: We would really prefer to have MCInstrInfo (the wrapper around 3561// the ARMInsts array) instead. Getting that here requires awkward 3562// API changes, though. Better way? 3563namespace llvm { 3564extern MCInstrDesc ARMInsts[]; 3565} 3566static MCInstrDesc &getInstDesc(unsigned Opcode) { 3567 return ARMInsts[Opcode]; 3568} 3569 3570// FIXME: We would really like to be able to tablegen'erate this. 3571bool ARMAsmParser:: 3572validateInstruction(MCInst &Inst, 3573 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3574 MCInstrDesc &MCID = getInstDesc(Inst.getOpcode()); 3575 SMLoc Loc = Operands[0]->getStartLoc(); 3576 // Check the IT block state first. 3577 // NOTE: In Thumb mode, the BKPT instruction has the interesting property of 3578 // being allowed in IT blocks, but not being predicable. It just always 3579 // executes. 3580 if (inITBlock() && Inst.getOpcode() != ARM::tBKPT) { 3581 unsigned bit = 1; 3582 if (ITState.FirstCond) 3583 ITState.FirstCond = false; 3584 else 3585 bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1; 3586 // The instruction must be predicable. 3587 if (!MCID.isPredicable()) 3588 return Error(Loc, "instructions in IT block must be predicable"); 3589 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm(); 3590 unsigned ITCond = bit ? ITState.Cond : 3591 ARMCC::getOppositeCondition(ITState.Cond); 3592 if (Cond != ITCond) { 3593 // Find the condition code Operand to get its SMLoc information. 3594 SMLoc CondLoc; 3595 for (unsigned i = 1; i < Operands.size(); ++i) 3596 if (static_cast<ARMOperand*>(Operands[i])->isCondCode()) 3597 CondLoc = Operands[i]->getStartLoc(); 3598 return Error(CondLoc, "incorrect condition in IT block; got '" + 3599 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) + 3600 "', but expected '" + 3601 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'"); 3602 } 3603 // Check for non-'al' condition codes outside of the IT block. 3604 } else if (isThumbTwo() && MCID.isPredicable() && 3605 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() != 3606 ARMCC::AL && Inst.getOpcode() != ARM::tB && 3607 Inst.getOpcode() != ARM::t2B) 3608 return Error(Loc, "predicated instructions must be in IT block"); 3609 3610 switch (Inst.getOpcode()) { 3611 case ARM::LDRD: 3612 case ARM::LDRD_PRE: 3613 case ARM::LDRD_POST: 3614 case ARM::LDREXD: { 3615 // Rt2 must be Rt + 1. 3616 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg()); 3617 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg()); 3618 if (Rt2 != Rt + 1) 3619 return Error(Operands[3]->getStartLoc(), 3620 "destination operands must be sequential"); 3621 return false; 3622 } 3623 case ARM::STRD: { 3624 // Rt2 must be Rt + 1. 3625 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg()); 3626 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg()); 3627 if (Rt2 != Rt + 1) 3628 return Error(Operands[3]->getStartLoc(), 3629 "source operands must be sequential"); 3630 return false; 3631 } 3632 case ARM::STRD_PRE: 3633 case ARM::STRD_POST: 3634 case ARM::STREXD: { 3635 // Rt2 must be Rt + 1. 3636 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg()); 3637 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(2).getReg()); 3638 if (Rt2 != Rt + 1) 3639 return Error(Operands[3]->getStartLoc(), 3640 "source operands must be sequential"); 3641 return false; 3642 } 3643 case ARM::SBFX: 3644 case ARM::UBFX: { 3645 // width must be in range [1, 32-lsb] 3646 unsigned lsb = Inst.getOperand(2).getImm(); 3647 unsigned widthm1 = Inst.getOperand(3).getImm(); 3648 if (widthm1 >= 32 - lsb) 3649 return Error(Operands[5]->getStartLoc(), 3650 "bitfield width must be in range [1,32-lsb]"); 3651 return false; 3652 } 3653 case ARM::tLDMIA: { 3654 // If we're parsing Thumb2, the .w variant is available and handles 3655 // most cases that are normally illegal for a Thumb1 LDM 3656 // instruction. We'll make the transformation in processInstruction() 3657 // if necessary. 3658 // 3659 // Thumb LDM instructions are writeback iff the base register is not 3660 // in the register list. 3661 unsigned Rn = Inst.getOperand(0).getReg(); 3662 bool hasWritebackToken = 3663 (static_cast<ARMOperand*>(Operands[3])->isToken() && 3664 static_cast<ARMOperand*>(Operands[3])->getToken() == "!"); 3665 bool listContainsBase; 3666 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo()) 3667 return Error(Operands[3 + hasWritebackToken]->getStartLoc(), 3668 "registers must be in range r0-r7"); 3669 // If we should have writeback, then there should be a '!' token. 3670 if (!listContainsBase && !hasWritebackToken && !isThumbTwo()) 3671 return Error(Operands[2]->getStartLoc(), 3672 "writeback operator '!' expected"); 3673 // If we should not have writeback, there must not be a '!'. This is 3674 // true even for the 32-bit wide encodings. 3675 if (listContainsBase && hasWritebackToken) 3676 return Error(Operands[3]->getStartLoc(), 3677 "writeback operator '!' not allowed when base register " 3678 "in register list"); 3679 3680 break; 3681 } 3682 case ARM::t2LDMIA_UPD: { 3683 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg())) 3684 return Error(Operands[4]->getStartLoc(), 3685 "writeback operator '!' not allowed when base register " 3686 "in register list"); 3687 break; 3688 } 3689 case ARM::tPOP: { 3690 bool listContainsBase; 3691 if (checkLowRegisterList(Inst, 3, 0, ARM::PC, listContainsBase)) 3692 return Error(Operands[2]->getStartLoc(), 3693 "registers must be in range r0-r7 or pc"); 3694 break; 3695 } 3696 case ARM::tPUSH: { 3697 bool listContainsBase; 3698 if (checkLowRegisterList(Inst, 3, 0, ARM::LR, listContainsBase)) 3699 return Error(Operands[2]->getStartLoc(), 3700 "registers must be in range r0-r7 or lr"); 3701 break; 3702 } 3703 case ARM::tSTMIA_UPD: { 3704 bool listContainsBase; 3705 if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase)) 3706 return Error(Operands[4]->getStartLoc(), 3707 "registers must be in range r0-r7"); 3708 break; 3709 } 3710 } 3711 3712 return false; 3713} 3714 3715void ARMAsmParser:: 3716processInstruction(MCInst &Inst, 3717 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3718 switch (Inst.getOpcode()) { 3719 case ARM::LDMIA_UPD: 3720 // If this is a load of a single register via a 'pop', then we should use 3721 // a post-indexed LDR instruction instead, per the ARM ARM. 3722 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" && 3723 Inst.getNumOperands() == 5) { 3724 MCInst TmpInst; 3725 TmpInst.setOpcode(ARM::LDR_POST_IMM); 3726 TmpInst.addOperand(Inst.getOperand(4)); // Rt 3727 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 3728 TmpInst.addOperand(Inst.getOperand(1)); // Rn 3729 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset 3730 TmpInst.addOperand(MCOperand::CreateImm(4)); 3731 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 3732 TmpInst.addOperand(Inst.getOperand(3)); 3733 Inst = TmpInst; 3734 } 3735 break; 3736 case ARM::STMDB_UPD: 3737 // If this is a store of a single register via a 'push', then we should use 3738 // a pre-indexed STR instruction instead, per the ARM ARM. 3739 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" && 3740 Inst.getNumOperands() == 5) { 3741 MCInst TmpInst; 3742 TmpInst.setOpcode(ARM::STR_PRE_IMM); 3743 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 3744 TmpInst.addOperand(Inst.getOperand(4)); // Rt 3745 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12 3746 TmpInst.addOperand(MCOperand::CreateImm(-4)); 3747 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 3748 TmpInst.addOperand(Inst.getOperand(3)); 3749 Inst = TmpInst; 3750 } 3751 break; 3752 case ARM::tADDi8: 3753 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was 3754 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred 3755 // to encoding T2 if <Rd> is specified and encoding T2 is preferred 3756 // to encoding T1 if <Rd> is omitted." 3757 if (Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) 3758 Inst.setOpcode(ARM::tADDi3); 3759 break; 3760 case ARM::tB: 3761 // A Thumb conditional branch outside of an IT block is a tBcc. 3762 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) 3763 Inst.setOpcode(ARM::tBcc); 3764 break; 3765 case ARM::t2B: 3766 // A Thumb2 conditional branch outside of an IT block is a t2Bcc. 3767 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) 3768 Inst.setOpcode(ARM::t2Bcc); 3769 break; 3770 case ARM::t2Bcc: 3771 // If the conditional is AL or we're in an IT block, we really want t2B. 3772 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) 3773 Inst.setOpcode(ARM::t2B); 3774 break; 3775 case ARM::tBcc: 3776 // If the conditional is AL, we really want tB. 3777 if (Inst.getOperand(1).getImm() == ARMCC::AL) 3778 Inst.setOpcode(ARM::tB); 3779 break; 3780 case ARM::tLDMIA: { 3781 // If the register list contains any high registers, or if the writeback 3782 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding 3783 // instead if we're in Thumb2. Otherwise, this should have generated 3784 // an error in validateInstruction(). 3785 unsigned Rn = Inst.getOperand(0).getReg(); 3786 bool hasWritebackToken = 3787 (static_cast<ARMOperand*>(Operands[3])->isToken() && 3788 static_cast<ARMOperand*>(Operands[3])->getToken() == "!"); 3789 bool listContainsBase; 3790 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) || 3791 (!listContainsBase && !hasWritebackToken) || 3792 (listContainsBase && hasWritebackToken)) { 3793 // 16-bit encoding isn't sufficient. Switch to the 32-bit version. 3794 assert (isThumbTwo()); 3795 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA); 3796 // If we're switching to the updating version, we need to insert 3797 // the writeback tied operand. 3798 if (hasWritebackToken) 3799 Inst.insert(Inst.begin(), 3800 MCOperand::CreateReg(Inst.getOperand(0).getReg())); 3801 } 3802 break; 3803 } 3804 case ARM::t2MOVi: { 3805 // If we can use the 16-bit encoding and the user didn't explicitly 3806 // request the 32-bit variant, transform it here. 3807 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 3808 Inst.getOperand(1).getImm() <= 255 && 3809 Inst.getOperand(2).getImm() == ARMCC::AL && 3810 Inst.getOperand(4).getReg() == ARM::CPSR && 3811 (!static_cast<ARMOperand*>(Operands[2])->isToken() || 3812 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) { 3813 // The operands aren't in the same order for tMOVi8... 3814 MCInst TmpInst; 3815 TmpInst.setOpcode(ARM::tMOVi8); 3816 TmpInst.addOperand(Inst.getOperand(0)); 3817 TmpInst.addOperand(Inst.getOperand(4)); 3818 TmpInst.addOperand(Inst.getOperand(1)); 3819 TmpInst.addOperand(Inst.getOperand(2)); 3820 TmpInst.addOperand(Inst.getOperand(3)); 3821 Inst = TmpInst; 3822 } 3823 break; 3824 } 3825 case ARM::t2MOVr: { 3826 // If we can use the 16-bit encoding and the user didn't explicitly 3827 // request the 32-bit variant, transform it here. 3828 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 3829 isARMLowRegister(Inst.getOperand(1).getReg()) && 3830 Inst.getOperand(2).getImm() == ARMCC::AL && 3831 Inst.getOperand(4).getReg() == ARM::CPSR && 3832 (!static_cast<ARMOperand*>(Operands[2])->isToken() || 3833 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) { 3834 // The operands aren't the same for tMOV[S]r... (no cc_out) 3835 MCInst TmpInst; 3836 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr); 3837 TmpInst.addOperand(Inst.getOperand(0)); 3838 TmpInst.addOperand(Inst.getOperand(1)); 3839 TmpInst.addOperand(Inst.getOperand(2)); 3840 TmpInst.addOperand(Inst.getOperand(3)); 3841 Inst = TmpInst; 3842 } 3843 break; 3844 } 3845 case ARM::t2IT: { 3846 // The mask bits for all but the first condition are represented as 3847 // the low bit of the condition code value implies 't'. We currently 3848 // always have 1 implies 't', so XOR toggle the bits if the low bit 3849 // of the condition code is zero. The encoding also expects the low 3850 // bit of the condition to be encoded as bit 4 of the mask operand, 3851 // so mask that in if needed 3852 MCOperand &MO = Inst.getOperand(1); 3853 unsigned Mask = MO.getImm(); 3854 unsigned OrigMask = Mask; 3855 unsigned TZ = CountTrailingZeros_32(Mask); 3856 if ((Inst.getOperand(0).getImm() & 1) == 0) { 3857 assert(Mask && TZ <= 3 && "illegal IT mask value!"); 3858 for (unsigned i = 3; i != TZ; --i) 3859 Mask ^= 1 << i; 3860 } else 3861 Mask |= 0x10; 3862 MO.setImm(Mask); 3863 3864 // Set up the IT block state according to the IT instruction we just 3865 // matched. 3866 assert(!inITBlock() && "nested IT blocks?!"); 3867 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm()); 3868 ITState.Mask = OrigMask; // Use the original mask, not the updated one. 3869 ITState.CurPosition = 0; 3870 ITState.FirstCond = true; 3871 break; 3872 } 3873 } 3874} 3875 3876unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) { 3877 // 16-bit thumb arithmetic instructions either require or preclude the 'S' 3878 // suffix depending on whether they're in an IT block or not. 3879 unsigned Opc = Inst.getOpcode(); 3880 MCInstrDesc &MCID = getInstDesc(Opc); 3881 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) { 3882 assert(MCID.hasOptionalDef() && 3883 "optionally flag setting instruction missing optional def operand"); 3884 assert(MCID.NumOperands == Inst.getNumOperands() && 3885 "operand count mismatch!"); 3886 // Find the optional-def operand (cc_out). 3887 unsigned OpNo; 3888 for (OpNo = 0; 3889 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands; 3890 ++OpNo) 3891 ; 3892 // If we're parsing Thumb1, reject it completely. 3893 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR) 3894 return Match_MnemonicFail; 3895 // If we're parsing Thumb2, which form is legal depends on whether we're 3896 // in an IT block. 3897 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR && 3898 !inITBlock()) 3899 return Match_RequiresITBlock; 3900 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR && 3901 inITBlock()) 3902 return Match_RequiresNotITBlock; 3903 } 3904 // Some high-register supporting Thumb1 encodings only allow both registers 3905 // to be from r0-r7 when in Thumb2. 3906 else if (Opc == ARM::tADDhirr && isThumbOne() && 3907 isARMLowRegister(Inst.getOperand(1).getReg()) && 3908 isARMLowRegister(Inst.getOperand(2).getReg())) 3909 return Match_RequiresThumb2; 3910 // Others only require ARMv6 or later. 3911 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() && 3912 isARMLowRegister(Inst.getOperand(0).getReg()) && 3913 isARMLowRegister(Inst.getOperand(1).getReg())) 3914 return Match_RequiresV6; 3915 return Match_Success; 3916} 3917 3918bool ARMAsmParser:: 3919MatchAndEmitInstruction(SMLoc IDLoc, 3920 SmallVectorImpl<MCParsedAsmOperand*> &Operands, 3921 MCStreamer &Out) { 3922 MCInst Inst; 3923 unsigned ErrorInfo; 3924 unsigned MatchResult; 3925 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo); 3926 switch (MatchResult) { 3927 default: break; 3928 case Match_Success: 3929 // Context sensitive operand constraints aren't handled by the matcher, 3930 // so check them here. 3931 if (validateInstruction(Inst, Operands)) { 3932 // Still progress the IT block, otherwise one wrong condition causes 3933 // nasty cascading errors. 3934 forwardITPosition(); 3935 return true; 3936 } 3937 3938 // Some instructions need post-processing to, for example, tweak which 3939 // encoding is selected. 3940 processInstruction(Inst, Operands); 3941 3942 // Only move forward at the very end so that everything in validate 3943 // and process gets a consistent answer about whether we're in an IT 3944 // block. 3945 forwardITPosition(); 3946 3947 Out.EmitInstruction(Inst); 3948 return false; 3949 case Match_MissingFeature: 3950 Error(IDLoc, "instruction requires a CPU feature not currently enabled"); 3951 return true; 3952 case Match_InvalidOperand: { 3953 SMLoc ErrorLoc = IDLoc; 3954 if (ErrorInfo != ~0U) { 3955 if (ErrorInfo >= Operands.size()) 3956 return Error(IDLoc, "too few operands for instruction"); 3957 3958 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc(); 3959 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 3960 } 3961 3962 return Error(ErrorLoc, "invalid operand for instruction"); 3963 } 3964 case Match_MnemonicFail: 3965 return Error(IDLoc, "invalid instruction"); 3966 case Match_ConversionFail: 3967 // The converter function will have already emited a diagnostic. 3968 return true; 3969 case Match_RequiresNotITBlock: 3970 return Error(IDLoc, "flag setting instruction only valid outside IT block"); 3971 case Match_RequiresITBlock: 3972 return Error(IDLoc, "instruction only valid inside IT block"); 3973 case Match_RequiresV6: 3974 return Error(IDLoc, "instruction variant requires ARMv6 or later"); 3975 case Match_RequiresThumb2: 3976 return Error(IDLoc, "instruction variant requires Thumb2"); 3977 } 3978 3979 llvm_unreachable("Implement any new match types added!"); 3980 return true; 3981} 3982 3983/// parseDirective parses the arm specific directives 3984bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) { 3985 StringRef IDVal = DirectiveID.getIdentifier(); 3986 if (IDVal == ".word") 3987 return parseDirectiveWord(4, DirectiveID.getLoc()); 3988 else if (IDVal == ".thumb") 3989 return parseDirectiveThumb(DirectiveID.getLoc()); 3990 else if (IDVal == ".thumb_func") 3991 return parseDirectiveThumbFunc(DirectiveID.getLoc()); 3992 else if (IDVal == ".code") 3993 return parseDirectiveCode(DirectiveID.getLoc()); 3994 else if (IDVal == ".syntax") 3995 return parseDirectiveSyntax(DirectiveID.getLoc()); 3996 return true; 3997} 3998 3999/// parseDirectiveWord 4000/// ::= .word [ expression (, expression)* ] 4001bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) { 4002 if (getLexer().isNot(AsmToken::EndOfStatement)) { 4003 for (;;) { 4004 const MCExpr *Value; 4005 if (getParser().ParseExpression(Value)) 4006 return true; 4007 4008 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/); 4009 4010 if (getLexer().is(AsmToken::EndOfStatement)) 4011 break; 4012 4013 // FIXME: Improve diagnostic. 4014 if (getLexer().isNot(AsmToken::Comma)) 4015 return Error(L, "unexpected token in directive"); 4016 Parser.Lex(); 4017 } 4018 } 4019 4020 Parser.Lex(); 4021 return false; 4022} 4023 4024/// parseDirectiveThumb 4025/// ::= .thumb 4026bool ARMAsmParser::parseDirectiveThumb(SMLoc L) { 4027 if (getLexer().isNot(AsmToken::EndOfStatement)) 4028 return Error(L, "unexpected token in directive"); 4029 Parser.Lex(); 4030 4031 // TODO: set thumb mode 4032 // TODO: tell the MC streamer the mode 4033 // getParser().getStreamer().Emit???(); 4034 return false; 4035} 4036 4037/// parseDirectiveThumbFunc 4038/// ::= .thumbfunc symbol_name 4039bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) { 4040 const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo(); 4041 bool isMachO = MAI.hasSubsectionsViaSymbols(); 4042 StringRef Name; 4043 4044 // Darwin asm has function name after .thumb_func direction 4045 // ELF doesn't 4046 if (isMachO) { 4047 const AsmToken &Tok = Parser.getTok(); 4048 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String)) 4049 return Error(L, "unexpected token in .thumb_func directive"); 4050 Name = Tok.getString(); 4051 Parser.Lex(); // Consume the identifier token. 4052 } 4053 4054 if (getLexer().isNot(AsmToken::EndOfStatement)) 4055 return Error(L, "unexpected token in directive"); 4056 Parser.Lex(); 4057 4058 // FIXME: assuming function name will be the line following .thumb_func 4059 if (!isMachO) { 4060 Name = Parser.getTok().getString(); 4061 } 4062 4063 // Mark symbol as a thumb symbol. 4064 MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name); 4065 getParser().getStreamer().EmitThumbFunc(Func); 4066 return false; 4067} 4068 4069/// parseDirectiveSyntax 4070/// ::= .syntax unified | divided 4071bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) { 4072 const AsmToken &Tok = Parser.getTok(); 4073 if (Tok.isNot(AsmToken::Identifier)) 4074 return Error(L, "unexpected token in .syntax directive"); 4075 StringRef Mode = Tok.getString(); 4076 if (Mode == "unified" || Mode == "UNIFIED") 4077 Parser.Lex(); 4078 else if (Mode == "divided" || Mode == "DIVIDED") 4079 return Error(L, "'.syntax divided' arm asssembly not supported"); 4080 else 4081 return Error(L, "unrecognized syntax mode in .syntax directive"); 4082 4083 if (getLexer().isNot(AsmToken::EndOfStatement)) 4084 return Error(Parser.getTok().getLoc(), "unexpected token in directive"); 4085 Parser.Lex(); 4086 4087 // TODO tell the MC streamer the mode 4088 // getParser().getStreamer().Emit???(); 4089 return false; 4090} 4091 4092/// parseDirectiveCode 4093/// ::= .code 16 | 32 4094bool ARMAsmParser::parseDirectiveCode(SMLoc L) { 4095 const AsmToken &Tok = Parser.getTok(); 4096 if (Tok.isNot(AsmToken::Integer)) 4097 return Error(L, "unexpected token in .code directive"); 4098 int64_t Val = Parser.getTok().getIntVal(); 4099 if (Val == 16) 4100 Parser.Lex(); 4101 else if (Val == 32) 4102 Parser.Lex(); 4103 else 4104 return Error(L, "invalid operand to .code directive"); 4105 4106 if (getLexer().isNot(AsmToken::EndOfStatement)) 4107 return Error(Parser.getTok().getLoc(), "unexpected token in directive"); 4108 Parser.Lex(); 4109 4110 if (Val == 16) { 4111 if (!isThumb()) 4112 SwitchMode(); 4113 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16); 4114 } else { 4115 if (isThumb()) 4116 SwitchMode(); 4117 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32); 4118 } 4119 4120 return false; 4121} 4122 4123extern "C" void LLVMInitializeARMAsmLexer(); 4124 4125/// Force static initialization. 4126extern "C" void LLVMInitializeARMAsmParser() { 4127 RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget); 4128 RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget); 4129 LLVMInitializeARMAsmLexer(); 4130} 4131 4132#define GET_REGISTER_MATCHER 4133#define GET_MATCHER_IMPLEMENTATION 4134#include "ARMGenAsmMatcher.inc" 4135