ARMAsmParser.cpp revision d300b94e51cf8c91928a66478c387c1c3d76faab 
1//===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "MCTargetDesc/ARMBaseInfo.h"
11#include "MCTargetDesc/ARMAddressingModes.h"
12#include "MCTargetDesc/ARMMCExpr.h"
13#include "llvm/MC/MCParser/MCAsmLexer.h"
14#include "llvm/MC/MCParser/MCAsmParser.h"
15#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16#include "llvm/MC/MCAsmInfo.h"
17#include "llvm/MC/MCContext.h"
18#include "llvm/MC/MCStreamer.h"
19#include "llvm/MC/MCExpr.h"
20#include "llvm/MC/MCInst.h"
21#include "llvm/MC/MCInstrDesc.h"
22#include "llvm/MC/MCRegisterInfo.h"
23#include "llvm/MC/MCSubtargetInfo.h"
24#include "llvm/MC/MCTargetAsmParser.h"
25#include "llvm/Support/MathExtras.h"
26#include "llvm/Support/SourceMgr.h"
27#include "llvm/Support/TargetRegistry.h"
28#include "llvm/Support/raw_ostream.h"
29#include "llvm/ADT/BitVector.h"
30#include "llvm/ADT/OwningPtr.h"
31#include "llvm/ADT/STLExtras.h"
32#include "llvm/ADT/SmallVector.h"
33#include "llvm/ADT/StringExtras.h"
34#include "llvm/ADT/StringSwitch.h"
35#include "llvm/ADT/Twine.h"
36
37using namespace llvm;
38
39namespace {
40
41class ARMOperand;
42
43class ARMAsmParser : public MCTargetAsmParser {
44  MCSubtargetInfo &STI;
45  MCAsmParser &Parser;
46
47  struct {
48    ARMCC::CondCodes Cond;    // Condition for IT block.
49    unsigned Mask:4;          // Condition mask for instructions.
50                              // Starting at first 1 (from lsb).
51                              //   '1'  condition as indicated in IT.
52                              //   '0'  inverse of condition (else).
53                              // Count of instructions in IT block is
54                              // 4 - trailingzeroes(mask)
55
56    bool FirstCond;           // Explicit flag for when we're parsing the
57                              // First instruction in the IT block. It's
58                              // implied in the mask, so needs special
59                              // handling.
60
61    unsigned CurPosition;     // Current position in parsing of IT
62                              // block. In range [0,3]. Initialized
63                              // according to count of instructions in block.
64                              // ~0U if no active IT block.
65  } ITState;
66  bool inITBlock() { return ITState.CurPosition != ~0U;}
67  void forwardITPosition() {
68    if (!inITBlock()) return;
69    // Move to the next instruction in the IT block, if there is one. If not,
70    // mark the block as done.
71    unsigned TZ = CountTrailingZeros_32(ITState.Mask);
72    if (++ITState.CurPosition == 5 - TZ)
73      ITState.CurPosition = ~0U; // Done with the IT block after this.
74  }
75
76
77  MCAsmParser &getParser() const { return Parser; }
78  MCAsmLexer &getLexer() const { return Parser.getLexer(); }
79
80  void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
81  bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
82
83  int tryParseRegister();
84  bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
85  int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
86  bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
87  bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
88  bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
89  bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
90  const MCExpr *applyPrefixToExpr(const MCExpr *E,
91                                  MCSymbolRefExpr::VariantKind Variant);
92
93
94  bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
95                              unsigned &ShiftAmount);
96  bool parseDirectiveWord(unsigned Size, SMLoc L);
97  bool parseDirectiveThumb(SMLoc L);
98  bool parseDirectiveThumbFunc(SMLoc L);
99  bool parseDirectiveCode(SMLoc L);
100  bool parseDirectiveSyntax(SMLoc L);
101
102  StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
103                          bool &CarrySetting, unsigned &ProcessorIMod,
104                          StringRef &ITMask);
105  void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
106                             bool &CanAcceptPredicationCode);
107
108  bool isThumb() const {
109    // FIXME: Can tablegen auto-generate this?
110    return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
111  }
112  bool isThumbOne() const {
113    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
114  }
115  bool isThumbTwo() const {
116    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
117  }
118  bool hasV6Ops() const {
119    return STI.getFeatureBits() & ARM::HasV6Ops;
120  }
121  void SwitchMode() {
122    unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
123    setAvailableFeatures(FB);
124  }
125
126  /// @name Auto-generated Match Functions
127  /// {
128
129#define GET_ASSEMBLER_HEADER
130#include "ARMGenAsmMatcher.inc"
131
132  /// }
133
134  OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
135  OperandMatchResultTy parseCoprocNumOperand(
136    SmallVectorImpl<MCParsedAsmOperand*>&);
137  OperandMatchResultTy parseCoprocRegOperand(
138    SmallVectorImpl<MCParsedAsmOperand*>&);
139  OperandMatchResultTy parseMemBarrierOptOperand(
140    SmallVectorImpl<MCParsedAsmOperand*>&);
141  OperandMatchResultTy parseProcIFlagsOperand(
142    SmallVectorImpl<MCParsedAsmOperand*>&);
143  OperandMatchResultTy parseMSRMaskOperand(
144    SmallVectorImpl<MCParsedAsmOperand*>&);
145  OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
146                                   StringRef Op, int Low, int High);
147  OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
148    return parsePKHImm(O, "lsl", 0, 31);
149  }
150  OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
151    return parsePKHImm(O, "asr", 1, 32);
152  }
153  OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
154  OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
155  OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
156  OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
157  OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
158  OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
159
160  // Asm Match Converter Methods
161  bool cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
162                    const SmallVectorImpl<MCParsedAsmOperand*> &);
163  bool cvtT2StrdPre(MCInst &Inst, unsigned Opcode,
164                    const SmallVectorImpl<MCParsedAsmOperand*> &);
165  bool cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
166                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
167  bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
168                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
169  bool cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
170                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
171  bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
172                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
173  bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
174                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
175  bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
176                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
177  bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
178                             const SmallVectorImpl<MCParsedAsmOperand*> &);
179  bool cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
180                             const SmallVectorImpl<MCParsedAsmOperand*> &);
181  bool cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
182                             const SmallVectorImpl<MCParsedAsmOperand*> &);
183  bool cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
184                             const SmallVectorImpl<MCParsedAsmOperand*> &);
185  bool cvtLdrdPre(MCInst &Inst, unsigned Opcode,
186                  const SmallVectorImpl<MCParsedAsmOperand*> &);
187  bool cvtStrdPre(MCInst &Inst, unsigned Opcode,
188                  const SmallVectorImpl<MCParsedAsmOperand*> &);
189  bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
190                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
191  bool cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
192                        const SmallVectorImpl<MCParsedAsmOperand*> &);
193
194  bool validateInstruction(MCInst &Inst,
195                           const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
196  void processInstruction(MCInst &Inst,
197                          const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
198  bool shouldOmitCCOutOperand(StringRef Mnemonic,
199                              SmallVectorImpl<MCParsedAsmOperand*> &Operands);
200
201public:
202  enum ARMMatchResultTy {
203    Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
204    Match_RequiresNotITBlock,
205    Match_RequiresV6,
206    Match_RequiresThumb2
207  };
208
209  ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
210    : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
211    MCAsmParserExtension::Initialize(_Parser);
212
213    // Initialize the set of available features.
214    setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
215
216    // Not in an ITBlock to start with.
217    ITState.CurPosition = ~0U;
218  }
219
220  // Implementation of the MCTargetAsmParser interface:
221  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
222  bool ParseInstruction(StringRef Name, SMLoc NameLoc,
223                        SmallVectorImpl<MCParsedAsmOperand*> &Operands);
224  bool ParseDirective(AsmToken DirectiveID);
225
226  unsigned checkTargetMatchPredicate(MCInst &Inst);
227
228  bool MatchAndEmitInstruction(SMLoc IDLoc,
229                               SmallVectorImpl<MCParsedAsmOperand*> &Operands,
230                               MCStreamer &Out);
231};
232} // end anonymous namespace
233
234namespace {
235
236/// ARMOperand - Instances of this class represent a parsed ARM machine
237/// instruction.
238class ARMOperand : public MCParsedAsmOperand {
239  enum KindTy {
240    CondCode,
241    CCOut,
242    ITCondMask,
243    CoprocNum,
244    CoprocReg,
245    Immediate,
246    MemBarrierOpt,
247    Memory,
248    PostIndexRegister,
249    MSRMask,
250    ProcIFlags,
251    Register,
252    RegisterList,
253    DPRRegisterList,
254    SPRRegisterList,
255    ShiftedRegister,
256    ShiftedImmediate,
257    ShifterImmediate,
258    RotateImmediate,
259    BitfieldDescriptor,
260    Token
261  } Kind;
262
263  SMLoc StartLoc, EndLoc;
264  SmallVector<unsigned, 8> Registers;
265
266  union {
267    struct {
268      ARMCC::CondCodes Val;
269    } CC;
270
271    struct {
272      unsigned Val;
273    } Cop;
274
275    struct {
276      unsigned Mask:4;
277    } ITMask;
278
279    struct {
280      ARM_MB::MemBOpt Val;
281    } MBOpt;
282
283    struct {
284      ARM_PROC::IFlags Val;
285    } IFlags;
286
287    struct {
288      unsigned Val;
289    } MMask;
290
291    struct {
292      const char *Data;
293      unsigned Length;
294    } Tok;
295
296    struct {
297      unsigned RegNum;
298    } Reg;
299
300    struct {
301      const MCExpr *Val;
302    } Imm;
303
304    /// Combined record for all forms of ARM address expressions.
305    struct {
306      unsigned BaseRegNum;
307      // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
308      // was specified.
309      const MCConstantExpr *OffsetImm;  // Offset immediate value
310      unsigned OffsetRegNum;    // Offset register num, when OffsetImm == NULL
311      ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
312      unsigned ShiftImm;      // shift for OffsetReg.
313      unsigned isNegative : 1;  // Negated OffsetReg? (~'U' bit)
314    } Mem;
315
316    struct {
317      unsigned RegNum;
318      bool isAdd;
319      ARM_AM::ShiftOpc ShiftTy;
320      unsigned ShiftImm;
321    } PostIdxReg;
322
323    struct {
324      bool isASR;
325      unsigned Imm;
326    } ShifterImm;
327    struct {
328      ARM_AM::ShiftOpc ShiftTy;
329      unsigned SrcReg;
330      unsigned ShiftReg;
331      unsigned ShiftImm;
332    } RegShiftedReg;
333    struct {
334      ARM_AM::ShiftOpc ShiftTy;
335      unsigned SrcReg;
336      unsigned ShiftImm;
337    } RegShiftedImm;
338    struct {
339      unsigned Imm;
340    } RotImm;
341    struct {
342      unsigned LSB;
343      unsigned Width;
344    } Bitfield;
345  };
346
347  ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
348public:
349  ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
350    Kind = o.Kind;
351    StartLoc = o.StartLoc;
352    EndLoc = o.EndLoc;
353    switch (Kind) {
354    case CondCode:
355      CC = o.CC;
356      break;
357    case ITCondMask:
358      ITMask = o.ITMask;
359      break;
360    case Token:
361      Tok = o.Tok;
362      break;
363    case CCOut:
364    case Register:
365      Reg = o.Reg;
366      break;
367    case RegisterList:
368    case DPRRegisterList:
369    case SPRRegisterList:
370      Registers = o.Registers;
371      break;
372    case CoprocNum:
373    case CoprocReg:
374      Cop = o.Cop;
375      break;
376    case Immediate:
377      Imm = o.Imm;
378      break;
379    case MemBarrierOpt:
380      MBOpt = o.MBOpt;
381      break;
382    case Memory:
383      Mem = o.Mem;
384      break;
385    case PostIndexRegister:
386      PostIdxReg = o.PostIdxReg;
387      break;
388    case MSRMask:
389      MMask = o.MMask;
390      break;
391    case ProcIFlags:
392      IFlags = o.IFlags;
393      break;
394    case ShifterImmediate:
395      ShifterImm = o.ShifterImm;
396      break;
397    case ShiftedRegister:
398      RegShiftedReg = o.RegShiftedReg;
399      break;
400    case ShiftedImmediate:
401      RegShiftedImm = o.RegShiftedImm;
402      break;
403    case RotateImmediate:
404      RotImm = o.RotImm;
405      break;
406    case BitfieldDescriptor:
407      Bitfield = o.Bitfield;
408      break;
409    }
410  }
411
412  /// getStartLoc - Get the location of the first token of this operand.
413  SMLoc getStartLoc() const { return StartLoc; }
414  /// getEndLoc - Get the location of the last token of this operand.
415  SMLoc getEndLoc() const { return EndLoc; }
416
417  ARMCC::CondCodes getCondCode() const {
418    assert(Kind == CondCode && "Invalid access!");
419    return CC.Val;
420  }
421
422  unsigned getCoproc() const {
423    assert((Kind == CoprocNum || Kind == CoprocReg) && "Invalid access!");
424    return Cop.Val;
425  }
426
427  StringRef getToken() const {
428    assert(Kind == Token && "Invalid access!");
429    return StringRef(Tok.Data, Tok.Length);
430  }
431
432  unsigned getReg() const {
433    assert((Kind == Register || Kind == CCOut) && "Invalid access!");
434    return Reg.RegNum;
435  }
436
437  const SmallVectorImpl<unsigned> &getRegList() const {
438    assert((Kind == RegisterList || Kind == DPRRegisterList ||
439            Kind == SPRRegisterList) && "Invalid access!");
440    return Registers;
441  }
442
443  const MCExpr *getImm() const {
444    assert(Kind == Immediate && "Invalid access!");
445    return Imm.Val;
446  }
447
448  ARM_MB::MemBOpt getMemBarrierOpt() const {
449    assert(Kind == MemBarrierOpt && "Invalid access!");
450    return MBOpt.Val;
451  }
452
453  ARM_PROC::IFlags getProcIFlags() const {
454    assert(Kind == ProcIFlags && "Invalid access!");
455    return IFlags.Val;
456  }
457
458  unsigned getMSRMask() const {
459    assert(Kind == MSRMask && "Invalid access!");
460    return MMask.Val;
461  }
462
463  bool isCoprocNum() const { return Kind == CoprocNum; }
464  bool isCoprocReg() const { return Kind == CoprocReg; }
465  bool isCondCode() const { return Kind == CondCode; }
466  bool isCCOut() const { return Kind == CCOut; }
467  bool isITMask() const { return Kind == ITCondMask; }
468  bool isITCondCode() const { return Kind == CondCode; }
469  bool isImm() const { return Kind == Immediate; }
470  bool isImm8s4() const {
471    if (Kind != Immediate)
472      return false;
473    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
474    if (!CE) return false;
475    int64_t Value = CE->getValue();
476    return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
477  }
478  bool isImm0_1020s4() const {
479    if (Kind != Immediate)
480      return false;
481    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
482    if (!CE) return false;
483    int64_t Value = CE->getValue();
484    return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
485  }
486  bool isImm0_508s4() const {
487    if (Kind != Immediate)
488      return false;
489    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
490    if (!CE) return false;
491    int64_t Value = CE->getValue();
492    return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
493  }
494  bool isImm0_255() const {
495    if (Kind != Immediate)
496      return false;
497    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
498    if (!CE) return false;
499    int64_t Value = CE->getValue();
500    return Value >= 0 && Value < 256;
501  }
502  bool isImm0_7() const {
503    if (Kind != Immediate)
504      return false;
505    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
506    if (!CE) return false;
507    int64_t Value = CE->getValue();
508    return Value >= 0 && Value < 8;
509  }
510  bool isImm0_15() const {
511    if (Kind != Immediate)
512      return false;
513    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
514    if (!CE) return false;
515    int64_t Value = CE->getValue();
516    return Value >= 0 && Value < 16;
517  }
518  bool isImm0_31() const {
519    if (Kind != Immediate)
520      return false;
521    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
522    if (!CE) return false;
523    int64_t Value = CE->getValue();
524    return Value >= 0 && Value < 32;
525  }
526  bool isImm1_16() const {
527    if (Kind != Immediate)
528      return false;
529    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
530    if (!CE) return false;
531    int64_t Value = CE->getValue();
532    return Value > 0 && Value < 17;
533  }
534  bool isImm1_32() const {
535    if (Kind != Immediate)
536      return false;
537    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
538    if (!CE) return false;
539    int64_t Value = CE->getValue();
540    return Value > 0 && Value < 33;
541  }
542  bool isImm0_65535() const {
543    if (Kind != Immediate)
544      return false;
545    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
546    if (!CE) return false;
547    int64_t Value = CE->getValue();
548    return Value >= 0 && Value < 65536;
549  }
550  bool isImm0_65535Expr() const {
551    if (Kind != Immediate)
552      return false;
553    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
554    // If it's not a constant expression, it'll generate a fixup and be
555    // handled later.
556    if (!CE) return true;
557    int64_t Value = CE->getValue();
558    return Value >= 0 && Value < 65536;
559  }
560  bool isImm24bit() const {
561    if (Kind != Immediate)
562      return false;
563    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
564    if (!CE) return false;
565    int64_t Value = CE->getValue();
566    return Value >= 0 && Value <= 0xffffff;
567  }
568  bool isImmThumbSR() const {
569    if (Kind != Immediate)
570      return false;
571    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
572    if (!CE) return false;
573    int64_t Value = CE->getValue();
574    return Value > 0 && Value < 33;
575  }
576  bool isPKHLSLImm() const {
577    if (Kind != Immediate)
578      return false;
579    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
580    if (!CE) return false;
581    int64_t Value = CE->getValue();
582    return Value >= 0 && Value < 32;
583  }
584  bool isPKHASRImm() const {
585    if (Kind != Immediate)
586      return false;
587    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
588    if (!CE) return false;
589    int64_t Value = CE->getValue();
590    return Value > 0 && Value <= 32;
591  }
592  bool isARMSOImm() const {
593    if (Kind != Immediate)
594      return false;
595    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
596    if (!CE) return false;
597    int64_t Value = CE->getValue();
598    return ARM_AM::getSOImmVal(Value) != -1;
599  }
600  bool isT2SOImm() const {
601    if (Kind != Immediate)
602      return false;
603    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
604    if (!CE) return false;
605    int64_t Value = CE->getValue();
606    return ARM_AM::getT2SOImmVal(Value) != -1;
607  }
608  bool isSetEndImm() const {
609    if (Kind != Immediate)
610      return false;
611    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
612    if (!CE) return false;
613    int64_t Value = CE->getValue();
614    return Value == 1 || Value == 0;
615  }
616  bool isReg() const { return Kind == Register; }
617  bool isRegList() const { return Kind == RegisterList; }
618  bool isDPRRegList() const { return Kind == DPRRegisterList; }
619  bool isSPRRegList() const { return Kind == SPRRegisterList; }
620  bool isToken() const { return Kind == Token; }
621  bool isMemBarrierOpt() const { return Kind == MemBarrierOpt; }
622  bool isMemory() const { return Kind == Memory; }
623  bool isShifterImm() const { return Kind == ShifterImmediate; }
624  bool isRegShiftedReg() const { return Kind == ShiftedRegister; }
625  bool isRegShiftedImm() const { return Kind == ShiftedImmediate; }
626  bool isRotImm() const { return Kind == RotateImmediate; }
627  bool isBitfield() const { return Kind == BitfieldDescriptor; }
628  bool isPostIdxRegShifted() const { return Kind == PostIndexRegister; }
629  bool isPostIdxReg() const {
630    return Kind == PostIndexRegister && PostIdxReg.ShiftTy == ARM_AM::no_shift;
631  }
632  bool isMemNoOffset() const {
633    if (Kind != Memory)
634      return false;
635    // No offset of any kind.
636    return Mem.OffsetRegNum == 0 && Mem.OffsetImm == 0;
637  }
638  bool isAddrMode2() const {
639    if (Kind != Memory)
640      return false;
641    // Check for register offset.
642    if (Mem.OffsetRegNum) return true;
643    // Immediate offset in range [-4095, 4095].
644    if (!Mem.OffsetImm) return true;
645    int64_t Val = Mem.OffsetImm->getValue();
646    return Val > -4096 && Val < 4096;
647  }
648  bool isAM2OffsetImm() const {
649    if (Kind != Immediate)
650      return false;
651    // Immediate offset in range [-4095, 4095].
652    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
653    if (!CE) return false;
654    int64_t Val = CE->getValue();
655    return Val > -4096 && Val < 4096;
656  }
657  bool isAddrMode3() const {
658    if (Kind != Memory)
659      return false;
660    // No shifts are legal for AM3.
661    if (Mem.ShiftType != ARM_AM::no_shift) return false;
662    // Check for register offset.
663    if (Mem.OffsetRegNum) return true;
664    // Immediate offset in range [-255, 255].
665    if (!Mem.OffsetImm) return true;
666    int64_t Val = Mem.OffsetImm->getValue();
667    return Val > -256 && Val < 256;
668  }
669  bool isAM3Offset() const {
670    if (Kind != Immediate && Kind != PostIndexRegister)
671      return false;
672    if (Kind == PostIndexRegister)
673      return PostIdxReg.ShiftTy == ARM_AM::no_shift;
674    // Immediate offset in range [-255, 255].
675    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
676    if (!CE) return false;
677    int64_t Val = CE->getValue();
678    // Special case, #-0 is INT32_MIN.
679    return (Val > -256 && Val < 256) || Val == INT32_MIN;
680  }
681  bool isAddrMode5() const {
682    if (Kind != Memory)
683      return false;
684    // Check for register offset.
685    if (Mem.OffsetRegNum) return false;
686    // Immediate offset in range [-1020, 1020] and a multiple of 4.
687    if (!Mem.OffsetImm) return true;
688    int64_t Val = Mem.OffsetImm->getValue();
689    return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
690           Val == INT32_MIN;
691  }
692  bool isMemRegOffset() const {
693    if (Kind != Memory || !Mem.OffsetRegNum)
694      return false;
695    return true;
696  }
697  bool isT2MemRegOffset() const {
698    if (Kind != Memory || !Mem.OffsetRegNum || Mem.isNegative)
699      return false;
700    // Only lsl #{0, 1, 2, 3} allowed.
701    if (Mem.ShiftType == ARM_AM::no_shift)
702      return true;
703    if (Mem.ShiftType != ARM_AM::lsl || Mem.ShiftImm > 3)
704      return false;
705    return true;
706  }
707  bool isMemThumbRR() const {
708    // Thumb reg+reg addressing is simple. Just two registers, a base and
709    // an offset. No shifts, negations or any other complicating factors.
710    if (Kind != Memory || !Mem.OffsetRegNum || Mem.isNegative ||
711        Mem.ShiftType != ARM_AM::no_shift)
712      return false;
713    return isARMLowRegister(Mem.BaseRegNum) &&
714      (!Mem.OffsetRegNum || isARMLowRegister(Mem.OffsetRegNum));
715  }
716  bool isMemThumbRIs4() const {
717    if (Kind != Memory || Mem.OffsetRegNum != 0 ||
718        !isARMLowRegister(Mem.BaseRegNum))
719      return false;
720    // Immediate offset, multiple of 4 in range [0, 124].
721    if (!Mem.OffsetImm) return true;
722    int64_t Val = Mem.OffsetImm->getValue();
723    return Val >= 0 && Val <= 124 && (Val % 4) == 0;
724  }
725  bool isMemThumbRIs2() const {
726    if (Kind != Memory || Mem.OffsetRegNum != 0 ||
727        !isARMLowRegister(Mem.BaseRegNum))
728      return false;
729    // Immediate offset, multiple of 4 in range [0, 62].
730    if (!Mem.OffsetImm) return true;
731    int64_t Val = Mem.OffsetImm->getValue();
732    return Val >= 0 && Val <= 62 && (Val % 2) == 0;
733  }
734  bool isMemThumbRIs1() const {
735    if (Kind != Memory || Mem.OffsetRegNum != 0 ||
736        !isARMLowRegister(Mem.BaseRegNum))
737      return false;
738    // Immediate offset in range [0, 31].
739    if (!Mem.OffsetImm) return true;
740    int64_t Val = Mem.OffsetImm->getValue();
741    return Val >= 0 && Val <= 31;
742  }
743  bool isMemThumbSPI() const {
744    if (Kind != Memory || Mem.OffsetRegNum != 0 || Mem.BaseRegNum != ARM::SP)
745      return false;
746    // Immediate offset, multiple of 4 in range [0, 1020].
747    if (!Mem.OffsetImm) return true;
748    int64_t Val = Mem.OffsetImm->getValue();
749    return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
750  }
751  bool isMemImm8s4Offset() const {
752    if (Kind != Memory || Mem.OffsetRegNum != 0)
753      return false;
754    // Immediate offset a multiple of 4 in range [-1020, 1020].
755    if (!Mem.OffsetImm) return true;
756    int64_t Val = Mem.OffsetImm->getValue();
757    return Val >= -1020 && Val <= 1020 && (Val & 3) == 0;
758  }
759  bool isMemImm0_1020s4Offset() const {
760    if (Kind != Memory || Mem.OffsetRegNum != 0)
761      return false;
762    // Immediate offset a multiple of 4 in range [0, 1020].
763    if (!Mem.OffsetImm) return true;
764    int64_t Val = Mem.OffsetImm->getValue();
765    return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
766  }
767  bool isMemImm8Offset() const {
768    if (Kind != Memory || Mem.OffsetRegNum != 0)
769      return false;
770    // Immediate offset in range [-255, 255].
771    if (!Mem.OffsetImm) return true;
772    int64_t Val = Mem.OffsetImm->getValue();
773    return Val > -256 && Val < 256;
774  }
775  bool isMemPosImm8Offset() const {
776    if (Kind != Memory || Mem.OffsetRegNum != 0)
777      return false;
778    // Immediate offset in range [0, 255].
779    if (!Mem.OffsetImm) return true;
780    int64_t Val = Mem.OffsetImm->getValue();
781    return Val >= 0 && Val < 256;
782  }
783  bool isMemNegImm8Offset() const {
784    if (Kind != Memory || Mem.OffsetRegNum != 0)
785      return false;
786    // Immediate offset in range [-255, -1].
787    if (!Mem.OffsetImm) return true;
788    int64_t Val = Mem.OffsetImm->getValue();
789    return Val > -256 && Val < 0;
790  }
791  bool isMemUImm12Offset() const {
792    // If we have an immediate that's not a constant, treat it as a label
793    // reference needing a fixup. If it is a constant, it's something else
794    // and we reject it.
795    if (Kind == Immediate && !isa<MCConstantExpr>(getImm()))
796      return true;
797
798    if (Kind != Memory || Mem.OffsetRegNum != 0)
799      return false;
800    // Immediate offset in range [0, 4095].
801    if (!Mem.OffsetImm) return true;
802    int64_t Val = Mem.OffsetImm->getValue();
803    return (Val >= 0 && Val < 4096);
804  }
805  bool isMemImm12Offset() const {
806    // If we have an immediate that's not a constant, treat it as a label
807    // reference needing a fixup. If it is a constant, it's something else
808    // and we reject it.
809    if (Kind == Immediate && !isa<MCConstantExpr>(getImm()))
810      return true;
811
812    if (Kind != Memory || Mem.OffsetRegNum != 0)
813      return false;
814    // Immediate offset in range [-4095, 4095].
815    if (!Mem.OffsetImm) return true;
816    int64_t Val = Mem.OffsetImm->getValue();
817    return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
818  }
819  bool isPostIdxImm8() const {
820    if (Kind != Immediate)
821      return false;
822    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
823    if (!CE) return false;
824    int64_t Val = CE->getValue();
825    return (Val > -256 && Val < 256) || (Val == INT32_MIN);
826  }
827
828  bool isMSRMask() const { return Kind == MSRMask; }
829  bool isProcIFlags() const { return Kind == ProcIFlags; }
830
831  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
832    // Add as immediates when possible.  Null MCExpr = 0.
833    if (Expr == 0)
834      Inst.addOperand(MCOperand::CreateImm(0));
835    else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
836      Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
837    else
838      Inst.addOperand(MCOperand::CreateExpr(Expr));
839  }
840
841  void addCondCodeOperands(MCInst &Inst, unsigned N) const {
842    assert(N == 2 && "Invalid number of operands!");
843    Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
844    unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
845    Inst.addOperand(MCOperand::CreateReg(RegNum));
846  }
847
848  void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
849    assert(N == 1 && "Invalid number of operands!");
850    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
851  }
852
853  void addITMaskOperands(MCInst &Inst, unsigned N) const {
854    assert(N == 1 && "Invalid number of operands!");
855    Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
856  }
857
858  void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
859    assert(N == 1 && "Invalid number of operands!");
860    Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
861  }
862
863  void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
864    assert(N == 1 && "Invalid number of operands!");
865    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
866  }
867
868  void addCCOutOperands(MCInst &Inst, unsigned N) const {
869    assert(N == 1 && "Invalid number of operands!");
870    Inst.addOperand(MCOperand::CreateReg(getReg()));
871  }
872
873  void addRegOperands(MCInst &Inst, unsigned N) const {
874    assert(N == 1 && "Invalid number of operands!");
875    Inst.addOperand(MCOperand::CreateReg(getReg()));
876  }
877
878  void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
879    assert(N == 3 && "Invalid number of operands!");
880    assert(isRegShiftedReg() && "addRegShiftedRegOperands() on non RegShiftedReg!");
881    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
882    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
883    Inst.addOperand(MCOperand::CreateImm(
884      ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
885  }
886
887  void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
888    assert(N == 2 && "Invalid number of operands!");
889    assert(isRegShiftedImm() && "addRegShiftedImmOperands() on non RegShiftedImm!");
890    Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
891    Inst.addOperand(MCOperand::CreateImm(
892      ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm)));
893  }
894
895  void addShifterImmOperands(MCInst &Inst, unsigned N) const {
896    assert(N == 1 && "Invalid number of operands!");
897    Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
898                                         ShifterImm.Imm));
899  }
900
901  void addRegListOperands(MCInst &Inst, unsigned N) const {
902    assert(N == 1 && "Invalid number of operands!");
903    const SmallVectorImpl<unsigned> &RegList = getRegList();
904    for (SmallVectorImpl<unsigned>::const_iterator
905           I = RegList.begin(), E = RegList.end(); I != E; ++I)
906      Inst.addOperand(MCOperand::CreateReg(*I));
907  }
908
909  void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
910    addRegListOperands(Inst, N);
911  }
912
913  void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
914    addRegListOperands(Inst, N);
915  }
916
917  void addRotImmOperands(MCInst &Inst, unsigned N) const {
918    assert(N == 1 && "Invalid number of operands!");
919    // Encoded as val>>3. The printer handles display as 8, 16, 24.
920    Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
921  }
922
923  void addBitfieldOperands(MCInst &Inst, unsigned N) const {
924    assert(N == 1 && "Invalid number of operands!");
925    // Munge the lsb/width into a bitfield mask.
926    unsigned lsb = Bitfield.LSB;
927    unsigned width = Bitfield.Width;
928    // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
929    uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
930                      (32 - (lsb + width)));
931    Inst.addOperand(MCOperand::CreateImm(Mask));
932  }
933
934  void addImmOperands(MCInst &Inst, unsigned N) const {
935    assert(N == 1 && "Invalid number of operands!");
936    addExpr(Inst, getImm());
937  }
938
939  void addImm8s4Operands(MCInst &Inst, unsigned N) const {
940    assert(N == 1 && "Invalid number of operands!");
941    // FIXME: We really want to scale the value here, but the LDRD/STRD
942    // instruction don't encode operands that way yet.
943    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
944    Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
945  }
946
947  void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
948    assert(N == 1 && "Invalid number of operands!");
949    // The immediate is scaled by four in the encoding and is stored
950    // in the MCInst as such. Lop off the low two bits here.
951    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
952    Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
953  }
954
955  void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
956    assert(N == 1 && "Invalid number of operands!");
957    // The immediate is scaled by four in the encoding and is stored
958    // in the MCInst as such. Lop off the low two bits here.
959    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
960    Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
961  }
962
963  void addImm0_255Operands(MCInst &Inst, unsigned N) const {
964    assert(N == 1 && "Invalid number of operands!");
965    addExpr(Inst, getImm());
966  }
967
968  void addImm0_7Operands(MCInst &Inst, unsigned N) const {
969    assert(N == 1 && "Invalid number of operands!");
970    addExpr(Inst, getImm());
971  }
972
973  void addImm0_15Operands(MCInst &Inst, unsigned N) const {
974    assert(N == 1 && "Invalid number of operands!");
975    addExpr(Inst, getImm());
976  }
977
978  void addImm0_31Operands(MCInst &Inst, unsigned N) const {
979    assert(N == 1 && "Invalid number of operands!");
980    addExpr(Inst, getImm());
981  }
982
983  void addImm1_16Operands(MCInst &Inst, unsigned N) const {
984    assert(N == 1 && "Invalid number of operands!");
985    // The constant encodes as the immediate-1, and we store in the instruction
986    // the bits as encoded, so subtract off one here.
987    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
988    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
989  }
990
991  void addImm1_32Operands(MCInst &Inst, unsigned N) const {
992    assert(N == 1 && "Invalid number of operands!");
993    // The constant encodes as the immediate-1, and we store in the instruction
994    // the bits as encoded, so subtract off one here.
995    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
996    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
997  }
998
999  void addImm0_65535Operands(MCInst &Inst, unsigned N) const {
1000    assert(N == 1 && "Invalid number of operands!");
1001    addExpr(Inst, getImm());
1002  }
1003
1004  void addImm0_65535ExprOperands(MCInst &Inst, unsigned N) const {
1005    assert(N == 1 && "Invalid number of operands!");
1006    addExpr(Inst, getImm());
1007  }
1008
1009  void addImm24bitOperands(MCInst &Inst, unsigned N) const {
1010    assert(N == 1 && "Invalid number of operands!");
1011    addExpr(Inst, getImm());
1012  }
1013
1014  void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1015    assert(N == 1 && "Invalid number of operands!");
1016    // The constant encodes as the immediate, except for 32, which encodes as
1017    // zero.
1018    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1019    unsigned Imm = CE->getValue();
1020    Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1021  }
1022
1023  void addPKHLSLImmOperands(MCInst &Inst, unsigned N) const {
1024    assert(N == 1 && "Invalid number of operands!");
1025    addExpr(Inst, getImm());
1026  }
1027
1028  void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1029    assert(N == 1 && "Invalid number of operands!");
1030    // An ASR value of 32 encodes as 0, so that's how we want to add it to
1031    // the instruction as well.
1032    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1033    int Val = CE->getValue();
1034    Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1035  }
1036
1037  void addARMSOImmOperands(MCInst &Inst, unsigned N) const {
1038    assert(N == 1 && "Invalid number of operands!");
1039    addExpr(Inst, getImm());
1040  }
1041
1042  void addT2SOImmOperands(MCInst &Inst, unsigned N) const {
1043    assert(N == 1 && "Invalid number of operands!");
1044    addExpr(Inst, getImm());
1045  }
1046
1047  void addSetEndImmOperands(MCInst &Inst, unsigned N) const {
1048    assert(N == 1 && "Invalid number of operands!");
1049    addExpr(Inst, getImm());
1050  }
1051
1052  void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1053    assert(N == 1 && "Invalid number of operands!");
1054    Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1055  }
1056
1057  void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1058    assert(N == 1 && "Invalid number of operands!");
1059    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1060  }
1061
1062  void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
1063    assert(N == 3 && "Invalid number of operands!");
1064    int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1065    if (!Mem.OffsetRegNum) {
1066      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1067      // Special case for #-0
1068      if (Val == INT32_MIN) Val = 0;
1069      if (Val < 0) Val = -Val;
1070      Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1071    } else {
1072      // For register offset, we encode the shift type and negation flag
1073      // here.
1074      Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add,
1075                              Mem.ShiftImm, Mem.ShiftType);
1076    }
1077    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1078    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1079    Inst.addOperand(MCOperand::CreateImm(Val));
1080  }
1081
1082  void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
1083    assert(N == 2 && "Invalid number of operands!");
1084    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1085    assert(CE && "non-constant AM2OffsetImm operand!");
1086    int32_t Val = CE->getValue();
1087    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1088    // Special case for #-0
1089    if (Val == INT32_MIN) Val = 0;
1090    if (Val < 0) Val = -Val;
1091    Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1092    Inst.addOperand(MCOperand::CreateReg(0));
1093    Inst.addOperand(MCOperand::CreateImm(Val));
1094  }
1095
1096  void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
1097    assert(N == 3 && "Invalid number of operands!");
1098    int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1099    if (!Mem.OffsetRegNum) {
1100      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1101      // Special case for #-0
1102      if (Val == INT32_MIN) Val = 0;
1103      if (Val < 0) Val = -Val;
1104      Val = ARM_AM::getAM3Opc(AddSub, Val);
1105    } else {
1106      // For register offset, we encode the shift type and negation flag
1107      // here.
1108      Val = ARM_AM::getAM3Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
1109    }
1110    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1111    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1112    Inst.addOperand(MCOperand::CreateImm(Val));
1113  }
1114
1115  void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
1116    assert(N == 2 && "Invalid number of operands!");
1117    if (Kind == PostIndexRegister) {
1118      int32_t Val =
1119        ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
1120      Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1121      Inst.addOperand(MCOperand::CreateImm(Val));
1122      return;
1123    }
1124
1125    // Constant offset.
1126    const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
1127    int32_t Val = CE->getValue();
1128    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1129    // Special case for #-0
1130    if (Val == INT32_MIN) Val = 0;
1131    if (Val < 0) Val = -Val;
1132    Val = ARM_AM::getAM3Opc(AddSub, Val);
1133    Inst.addOperand(MCOperand::CreateReg(0));
1134    Inst.addOperand(MCOperand::CreateImm(Val));
1135  }
1136
1137  void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
1138    assert(N == 2 && "Invalid number of operands!");
1139    // The lower two bits are always zero and as such are not encoded.
1140    int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() / 4 : 0;
1141    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1142    // Special case for #-0
1143    if (Val == INT32_MIN) Val = 0;
1144    if (Val < 0) Val = -Val;
1145    Val = ARM_AM::getAM5Opc(AddSub, Val);
1146    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1147    Inst.addOperand(MCOperand::CreateImm(Val));
1148  }
1149
1150  void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
1151    assert(N == 2 && "Invalid number of operands!");
1152    int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1153    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1154    Inst.addOperand(MCOperand::CreateImm(Val));
1155  }
1156
1157  void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
1158    assert(N == 2 && "Invalid number of operands!");
1159    // The lower two bits are always zero and as such are not encoded.
1160    int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() / 4 : 0;
1161    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1162    Inst.addOperand(MCOperand::CreateImm(Val));
1163  }
1164
1165  void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1166    assert(N == 2 && "Invalid number of operands!");
1167    int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1168    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1169    Inst.addOperand(MCOperand::CreateImm(Val));
1170  }
1171
1172  void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1173    addMemImm8OffsetOperands(Inst, N);
1174  }
1175
1176  void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1177    addMemImm8OffsetOperands(Inst, N);
1178  }
1179
1180  void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1181    assert(N == 2 && "Invalid number of operands!");
1182    // If this is an immediate, it's a label reference.
1183    if (Kind == Immediate) {
1184      addExpr(Inst, getImm());
1185      Inst.addOperand(MCOperand::CreateImm(0));
1186      return;
1187    }
1188
1189    // Otherwise, it's a normal memory reg+offset.
1190    int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1191    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1192    Inst.addOperand(MCOperand::CreateImm(Val));
1193  }
1194
1195  void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1196    assert(N == 2 && "Invalid number of operands!");
1197    // If this is an immediate, it's a label reference.
1198    if (Kind == Immediate) {
1199      addExpr(Inst, getImm());
1200      Inst.addOperand(MCOperand::CreateImm(0));
1201      return;
1202    }
1203
1204    // Otherwise, it's a normal memory reg+offset.
1205    int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1206    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1207    Inst.addOperand(MCOperand::CreateImm(Val));
1208  }
1209
1210  void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1211    assert(N == 3 && "Invalid number of operands!");
1212    unsigned Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add,
1213                                     Mem.ShiftImm, Mem.ShiftType);
1214    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1215    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1216    Inst.addOperand(MCOperand::CreateImm(Val));
1217  }
1218
1219  void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1220    assert(N == 3 && "Invalid number of operands!");
1221    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1222    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1223    Inst.addOperand(MCOperand::CreateImm(Mem.ShiftImm));
1224  }
1225
1226  void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
1227    assert(N == 2 && "Invalid number of operands!");
1228    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1229    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1230  }
1231
1232  void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
1233    assert(N == 2 && "Invalid number of operands!");
1234    int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 4) : 0;
1235    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1236    Inst.addOperand(MCOperand::CreateImm(Val));
1237  }
1238
1239  void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
1240    assert(N == 2 && "Invalid number of operands!");
1241    int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 2) : 0;
1242    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1243    Inst.addOperand(MCOperand::CreateImm(Val));
1244  }
1245
1246  void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
1247    assert(N == 2 && "Invalid number of operands!");
1248    int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue()) : 0;
1249    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1250    Inst.addOperand(MCOperand::CreateImm(Val));
1251  }
1252
1253  void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
1254    assert(N == 2 && "Invalid number of operands!");
1255    int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 4) : 0;
1256    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1257    Inst.addOperand(MCOperand::CreateImm(Val));
1258  }
1259
1260  void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
1261    assert(N == 1 && "Invalid number of operands!");
1262    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1263    assert(CE && "non-constant post-idx-imm8 operand!");
1264    int Imm = CE->getValue();
1265    bool isAdd = Imm >= 0;
1266    if (Imm == INT32_MIN) Imm = 0;
1267    Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
1268    Inst.addOperand(MCOperand::CreateImm(Imm));
1269  }
1270
1271  void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
1272    assert(N == 2 && "Invalid number of operands!");
1273    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1274    Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
1275  }
1276
1277  void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
1278    assert(N == 2 && "Invalid number of operands!");
1279    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1280    // The sign, shift type, and shift amount are encoded in a single operand
1281    // using the AM2 encoding helpers.
1282    ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
1283    unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
1284                                     PostIdxReg.ShiftTy);
1285    Inst.addOperand(MCOperand::CreateImm(Imm));
1286  }
1287
1288  void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
1289    assert(N == 1 && "Invalid number of operands!");
1290    Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
1291  }
1292
1293  void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
1294    assert(N == 1 && "Invalid number of operands!");
1295    Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
1296  }
1297
1298  virtual void print(raw_ostream &OS) const;
1299
1300  static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
1301    ARMOperand *Op = new ARMOperand(ITCondMask);
1302    Op->ITMask.Mask = Mask;
1303    Op->StartLoc = S;
1304    Op->EndLoc = S;
1305    return Op;
1306  }
1307
1308  static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
1309    ARMOperand *Op = new ARMOperand(CondCode);
1310    Op->CC.Val = CC;
1311    Op->StartLoc = S;
1312    Op->EndLoc = S;
1313    return Op;
1314  }
1315
1316  static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
1317    ARMOperand *Op = new ARMOperand(CoprocNum);
1318    Op->Cop.Val = CopVal;
1319    Op->StartLoc = S;
1320    Op->EndLoc = S;
1321    return Op;
1322  }
1323
1324  static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
1325    ARMOperand *Op = new ARMOperand(CoprocReg);
1326    Op->Cop.Val = CopVal;
1327    Op->StartLoc = S;
1328    Op->EndLoc = S;
1329    return Op;
1330  }
1331
1332  static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
1333    ARMOperand *Op = new ARMOperand(CCOut);
1334    Op->Reg.RegNum = RegNum;
1335    Op->StartLoc = S;
1336    Op->EndLoc = S;
1337    return Op;
1338  }
1339
1340  static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
1341    ARMOperand *Op = new ARMOperand(Token);
1342    Op->Tok.Data = Str.data();
1343    Op->Tok.Length = Str.size();
1344    Op->StartLoc = S;
1345    Op->EndLoc = S;
1346    return Op;
1347  }
1348
1349  static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
1350    ARMOperand *Op = new ARMOperand(Register);
1351    Op->Reg.RegNum = RegNum;
1352    Op->StartLoc = S;
1353    Op->EndLoc = E;
1354    return Op;
1355  }
1356
1357  static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
1358                                           unsigned SrcReg,
1359                                           unsigned ShiftReg,
1360                                           unsigned ShiftImm,
1361                                           SMLoc S, SMLoc E) {
1362    ARMOperand *Op = new ARMOperand(ShiftedRegister);
1363    Op->RegShiftedReg.ShiftTy = ShTy;
1364    Op->RegShiftedReg.SrcReg = SrcReg;
1365    Op->RegShiftedReg.ShiftReg = ShiftReg;
1366    Op->RegShiftedReg.ShiftImm = ShiftImm;
1367    Op->StartLoc = S;
1368    Op->EndLoc = E;
1369    return Op;
1370  }
1371
1372  static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
1373                                            unsigned SrcReg,
1374                                            unsigned ShiftImm,
1375                                            SMLoc S, SMLoc E) {
1376    ARMOperand *Op = new ARMOperand(ShiftedImmediate);
1377    Op->RegShiftedImm.ShiftTy = ShTy;
1378    Op->RegShiftedImm.SrcReg = SrcReg;
1379    Op->RegShiftedImm.ShiftImm = ShiftImm;
1380    Op->StartLoc = S;
1381    Op->EndLoc = E;
1382    return Op;
1383  }
1384
1385  static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
1386                                   SMLoc S, SMLoc E) {
1387    ARMOperand *Op = new ARMOperand(ShifterImmediate);
1388    Op->ShifterImm.isASR = isASR;
1389    Op->ShifterImm.Imm = Imm;
1390    Op->StartLoc = S;
1391    Op->EndLoc = E;
1392    return Op;
1393  }
1394
1395  static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
1396    ARMOperand *Op = new ARMOperand(RotateImmediate);
1397    Op->RotImm.Imm = Imm;
1398    Op->StartLoc = S;
1399    Op->EndLoc = E;
1400    return Op;
1401  }
1402
1403  static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
1404                                    SMLoc S, SMLoc E) {
1405    ARMOperand *Op = new ARMOperand(BitfieldDescriptor);
1406    Op->Bitfield.LSB = LSB;
1407    Op->Bitfield.Width = Width;
1408    Op->StartLoc = S;
1409    Op->EndLoc = E;
1410    return Op;
1411  }
1412
1413  static ARMOperand *
1414  CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
1415                SMLoc StartLoc, SMLoc EndLoc) {
1416    KindTy Kind = RegisterList;
1417
1418    if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().first))
1419      Kind = DPRRegisterList;
1420    else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
1421             contains(Regs.front().first))
1422      Kind = SPRRegisterList;
1423
1424    ARMOperand *Op = new ARMOperand(Kind);
1425    for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
1426           I = Regs.begin(), E = Regs.end(); I != E; ++I)
1427      Op->Registers.push_back(I->first);
1428    array_pod_sort(Op->Registers.begin(), Op->Registers.end());
1429    Op->StartLoc = StartLoc;
1430    Op->EndLoc = EndLoc;
1431    return Op;
1432  }
1433
1434  static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
1435    ARMOperand *Op = new ARMOperand(Immediate);
1436    Op->Imm.Val = Val;
1437    Op->StartLoc = S;
1438    Op->EndLoc = E;
1439    return Op;
1440  }
1441
1442  static ARMOperand *CreateMem(unsigned BaseRegNum,
1443                               const MCConstantExpr *OffsetImm,
1444                               unsigned OffsetRegNum,
1445                               ARM_AM::ShiftOpc ShiftType,
1446                               unsigned ShiftImm,
1447                               bool isNegative,
1448                               SMLoc S, SMLoc E) {
1449    ARMOperand *Op = new ARMOperand(Memory);
1450    Op->Mem.BaseRegNum = BaseRegNum;
1451    Op->Mem.OffsetImm = OffsetImm;
1452    Op->Mem.OffsetRegNum = OffsetRegNum;
1453    Op->Mem.ShiftType = ShiftType;
1454    Op->Mem.ShiftImm = ShiftImm;
1455    Op->Mem.isNegative = isNegative;
1456    Op->StartLoc = S;
1457    Op->EndLoc = E;
1458    return Op;
1459  }
1460
1461  static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
1462                                      ARM_AM::ShiftOpc ShiftTy,
1463                                      unsigned ShiftImm,
1464                                      SMLoc S, SMLoc E) {
1465    ARMOperand *Op = new ARMOperand(PostIndexRegister);
1466    Op->PostIdxReg.RegNum = RegNum;
1467    Op->PostIdxReg.isAdd = isAdd;
1468    Op->PostIdxReg.ShiftTy = ShiftTy;
1469    Op->PostIdxReg.ShiftImm = ShiftImm;
1470    Op->StartLoc = S;
1471    Op->EndLoc = E;
1472    return Op;
1473  }
1474
1475  static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
1476    ARMOperand *Op = new ARMOperand(MemBarrierOpt);
1477    Op->MBOpt.Val = Opt;
1478    Op->StartLoc = S;
1479    Op->EndLoc = S;
1480    return Op;
1481  }
1482
1483  static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
1484    ARMOperand *Op = new ARMOperand(ProcIFlags);
1485    Op->IFlags.Val = IFlags;
1486    Op->StartLoc = S;
1487    Op->EndLoc = S;
1488    return Op;
1489  }
1490
1491  static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
1492    ARMOperand *Op = new ARMOperand(MSRMask);
1493    Op->MMask.Val = MMask;
1494    Op->StartLoc = S;
1495    Op->EndLoc = S;
1496    return Op;
1497  }
1498};
1499
1500} // end anonymous namespace.
1501
1502void ARMOperand::print(raw_ostream &OS) const {
1503  switch (Kind) {
1504  case CondCode:
1505    OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
1506    break;
1507  case CCOut:
1508    OS << "<ccout " << getReg() << ">";
1509    break;
1510  case ITCondMask: {
1511    static char MaskStr[][6] = { "()", "(t)", "(e)", "(tt)", "(et)", "(te)",
1512      "(ee)", "(ttt)", "(ett)", "(tet)", "(eet)", "(tte)", "(ete)",
1513      "(tee)", "(eee)" };
1514    assert((ITMask.Mask & 0xf) == ITMask.Mask);
1515    OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
1516    break;
1517  }
1518  case CoprocNum:
1519    OS << "<coprocessor number: " << getCoproc() << ">";
1520    break;
1521  case CoprocReg:
1522    OS << "<coprocessor register: " << getCoproc() << ">";
1523    break;
1524  case MSRMask:
1525    OS << "<mask: " << getMSRMask() << ">";
1526    break;
1527  case Immediate:
1528    getImm()->print(OS);
1529    break;
1530  case MemBarrierOpt:
1531    OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
1532    break;
1533  case Memory:
1534    OS << "<memory "
1535       << " base:" << Mem.BaseRegNum;
1536    OS << ">";
1537    break;
1538  case PostIndexRegister:
1539    OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
1540       << PostIdxReg.RegNum;
1541    if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
1542      OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
1543         << PostIdxReg.ShiftImm;
1544    OS << ">";
1545    break;
1546  case ProcIFlags: {
1547    OS << "<ARM_PROC::";
1548    unsigned IFlags = getProcIFlags();
1549    for (int i=2; i >= 0; --i)
1550      if (IFlags & (1 << i))
1551        OS << ARM_PROC::IFlagsToString(1 << i);
1552    OS << ">";
1553    break;
1554  }
1555  case Register:
1556    OS << "<register " << getReg() << ">";
1557    break;
1558  case ShifterImmediate:
1559    OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
1560       << " #" << ShifterImm.Imm << ">";
1561    break;
1562  case ShiftedRegister:
1563    OS << "<so_reg_reg "
1564       << RegShiftedReg.SrcReg
1565       << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedReg.ShiftImm))
1566       << ", " << RegShiftedReg.ShiftReg << ", "
1567       << ARM_AM::getSORegOffset(RegShiftedReg.ShiftImm)
1568       << ">";
1569    break;
1570  case ShiftedImmediate:
1571    OS << "<so_reg_imm "
1572       << RegShiftedImm.SrcReg
1573       << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedImm.ShiftImm))
1574       << ", " << ARM_AM::getSORegOffset(RegShiftedImm.ShiftImm)
1575       << ">";
1576    break;
1577  case RotateImmediate:
1578    OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
1579    break;
1580  case BitfieldDescriptor:
1581    OS << "<bitfield " << "lsb: " << Bitfield.LSB
1582       << ", width: " << Bitfield.Width << ">";
1583    break;
1584  case RegisterList:
1585  case DPRRegisterList:
1586  case SPRRegisterList: {
1587    OS << "<register_list ";
1588
1589    const SmallVectorImpl<unsigned> &RegList = getRegList();
1590    for (SmallVectorImpl<unsigned>::const_iterator
1591           I = RegList.begin(), E = RegList.end(); I != E; ) {
1592      OS << *I;
1593      if (++I < E) OS << ", ";
1594    }
1595
1596    OS << ">";
1597    break;
1598  }
1599  case Token:
1600    OS << "'" << getToken() << "'";
1601    break;
1602  }
1603}
1604
1605/// @name Auto-generated Match Functions
1606/// {
1607
1608static unsigned MatchRegisterName(StringRef Name);
1609
1610/// }
1611
1612bool ARMAsmParser::ParseRegister(unsigned &RegNo,
1613                                 SMLoc &StartLoc, SMLoc &EndLoc) {
1614  RegNo = tryParseRegister();
1615
1616  return (RegNo == (unsigned)-1);
1617}
1618
1619/// Try to parse a register name.  The token must be an Identifier when called,
1620/// and if it is a register name the token is eaten and the register number is
1621/// returned.  Otherwise return -1.
1622///
1623int ARMAsmParser::tryParseRegister() {
1624  const AsmToken &Tok = Parser.getTok();
1625  if (Tok.isNot(AsmToken::Identifier)) return -1;
1626
1627  // FIXME: Validate register for the current architecture; we have to do
1628  // validation later, so maybe there is no need for this here.
1629  std::string upperCase = Tok.getString().str();
1630  std::string lowerCase = LowercaseString(upperCase);
1631  unsigned RegNum = MatchRegisterName(lowerCase);
1632  if (!RegNum) {
1633    RegNum = StringSwitch<unsigned>(lowerCase)
1634      .Case("r13", ARM::SP)
1635      .Case("r14", ARM::LR)
1636      .Case("r15", ARM::PC)
1637      .Case("ip", ARM::R12)
1638      .Default(0);
1639  }
1640  if (!RegNum) return -1;
1641
1642  Parser.Lex(); // Eat identifier token.
1643  return RegNum;
1644}
1645
1646// Try to parse a shifter  (e.g., "lsl <amt>"). On success, return 0.
1647// If a recoverable error occurs, return 1. If an irrecoverable error
1648// occurs, return -1. An irrecoverable error is one where tokens have been
1649// consumed in the process of trying to parse the shifter (i.e., when it is
1650// indeed a shifter operand, but malformed).
1651int ARMAsmParser::tryParseShiftRegister(
1652                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1653  SMLoc S = Parser.getTok().getLoc();
1654  const AsmToken &Tok = Parser.getTok();
1655  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1656
1657  std::string upperCase = Tok.getString().str();
1658  std::string lowerCase = LowercaseString(upperCase);
1659  ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
1660      .Case("lsl", ARM_AM::lsl)
1661      .Case("lsr", ARM_AM::lsr)
1662      .Case("asr", ARM_AM::asr)
1663      .Case("ror", ARM_AM::ror)
1664      .Case("rrx", ARM_AM::rrx)
1665      .Default(ARM_AM::no_shift);
1666
1667  if (ShiftTy == ARM_AM::no_shift)
1668    return 1;
1669
1670  Parser.Lex(); // Eat the operator.
1671
1672  // The source register for the shift has already been added to the
1673  // operand list, so we need to pop it off and combine it into the shifted
1674  // register operand instead.
1675  OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
1676  if (!PrevOp->isReg())
1677    return Error(PrevOp->getStartLoc(), "shift must be of a register");
1678  int SrcReg = PrevOp->getReg();
1679  int64_t Imm = 0;
1680  int ShiftReg = 0;
1681  if (ShiftTy == ARM_AM::rrx) {
1682    // RRX Doesn't have an explicit shift amount. The encoder expects
1683    // the shift register to be the same as the source register. Seems odd,
1684    // but OK.
1685    ShiftReg = SrcReg;
1686  } else {
1687    // Figure out if this is shifted by a constant or a register (for non-RRX).
1688    if (Parser.getTok().is(AsmToken::Hash)) {
1689      Parser.Lex(); // Eat hash.
1690      SMLoc ImmLoc = Parser.getTok().getLoc();
1691      const MCExpr *ShiftExpr = 0;
1692      if (getParser().ParseExpression(ShiftExpr)) {
1693        Error(ImmLoc, "invalid immediate shift value");
1694        return -1;
1695      }
1696      // The expression must be evaluatable as an immediate.
1697      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
1698      if (!CE) {
1699        Error(ImmLoc, "invalid immediate shift value");
1700        return -1;
1701      }
1702      // Range check the immediate.
1703      // lsl, ror: 0 <= imm <= 31
1704      // lsr, asr: 0 <= imm <= 32
1705      Imm = CE->getValue();
1706      if (Imm < 0 ||
1707          ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
1708          ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
1709        Error(ImmLoc, "immediate shift value out of range");
1710        return -1;
1711      }
1712    } else if (Parser.getTok().is(AsmToken::Identifier)) {
1713      ShiftReg = tryParseRegister();
1714      SMLoc L = Parser.getTok().getLoc();
1715      if (ShiftReg == -1) {
1716        Error (L, "expected immediate or register in shift operand");
1717        return -1;
1718      }
1719    } else {
1720      Error (Parser.getTok().getLoc(),
1721                    "expected immediate or register in shift operand");
1722      return -1;
1723    }
1724  }
1725
1726  if (ShiftReg && ShiftTy != ARM_AM::rrx)
1727    Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
1728                                                         ShiftReg, Imm,
1729                                               S, Parser.getTok().getLoc()));
1730  else
1731    Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
1732                                               S, Parser.getTok().getLoc()));
1733
1734  return 0;
1735}
1736
1737
1738/// Try to parse a register name.  The token must be an Identifier when called.
1739/// If it's a register, an AsmOperand is created. Another AsmOperand is created
1740/// if there is a "writeback". 'true' if it's not a register.
1741///
1742/// TODO this is likely to change to allow different register types and or to
1743/// parse for a specific register type.
1744bool ARMAsmParser::
1745tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1746  SMLoc S = Parser.getTok().getLoc();
1747  int RegNo = tryParseRegister();
1748  if (RegNo == -1)
1749    return true;
1750
1751  Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
1752
1753  const AsmToken &ExclaimTok = Parser.getTok();
1754  if (ExclaimTok.is(AsmToken::Exclaim)) {
1755    Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
1756                                               ExclaimTok.getLoc()));
1757    Parser.Lex(); // Eat exclaim token
1758  }
1759
1760  return false;
1761}
1762
1763/// MatchCoprocessorOperandName - Try to parse an coprocessor related
1764/// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
1765/// "c5", ...
1766static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
1767  // Use the same layout as the tablegen'erated register name matcher. Ugly,
1768  // but efficient.
1769  switch (Name.size()) {
1770  default: break;
1771  case 2:
1772    if (Name[0] != CoprocOp)
1773      return -1;
1774    switch (Name[1]) {
1775    default:  return -1;
1776    case '0': return 0;
1777    case '1': return 1;
1778    case '2': return 2;
1779    case '3': return 3;
1780    case '4': return 4;
1781    case '5': return 5;
1782    case '6': return 6;
1783    case '7': return 7;
1784    case '8': return 8;
1785    case '9': return 9;
1786    }
1787    break;
1788  case 3:
1789    if (Name[0] != CoprocOp || Name[1] != '1')
1790      return -1;
1791    switch (Name[2]) {
1792    default:  return -1;
1793    case '0': return 10;
1794    case '1': return 11;
1795    case '2': return 12;
1796    case '3': return 13;
1797    case '4': return 14;
1798    case '5': return 15;
1799    }
1800    break;
1801  }
1802
1803  return -1;
1804}
1805
1806/// parseITCondCode - Try to parse a condition code for an IT instruction.
1807ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1808parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1809  SMLoc S = Parser.getTok().getLoc();
1810  const AsmToken &Tok = Parser.getTok();
1811  if (!Tok.is(AsmToken::Identifier))
1812    return MatchOperand_NoMatch;
1813  unsigned CC = StringSwitch<unsigned>(Tok.getString())
1814    .Case("eq", ARMCC::EQ)
1815    .Case("ne", ARMCC::NE)
1816    .Case("hs", ARMCC::HS)
1817    .Case("cs", ARMCC::HS)
1818    .Case("lo", ARMCC::LO)
1819    .Case("cc", ARMCC::LO)
1820    .Case("mi", ARMCC::MI)
1821    .Case("pl", ARMCC::PL)
1822    .Case("vs", ARMCC::VS)
1823    .Case("vc", ARMCC::VC)
1824    .Case("hi", ARMCC::HI)
1825    .Case("ls", ARMCC::LS)
1826    .Case("ge", ARMCC::GE)
1827    .Case("lt", ARMCC::LT)
1828    .Case("gt", ARMCC::GT)
1829    .Case("le", ARMCC::LE)
1830    .Case("al", ARMCC::AL)
1831    .Default(~0U);
1832  if (CC == ~0U)
1833    return MatchOperand_NoMatch;
1834  Parser.Lex(); // Eat the token.
1835
1836  Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
1837
1838  return MatchOperand_Success;
1839}
1840
1841/// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
1842/// token must be an Identifier when called, and if it is a coprocessor
1843/// number, the token is eaten and the operand is added to the operand list.
1844ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1845parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1846  SMLoc S = Parser.getTok().getLoc();
1847  const AsmToken &Tok = Parser.getTok();
1848  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1849
1850  int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
1851  if (Num == -1)
1852    return MatchOperand_NoMatch;
1853
1854  Parser.Lex(); // Eat identifier token.
1855  Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
1856  return MatchOperand_Success;
1857}
1858
1859/// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
1860/// token must be an Identifier when called, and if it is a coprocessor
1861/// number, the token is eaten and the operand is added to the operand list.
1862ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1863parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1864  SMLoc S = Parser.getTok().getLoc();
1865  const AsmToken &Tok = Parser.getTok();
1866  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1867
1868  int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
1869  if (Reg == -1)
1870    return MatchOperand_NoMatch;
1871
1872  Parser.Lex(); // Eat identifier token.
1873  Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
1874  return MatchOperand_Success;
1875}
1876
1877/// Parse a register list, return it if successful else return null.  The first
1878/// token must be a '{' when called.
1879bool ARMAsmParser::
1880parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1881  assert(Parser.getTok().is(AsmToken::LCurly) &&
1882         "Token is not a Left Curly Brace");
1883  SMLoc S = Parser.getTok().getLoc();
1884
1885  // Read the rest of the registers in the list.
1886  unsigned PrevRegNum = 0;
1887  SmallVector<std::pair<unsigned, SMLoc>, 16> Registers;
1888
1889  do {
1890    bool IsRange = Parser.getTok().is(AsmToken::Minus);
1891    Parser.Lex(); // Eat non-identifier token.
1892
1893    const AsmToken &RegTok = Parser.getTok();
1894    SMLoc RegLoc = RegTok.getLoc();
1895    if (RegTok.isNot(AsmToken::Identifier))
1896      return Error(RegLoc, "register expected");
1897
1898    int RegNum = tryParseRegister();
1899    if (RegNum == -1)
1900      return Error(RegLoc, "register expected");
1901
1902    if (IsRange) {
1903      int Reg = PrevRegNum;
1904      do {
1905        ++Reg;
1906        Registers.push_back(std::make_pair(Reg, RegLoc));
1907      } while (Reg != RegNum);
1908    } else
1909      Registers.push_back(std::make_pair(RegNum, RegLoc));
1910
1911    PrevRegNum = RegNum;
1912  } while (Parser.getTok().is(AsmToken::Comma) ||
1913           Parser.getTok().is(AsmToken::Minus));
1914
1915  // Process the right curly brace of the list.
1916  const AsmToken &RCurlyTok = Parser.getTok();
1917  if (RCurlyTok.isNot(AsmToken::RCurly))
1918    return Error(RCurlyTok.getLoc(), "'}' expected");
1919
1920  SMLoc E = RCurlyTok.getLoc();
1921  Parser.Lex(); // Eat right curly brace token.
1922
1923  // Verify the register list.
1924  bool EmittedWarning = false;
1925  unsigned HighRegNum = 0;
1926  BitVector RegMap(32);
1927  for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
1928    const std::pair<unsigned, SMLoc> &RegInfo = Registers[i];
1929    unsigned Reg = getARMRegisterNumbering(RegInfo.first);
1930
1931    if (RegMap[Reg])
1932      return Error(RegInfo.second, "register duplicated in register list");
1933
1934    if (!EmittedWarning && Reg < HighRegNum)
1935      Warning(RegInfo.second,
1936              "register not in ascending order in register list");
1937
1938    RegMap.set(Reg);
1939    HighRegNum = std::max(Reg, HighRegNum);
1940  }
1941
1942  Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
1943  return false;
1944}
1945
1946/// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
1947ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1948parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1949  SMLoc S = Parser.getTok().getLoc();
1950  const AsmToken &Tok = Parser.getTok();
1951  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1952  StringRef OptStr = Tok.getString();
1953
1954  unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()))
1955    .Case("sy",    ARM_MB::SY)
1956    .Case("st",    ARM_MB::ST)
1957    .Case("sh",    ARM_MB::ISH)
1958    .Case("ish",   ARM_MB::ISH)
1959    .Case("shst",  ARM_MB::ISHST)
1960    .Case("ishst", ARM_MB::ISHST)
1961    .Case("nsh",   ARM_MB::NSH)
1962    .Case("un",    ARM_MB::NSH)
1963    .Case("nshst", ARM_MB::NSHST)
1964    .Case("unst",  ARM_MB::NSHST)
1965    .Case("osh",   ARM_MB::OSH)
1966    .Case("oshst", ARM_MB::OSHST)
1967    .Default(~0U);
1968
1969  if (Opt == ~0U)
1970    return MatchOperand_NoMatch;
1971
1972  Parser.Lex(); // Eat identifier token.
1973  Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
1974  return MatchOperand_Success;
1975}
1976
1977/// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
1978ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1979parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1980  SMLoc S = Parser.getTok().getLoc();
1981  const AsmToken &Tok = Parser.getTok();
1982  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1983  StringRef IFlagsStr = Tok.getString();
1984
1985  unsigned IFlags = 0;
1986  for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
1987    unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
1988    .Case("a", ARM_PROC::A)
1989    .Case("i", ARM_PROC::I)
1990    .Case("f", ARM_PROC::F)
1991    .Default(~0U);
1992
1993    // If some specific iflag is already set, it means that some letter is
1994    // present more than once, this is not acceptable.
1995    if (Flag == ~0U || (IFlags & Flag))
1996      return MatchOperand_NoMatch;
1997
1998    IFlags |= Flag;
1999  }
2000
2001  Parser.Lex(); // Eat identifier token.
2002  Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
2003  return MatchOperand_Success;
2004}
2005
2006/// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
2007ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2008parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2009  SMLoc S = Parser.getTok().getLoc();
2010  const AsmToken &Tok = Parser.getTok();
2011  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2012  StringRef Mask = Tok.getString();
2013
2014  // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
2015  size_t Start = 0, Next = Mask.find('_');
2016  StringRef Flags = "";
2017  std::string SpecReg = LowercaseString(Mask.slice(Start, Next));
2018  if (Next != StringRef::npos)
2019    Flags = Mask.slice(Next+1, Mask.size());
2020
2021  // FlagsVal contains the complete mask:
2022  // 3-0: Mask
2023  // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
2024  unsigned FlagsVal = 0;
2025
2026  if (SpecReg == "apsr") {
2027    FlagsVal = StringSwitch<unsigned>(Flags)
2028    .Case("nzcvq",  0x8) // same as CPSR_f
2029    .Case("g",      0x4) // same as CPSR_s
2030    .Case("nzcvqg", 0xc) // same as CPSR_fs
2031    .Default(~0U);
2032
2033    if (FlagsVal == ~0U) {
2034      if (!Flags.empty())
2035        return MatchOperand_NoMatch;
2036      else
2037        FlagsVal = 0; // No flag
2038    }
2039  } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
2040    if (Flags == "all") // cpsr_all is an alias for cpsr_fc
2041      Flags = "fc";
2042    for (int i = 0, e = Flags.size(); i != e; ++i) {
2043      unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
2044      .Case("c", 1)
2045      .Case("x", 2)
2046      .Case("s", 4)
2047      .Case("f", 8)
2048      .Default(~0U);
2049
2050      // If some specific flag is already set, it means that some letter is
2051      // present more than once, this is not acceptable.
2052      if (FlagsVal == ~0U || (FlagsVal & Flag))
2053        return MatchOperand_NoMatch;
2054      FlagsVal |= Flag;
2055    }
2056  } else // No match for special register.
2057    return MatchOperand_NoMatch;
2058
2059  // Special register without flags are equivalent to "fc" flags.
2060  if (!FlagsVal)
2061    FlagsVal = 0x9;
2062
2063  // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
2064  if (SpecReg == "spsr")
2065    FlagsVal |= 16;
2066
2067  Parser.Lex(); // Eat identifier token.
2068  Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
2069  return MatchOperand_Success;
2070}
2071
2072ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2073parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
2074            int Low, int High) {
2075  const AsmToken &Tok = Parser.getTok();
2076  if (Tok.isNot(AsmToken::Identifier)) {
2077    Error(Parser.getTok().getLoc(), Op + " operand expected.");
2078    return MatchOperand_ParseFail;
2079  }
2080  StringRef ShiftName = Tok.getString();
2081  std::string LowerOp = LowercaseString(Op);
2082  std::string UpperOp = UppercaseString(Op);
2083  if (ShiftName != LowerOp && ShiftName != UpperOp) {
2084    Error(Parser.getTok().getLoc(), Op + " operand expected.");
2085    return MatchOperand_ParseFail;
2086  }
2087  Parser.Lex(); // Eat shift type token.
2088
2089  // There must be a '#' and a shift amount.
2090  if (Parser.getTok().isNot(AsmToken::Hash)) {
2091    Error(Parser.getTok().getLoc(), "'#' expected");
2092    return MatchOperand_ParseFail;
2093  }
2094  Parser.Lex(); // Eat hash token.
2095
2096  const MCExpr *ShiftAmount;
2097  SMLoc Loc = Parser.getTok().getLoc();
2098  if (getParser().ParseExpression(ShiftAmount)) {
2099    Error(Loc, "illegal expression");
2100    return MatchOperand_ParseFail;
2101  }
2102  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
2103  if (!CE) {
2104    Error(Loc, "constant expression expected");
2105    return MatchOperand_ParseFail;
2106  }
2107  int Val = CE->getValue();
2108  if (Val < Low || Val > High) {
2109    Error(Loc, "immediate value out of range");
2110    return MatchOperand_ParseFail;
2111  }
2112
2113  Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc()));
2114
2115  return MatchOperand_Success;
2116}
2117
2118ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2119parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2120  const AsmToken &Tok = Parser.getTok();
2121  SMLoc S = Tok.getLoc();
2122  if (Tok.isNot(AsmToken::Identifier)) {
2123    Error(Tok.getLoc(), "'be' or 'le' operand expected");
2124    return MatchOperand_ParseFail;
2125  }
2126  int Val = StringSwitch<int>(Tok.getString())
2127    .Case("be", 1)
2128    .Case("le", 0)
2129    .Default(-1);
2130  Parser.Lex(); // Eat the token.
2131
2132  if (Val == -1) {
2133    Error(Tok.getLoc(), "'be' or 'le' operand expected");
2134    return MatchOperand_ParseFail;
2135  }
2136  Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
2137                                                                  getContext()),
2138                                           S, Parser.getTok().getLoc()));
2139  return MatchOperand_Success;
2140}
2141
2142/// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
2143/// instructions. Legal values are:
2144///     lsl #n  'n' in [0,31]
2145///     asr #n  'n' in [1,32]
2146///             n == 32 encoded as n == 0.
2147ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2148parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2149  const AsmToken &Tok = Parser.getTok();
2150  SMLoc S = Tok.getLoc();
2151  if (Tok.isNot(AsmToken::Identifier)) {
2152    Error(S, "shift operator 'asr' or 'lsl' expected");
2153    return MatchOperand_ParseFail;
2154  }
2155  StringRef ShiftName = Tok.getString();
2156  bool isASR;
2157  if (ShiftName == "lsl" || ShiftName == "LSL")
2158    isASR = false;
2159  else if (ShiftName == "asr" || ShiftName == "ASR")
2160    isASR = true;
2161  else {
2162    Error(S, "shift operator 'asr' or 'lsl' expected");
2163    return MatchOperand_ParseFail;
2164  }
2165  Parser.Lex(); // Eat the operator.
2166
2167  // A '#' and a shift amount.
2168  if (Parser.getTok().isNot(AsmToken::Hash)) {
2169    Error(Parser.getTok().getLoc(), "'#' expected");
2170    return MatchOperand_ParseFail;
2171  }
2172  Parser.Lex(); // Eat hash token.
2173
2174  const MCExpr *ShiftAmount;
2175  SMLoc E = Parser.getTok().getLoc();
2176  if (getParser().ParseExpression(ShiftAmount)) {
2177    Error(E, "malformed shift expression");
2178    return MatchOperand_ParseFail;
2179  }
2180  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
2181  if (!CE) {
2182    Error(E, "shift amount must be an immediate");
2183    return MatchOperand_ParseFail;
2184  }
2185
2186  int64_t Val = CE->getValue();
2187  if (isASR) {
2188    // Shift amount must be in [1,32]
2189    if (Val < 1 || Val > 32) {
2190      Error(E, "'asr' shift amount must be in range [1,32]");
2191      return MatchOperand_ParseFail;
2192    }
2193    // asr #32 encoded as asr #0.
2194    if (Val == 32) Val = 0;
2195  } else {
2196    // Shift amount must be in [1,32]
2197    if (Val < 0 || Val > 31) {
2198      Error(E, "'lsr' shift amount must be in range [0,31]");
2199      return MatchOperand_ParseFail;
2200    }
2201  }
2202
2203  E = Parser.getTok().getLoc();
2204  Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E));
2205
2206  return MatchOperand_Success;
2207}
2208
2209/// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
2210/// of instructions. Legal values are:
2211///     ror #n  'n' in {0, 8, 16, 24}
2212ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2213parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2214  const AsmToken &Tok = Parser.getTok();
2215  SMLoc S = Tok.getLoc();
2216  if (Tok.isNot(AsmToken::Identifier)) {
2217    Error(S, "rotate operator 'ror' expected");
2218    return MatchOperand_ParseFail;
2219  }
2220  StringRef ShiftName = Tok.getString();
2221  if (ShiftName != "ror" && ShiftName != "ROR") {
2222    Error(S, "rotate operator 'ror' expected");
2223    return MatchOperand_ParseFail;
2224  }
2225  Parser.Lex(); // Eat the operator.
2226
2227  // A '#' and a rotate amount.
2228  if (Parser.getTok().isNot(AsmToken::Hash)) {
2229    Error(Parser.getTok().getLoc(), "'#' expected");
2230    return MatchOperand_ParseFail;
2231  }
2232  Parser.Lex(); // Eat hash token.
2233
2234  const MCExpr *ShiftAmount;
2235  SMLoc E = Parser.getTok().getLoc();
2236  if (getParser().ParseExpression(ShiftAmount)) {
2237    Error(E, "malformed rotate expression");
2238    return MatchOperand_ParseFail;
2239  }
2240  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
2241  if (!CE) {
2242    Error(E, "rotate amount must be an immediate");
2243    return MatchOperand_ParseFail;
2244  }
2245
2246  int64_t Val = CE->getValue();
2247  // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
2248  // normally, zero is represented in asm by omitting the rotate operand
2249  // entirely.
2250  if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
2251    Error(E, "'ror' rotate amount must be 8, 16, or 24");
2252    return MatchOperand_ParseFail;
2253  }
2254
2255  E = Parser.getTok().getLoc();
2256  Operands.push_back(ARMOperand::CreateRotImm(Val, S, E));
2257
2258  return MatchOperand_Success;
2259}
2260
2261ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2262parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2263  SMLoc S = Parser.getTok().getLoc();
2264  // The bitfield descriptor is really two operands, the LSB and the width.
2265  if (Parser.getTok().isNot(AsmToken::Hash)) {
2266    Error(Parser.getTok().getLoc(), "'#' expected");
2267    return MatchOperand_ParseFail;
2268  }
2269  Parser.Lex(); // Eat hash token.
2270
2271  const MCExpr *LSBExpr;
2272  SMLoc E = Parser.getTok().getLoc();
2273  if (getParser().ParseExpression(LSBExpr)) {
2274    Error(E, "malformed immediate expression");
2275    return MatchOperand_ParseFail;
2276  }
2277  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
2278  if (!CE) {
2279    Error(E, "'lsb' operand must be an immediate");
2280    return MatchOperand_ParseFail;
2281  }
2282
2283  int64_t LSB = CE->getValue();
2284  // The LSB must be in the range [0,31]
2285  if (LSB < 0 || LSB > 31) {
2286    Error(E, "'lsb' operand must be in the range [0,31]");
2287    return MatchOperand_ParseFail;
2288  }
2289  E = Parser.getTok().getLoc();
2290
2291  // Expect another immediate operand.
2292  if (Parser.getTok().isNot(AsmToken::Comma)) {
2293    Error(Parser.getTok().getLoc(), "too few operands");
2294    return MatchOperand_ParseFail;
2295  }
2296  Parser.Lex(); // Eat hash token.
2297  if (Parser.getTok().isNot(AsmToken::Hash)) {
2298    Error(Parser.getTok().getLoc(), "'#' expected");
2299    return MatchOperand_ParseFail;
2300  }
2301  Parser.Lex(); // Eat hash token.
2302
2303  const MCExpr *WidthExpr;
2304  if (getParser().ParseExpression(WidthExpr)) {
2305    Error(E, "malformed immediate expression");
2306    return MatchOperand_ParseFail;
2307  }
2308  CE = dyn_cast<MCConstantExpr>(WidthExpr);
2309  if (!CE) {
2310    Error(E, "'width' operand must be an immediate");
2311    return MatchOperand_ParseFail;
2312  }
2313
2314  int64_t Width = CE->getValue();
2315  // The LSB must be in the range [1,32-lsb]
2316  if (Width < 1 || Width > 32 - LSB) {
2317    Error(E, "'width' operand must be in the range [1,32-lsb]");
2318    return MatchOperand_ParseFail;
2319  }
2320  E = Parser.getTok().getLoc();
2321
2322  Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E));
2323
2324  return MatchOperand_Success;
2325}
2326
2327ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2328parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2329  // Check for a post-index addressing register operand. Specifically:
2330  // postidx_reg := '+' register {, shift}
2331  //              | '-' register {, shift}
2332  //              | register {, shift}
2333
2334  // This method must return MatchOperand_NoMatch without consuming any tokens
2335  // in the case where there is no match, as other alternatives take other
2336  // parse methods.
2337  AsmToken Tok = Parser.getTok();
2338  SMLoc S = Tok.getLoc();
2339  bool haveEaten = false;
2340  bool isAdd = true;
2341  int Reg = -1;
2342  if (Tok.is(AsmToken::Plus)) {
2343    Parser.Lex(); // Eat the '+' token.
2344    haveEaten = true;
2345  } else if (Tok.is(AsmToken::Minus)) {
2346    Parser.Lex(); // Eat the '-' token.
2347    isAdd = false;
2348    haveEaten = true;
2349  }
2350  if (Parser.getTok().is(AsmToken::Identifier))
2351    Reg = tryParseRegister();
2352  if (Reg == -1) {
2353    if (!haveEaten)
2354      return MatchOperand_NoMatch;
2355    Error(Parser.getTok().getLoc(), "register expected");
2356    return MatchOperand_ParseFail;
2357  }
2358  SMLoc E = Parser.getTok().getLoc();
2359
2360  ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
2361  unsigned ShiftImm = 0;
2362  if (Parser.getTok().is(AsmToken::Comma)) {
2363    Parser.Lex(); // Eat the ','.
2364    if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
2365      return MatchOperand_ParseFail;
2366  }
2367
2368  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
2369                                                  ShiftImm, S, E));
2370
2371  return MatchOperand_Success;
2372}
2373
2374ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2375parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2376  // Check for a post-index addressing register operand. Specifically:
2377  // am3offset := '+' register
2378  //              | '-' register
2379  //              | register
2380  //              | # imm
2381  //              | # + imm
2382  //              | # - imm
2383
2384  // This method must return MatchOperand_NoMatch without consuming any tokens
2385  // in the case where there is no match, as other alternatives take other
2386  // parse methods.
2387  AsmToken Tok = Parser.getTok();
2388  SMLoc S = Tok.getLoc();
2389
2390  // Do immediates first, as we always parse those if we have a '#'.
2391  if (Parser.getTok().is(AsmToken::Hash)) {
2392    Parser.Lex(); // Eat the '#'.
2393    // Explicitly look for a '-', as we need to encode negative zero
2394    // differently.
2395    bool isNegative = Parser.getTok().is(AsmToken::Minus);
2396    const MCExpr *Offset;
2397    if (getParser().ParseExpression(Offset))
2398      return MatchOperand_ParseFail;
2399    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
2400    if (!CE) {
2401      Error(S, "constant expression expected");
2402      return MatchOperand_ParseFail;
2403    }
2404    SMLoc E = Tok.getLoc();
2405    // Negative zero is encoded as the flag value INT32_MIN.
2406    int32_t Val = CE->getValue();
2407    if (isNegative && Val == 0)
2408      Val = INT32_MIN;
2409
2410    Operands.push_back(
2411      ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
2412
2413    return MatchOperand_Success;
2414  }
2415
2416
2417  bool haveEaten = false;
2418  bool isAdd = true;
2419  int Reg = -1;
2420  if (Tok.is(AsmToken::Plus)) {
2421    Parser.Lex(); // Eat the '+' token.
2422    haveEaten = true;
2423  } else if (Tok.is(AsmToken::Minus)) {
2424    Parser.Lex(); // Eat the '-' token.
2425    isAdd = false;
2426    haveEaten = true;
2427  }
2428  if (Parser.getTok().is(AsmToken::Identifier))
2429    Reg = tryParseRegister();
2430  if (Reg == -1) {
2431    if (!haveEaten)
2432      return MatchOperand_NoMatch;
2433    Error(Parser.getTok().getLoc(), "register expected");
2434    return MatchOperand_ParseFail;
2435  }
2436  SMLoc E = Parser.getTok().getLoc();
2437
2438  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
2439                                                  0, S, E));
2440
2441  return MatchOperand_Success;
2442}
2443
2444/// cvtT2LdrdPre - Convert parsed operands to MCInst.
2445/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2446/// when they refer multiple MIOperands inside a single one.
2447bool ARMAsmParser::
2448cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
2449             const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2450  // Rt, Rt2
2451  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2452  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2453  // Create a writeback register dummy placeholder.
2454  Inst.addOperand(MCOperand::CreateReg(0));
2455  // addr
2456  ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
2457  // pred
2458  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2459  return true;
2460}
2461
2462/// cvtT2StrdPre - Convert parsed operands to MCInst.
2463/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2464/// when they refer multiple MIOperands inside a single one.
2465bool ARMAsmParser::
2466cvtT2StrdPre(MCInst &Inst, unsigned Opcode,
2467             const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2468  // Create a writeback register dummy placeholder.
2469  Inst.addOperand(MCOperand::CreateReg(0));
2470  // Rt, Rt2
2471  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2472  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2473  // addr
2474  ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
2475  // pred
2476  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2477  return true;
2478}
2479
2480/// cvtLdWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
2481/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2482/// when they refer multiple MIOperands inside a single one.
2483bool ARMAsmParser::
2484cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
2485                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2486  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2487
2488  // Create a writeback register dummy placeholder.
2489  Inst.addOperand(MCOperand::CreateImm(0));
2490
2491  ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
2492  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2493  return true;
2494}
2495
2496/// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
2497/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2498/// when they refer multiple MIOperands inside a single one.
2499bool ARMAsmParser::
2500cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
2501                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2502  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2503
2504  // Create a writeback register dummy placeholder.
2505  Inst.addOperand(MCOperand::CreateImm(0));
2506
2507  ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
2508  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2509  return true;
2510}
2511
2512/// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
2513/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2514/// when they refer multiple MIOperands inside a single one.
2515bool ARMAsmParser::
2516cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
2517                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2518  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2519
2520  // Create a writeback register dummy placeholder.
2521  Inst.addOperand(MCOperand::CreateImm(0));
2522
2523  ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
2524  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2525  return true;
2526}
2527
2528
2529/// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
2530/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2531/// when they refer multiple MIOperands inside a single one.
2532bool ARMAsmParser::
2533cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
2534                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2535  // Create a writeback register dummy placeholder.
2536  Inst.addOperand(MCOperand::CreateImm(0));
2537  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2538  ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
2539  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2540  return true;
2541}
2542
2543/// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
2544/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2545/// when they refer multiple MIOperands inside a single one.
2546bool ARMAsmParser::
2547cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
2548                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2549  // Create a writeback register dummy placeholder.
2550  Inst.addOperand(MCOperand::CreateImm(0));
2551  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2552  ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
2553  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2554  return true;
2555}
2556
2557/// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
2558/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2559/// when they refer multiple MIOperands inside a single one.
2560bool ARMAsmParser::
2561cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
2562                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2563  // Create a writeback register dummy placeholder.
2564  Inst.addOperand(MCOperand::CreateImm(0));
2565  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2566  ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
2567  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2568  return true;
2569}
2570
2571/// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst.
2572/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2573/// when they refer multiple MIOperands inside a single one.
2574bool ARMAsmParser::
2575cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
2576                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2577  // Rt
2578  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2579  // Create a writeback register dummy placeholder.
2580  Inst.addOperand(MCOperand::CreateImm(0));
2581  // addr
2582  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2583  // offset
2584  ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
2585  // pred
2586  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2587  return true;
2588}
2589
2590/// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst.
2591/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2592/// when they refer multiple MIOperands inside a single one.
2593bool ARMAsmParser::
2594cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
2595                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2596  // Rt
2597  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2598  // Create a writeback register dummy placeholder.
2599  Inst.addOperand(MCOperand::CreateImm(0));
2600  // addr
2601  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2602  // offset
2603  ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
2604  // pred
2605  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2606  return true;
2607}
2608
2609/// cvtStExtTWriteBackImm - Convert parsed operands to MCInst.
2610/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2611/// when they refer multiple MIOperands inside a single one.
2612bool ARMAsmParser::
2613cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
2614                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2615  // Create a writeback register dummy placeholder.
2616  Inst.addOperand(MCOperand::CreateImm(0));
2617  // Rt
2618  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2619  // addr
2620  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2621  // offset
2622  ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
2623  // pred
2624  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2625  return true;
2626}
2627
2628/// cvtStExtTWriteBackReg - Convert parsed operands to MCInst.
2629/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2630/// when they refer multiple MIOperands inside a single one.
2631bool ARMAsmParser::
2632cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
2633                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2634  // Create a writeback register dummy placeholder.
2635  Inst.addOperand(MCOperand::CreateImm(0));
2636  // Rt
2637  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2638  // addr
2639  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2640  // offset
2641  ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
2642  // pred
2643  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2644  return true;
2645}
2646
2647/// cvtLdrdPre - Convert parsed operands to MCInst.
2648/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2649/// when they refer multiple MIOperands inside a single one.
2650bool ARMAsmParser::
2651cvtLdrdPre(MCInst &Inst, unsigned Opcode,
2652           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2653  // Rt, Rt2
2654  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2655  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2656  // Create a writeback register dummy placeholder.
2657  Inst.addOperand(MCOperand::CreateImm(0));
2658  // addr
2659  ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
2660  // pred
2661  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2662  return true;
2663}
2664
2665/// cvtStrdPre - Convert parsed operands to MCInst.
2666/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2667/// when they refer multiple MIOperands inside a single one.
2668bool ARMAsmParser::
2669cvtStrdPre(MCInst &Inst, unsigned Opcode,
2670           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2671  // Create a writeback register dummy placeholder.
2672  Inst.addOperand(MCOperand::CreateImm(0));
2673  // Rt, Rt2
2674  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2675  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2676  // addr
2677  ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
2678  // pred
2679  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2680  return true;
2681}
2682
2683/// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
2684/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2685/// when they refer multiple MIOperands inside a single one.
2686bool ARMAsmParser::
2687cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
2688                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2689  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2690  // Create a writeback register dummy placeholder.
2691  Inst.addOperand(MCOperand::CreateImm(0));
2692  ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
2693  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2694  return true;
2695}
2696
2697/// cvtThumbMultiple- Convert parsed operands to MCInst.
2698/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2699/// when they refer multiple MIOperands inside a single one.
2700bool ARMAsmParser::
2701cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
2702           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2703  // The second source operand must be the same register as the destination
2704  // operand.
2705  if (Operands.size() == 6 &&
2706      (((ARMOperand*)Operands[3])->getReg() !=
2707       ((ARMOperand*)Operands[5])->getReg()) &&
2708      (((ARMOperand*)Operands[3])->getReg() !=
2709       ((ARMOperand*)Operands[4])->getReg())) {
2710    Error(Operands[3]->getStartLoc(),
2711          "destination register must match source register");
2712    return false;
2713  }
2714  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2715  ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
2716  ((ARMOperand*)Operands[4])->addRegOperands(Inst, 1);
2717  // If we have a three-operand form, use that, else the second source operand
2718  // is just the destination operand again.
2719  if (Operands.size() == 6)
2720    ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
2721  else
2722    Inst.addOperand(Inst.getOperand(0));
2723  ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
2724
2725  return true;
2726}
2727
2728/// Parse an ARM memory expression, return false if successful else return true
2729/// or an error.  The first token must be a '[' when called.
2730bool ARMAsmParser::
2731parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2732  SMLoc S, E;
2733  assert(Parser.getTok().is(AsmToken::LBrac) &&
2734         "Token is not a Left Bracket");
2735  S = Parser.getTok().getLoc();
2736  Parser.Lex(); // Eat left bracket token.
2737
2738  const AsmToken &BaseRegTok = Parser.getTok();
2739  int BaseRegNum = tryParseRegister();
2740  if (BaseRegNum == -1)
2741    return Error(BaseRegTok.getLoc(), "register expected");
2742
2743  // The next token must either be a comma or a closing bracket.
2744  const AsmToken &Tok = Parser.getTok();
2745  if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac))
2746    return Error(Tok.getLoc(), "malformed memory operand");
2747
2748  if (Tok.is(AsmToken::RBrac)) {
2749    E = Tok.getLoc();
2750    Parser.Lex(); // Eat right bracket token.
2751
2752    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
2753                                             0, false, S, E));
2754
2755    return false;
2756  }
2757
2758  assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!");
2759  Parser.Lex(); // Eat the comma.
2760
2761  // If we have a '#' it's an immediate offset, else assume it's a register
2762  // offset.
2763  if (Parser.getTok().is(AsmToken::Hash)) {
2764    Parser.Lex(); // Eat the '#'.
2765    E = Parser.getTok().getLoc();
2766
2767    bool isNegative = getParser().getTok().is(AsmToken::Minus);
2768    const MCExpr *Offset;
2769    if (getParser().ParseExpression(Offset))
2770     return true;
2771
2772    // The expression has to be a constant. Memory references with relocations
2773    // don't come through here, as they use the <label> forms of the relevant
2774    // instructions.
2775    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
2776    if (!CE)
2777      return Error (E, "constant expression expected");
2778
2779    // If the constant was #-0, represent it as INT32_MIN.
2780    int32_t Val = CE->getValue();
2781    if (isNegative && Val == 0)
2782      CE = MCConstantExpr::Create(INT32_MIN, getContext());
2783
2784    // Now we should have the closing ']'
2785    E = Parser.getTok().getLoc();
2786    if (Parser.getTok().isNot(AsmToken::RBrac))
2787      return Error(E, "']' expected");
2788    Parser.Lex(); // Eat right bracket token.
2789
2790    // Don't worry about range checking the value here. That's handled by
2791    // the is*() predicates.
2792    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
2793                                             ARM_AM::no_shift, 0, false, S,E));
2794
2795    // If there's a pre-indexing writeback marker, '!', just add it as a token
2796    // operand.
2797    if (Parser.getTok().is(AsmToken::Exclaim)) {
2798      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
2799      Parser.Lex(); // Eat the '!'.
2800    }
2801
2802    return false;
2803  }
2804
2805  // The register offset is optionally preceded by a '+' or '-'
2806  bool isNegative = false;
2807  if (Parser.getTok().is(AsmToken::Minus)) {
2808    isNegative = true;
2809    Parser.Lex(); // Eat the '-'.
2810  } else if (Parser.getTok().is(AsmToken::Plus)) {
2811    // Nothing to do.
2812    Parser.Lex(); // Eat the '+'.
2813  }
2814
2815  E = Parser.getTok().getLoc();
2816  int OffsetRegNum = tryParseRegister();
2817  if (OffsetRegNum == -1)
2818    return Error(E, "register expected");
2819
2820  // If there's a shift operator, handle it.
2821  ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
2822  unsigned ShiftImm = 0;
2823  if (Parser.getTok().is(AsmToken::Comma)) {
2824    Parser.Lex(); // Eat the ','.
2825    if (parseMemRegOffsetShift(ShiftType, ShiftImm))
2826      return true;
2827  }
2828
2829  // Now we should have the closing ']'
2830  E = Parser.getTok().getLoc();
2831  if (Parser.getTok().isNot(AsmToken::RBrac))
2832    return Error(E, "']' expected");
2833  Parser.Lex(); // Eat right bracket token.
2834
2835  Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
2836                                           ShiftType, ShiftImm, isNegative,
2837                                           S, E));
2838
2839  // If there's a pre-indexing writeback marker, '!', just add it as a token
2840  // operand.
2841  if (Parser.getTok().is(AsmToken::Exclaim)) {
2842    Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
2843    Parser.Lex(); // Eat the '!'.
2844  }
2845
2846  return false;
2847}
2848
2849/// parseMemRegOffsetShift - one of these two:
2850///   ( lsl | lsr | asr | ror ) , # shift_amount
2851///   rrx
2852/// return true if it parses a shift otherwise it returns false.
2853bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
2854                                          unsigned &Amount) {
2855  SMLoc Loc = Parser.getTok().getLoc();
2856  const AsmToken &Tok = Parser.getTok();
2857  if (Tok.isNot(AsmToken::Identifier))
2858    return true;
2859  StringRef ShiftName = Tok.getString();
2860  if (ShiftName == "lsl" || ShiftName == "LSL")
2861    St = ARM_AM::lsl;
2862  else if (ShiftName == "lsr" || ShiftName == "LSR")
2863    St = ARM_AM::lsr;
2864  else if (ShiftName == "asr" || ShiftName == "ASR")
2865    St = ARM_AM::asr;
2866  else if (ShiftName == "ror" || ShiftName == "ROR")
2867    St = ARM_AM::ror;
2868  else if (ShiftName == "rrx" || ShiftName == "RRX")
2869    St = ARM_AM::rrx;
2870  else
2871    return Error(Loc, "illegal shift operator");
2872  Parser.Lex(); // Eat shift type token.
2873
2874  // rrx stands alone.
2875  Amount = 0;
2876  if (St != ARM_AM::rrx) {
2877    Loc = Parser.getTok().getLoc();
2878    // A '#' and a shift amount.
2879    const AsmToken &HashTok = Parser.getTok();
2880    if (HashTok.isNot(AsmToken::Hash))
2881      return Error(HashTok.getLoc(), "'#' expected");
2882    Parser.Lex(); // Eat hash token.
2883
2884    const MCExpr *Expr;
2885    if (getParser().ParseExpression(Expr))
2886      return true;
2887    // Range check the immediate.
2888    // lsl, ror: 0 <= imm <= 31
2889    // lsr, asr: 0 <= imm <= 32
2890    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2891    if (!CE)
2892      return Error(Loc, "shift amount must be an immediate");
2893    int64_t Imm = CE->getValue();
2894    if (Imm < 0 ||
2895        ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
2896        ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
2897      return Error(Loc, "immediate shift value out of range");
2898    Amount = Imm;
2899  }
2900
2901  return false;
2902}
2903
2904/// Parse a arm instruction operand.  For now this parses the operand regardless
2905/// of the mnemonic.
2906bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
2907                                StringRef Mnemonic) {
2908  SMLoc S, E;
2909
2910  // Check if the current operand has a custom associated parser, if so, try to
2911  // custom parse the operand, or fallback to the general approach.
2912  OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
2913  if (ResTy == MatchOperand_Success)
2914    return false;
2915  // If there wasn't a custom match, try the generic matcher below. Otherwise,
2916  // there was a match, but an error occurred, in which case, just return that
2917  // the operand parsing failed.
2918  if (ResTy == MatchOperand_ParseFail)
2919    return true;
2920
2921  switch (getLexer().getKind()) {
2922  default:
2923    Error(Parser.getTok().getLoc(), "unexpected token in operand");
2924    return true;
2925  case AsmToken::Identifier: {
2926    if (!tryParseRegisterWithWriteBack(Operands))
2927      return false;
2928    int Res = tryParseShiftRegister(Operands);
2929    if (Res == 0) // success
2930      return false;
2931    else if (Res == -1) // irrecoverable error
2932      return true;
2933
2934    // Fall though for the Identifier case that is not a register or a
2935    // special name.
2936  }
2937  case AsmToken::Integer: // things like 1f and 2b as a branch targets
2938  case AsmToken::Dot: {   // . as a branch target
2939    // This was not a register so parse other operands that start with an
2940    // identifier (like labels) as expressions and create them as immediates.
2941    const MCExpr *IdVal;
2942    S = Parser.getTok().getLoc();
2943    if (getParser().ParseExpression(IdVal))
2944      return true;
2945    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2946    Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
2947    return false;
2948  }
2949  case AsmToken::LBrac:
2950    return parseMemory(Operands);
2951  case AsmToken::LCurly:
2952    return parseRegisterList(Operands);
2953  case AsmToken::Hash: {
2954    // #42 -> immediate.
2955    // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
2956    S = Parser.getTok().getLoc();
2957    Parser.Lex();
2958    bool isNegative = Parser.getTok().is(AsmToken::Minus);
2959    const MCExpr *ImmVal;
2960    if (getParser().ParseExpression(ImmVal))
2961      return true;
2962    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
2963    if (!CE) {
2964      Error(S, "constant expression expected");
2965      return MatchOperand_ParseFail;
2966    }
2967    int32_t Val = CE->getValue();
2968    if (isNegative && Val == 0)
2969      ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
2970    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2971    Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
2972    return false;
2973  }
2974  case AsmToken::Colon: {
2975    // ":lower16:" and ":upper16:" expression prefixes
2976    // FIXME: Check it's an expression prefix,
2977    // e.g. (FOO - :lower16:BAR) isn't legal.
2978    ARMMCExpr::VariantKind RefKind;
2979    if (parsePrefix(RefKind))
2980      return true;
2981
2982    const MCExpr *SubExprVal;
2983    if (getParser().ParseExpression(SubExprVal))
2984      return true;
2985
2986    const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
2987                                                   getContext());
2988    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2989    Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
2990    return false;
2991  }
2992  }
2993}
2994
2995// parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
2996//  :lower16: and :upper16:.
2997bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
2998  RefKind = ARMMCExpr::VK_ARM_None;
2999
3000  // :lower16: and :upper16: modifiers
3001  assert(getLexer().is(AsmToken::Colon) && "expected a :");
3002  Parser.Lex(); // Eat ':'
3003
3004  if (getLexer().isNot(AsmToken::Identifier)) {
3005    Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
3006    return true;
3007  }
3008
3009  StringRef IDVal = Parser.getTok().getIdentifier();
3010  if (IDVal == "lower16") {
3011    RefKind = ARMMCExpr::VK_ARM_LO16;
3012  } else if (IDVal == "upper16") {
3013    RefKind = ARMMCExpr::VK_ARM_HI16;
3014  } else {
3015    Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
3016    return true;
3017  }
3018  Parser.Lex();
3019
3020  if (getLexer().isNot(AsmToken::Colon)) {
3021    Error(Parser.getTok().getLoc(), "unexpected token after prefix");
3022    return true;
3023  }
3024  Parser.Lex(); // Eat the last ':'
3025  return false;
3026}
3027
3028const MCExpr *
3029ARMAsmParser::applyPrefixToExpr(const MCExpr *E,
3030                                MCSymbolRefExpr::VariantKind Variant) {
3031  // Recurse over the given expression, rebuilding it to apply the given variant
3032  // to the leftmost symbol.
3033  if (Variant == MCSymbolRefExpr::VK_None)
3034    return E;
3035
3036  switch (E->getKind()) {
3037  case MCExpr::Target:
3038    llvm_unreachable("Can't handle target expr yet");
3039  case MCExpr::Constant:
3040    llvm_unreachable("Can't handle lower16/upper16 of constant yet");
3041
3042  case MCExpr::SymbolRef: {
3043    const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
3044
3045    if (SRE->getKind() != MCSymbolRefExpr::VK_None)
3046      return 0;
3047
3048    return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, getContext());
3049  }
3050
3051  case MCExpr::Unary:
3052    llvm_unreachable("Can't handle unary expressions yet");
3053
3054  case MCExpr::Binary: {
3055    const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
3056    const MCExpr *LHS = applyPrefixToExpr(BE->getLHS(), Variant);
3057    const MCExpr *RHS = BE->getRHS();
3058    if (!LHS)
3059      return 0;
3060
3061    return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, getContext());
3062  }
3063  }
3064
3065  assert(0 && "Invalid expression kind!");
3066  return 0;
3067}
3068
3069/// \brief Given a mnemonic, split out possible predication code and carry
3070/// setting letters to form a canonical mnemonic and flags.
3071//
3072// FIXME: Would be nice to autogen this.
3073// FIXME: This is a bit of a maze of special cases.
3074StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
3075                                      unsigned &PredicationCode,
3076                                      bool &CarrySetting,
3077                                      unsigned &ProcessorIMod,
3078                                      StringRef &ITMask) {
3079  PredicationCode = ARMCC::AL;
3080  CarrySetting = false;
3081  ProcessorIMod = 0;
3082
3083  // Ignore some mnemonics we know aren't predicated forms.
3084  //
3085  // FIXME: Would be nice to autogen this.
3086  if ((Mnemonic == "movs" && isThumb()) ||
3087      Mnemonic == "teq"   || Mnemonic == "vceq"   || Mnemonic == "svc"   ||
3088      Mnemonic == "mls"   || Mnemonic == "smmls"  || Mnemonic == "vcls"  ||
3089      Mnemonic == "vmls"  || Mnemonic == "vnmls"  || Mnemonic == "vacge" ||
3090      Mnemonic == "vcge"  || Mnemonic == "vclt"   || Mnemonic == "vacgt" ||
3091      Mnemonic == "vcgt"  || Mnemonic == "vcle"   || Mnemonic == "smlal" ||
3092      Mnemonic == "umaal" || Mnemonic == "umlal"  || Mnemonic == "vabal" ||
3093      Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal")
3094    return Mnemonic;
3095
3096  // First, split out any predication code. Ignore mnemonics we know aren't
3097  // predicated but do have a carry-set and so weren't caught above.
3098  if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
3099      Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
3100      Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
3101      Mnemonic != "sbcs" && Mnemonic != "rscs") {
3102    unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
3103      .Case("eq", ARMCC::EQ)
3104      .Case("ne", ARMCC::NE)
3105      .Case("hs", ARMCC::HS)
3106      .Case("cs", ARMCC::HS)
3107      .Case("lo", ARMCC::LO)
3108      .Case("cc", ARMCC::LO)
3109      .Case("mi", ARMCC::MI)
3110      .Case("pl", ARMCC::PL)
3111      .Case("vs", ARMCC::VS)
3112      .Case("vc", ARMCC::VC)
3113      .Case("hi", ARMCC::HI)
3114      .Case("ls", ARMCC::LS)
3115      .Case("ge", ARMCC::GE)
3116      .Case("lt", ARMCC::LT)
3117      .Case("gt", ARMCC::GT)
3118      .Case("le", ARMCC::LE)
3119      .Case("al", ARMCC::AL)
3120      .Default(~0U);
3121    if (CC != ~0U) {
3122      Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
3123      PredicationCode = CC;
3124    }
3125  }
3126
3127  // Next, determine if we have a carry setting bit. We explicitly ignore all
3128  // the instructions we know end in 's'.
3129  if (Mnemonic.endswith("s") &&
3130      !(Mnemonic == "cps" || Mnemonic == "mls" ||
3131        Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
3132        Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
3133        Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
3134        Mnemonic == "vrsqrts" || Mnemonic == "srs" ||
3135        (Mnemonic == "movs" && isThumb()))) {
3136    Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
3137    CarrySetting = true;
3138  }
3139
3140  // The "cps" instruction can have a interrupt mode operand which is glued into
3141  // the mnemonic. Check if this is the case, split it and parse the imod op
3142  if (Mnemonic.startswith("cps")) {
3143    // Split out any imod code.
3144    unsigned IMod =
3145      StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
3146      .Case("ie", ARM_PROC::IE)
3147      .Case("id", ARM_PROC::ID)
3148      .Default(~0U);
3149    if (IMod != ~0U) {
3150      Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
3151      ProcessorIMod = IMod;
3152    }
3153  }
3154
3155  // The "it" instruction has the condition mask on the end of the mnemonic.
3156  if (Mnemonic.startswith("it")) {
3157    ITMask = Mnemonic.slice(2, Mnemonic.size());
3158    Mnemonic = Mnemonic.slice(0, 2);
3159  }
3160
3161  return Mnemonic;
3162}
3163
3164/// \brief Given a canonical mnemonic, determine if the instruction ever allows
3165/// inclusion of carry set or predication code operands.
3166//
3167// FIXME: It would be nice to autogen this.
3168void ARMAsmParser::
3169getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
3170                      bool &CanAcceptPredicationCode) {
3171  if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
3172      Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
3173      Mnemonic == "smull" || Mnemonic == "add" || Mnemonic == "adc" ||
3174      Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
3175      Mnemonic == "umlal" || Mnemonic == "orr" || Mnemonic == "mvn" ||
3176      Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
3177      Mnemonic == "sbc" || Mnemonic == "umull" ||
3178      Mnemonic == "eor" || Mnemonic == "smlal" || Mnemonic == "neg" ||
3179      ((Mnemonic == "mov" || Mnemonic == "mla") && !isThumb())) {
3180    CanAcceptCarrySet = true;
3181  } else {
3182    CanAcceptCarrySet = false;
3183  }
3184
3185  if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
3186      Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
3187      Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
3188      Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
3189      Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "setend" ||
3190      (Mnemonic == "clrex" && !isThumb()) ||
3191      (Mnemonic == "nop" && isThumbOne()) ||
3192      ((Mnemonic == "pld" || Mnemonic == "pli" || Mnemonic == "pldw") &&
3193       !isThumb()) ||
3194      ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs")) &&
3195       !isThumb()) ||
3196      Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumbOne())) {
3197    CanAcceptPredicationCode = false;
3198  } else {
3199    CanAcceptPredicationCode = true;
3200  }
3201
3202  if (isThumb())
3203    if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
3204        Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
3205      CanAcceptPredicationCode = false;
3206}
3207
3208bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
3209                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3210  // FIXME: This is all horribly hacky. We really need a better way to deal
3211  // with optional operands like this in the matcher table.
3212
3213  // The 'mov' mnemonic is special. One variant has a cc_out operand, while
3214  // another does not. Specifically, the MOVW instruction does not. So we
3215  // special case it here and remove the defaulted (non-setting) cc_out
3216  // operand if that's the instruction we're trying to match.
3217  //
3218  // We do this as post-processing of the explicit operands rather than just
3219  // conditionally adding the cc_out in the first place because we need
3220  // to check the type of the parsed immediate operand.
3221  if (Mnemonic == "mov" && Operands.size() > 4 &&
3222      !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
3223      static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
3224      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
3225    return true;
3226
3227  // Register-register 'add' for thumb does not have a cc_out operand
3228  // when there are only two register operands.
3229  if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
3230      static_cast<ARMOperand*>(Operands[3])->isReg() &&
3231      static_cast<ARMOperand*>(Operands[4])->isReg() &&
3232      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
3233    return true;
3234  // Register-register 'add' for thumb does not have a cc_out operand
3235  // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
3236  // have to check the immediate range here since Thumb2 has a variant
3237  // that can handle a different range and has a cc_out operand.
3238  if (isThumb() && Mnemonic == "add" && Operands.size() == 6 &&
3239      static_cast<ARMOperand*>(Operands[3])->isReg() &&
3240      static_cast<ARMOperand*>(Operands[4])->isReg() &&
3241      static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
3242      static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
3243      (static_cast<ARMOperand*>(Operands[5])->isReg() ||
3244       static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
3245    return true;
3246  // For Thumb2, add immediate does not have a cc_out operand for the
3247  // imm0_4096 variant. That's the least-preferred variant when
3248  // selecting via the generic "add" mnemonic, so to know that we
3249  // should remove the cc_out operand, we have to explicitly check that
3250  // it's not one of the other variants. Ugh.
3251  if (isThumbTwo() && Mnemonic == "add" && Operands.size() == 6 &&
3252      static_cast<ARMOperand*>(Operands[3])->isReg() &&
3253      static_cast<ARMOperand*>(Operands[4])->isReg() &&
3254      static_cast<ARMOperand*>(Operands[5])->isImm()) {
3255    // Nest conditions rather than one big 'if' statement for readability.
3256    //
3257    // If either register is a high reg, it's either one of the SP
3258    // variants (handled above) or a 32-bit encoding, so we just
3259    // check against T3.
3260    if ((!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
3261         !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg())) &&
3262        static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
3263      return false;
3264    // If both registers are low, we're in an IT block, and the immediate is
3265    // in range, we should use encoding T1 instead, which has a cc_out.
3266    if (inITBlock() &&
3267        isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
3268        isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
3269        static_cast<ARMOperand*>(Operands[5])->isImm0_7())
3270      return false;
3271
3272    // Otherwise, we use encoding T4, which does not have a cc_out
3273    // operand.
3274    return true;
3275  }
3276
3277
3278  // Register-register 'add/sub' for thumb does not have a cc_out operand
3279  // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
3280  // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
3281  // right, this will result in better diagnostics (which operand is off)
3282  // anyway.
3283  if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
3284      (Operands.size() == 5 || Operands.size() == 6) &&
3285      static_cast<ARMOperand*>(Operands[3])->isReg() &&
3286      static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
3287      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
3288    return true;
3289
3290  return false;
3291}
3292
3293/// Parse an arm instruction mnemonic followed by its operands.
3294bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
3295                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3296  // Create the leading tokens for the mnemonic, split by '.' characters.
3297  size_t Start = 0, Next = Name.find('.');
3298  StringRef Mnemonic = Name.slice(Start, Next);
3299
3300  // Split out the predication code and carry setting flag from the mnemonic.
3301  unsigned PredicationCode;
3302  unsigned ProcessorIMod;
3303  bool CarrySetting;
3304  StringRef ITMask;
3305  Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
3306                           ProcessorIMod, ITMask);
3307
3308  // In Thumb1, only the branch (B) instruction can be predicated.
3309  if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
3310    Parser.EatToEndOfStatement();
3311    return Error(NameLoc, "conditional execution not supported in Thumb1");
3312  }
3313
3314  Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
3315
3316  // Handle the IT instruction ITMask. Convert it to a bitmask. This
3317  // is the mask as it will be for the IT encoding if the conditional
3318  // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
3319  // where the conditional bit0 is zero, the instruction post-processing
3320  // will adjust the mask accordingly.
3321  if (Mnemonic == "it") {
3322    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
3323    if (ITMask.size() > 3) {
3324      Parser.EatToEndOfStatement();
3325      return Error(Loc, "too many conditions on IT instruction");
3326    }
3327    unsigned Mask = 8;
3328    for (unsigned i = ITMask.size(); i != 0; --i) {
3329      char pos = ITMask[i - 1];
3330      if (pos != 't' && pos != 'e') {
3331        Parser.EatToEndOfStatement();
3332        return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
3333      }
3334      Mask >>= 1;
3335      if (ITMask[i - 1] == 't')
3336        Mask |= 8;
3337    }
3338    Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
3339  }
3340
3341  // FIXME: This is all a pretty gross hack. We should automatically handle
3342  // optional operands like this via tblgen.
3343
3344  // Next, add the CCOut and ConditionCode operands, if needed.
3345  //
3346  // For mnemonics which can ever incorporate a carry setting bit or predication
3347  // code, our matching model involves us always generating CCOut and
3348  // ConditionCode operands to match the mnemonic "as written" and then we let
3349  // the matcher deal with finding the right instruction or generating an
3350  // appropriate error.
3351  bool CanAcceptCarrySet, CanAcceptPredicationCode;
3352  getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
3353
3354  // If we had a carry-set on an instruction that can't do that, issue an
3355  // error.
3356  if (!CanAcceptCarrySet && CarrySetting) {
3357    Parser.EatToEndOfStatement();
3358    return Error(NameLoc, "instruction '" + Mnemonic +
3359                 "' can not set flags, but 's' suffix specified");
3360  }
3361  // If we had a predication code on an instruction that can't do that, issue an
3362  // error.
3363  if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
3364    Parser.EatToEndOfStatement();
3365    return Error(NameLoc, "instruction '" + Mnemonic +
3366                 "' is not predicable, but condition code specified");
3367  }
3368
3369  // Add the carry setting operand, if necessary.
3370  if (CanAcceptCarrySet) {
3371    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
3372    Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
3373                                               Loc));
3374  }
3375
3376  // Add the predication code operand, if necessary.
3377  if (CanAcceptPredicationCode) {
3378    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
3379                                      CarrySetting);
3380    Operands.push_back(ARMOperand::CreateCondCode(
3381                         ARMCC::CondCodes(PredicationCode), Loc));
3382  }
3383
3384  // Add the processor imod operand, if necessary.
3385  if (ProcessorIMod) {
3386    Operands.push_back(ARMOperand::CreateImm(
3387          MCConstantExpr::Create(ProcessorIMod, getContext()),
3388                                 NameLoc, NameLoc));
3389  }
3390
3391  // Add the remaining tokens in the mnemonic.
3392  while (Next != StringRef::npos) {
3393    Start = Next;
3394    Next = Name.find('.', Start + 1);
3395    StringRef ExtraToken = Name.slice(Start, Next);
3396
3397    // For now, we're only parsing Thumb1 (for the most part), so
3398    // just ignore ".n" qualifiers. We'll use them to restrict
3399    // matching when we do Thumb2.
3400    if (ExtraToken != ".n") {
3401      SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
3402      Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
3403    }
3404  }
3405
3406  // Read the remaining operands.
3407  if (getLexer().isNot(AsmToken::EndOfStatement)) {
3408    // Read the first operand.
3409    if (parseOperand(Operands, Mnemonic)) {
3410      Parser.EatToEndOfStatement();
3411      return true;
3412    }
3413
3414    while (getLexer().is(AsmToken::Comma)) {
3415      Parser.Lex();  // Eat the comma.
3416
3417      // Parse and remember the operand.
3418      if (parseOperand(Operands, Mnemonic)) {
3419        Parser.EatToEndOfStatement();
3420        return true;
3421      }
3422    }
3423  }
3424
3425  if (getLexer().isNot(AsmToken::EndOfStatement)) {
3426    Parser.EatToEndOfStatement();
3427    return TokError("unexpected token in argument list");
3428  }
3429
3430  Parser.Lex(); // Consume the EndOfStatement
3431
3432  // Some instructions, mostly Thumb, have forms for the same mnemonic that
3433  // do and don't have a cc_out optional-def operand. With some spot-checks
3434  // of the operand list, we can figure out which variant we're trying to
3435  // parse and adjust accordingly before actually matching. We shouldn't ever
3436  // try to remove a cc_out operand that was explicitly set on the the
3437  // mnemonic, of course (CarrySetting == true). Reason number #317 the
3438  // table driven matcher doesn't fit well with the ARM instruction set.
3439  if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
3440    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
3441    Operands.erase(Operands.begin() + 1);
3442    delete Op;
3443  }
3444
3445  // ARM mode 'blx' need special handling, as the register operand version
3446  // is predicable, but the label operand version is not. So, we can't rely
3447  // on the Mnemonic based checking to correctly figure out when to put
3448  // a CondCode operand in the list. If we're trying to match the label
3449  // version, remove the CondCode operand here.
3450  if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
3451      static_cast<ARMOperand*>(Operands[2])->isImm()) {
3452    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
3453    Operands.erase(Operands.begin() + 1);
3454    delete Op;
3455  }
3456
3457  // The vector-compare-to-zero instructions have a literal token "#0" at
3458  // the end that comes to here as an immediate operand. Convert it to a
3459  // token to play nicely with the matcher.
3460  if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" ||
3461      Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 &&
3462      static_cast<ARMOperand*>(Operands[5])->isImm()) {
3463    ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
3464    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
3465    if (CE && CE->getValue() == 0) {
3466      Operands.erase(Operands.begin() + 5);
3467      Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
3468      delete Op;
3469    }
3470  }
3471  // Similarly, the Thumb1 "RSB" instruction has a literal "#0" on the
3472  // end. Convert it to a token here.
3473  if (Mnemonic == "rsb" && isThumb() && Operands.size() == 6 &&
3474      static_cast<ARMOperand*>(Operands[5])->isImm()) {
3475    ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
3476    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
3477    if (CE && CE->getValue() == 0) {
3478      Operands.erase(Operands.begin() + 5);
3479      Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
3480      delete Op;
3481    }
3482  }
3483
3484  return false;
3485}
3486
3487// Validate context-sensitive operand constraints.
3488
3489// return 'true' if register list contains non-low GPR registers,
3490// 'false' otherwise. If Reg is in the register list or is HiReg, set
3491// 'containsReg' to true.
3492static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
3493                                 unsigned HiReg, bool &containsReg) {
3494  containsReg = false;
3495  for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
3496    unsigned OpReg = Inst.getOperand(i).getReg();
3497    if (OpReg == Reg)
3498      containsReg = true;
3499    // Anything other than a low register isn't legal here.
3500    if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
3501      return true;
3502  }
3503  return false;
3504}
3505
3506// Check if the specified regisgter is in the register list of the inst,
3507// starting at the indicated operand number.
3508static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
3509  for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
3510    unsigned OpReg = Inst.getOperand(i).getReg();
3511    if (OpReg == Reg)
3512      return true;
3513  }
3514  return false;
3515}
3516
3517// FIXME: We would really prefer to have MCInstrInfo (the wrapper around
3518// the ARMInsts array) instead. Getting that here requires awkward
3519// API changes, though. Better way?
3520namespace llvm {
3521extern MCInstrDesc ARMInsts[];
3522}
3523static MCInstrDesc &getInstDesc(unsigned Opcode) {
3524  return ARMInsts[Opcode];
3525}
3526
3527// FIXME: We would really like to be able to tablegen'erate this.
3528bool ARMAsmParser::
3529validateInstruction(MCInst &Inst,
3530                    const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3531  MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
3532  SMLoc Loc = Operands[0]->getStartLoc();
3533  // Check the IT block state first.
3534  // NOTE: In Thumb mode, the BKPT instruction has the interesting property of
3535  // being allowed in IT blocks, but not being predicable.  It just always
3536  // executes.
3537  if (inITBlock() && Inst.getOpcode() != ARM::tBKPT) {
3538    unsigned bit = 1;
3539    if (ITState.FirstCond)
3540      ITState.FirstCond = false;
3541    else
3542      bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
3543    // The instruction must be predicable.
3544    if (!MCID.isPredicable())
3545      return Error(Loc, "instructions in IT block must be predicable");
3546    unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
3547    unsigned ITCond = bit ? ITState.Cond :
3548      ARMCC::getOppositeCondition(ITState.Cond);
3549    if (Cond != ITCond) {
3550      // Find the condition code Operand to get its SMLoc information.
3551      SMLoc CondLoc;
3552      for (unsigned i = 1; i < Operands.size(); ++i)
3553        if (static_cast<ARMOperand*>(Operands[i])->isCondCode())
3554          CondLoc = Operands[i]->getStartLoc();
3555      return Error(CondLoc, "incorrect condition in IT block; got '" +
3556                   StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
3557                   "', but expected '" +
3558                   ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
3559    }
3560  // Check for non-'al' condition codes outside of the IT block.
3561  } else if (isThumbTwo() && MCID.isPredicable() &&
3562             Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
3563             ARMCC::AL && Inst.getOpcode() != ARM::tB &&
3564             Inst.getOpcode() != ARM::t2B)
3565    return Error(Loc, "predicated instructions must be in IT block");
3566
3567  switch (Inst.getOpcode()) {
3568  case ARM::LDRD:
3569  case ARM::LDRD_PRE:
3570  case ARM::LDRD_POST:
3571  case ARM::LDREXD: {
3572    // Rt2 must be Rt + 1.
3573    unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
3574    unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
3575    if (Rt2 != Rt + 1)
3576      return Error(Operands[3]->getStartLoc(),
3577                   "destination operands must be sequential");
3578    return false;
3579  }
3580  case ARM::STRD: {
3581    // Rt2 must be Rt + 1.
3582    unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
3583    unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
3584    if (Rt2 != Rt + 1)
3585      return Error(Operands[3]->getStartLoc(),
3586                   "source operands must be sequential");
3587    return false;
3588  }
3589  case ARM::STRD_PRE:
3590  case ARM::STRD_POST:
3591  case ARM::STREXD: {
3592    // Rt2 must be Rt + 1.
3593    unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg());
3594    unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(2).getReg());
3595    if (Rt2 != Rt + 1)
3596      return Error(Operands[3]->getStartLoc(),
3597                   "source operands must be sequential");
3598    return false;
3599  }
3600  case ARM::SBFX:
3601  case ARM::UBFX: {
3602    // width must be in range [1, 32-lsb]
3603    unsigned lsb = Inst.getOperand(2).getImm();
3604    unsigned widthm1 = Inst.getOperand(3).getImm();
3605    if (widthm1 >= 32 - lsb)
3606      return Error(Operands[5]->getStartLoc(),
3607                   "bitfield width must be in range [1,32-lsb]");
3608    return false;
3609  }
3610  case ARM::tLDMIA: {
3611    // If we're parsing Thumb2, the .w variant is available and handles
3612    // most cases that are normally illegal for a Thumb1 LDM
3613    // instruction. We'll make the transformation in processInstruction()
3614    // if necessary.
3615    //
3616    // Thumb LDM instructions are writeback iff the base register is not
3617    // in the register list.
3618    unsigned Rn = Inst.getOperand(0).getReg();
3619    bool hasWritebackToken =
3620      (static_cast<ARMOperand*>(Operands[3])->isToken() &&
3621       static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
3622    bool listContainsBase;
3623    if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo())
3624      return Error(Operands[3 + hasWritebackToken]->getStartLoc(),
3625                   "registers must be in range r0-r7");
3626    // If we should have writeback, then there should be a '!' token.
3627    if (!listContainsBase && !hasWritebackToken && !isThumbTwo())
3628      return Error(Operands[2]->getStartLoc(),
3629                   "writeback operator '!' expected");
3630    // If we should not have writeback, there must not be a '!'. This is
3631    // true even for the 32-bit wide encodings.
3632    if (listContainsBase && hasWritebackToken)
3633      return Error(Operands[3]->getStartLoc(),
3634                   "writeback operator '!' not allowed when base register "
3635                   "in register list");
3636
3637    break;
3638  }
3639  case ARM::t2LDMIA_UPD: {
3640    if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
3641      return Error(Operands[4]->getStartLoc(),
3642                   "writeback operator '!' not allowed when base register "
3643                   "in register list");
3644    break;
3645  }
3646  case ARM::tPOP: {
3647    bool listContainsBase;
3648    if (checkLowRegisterList(Inst, 3, 0, ARM::PC, listContainsBase))
3649      return Error(Operands[2]->getStartLoc(),
3650                   "registers must be in range r0-r7 or pc");
3651    break;
3652  }
3653  case ARM::tPUSH: {
3654    bool listContainsBase;
3655    if (checkLowRegisterList(Inst, 3, 0, ARM::LR, listContainsBase))
3656      return Error(Operands[2]->getStartLoc(),
3657                   "registers must be in range r0-r7 or lr");
3658    break;
3659  }
3660  case ARM::tSTMIA_UPD: {
3661    bool listContainsBase;
3662    if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase))
3663      return Error(Operands[4]->getStartLoc(),
3664                   "registers must be in range r0-r7");
3665    break;
3666  }
3667  }
3668
3669  return false;
3670}
3671
3672void ARMAsmParser::
3673processInstruction(MCInst &Inst,
3674                   const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3675  switch (Inst.getOpcode()) {
3676  case ARM::LDMIA_UPD:
3677    // If this is a load of a single register via a 'pop', then we should use
3678    // a post-indexed LDR instruction instead, per the ARM ARM.
3679    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
3680        Inst.getNumOperands() == 5) {
3681      MCInst TmpInst;
3682      TmpInst.setOpcode(ARM::LDR_POST_IMM);
3683      TmpInst.addOperand(Inst.getOperand(4)); // Rt
3684      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
3685      TmpInst.addOperand(Inst.getOperand(1)); // Rn
3686      TmpInst.addOperand(MCOperand::CreateReg(0));  // am2offset
3687      TmpInst.addOperand(MCOperand::CreateImm(4));
3688      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
3689      TmpInst.addOperand(Inst.getOperand(3));
3690      Inst = TmpInst;
3691    }
3692    break;
3693  case ARM::STMDB_UPD:
3694    // If this is a store of a single register via a 'push', then we should use
3695    // a pre-indexed STR instruction instead, per the ARM ARM.
3696    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
3697        Inst.getNumOperands() == 5) {
3698      MCInst TmpInst;
3699      TmpInst.setOpcode(ARM::STR_PRE_IMM);
3700      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
3701      TmpInst.addOperand(Inst.getOperand(4)); // Rt
3702      TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
3703      TmpInst.addOperand(MCOperand::CreateImm(-4));
3704      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
3705      TmpInst.addOperand(Inst.getOperand(3));
3706      Inst = TmpInst;
3707    }
3708    break;
3709  case ARM::tADDi8:
3710    // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
3711    // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
3712    // to encoding T2 if <Rd> is specified and encoding T2 is preferred
3713    // to encoding T1 if <Rd> is omitted."
3714    if (Inst.getOperand(3).getImm() < 8 && Operands.size() == 6)
3715      Inst.setOpcode(ARM::tADDi3);
3716    break;
3717  case ARM::tB:
3718    // A Thumb conditional branch outside of an IT block is a tBcc.
3719    if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock())
3720      Inst.setOpcode(ARM::tBcc);
3721    break;
3722  case ARM::t2B:
3723    // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
3724    if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock())
3725      Inst.setOpcode(ARM::t2Bcc);
3726    break;
3727  case ARM::t2Bcc:
3728    // If the conditional is AL or we're in an IT block, we really want t2B.
3729    if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock())
3730      Inst.setOpcode(ARM::t2B);
3731    break;
3732  case ARM::tBcc:
3733    // If the conditional is AL, we really want tB.
3734    if (Inst.getOperand(1).getImm() == ARMCC::AL)
3735      Inst.setOpcode(ARM::tB);
3736    break;
3737  case ARM::tLDMIA: {
3738    // If the register list contains any high registers, or if the writeback
3739    // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
3740    // instead if we're in Thumb2. Otherwise, this should have generated
3741    // an error in validateInstruction().
3742    unsigned Rn = Inst.getOperand(0).getReg();
3743    bool hasWritebackToken =
3744      (static_cast<ARMOperand*>(Operands[3])->isToken() &&
3745       static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
3746    bool listContainsBase;
3747    if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
3748        (!listContainsBase && !hasWritebackToken) ||
3749        (listContainsBase && hasWritebackToken)) {
3750      // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
3751      assert (isThumbTwo());
3752      Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
3753      // If we're switching to the updating version, we need to insert
3754      // the writeback tied operand.
3755      if (hasWritebackToken)
3756        Inst.insert(Inst.begin(),
3757                    MCOperand::CreateReg(Inst.getOperand(0).getReg()));
3758    }
3759    break;
3760  }
3761  case ARM::t2MOVi: {
3762    // If we can use the 16-bit encoding and the user didn't explicitly
3763    // request the 32-bit variant, transform it here.
3764    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
3765        Inst.getOperand(1).getImm() <= 255 &&
3766        Inst.getOperand(2).getImm() == ARMCC::AL &&
3767        Inst.getOperand(4).getReg() == ARM::CPSR &&
3768        (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
3769         static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
3770      // The operands aren't in the same order for tMOVi8...
3771      MCInst TmpInst;
3772      TmpInst.setOpcode(ARM::tMOVi8);
3773      TmpInst.addOperand(Inst.getOperand(0));
3774      TmpInst.addOperand(Inst.getOperand(4));
3775      TmpInst.addOperand(Inst.getOperand(1));
3776      TmpInst.addOperand(Inst.getOperand(2));
3777      TmpInst.addOperand(Inst.getOperand(3));
3778      Inst = TmpInst;
3779    }
3780    break;
3781  }
3782  case ARM::t2MOVr: {
3783    // If we can use the 16-bit encoding and the user didn't explicitly
3784    // request the 32-bit variant, transform it here.
3785    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
3786        isARMLowRegister(Inst.getOperand(1).getReg()) &&
3787        Inst.getOperand(2).getImm() == ARMCC::AL &&
3788        Inst.getOperand(4).getReg() == ARM::CPSR &&
3789        (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
3790         static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
3791      // The operands aren't the same for tMOV[S]r... (no cc_out)
3792      MCInst TmpInst;
3793      TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
3794      TmpInst.addOperand(Inst.getOperand(0));
3795      TmpInst.addOperand(Inst.getOperand(1));
3796      TmpInst.addOperand(Inst.getOperand(2));
3797      TmpInst.addOperand(Inst.getOperand(3));
3798      Inst = TmpInst;
3799    }
3800    break;
3801  }
3802  case ARM::t2IT: {
3803    // The mask bits for all but the first condition are represented as
3804    // the low bit of the condition code value implies 't'. We currently
3805    // always have 1 implies 't', so XOR toggle the bits if the low bit
3806    // of the condition code is zero. The encoding also expects the low
3807    // bit of the condition to be encoded as bit 4 of the mask operand,
3808    // so mask that in if needed
3809    MCOperand &MO = Inst.getOperand(1);
3810    unsigned Mask = MO.getImm();
3811    unsigned OrigMask = Mask;
3812    unsigned TZ = CountTrailingZeros_32(Mask);
3813    if ((Inst.getOperand(0).getImm() & 1) == 0) {
3814      assert(Mask && TZ <= 3 && "illegal IT mask value!");
3815      for (unsigned i = 3; i != TZ; --i)
3816        Mask ^= 1 << i;
3817    } else
3818      Mask |= 0x10;
3819    MO.setImm(Mask);
3820
3821    // Set up the IT block state according to the IT instruction we just
3822    // matched.
3823    assert(!inITBlock() && "nested IT blocks?!");
3824    ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
3825    ITState.Mask = OrigMask; // Use the original mask, not the updated one.
3826    ITState.CurPosition = 0;
3827    ITState.FirstCond = true;
3828    break;
3829  }
3830  }
3831}
3832
3833unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
3834  // 16-bit thumb arithmetic instructions either require or preclude the 'S'
3835  // suffix depending on whether they're in an IT block or not.
3836  unsigned Opc = Inst.getOpcode();
3837  MCInstrDesc &MCID = getInstDesc(Opc);
3838  if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
3839    assert(MCID.hasOptionalDef() &&
3840           "optionally flag setting instruction missing optional def operand");
3841    assert(MCID.NumOperands == Inst.getNumOperands() &&
3842           "operand count mismatch!");
3843    // Find the optional-def operand (cc_out).
3844    unsigned OpNo;
3845    for (OpNo = 0;
3846         !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
3847         ++OpNo)
3848      ;
3849    // If we're parsing Thumb1, reject it completely.
3850    if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
3851      return Match_MnemonicFail;
3852    // If we're parsing Thumb2, which form is legal depends on whether we're
3853    // in an IT block.
3854    if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
3855        !inITBlock())
3856      return Match_RequiresITBlock;
3857    if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
3858        inITBlock())
3859      return Match_RequiresNotITBlock;
3860  }
3861  // Some high-register supporting Thumb1 encodings only allow both registers
3862  // to be from r0-r7 when in Thumb2.
3863  else if (Opc == ARM::tADDhirr && isThumbOne() &&
3864           isARMLowRegister(Inst.getOperand(1).getReg()) &&
3865           isARMLowRegister(Inst.getOperand(2).getReg()))
3866    return Match_RequiresThumb2;
3867  // Others only require ARMv6 or later.
3868  else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
3869           isARMLowRegister(Inst.getOperand(0).getReg()) &&
3870           isARMLowRegister(Inst.getOperand(1).getReg()))
3871    return Match_RequiresV6;
3872  return Match_Success;
3873}
3874
3875bool ARMAsmParser::
3876MatchAndEmitInstruction(SMLoc IDLoc,
3877                        SmallVectorImpl<MCParsedAsmOperand*> &Operands,
3878                        MCStreamer &Out) {
3879  MCInst Inst;
3880  unsigned ErrorInfo;
3881  unsigned MatchResult;
3882  MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo);
3883  switch (MatchResult) {
3884  default: break;
3885  case Match_Success:
3886    // Context sensitive operand constraints aren't handled by the matcher,
3887    // so check them here.
3888    if (validateInstruction(Inst, Operands)) {
3889      // Still progress the IT block, otherwise one wrong condition causes
3890      // nasty cascading errors.
3891      forwardITPosition();
3892      return true;
3893    }
3894
3895    // Some instructions need post-processing to, for example, tweak which
3896    // encoding is selected.
3897    processInstruction(Inst, Operands);
3898
3899    // Only move forward at the very end so that everything in validate
3900    // and process gets a consistent answer about whether we're in an IT
3901    // block.
3902    forwardITPosition();
3903
3904    Out.EmitInstruction(Inst);
3905    return false;
3906  case Match_MissingFeature:
3907    Error(IDLoc, "instruction requires a CPU feature not currently enabled");
3908    return true;
3909  case Match_InvalidOperand: {
3910    SMLoc ErrorLoc = IDLoc;
3911    if (ErrorInfo != ~0U) {
3912      if (ErrorInfo >= Operands.size())
3913        return Error(IDLoc, "too few operands for instruction");
3914
3915      ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
3916      if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
3917    }
3918
3919    return Error(ErrorLoc, "invalid operand for instruction");
3920  }
3921  case Match_MnemonicFail:
3922    return Error(IDLoc, "invalid instruction");
3923  case Match_ConversionFail:
3924    // The converter function will have already emited a diagnostic.
3925    return true;
3926  case Match_RequiresNotITBlock:
3927    return Error(IDLoc, "flag setting instruction only valid outside IT block");
3928  case Match_RequiresITBlock:
3929    return Error(IDLoc, "instruction only valid inside IT block");
3930  case Match_RequiresV6:
3931    return Error(IDLoc, "instruction variant requires ARMv6 or later");
3932  case Match_RequiresThumb2:
3933    return Error(IDLoc, "instruction variant requires Thumb2");
3934  }
3935
3936  llvm_unreachable("Implement any new match types added!");
3937  return true;
3938}
3939
3940/// parseDirective parses the arm specific directives
3941bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
3942  StringRef IDVal = DirectiveID.getIdentifier();
3943  if (IDVal == ".word")
3944    return parseDirectiveWord(4, DirectiveID.getLoc());
3945  else if (IDVal == ".thumb")
3946    return parseDirectiveThumb(DirectiveID.getLoc());
3947  else if (IDVal == ".thumb_func")
3948    return parseDirectiveThumbFunc(DirectiveID.getLoc());
3949  else if (IDVal == ".code")
3950    return parseDirectiveCode(DirectiveID.getLoc());
3951  else if (IDVal == ".syntax")
3952    return parseDirectiveSyntax(DirectiveID.getLoc());
3953  return true;
3954}
3955
3956/// parseDirectiveWord
3957///  ::= .word [ expression (, expression)* ]
3958bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
3959  if (getLexer().isNot(AsmToken::EndOfStatement)) {
3960    for (;;) {
3961      const MCExpr *Value;
3962      if (getParser().ParseExpression(Value))
3963        return true;
3964
3965      getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
3966
3967      if (getLexer().is(AsmToken::EndOfStatement))
3968        break;
3969
3970      // FIXME: Improve diagnostic.
3971      if (getLexer().isNot(AsmToken::Comma))
3972        return Error(L, "unexpected token in directive");
3973      Parser.Lex();
3974    }
3975  }
3976
3977  Parser.Lex();
3978  return false;
3979}
3980
3981/// parseDirectiveThumb
3982///  ::= .thumb
3983bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
3984  if (getLexer().isNot(AsmToken::EndOfStatement))
3985    return Error(L, "unexpected token in directive");
3986  Parser.Lex();
3987
3988  // TODO: set thumb mode
3989  // TODO: tell the MC streamer the mode
3990  // getParser().getStreamer().Emit???();
3991  return false;
3992}
3993
3994/// parseDirectiveThumbFunc
3995///  ::= .thumbfunc symbol_name
3996bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
3997  const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
3998  bool isMachO = MAI.hasSubsectionsViaSymbols();
3999  StringRef Name;
4000
4001  // Darwin asm has function name after .thumb_func direction
4002  // ELF doesn't
4003  if (isMachO) {
4004    const AsmToken &Tok = Parser.getTok();
4005    if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
4006      return Error(L, "unexpected token in .thumb_func directive");
4007    Name = Tok.getString();
4008    Parser.Lex(); // Consume the identifier token.
4009  }
4010
4011  if (getLexer().isNot(AsmToken::EndOfStatement))
4012    return Error(L, "unexpected token in directive");
4013  Parser.Lex();
4014
4015  // FIXME: assuming function name will be the line following .thumb_func
4016  if (!isMachO) {
4017    Name = Parser.getTok().getString();
4018  }
4019
4020  // Mark symbol as a thumb symbol.
4021  MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
4022  getParser().getStreamer().EmitThumbFunc(Func);
4023  return false;
4024}
4025
4026/// parseDirectiveSyntax
4027///  ::= .syntax unified | divided
4028bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
4029  const AsmToken &Tok = Parser.getTok();
4030  if (Tok.isNot(AsmToken::Identifier))
4031    return Error(L, "unexpected token in .syntax directive");
4032  StringRef Mode = Tok.getString();
4033  if (Mode == "unified" || Mode == "UNIFIED")
4034    Parser.Lex();
4035  else if (Mode == "divided" || Mode == "DIVIDED")
4036    return Error(L, "'.syntax divided' arm asssembly not supported");
4037  else
4038    return Error(L, "unrecognized syntax mode in .syntax directive");
4039
4040  if (getLexer().isNot(AsmToken::EndOfStatement))
4041    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
4042  Parser.Lex();
4043
4044  // TODO tell the MC streamer the mode
4045  // getParser().getStreamer().Emit???();
4046  return false;
4047}
4048
4049/// parseDirectiveCode
4050///  ::= .code 16 | 32
4051bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
4052  const AsmToken &Tok = Parser.getTok();
4053  if (Tok.isNot(AsmToken::Integer))
4054    return Error(L, "unexpected token in .code directive");
4055  int64_t Val = Parser.getTok().getIntVal();
4056  if (Val == 16)
4057    Parser.Lex();
4058  else if (Val == 32)
4059    Parser.Lex();
4060  else
4061    return Error(L, "invalid operand to .code directive");
4062
4063  if (getLexer().isNot(AsmToken::EndOfStatement))
4064    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
4065  Parser.Lex();
4066
4067  if (Val == 16) {
4068    if (!isThumb())
4069      SwitchMode();
4070    getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
4071  } else {
4072    if (isThumb())
4073      SwitchMode();
4074    getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
4075  }
4076
4077  return false;
4078}
4079
4080extern "C" void LLVMInitializeARMAsmLexer();
4081
4082/// Force static initialization.
4083extern "C" void LLVMInitializeARMAsmParser() {
4084  RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
4085  RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
4086  LLVMInitializeARMAsmLexer();
4087}
4088
4089#define GET_REGISTER_MATCHER
4090#define GET_MATCHER_IMPLEMENTATION
4091#include "ARMGenAsmMatcher.inc"
4092