ARMAsmParser.cpp revision eeec025cf5a2236ee9527a3312496a6ea42100c6 
1//===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "MCTargetDesc/ARMBaseInfo.h"
11#include "MCTargetDesc/ARMAddressingModes.h"
12#include "MCTargetDesc/ARMMCExpr.h"
13#include "llvm/MC/MCParser/MCAsmLexer.h"
14#include "llvm/MC/MCParser/MCAsmParser.h"
15#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16#include "llvm/MC/MCAsmInfo.h"
17#include "llvm/MC/MCContext.h"
18#include "llvm/MC/MCStreamer.h"
19#include "llvm/MC/MCExpr.h"
20#include "llvm/MC/MCInst.h"
21#include "llvm/MC/MCInstrDesc.h"
22#include "llvm/MC/MCRegisterInfo.h"
23#include "llvm/MC/MCSubtargetInfo.h"
24#include "llvm/MC/MCTargetAsmParser.h"
25#include "llvm/Support/MathExtras.h"
26#include "llvm/Support/SourceMgr.h"
27#include "llvm/Support/TargetRegistry.h"
28#include "llvm/Support/raw_ostream.h"
29#include "llvm/ADT/BitVector.h"
30#include "llvm/ADT/OwningPtr.h"
31#include "llvm/ADT/STLExtras.h"
32#include "llvm/ADT/SmallVector.h"
33#include "llvm/ADT/StringExtras.h"
34#include "llvm/ADT/StringSwitch.h"
35#include "llvm/ADT/Twine.h"
36
37using namespace llvm;
38
39namespace {
40
41class ARMOperand;
42
43class ARMAsmParser : public MCTargetAsmParser {
44  MCSubtargetInfo &STI;
45  MCAsmParser &Parser;
46
47  struct {
48    ARMCC::CondCodes Cond;    // Condition for IT block.
49    unsigned Mask:4;          // Condition mask for instructions.
50                              // Starting at first 1 (from lsb).
51                              //   '1'  condition as indicated in IT.
52                              //   '0'  inverse of condition (else).
53                              // Count of instructions in IT block is
54                              // 4 - trailingzeroes(mask)
55
56    bool FirstCond;           // Explicit flag for when we're parsing the
57                              // First instruction in the IT block. It's
58                              // implied in the mask, so needs special
59                              // handling.
60
61    unsigned CurPosition;     // Current position in parsing of IT
62                              // block. In range [0,3]. Initialized
63                              // according to count of instructions in block.
64                              // ~0U if no active IT block.
65  } ITState;
66  bool inITBlock() { return ITState.CurPosition != ~0U;}
67  void forwardITPosition() {
68    if (!inITBlock()) return;
69    // Move to the next instruction in the IT block, if there is one. If not,
70    // mark the block as done.
71    unsigned TZ = CountTrailingZeros_32(ITState.Mask);
72    if (++ITState.CurPosition == 5 - TZ)
73      ITState.CurPosition = ~0U; // Done with the IT block after this.
74  }
75
76
77  MCAsmParser &getParser() const { return Parser; }
78  MCAsmLexer &getLexer() const { return Parser.getLexer(); }
79
80  void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
81  bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
82
83  int tryParseRegister();
84  bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
85  int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
86  bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
87  bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
88  bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
89  bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
90  const MCExpr *applyPrefixToExpr(const MCExpr *E,
91                                  MCSymbolRefExpr::VariantKind Variant);
92
93
94  bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
95                              unsigned &ShiftAmount);
96  bool parseDirectiveWord(unsigned Size, SMLoc L);
97  bool parseDirectiveThumb(SMLoc L);
98  bool parseDirectiveThumbFunc(SMLoc L);
99  bool parseDirectiveCode(SMLoc L);
100  bool parseDirectiveSyntax(SMLoc L);
101
102  StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
103                          bool &CarrySetting, unsigned &ProcessorIMod,
104                          StringRef &ITMask);
105  void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
106                             bool &CanAcceptPredicationCode);
107
108  bool isThumb() const {
109    // FIXME: Can tablegen auto-generate this?
110    return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
111  }
112  bool isThumbOne() const {
113    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
114  }
115  bool isThumbTwo() const {
116    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
117  }
118  bool hasV6Ops() const {
119    return STI.getFeatureBits() & ARM::HasV6Ops;
120  }
121  void SwitchMode() {
122    unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
123    setAvailableFeatures(FB);
124  }
125
126  /// @name Auto-generated Match Functions
127  /// {
128
129#define GET_ASSEMBLER_HEADER
130#include "ARMGenAsmMatcher.inc"
131
132  /// }
133
134  OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
135  OperandMatchResultTy parseCoprocNumOperand(
136    SmallVectorImpl<MCParsedAsmOperand*>&);
137  OperandMatchResultTy parseCoprocRegOperand(
138    SmallVectorImpl<MCParsedAsmOperand*>&);
139  OperandMatchResultTy parseMemBarrierOptOperand(
140    SmallVectorImpl<MCParsedAsmOperand*>&);
141  OperandMatchResultTy parseProcIFlagsOperand(
142    SmallVectorImpl<MCParsedAsmOperand*>&);
143  OperandMatchResultTy parseMSRMaskOperand(
144    SmallVectorImpl<MCParsedAsmOperand*>&);
145  OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
146                                   StringRef Op, int Low, int High);
147  OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
148    return parsePKHImm(O, "lsl", 0, 31);
149  }
150  OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
151    return parsePKHImm(O, "asr", 1, 32);
152  }
153  OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
154  OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
155  OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
156  OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
157  OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
158  OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
159
160  // Asm Match Converter Methods
161  bool cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
162                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
163  bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
164                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
165  bool cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
166                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
167  bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
168                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
169  bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
170                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
171  bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
172                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
173  bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
174                             const SmallVectorImpl<MCParsedAsmOperand*> &);
175  bool cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
176                             const SmallVectorImpl<MCParsedAsmOperand*> &);
177  bool cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
178                             const SmallVectorImpl<MCParsedAsmOperand*> &);
179  bool cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
180                             const SmallVectorImpl<MCParsedAsmOperand*> &);
181  bool cvtLdrdPre(MCInst &Inst, unsigned Opcode,
182                  const SmallVectorImpl<MCParsedAsmOperand*> &);
183  bool cvtStrdPre(MCInst &Inst, unsigned Opcode,
184                  const SmallVectorImpl<MCParsedAsmOperand*> &);
185  bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
186                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
187  bool cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
188                        const SmallVectorImpl<MCParsedAsmOperand*> &);
189
190  bool validateInstruction(MCInst &Inst,
191                           const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
192  void processInstruction(MCInst &Inst,
193                          const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
194  bool shouldOmitCCOutOperand(StringRef Mnemonic,
195                              SmallVectorImpl<MCParsedAsmOperand*> &Operands);
196
197public:
198  enum ARMMatchResultTy {
199    Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
200    Match_RequiresNotITBlock,
201    Match_RequiresV6,
202    Match_RequiresThumb2
203  };
204
205  ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
206    : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
207    MCAsmParserExtension::Initialize(_Parser);
208
209    // Initialize the set of available features.
210    setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
211
212    // Not in an ITBlock to start with.
213    ITState.CurPosition = ~0U;
214  }
215
216  // Implementation of the MCTargetAsmParser interface:
217  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
218  bool ParseInstruction(StringRef Name, SMLoc NameLoc,
219                        SmallVectorImpl<MCParsedAsmOperand*> &Operands);
220  bool ParseDirective(AsmToken DirectiveID);
221
222  unsigned checkTargetMatchPredicate(MCInst &Inst);
223
224  bool MatchAndEmitInstruction(SMLoc IDLoc,
225                               SmallVectorImpl<MCParsedAsmOperand*> &Operands,
226                               MCStreamer &Out);
227};
228} // end anonymous namespace
229
230namespace {
231
232/// ARMOperand - Instances of this class represent a parsed ARM machine
233/// instruction.
234class ARMOperand : public MCParsedAsmOperand {
235  enum KindTy {
236    CondCode,
237    CCOut,
238    ITCondMask,
239    CoprocNum,
240    CoprocReg,
241    Immediate,
242    MemBarrierOpt,
243    Memory,
244    PostIndexRegister,
245    MSRMask,
246    ProcIFlags,
247    Register,
248    RegisterList,
249    DPRRegisterList,
250    SPRRegisterList,
251    ShiftedRegister,
252    ShiftedImmediate,
253    ShifterImmediate,
254    RotateImmediate,
255    BitfieldDescriptor,
256    Token
257  } Kind;
258
259  SMLoc StartLoc, EndLoc;
260  SmallVector<unsigned, 8> Registers;
261
262  union {
263    struct {
264      ARMCC::CondCodes Val;
265    } CC;
266
267    struct {
268      unsigned Val;
269    } Cop;
270
271    struct {
272      unsigned Mask:4;
273    } ITMask;
274
275    struct {
276      ARM_MB::MemBOpt Val;
277    } MBOpt;
278
279    struct {
280      ARM_PROC::IFlags Val;
281    } IFlags;
282
283    struct {
284      unsigned Val;
285    } MMask;
286
287    struct {
288      const char *Data;
289      unsigned Length;
290    } Tok;
291
292    struct {
293      unsigned RegNum;
294    } Reg;
295
296    struct {
297      const MCExpr *Val;
298    } Imm;
299
300    /// Combined record for all forms of ARM address expressions.
301    struct {
302      unsigned BaseRegNum;
303      // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
304      // was specified.
305      const MCConstantExpr *OffsetImm;  // Offset immediate value
306      unsigned OffsetRegNum;    // Offset register num, when OffsetImm == NULL
307      ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
308      unsigned ShiftImm;      // shift for OffsetReg.
309      unsigned isNegative : 1;  // Negated OffsetReg? (~'U' bit)
310    } Mem;
311
312    struct {
313      unsigned RegNum;
314      bool isAdd;
315      ARM_AM::ShiftOpc ShiftTy;
316      unsigned ShiftImm;
317    } PostIdxReg;
318
319    struct {
320      bool isASR;
321      unsigned Imm;
322    } ShifterImm;
323    struct {
324      ARM_AM::ShiftOpc ShiftTy;
325      unsigned SrcReg;
326      unsigned ShiftReg;
327      unsigned ShiftImm;
328    } RegShiftedReg;
329    struct {
330      ARM_AM::ShiftOpc ShiftTy;
331      unsigned SrcReg;
332      unsigned ShiftImm;
333    } RegShiftedImm;
334    struct {
335      unsigned Imm;
336    } RotImm;
337    struct {
338      unsigned LSB;
339      unsigned Width;
340    } Bitfield;
341  };
342
343  ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
344public:
345  ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
346    Kind = o.Kind;
347    StartLoc = o.StartLoc;
348    EndLoc = o.EndLoc;
349    switch (Kind) {
350    case CondCode:
351      CC = o.CC;
352      break;
353    case ITCondMask:
354      ITMask = o.ITMask;
355      break;
356    case Token:
357      Tok = o.Tok;
358      break;
359    case CCOut:
360    case Register:
361      Reg = o.Reg;
362      break;
363    case RegisterList:
364    case DPRRegisterList:
365    case SPRRegisterList:
366      Registers = o.Registers;
367      break;
368    case CoprocNum:
369    case CoprocReg:
370      Cop = o.Cop;
371      break;
372    case Immediate:
373      Imm = o.Imm;
374      break;
375    case MemBarrierOpt:
376      MBOpt = o.MBOpt;
377      break;
378    case Memory:
379      Mem = o.Mem;
380      break;
381    case PostIndexRegister:
382      PostIdxReg = o.PostIdxReg;
383      break;
384    case MSRMask:
385      MMask = o.MMask;
386      break;
387    case ProcIFlags:
388      IFlags = o.IFlags;
389      break;
390    case ShifterImmediate:
391      ShifterImm = o.ShifterImm;
392      break;
393    case ShiftedRegister:
394      RegShiftedReg = o.RegShiftedReg;
395      break;
396    case ShiftedImmediate:
397      RegShiftedImm = o.RegShiftedImm;
398      break;
399    case RotateImmediate:
400      RotImm = o.RotImm;
401      break;
402    case BitfieldDescriptor:
403      Bitfield = o.Bitfield;
404      break;
405    }
406  }
407
408  /// getStartLoc - Get the location of the first token of this operand.
409  SMLoc getStartLoc() const { return StartLoc; }
410  /// getEndLoc - Get the location of the last token of this operand.
411  SMLoc getEndLoc() const { return EndLoc; }
412
413  ARMCC::CondCodes getCondCode() const {
414    assert(Kind == CondCode && "Invalid access!");
415    return CC.Val;
416  }
417
418  unsigned getCoproc() const {
419    assert((Kind == CoprocNum || Kind == CoprocReg) && "Invalid access!");
420    return Cop.Val;
421  }
422
423  StringRef getToken() const {
424    assert(Kind == Token && "Invalid access!");
425    return StringRef(Tok.Data, Tok.Length);
426  }
427
428  unsigned getReg() const {
429    assert((Kind == Register || Kind == CCOut) && "Invalid access!");
430    return Reg.RegNum;
431  }
432
433  const SmallVectorImpl<unsigned> &getRegList() const {
434    assert((Kind == RegisterList || Kind == DPRRegisterList ||
435            Kind == SPRRegisterList) && "Invalid access!");
436    return Registers;
437  }
438
439  const MCExpr *getImm() const {
440    assert(Kind == Immediate && "Invalid access!");
441    return Imm.Val;
442  }
443
444  ARM_MB::MemBOpt getMemBarrierOpt() const {
445    assert(Kind == MemBarrierOpt && "Invalid access!");
446    return MBOpt.Val;
447  }
448
449  ARM_PROC::IFlags getProcIFlags() const {
450    assert(Kind == ProcIFlags && "Invalid access!");
451    return IFlags.Val;
452  }
453
454  unsigned getMSRMask() const {
455    assert(Kind == MSRMask && "Invalid access!");
456    return MMask.Val;
457  }
458
459  bool isCoprocNum() const { return Kind == CoprocNum; }
460  bool isCoprocReg() const { return Kind == CoprocReg; }
461  bool isCondCode() const { return Kind == CondCode; }
462  bool isCCOut() const { return Kind == CCOut; }
463  bool isITMask() const { return Kind == ITCondMask; }
464  bool isITCondCode() const { return Kind == CondCode; }
465  bool isImm() const { return Kind == Immediate; }
466  bool isImm0_1020s4() const {
467    if (Kind != Immediate)
468      return false;
469    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
470    if (!CE) return false;
471    int64_t Value = CE->getValue();
472    return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
473  }
474  bool isImm0_508s4() const {
475    if (Kind != Immediate)
476      return false;
477    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
478    if (!CE) return false;
479    int64_t Value = CE->getValue();
480    return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
481  }
482  bool isImm0_255() const {
483    if (Kind != Immediate)
484      return false;
485    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
486    if (!CE) return false;
487    int64_t Value = CE->getValue();
488    return Value >= 0 && Value < 256;
489  }
490  bool isImm0_7() const {
491    if (Kind != Immediate)
492      return false;
493    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
494    if (!CE) return false;
495    int64_t Value = CE->getValue();
496    return Value >= 0 && Value < 8;
497  }
498  bool isImm0_15() const {
499    if (Kind != Immediate)
500      return false;
501    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
502    if (!CE) return false;
503    int64_t Value = CE->getValue();
504    return Value >= 0 && Value < 16;
505  }
506  bool isImm0_31() const {
507    if (Kind != Immediate)
508      return false;
509    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
510    if (!CE) return false;
511    int64_t Value = CE->getValue();
512    return Value >= 0 && Value < 32;
513  }
514  bool isImm1_16() const {
515    if (Kind != Immediate)
516      return false;
517    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
518    if (!CE) return false;
519    int64_t Value = CE->getValue();
520    return Value > 0 && Value < 17;
521  }
522  bool isImm1_32() const {
523    if (Kind != Immediate)
524      return false;
525    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
526    if (!CE) return false;
527    int64_t Value = CE->getValue();
528    return Value > 0 && Value < 33;
529  }
530  bool isImm0_65535() const {
531    if (Kind != Immediate)
532      return false;
533    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
534    if (!CE) return false;
535    int64_t Value = CE->getValue();
536    return Value >= 0 && Value < 65536;
537  }
538  bool isImm0_65535Expr() const {
539    if (Kind != Immediate)
540      return false;
541    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
542    // If it's not a constant expression, it'll generate a fixup and be
543    // handled later.
544    if (!CE) return true;
545    int64_t Value = CE->getValue();
546    return Value >= 0 && Value < 65536;
547  }
548  bool isImm24bit() const {
549    if (Kind != Immediate)
550      return false;
551    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
552    if (!CE) return false;
553    int64_t Value = CE->getValue();
554    return Value >= 0 && Value <= 0xffffff;
555  }
556  bool isImmThumbSR() const {
557    if (Kind != Immediate)
558      return false;
559    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
560    if (!CE) return false;
561    int64_t Value = CE->getValue();
562    return Value > 0 && Value < 33;
563  }
564  bool isPKHLSLImm() const {
565    if (Kind != Immediate)
566      return false;
567    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
568    if (!CE) return false;
569    int64_t Value = CE->getValue();
570    return Value >= 0 && Value < 32;
571  }
572  bool isPKHASRImm() const {
573    if (Kind != Immediate)
574      return false;
575    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
576    if (!CE) return false;
577    int64_t Value = CE->getValue();
578    return Value > 0 && Value <= 32;
579  }
580  bool isARMSOImm() const {
581    if (Kind != Immediate)
582      return false;
583    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
584    if (!CE) return false;
585    int64_t Value = CE->getValue();
586    return ARM_AM::getSOImmVal(Value) != -1;
587  }
588  bool isT2SOImm() const {
589    if (Kind != Immediate)
590      return false;
591    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
592    if (!CE) return false;
593    int64_t Value = CE->getValue();
594    return ARM_AM::getT2SOImmVal(Value) != -1;
595  }
596  bool isSetEndImm() const {
597    if (Kind != Immediate)
598      return false;
599    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
600    if (!CE) return false;
601    int64_t Value = CE->getValue();
602    return Value == 1 || Value == 0;
603  }
604  bool isReg() const { return Kind == Register; }
605  bool isRegList() const { return Kind == RegisterList; }
606  bool isDPRRegList() const { return Kind == DPRRegisterList; }
607  bool isSPRRegList() const { return Kind == SPRRegisterList; }
608  bool isToken() const { return Kind == Token; }
609  bool isMemBarrierOpt() const { return Kind == MemBarrierOpt; }
610  bool isMemory() const { return Kind == Memory; }
611  bool isShifterImm() const { return Kind == ShifterImmediate; }
612  bool isRegShiftedReg() const { return Kind == ShiftedRegister; }
613  bool isRegShiftedImm() const { return Kind == ShiftedImmediate; }
614  bool isRotImm() const { return Kind == RotateImmediate; }
615  bool isBitfield() const { return Kind == BitfieldDescriptor; }
616  bool isPostIdxRegShifted() const { return Kind == PostIndexRegister; }
617  bool isPostIdxReg() const {
618    return Kind == PostIndexRegister && PostIdxReg.ShiftTy == ARM_AM::no_shift;
619  }
620  bool isMemNoOffset() const {
621    if (Kind != Memory)
622      return false;
623    // No offset of any kind.
624    return Mem.OffsetRegNum == 0 && Mem.OffsetImm == 0;
625  }
626  bool isAddrMode2() const {
627    if (Kind != Memory)
628      return false;
629    // Check for register offset.
630    if (Mem.OffsetRegNum) return true;
631    // Immediate offset in range [-4095, 4095].
632    if (!Mem.OffsetImm) return true;
633    int64_t Val = Mem.OffsetImm->getValue();
634    return Val > -4096 && Val < 4096;
635  }
636  bool isAM2OffsetImm() const {
637    if (Kind != Immediate)
638      return false;
639    // Immediate offset in range [-4095, 4095].
640    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
641    if (!CE) return false;
642    int64_t Val = CE->getValue();
643    return Val > -4096 && Val < 4096;
644  }
645  bool isAddrMode3() const {
646    if (Kind != Memory)
647      return false;
648    // No shifts are legal for AM3.
649    if (Mem.ShiftType != ARM_AM::no_shift) return false;
650    // Check for register offset.
651    if (Mem.OffsetRegNum) return true;
652    // Immediate offset in range [-255, 255].
653    if (!Mem.OffsetImm) return true;
654    int64_t Val = Mem.OffsetImm->getValue();
655    return Val > -256 && Val < 256;
656  }
657  bool isAM3Offset() const {
658    if (Kind != Immediate && Kind != PostIndexRegister)
659      return false;
660    if (Kind == PostIndexRegister)
661      return PostIdxReg.ShiftTy == ARM_AM::no_shift;
662    // Immediate offset in range [-255, 255].
663    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
664    if (!CE) return false;
665    int64_t Val = CE->getValue();
666    // Special case, #-0 is INT32_MIN.
667    return (Val > -256 && Val < 256) || Val == INT32_MIN;
668  }
669  bool isAddrMode5() const {
670    if (Kind != Memory)
671      return false;
672    // Check for register offset.
673    if (Mem.OffsetRegNum) return false;
674    // Immediate offset in range [-1020, 1020] and a multiple of 4.
675    if (!Mem.OffsetImm) return true;
676    int64_t Val = Mem.OffsetImm->getValue();
677    return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
678           Val == INT32_MIN;
679  }
680  bool isMemRegOffset() const {
681    if (Kind != Memory || !Mem.OffsetRegNum)
682      return false;
683    return true;
684  }
685  bool isT2MemRegOffset() const {
686    if (Kind != Memory || !Mem.OffsetRegNum || Mem.isNegative)
687      return false;
688    // Only lsl #{0, 1, 2, 3} allowed.
689    if (Mem.ShiftType == ARM_AM::no_shift)
690      return true;
691    if (Mem.ShiftType != ARM_AM::lsl || Mem.ShiftImm > 3)
692      return false;
693    return true;
694  }
695  bool isMemThumbRR() const {
696    // Thumb reg+reg addressing is simple. Just two registers, a base and
697    // an offset. No shifts, negations or any other complicating factors.
698    if (Kind != Memory || !Mem.OffsetRegNum || Mem.isNegative ||
699        Mem.ShiftType != ARM_AM::no_shift)
700      return false;
701    return isARMLowRegister(Mem.BaseRegNum) &&
702      (!Mem.OffsetRegNum || isARMLowRegister(Mem.OffsetRegNum));
703  }
704  bool isMemThumbRIs4() const {
705    if (Kind != Memory || Mem.OffsetRegNum != 0 ||
706        !isARMLowRegister(Mem.BaseRegNum))
707      return false;
708    // Immediate offset, multiple of 4 in range [0, 124].
709    if (!Mem.OffsetImm) return true;
710    int64_t Val = Mem.OffsetImm->getValue();
711    return Val >= 0 && Val <= 124 && (Val % 4) == 0;
712  }
713  bool isMemThumbRIs2() const {
714    if (Kind != Memory || Mem.OffsetRegNum != 0 ||
715        !isARMLowRegister(Mem.BaseRegNum))
716      return false;
717    // Immediate offset, multiple of 4 in range [0, 62].
718    if (!Mem.OffsetImm) return true;
719    int64_t Val = Mem.OffsetImm->getValue();
720    return Val >= 0 && Val <= 62 && (Val % 2) == 0;
721  }
722  bool isMemThumbRIs1() const {
723    if (Kind != Memory || Mem.OffsetRegNum != 0 ||
724        !isARMLowRegister(Mem.BaseRegNum))
725      return false;
726    // Immediate offset in range [0, 31].
727    if (!Mem.OffsetImm) return true;
728    int64_t Val = Mem.OffsetImm->getValue();
729    return Val >= 0 && Val <= 31;
730  }
731  bool isMemThumbSPI() const {
732    if (Kind != Memory || Mem.OffsetRegNum != 0 || Mem.BaseRegNum != ARM::SP)
733      return false;
734    // Immediate offset, multiple of 4 in range [0, 1020].
735    if (!Mem.OffsetImm) return true;
736    int64_t Val = Mem.OffsetImm->getValue();
737    return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
738  }
739  bool isMemImm8Offset() const {
740    if (Kind != Memory || Mem.OffsetRegNum != 0)
741      return false;
742    // Immediate offset in range [-255, 255].
743    if (!Mem.OffsetImm) return true;
744    int64_t Val = Mem.OffsetImm->getValue();
745    return Val > -256 && Val < 256;
746  }
747  bool isMemPosImm8Offset() const {
748    if (Kind != Memory || Mem.OffsetRegNum != 0)
749      return false;
750    // Immediate offset in range [0, 255].
751    if (!Mem.OffsetImm) return true;
752    int64_t Val = Mem.OffsetImm->getValue();
753    return Val >= 0 && Val < 256;
754  }
755  bool isMemNegImm8Offset() const {
756    if (Kind != Memory || Mem.OffsetRegNum != 0)
757      return false;
758    // Immediate offset in range [-255, -1].
759    if (!Mem.OffsetImm) return true;
760    int64_t Val = Mem.OffsetImm->getValue();
761    return Val > -256 && Val < 0;
762  }
763  bool isMemUImm12Offset() const {
764    // If we have an immediate that's not a constant, treat it as a label
765    // reference needing a fixup. If it is a constant, it's something else
766    // and we reject it.
767    if (Kind == Immediate && !isa<MCConstantExpr>(getImm()))
768      return true;
769
770    if (Kind != Memory || Mem.OffsetRegNum != 0)
771      return false;
772    // Immediate offset in range [0, 4095].
773    if (!Mem.OffsetImm) return true;
774    int64_t Val = Mem.OffsetImm->getValue();
775    return (Val >= 0 && Val < 4096);
776  }
777  bool isMemImm12Offset() const {
778    // If we have an immediate that's not a constant, treat it as a label
779    // reference needing a fixup. If it is a constant, it's something else
780    // and we reject it.
781    if (Kind == Immediate && !isa<MCConstantExpr>(getImm()))
782      return true;
783
784    if (Kind != Memory || Mem.OffsetRegNum != 0)
785      return false;
786    // Immediate offset in range [-4095, 4095].
787    if (!Mem.OffsetImm) return true;
788    int64_t Val = Mem.OffsetImm->getValue();
789    return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
790  }
791  bool isPostIdxImm8() const {
792    if (Kind != Immediate)
793      return false;
794    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
795    if (!CE) return false;
796    int64_t Val = CE->getValue();
797    return (Val > -256 && Val < 256) || (Val == INT32_MIN);
798  }
799
800  bool isMSRMask() const { return Kind == MSRMask; }
801  bool isProcIFlags() const { return Kind == ProcIFlags; }
802
803  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
804    // Add as immediates when possible.  Null MCExpr = 0.
805    if (Expr == 0)
806      Inst.addOperand(MCOperand::CreateImm(0));
807    else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
808      Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
809    else
810      Inst.addOperand(MCOperand::CreateExpr(Expr));
811  }
812
813  void addCondCodeOperands(MCInst &Inst, unsigned N) const {
814    assert(N == 2 && "Invalid number of operands!");
815    Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
816    unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
817    Inst.addOperand(MCOperand::CreateReg(RegNum));
818  }
819
820  void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
821    assert(N == 1 && "Invalid number of operands!");
822    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
823  }
824
825  void addITMaskOperands(MCInst &Inst, unsigned N) const {
826    assert(N == 1 && "Invalid number of operands!");
827    Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
828  }
829
830  void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
831    assert(N == 1 && "Invalid number of operands!");
832    Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
833  }
834
835  void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
836    assert(N == 1 && "Invalid number of operands!");
837    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
838  }
839
840  void addCCOutOperands(MCInst &Inst, unsigned N) const {
841    assert(N == 1 && "Invalid number of operands!");
842    Inst.addOperand(MCOperand::CreateReg(getReg()));
843  }
844
845  void addRegOperands(MCInst &Inst, unsigned N) const {
846    assert(N == 1 && "Invalid number of operands!");
847    Inst.addOperand(MCOperand::CreateReg(getReg()));
848  }
849
850  void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
851    assert(N == 3 && "Invalid number of operands!");
852    assert(isRegShiftedReg() && "addRegShiftedRegOperands() on non RegShiftedReg!");
853    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
854    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
855    Inst.addOperand(MCOperand::CreateImm(
856      ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
857  }
858
859  void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
860    assert(N == 2 && "Invalid number of operands!");
861    assert(isRegShiftedImm() && "addRegShiftedImmOperands() on non RegShiftedImm!");
862    Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
863    Inst.addOperand(MCOperand::CreateImm(
864      ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm)));
865  }
866
867  void addShifterImmOperands(MCInst &Inst, unsigned N) const {
868    assert(N == 1 && "Invalid number of operands!");
869    Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
870                                         ShifterImm.Imm));
871  }
872
873  void addRegListOperands(MCInst &Inst, unsigned N) const {
874    assert(N == 1 && "Invalid number of operands!");
875    const SmallVectorImpl<unsigned> &RegList = getRegList();
876    for (SmallVectorImpl<unsigned>::const_iterator
877           I = RegList.begin(), E = RegList.end(); I != E; ++I)
878      Inst.addOperand(MCOperand::CreateReg(*I));
879  }
880
881  void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
882    addRegListOperands(Inst, N);
883  }
884
885  void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
886    addRegListOperands(Inst, N);
887  }
888
889  void addRotImmOperands(MCInst &Inst, unsigned N) const {
890    assert(N == 1 && "Invalid number of operands!");
891    // Encoded as val>>3. The printer handles display as 8, 16, 24.
892    Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
893  }
894
895  void addBitfieldOperands(MCInst &Inst, unsigned N) const {
896    assert(N == 1 && "Invalid number of operands!");
897    // Munge the lsb/width into a bitfield mask.
898    unsigned lsb = Bitfield.LSB;
899    unsigned width = Bitfield.Width;
900    // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
901    uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
902                      (32 - (lsb + width)));
903    Inst.addOperand(MCOperand::CreateImm(Mask));
904  }
905
906  void addImmOperands(MCInst &Inst, unsigned N) const {
907    assert(N == 1 && "Invalid number of operands!");
908    addExpr(Inst, getImm());
909  }
910
911  void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
912    assert(N == 1 && "Invalid number of operands!");
913    // The immediate is scaled by four in the encoding and is stored
914    // in the MCInst as such. Lop off the low two bits here.
915    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
916    Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
917  }
918
919  void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
920    assert(N == 1 && "Invalid number of operands!");
921    // The immediate is scaled by four in the encoding and is stored
922    // in the MCInst as such. Lop off the low two bits here.
923    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
924    Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
925  }
926
927  void addImm0_255Operands(MCInst &Inst, unsigned N) const {
928    assert(N == 1 && "Invalid number of operands!");
929    addExpr(Inst, getImm());
930  }
931
932  void addImm0_7Operands(MCInst &Inst, unsigned N) const {
933    assert(N == 1 && "Invalid number of operands!");
934    addExpr(Inst, getImm());
935  }
936
937  void addImm0_15Operands(MCInst &Inst, unsigned N) const {
938    assert(N == 1 && "Invalid number of operands!");
939    addExpr(Inst, getImm());
940  }
941
942  void addImm0_31Operands(MCInst &Inst, unsigned N) const {
943    assert(N == 1 && "Invalid number of operands!");
944    addExpr(Inst, getImm());
945  }
946
947  void addImm1_16Operands(MCInst &Inst, unsigned N) const {
948    assert(N == 1 && "Invalid number of operands!");
949    // The constant encodes as the immediate-1, and we store in the instruction
950    // the bits as encoded, so subtract off one here.
951    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
952    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
953  }
954
955  void addImm1_32Operands(MCInst &Inst, unsigned N) const {
956    assert(N == 1 && "Invalid number of operands!");
957    // The constant encodes as the immediate-1, and we store in the instruction
958    // the bits as encoded, so subtract off one here.
959    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
960    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
961  }
962
963  void addImm0_65535Operands(MCInst &Inst, unsigned N) const {
964    assert(N == 1 && "Invalid number of operands!");
965    addExpr(Inst, getImm());
966  }
967
968  void addImm0_65535ExprOperands(MCInst &Inst, unsigned N) const {
969    assert(N == 1 && "Invalid number of operands!");
970    addExpr(Inst, getImm());
971  }
972
973  void addImm24bitOperands(MCInst &Inst, unsigned N) const {
974    assert(N == 1 && "Invalid number of operands!");
975    addExpr(Inst, getImm());
976  }
977
978  void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
979    assert(N == 1 && "Invalid number of operands!");
980    // The constant encodes as the immediate, except for 32, which encodes as
981    // zero.
982    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
983    unsigned Imm = CE->getValue();
984    Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
985  }
986
987  void addPKHLSLImmOperands(MCInst &Inst, unsigned N) const {
988    assert(N == 1 && "Invalid number of operands!");
989    addExpr(Inst, getImm());
990  }
991
992  void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
993    assert(N == 1 && "Invalid number of operands!");
994    // An ASR value of 32 encodes as 0, so that's how we want to add it to
995    // the instruction as well.
996    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
997    int Val = CE->getValue();
998    Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
999  }
1000
1001  void addARMSOImmOperands(MCInst &Inst, unsigned N) const {
1002    assert(N == 1 && "Invalid number of operands!");
1003    addExpr(Inst, getImm());
1004  }
1005
1006  void addT2SOImmOperands(MCInst &Inst, unsigned N) const {
1007    assert(N == 1 && "Invalid number of operands!");
1008    addExpr(Inst, getImm());
1009  }
1010
1011  void addSetEndImmOperands(MCInst &Inst, unsigned N) const {
1012    assert(N == 1 && "Invalid number of operands!");
1013    addExpr(Inst, getImm());
1014  }
1015
1016  void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1017    assert(N == 1 && "Invalid number of operands!");
1018    Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1019  }
1020
1021  void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1022    assert(N == 1 && "Invalid number of operands!");
1023    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1024  }
1025
1026  void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
1027    assert(N == 3 && "Invalid number of operands!");
1028    int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1029    if (!Mem.OffsetRegNum) {
1030      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1031      // Special case for #-0
1032      if (Val == INT32_MIN) Val = 0;
1033      if (Val < 0) Val = -Val;
1034      Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1035    } else {
1036      // For register offset, we encode the shift type and negation flag
1037      // here.
1038      Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add,
1039                              Mem.ShiftImm, Mem.ShiftType);
1040    }
1041    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1042    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1043    Inst.addOperand(MCOperand::CreateImm(Val));
1044  }
1045
1046  void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
1047    assert(N == 2 && "Invalid number of operands!");
1048    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1049    assert(CE && "non-constant AM2OffsetImm operand!");
1050    int32_t Val = CE->getValue();
1051    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1052    // Special case for #-0
1053    if (Val == INT32_MIN) Val = 0;
1054    if (Val < 0) Val = -Val;
1055    Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1056    Inst.addOperand(MCOperand::CreateReg(0));
1057    Inst.addOperand(MCOperand::CreateImm(Val));
1058  }
1059
1060  void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
1061    assert(N == 3 && "Invalid number of operands!");
1062    int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1063    if (!Mem.OffsetRegNum) {
1064      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1065      // Special case for #-0
1066      if (Val == INT32_MIN) Val = 0;
1067      if (Val < 0) Val = -Val;
1068      Val = ARM_AM::getAM3Opc(AddSub, Val);
1069    } else {
1070      // For register offset, we encode the shift type and negation flag
1071      // here.
1072      Val = ARM_AM::getAM3Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
1073    }
1074    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1075    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1076    Inst.addOperand(MCOperand::CreateImm(Val));
1077  }
1078
1079  void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
1080    assert(N == 2 && "Invalid number of operands!");
1081    if (Kind == PostIndexRegister) {
1082      int32_t Val =
1083        ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
1084      Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1085      Inst.addOperand(MCOperand::CreateImm(Val));
1086      return;
1087    }
1088
1089    // Constant offset.
1090    const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
1091    int32_t Val = CE->getValue();
1092    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1093    // Special case for #-0
1094    if (Val == INT32_MIN) Val = 0;
1095    if (Val < 0) Val = -Val;
1096    Val = ARM_AM::getAM3Opc(AddSub, Val);
1097    Inst.addOperand(MCOperand::CreateReg(0));
1098    Inst.addOperand(MCOperand::CreateImm(Val));
1099  }
1100
1101  void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
1102    assert(N == 2 && "Invalid number of operands!");
1103    // The lower two bits are always zero and as such are not encoded.
1104    int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() / 4 : 0;
1105    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1106    // Special case for #-0
1107    if (Val == INT32_MIN) Val = 0;
1108    if (Val < 0) Val = -Val;
1109    Val = ARM_AM::getAM5Opc(AddSub, Val);
1110    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1111    Inst.addOperand(MCOperand::CreateImm(Val));
1112  }
1113
1114  void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1115    assert(N == 2 && "Invalid number of operands!");
1116    int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1117    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1118    Inst.addOperand(MCOperand::CreateImm(Val));
1119  }
1120
1121  void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1122    addMemImm8OffsetOperands(Inst, N);
1123  }
1124
1125  void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1126    addMemImm8OffsetOperands(Inst, N);
1127  }
1128
1129  void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1130    assert(N == 2 && "Invalid number of operands!");
1131    // If this is an immediate, it's a label reference.
1132    if (Kind == Immediate) {
1133      addExpr(Inst, getImm());
1134      Inst.addOperand(MCOperand::CreateImm(0));
1135      return;
1136    }
1137
1138    // Otherwise, it's a normal memory reg+offset.
1139    int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1140    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1141    Inst.addOperand(MCOperand::CreateImm(Val));
1142  }
1143
1144  void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1145    assert(N == 2 && "Invalid number of operands!");
1146    // If this is an immediate, it's a label reference.
1147    if (Kind == Immediate) {
1148      addExpr(Inst, getImm());
1149      Inst.addOperand(MCOperand::CreateImm(0));
1150      return;
1151    }
1152
1153    // Otherwise, it's a normal memory reg+offset.
1154    int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1155    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1156    Inst.addOperand(MCOperand::CreateImm(Val));
1157  }
1158
1159  void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1160    assert(N == 3 && "Invalid number of operands!");
1161    unsigned Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add,
1162                                     Mem.ShiftImm, Mem.ShiftType);
1163    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1164    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1165    Inst.addOperand(MCOperand::CreateImm(Val));
1166  }
1167
1168  void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1169    assert(N == 3 && "Invalid number of operands!");
1170    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1171    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1172    Inst.addOperand(MCOperand::CreateImm(Mem.ShiftImm));
1173  }
1174
1175  void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
1176    assert(N == 2 && "Invalid number of operands!");
1177    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1178    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1179  }
1180
1181  void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
1182    assert(N == 2 && "Invalid number of operands!");
1183    int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 4) : 0;
1184    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1185    Inst.addOperand(MCOperand::CreateImm(Val));
1186  }
1187
1188  void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
1189    assert(N == 2 && "Invalid number of operands!");
1190    int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 2) : 0;
1191    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1192    Inst.addOperand(MCOperand::CreateImm(Val));
1193  }
1194
1195  void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
1196    assert(N == 2 && "Invalid number of operands!");
1197    int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue()) : 0;
1198    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1199    Inst.addOperand(MCOperand::CreateImm(Val));
1200  }
1201
1202  void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
1203    assert(N == 2 && "Invalid number of operands!");
1204    int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 4) : 0;
1205    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1206    Inst.addOperand(MCOperand::CreateImm(Val));
1207  }
1208
1209  void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
1210    assert(N == 1 && "Invalid number of operands!");
1211    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1212    assert(CE && "non-constant post-idx-imm8 operand!");
1213    int Imm = CE->getValue();
1214    bool isAdd = Imm >= 0;
1215    if (Imm == INT32_MIN) Imm = 0;
1216    Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
1217    Inst.addOperand(MCOperand::CreateImm(Imm));
1218  }
1219
1220  void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
1221    assert(N == 2 && "Invalid number of operands!");
1222    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1223    Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
1224  }
1225
1226  void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
1227    assert(N == 2 && "Invalid number of operands!");
1228    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1229    // The sign, shift type, and shift amount are encoded in a single operand
1230    // using the AM2 encoding helpers.
1231    ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
1232    unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
1233                                     PostIdxReg.ShiftTy);
1234    Inst.addOperand(MCOperand::CreateImm(Imm));
1235  }
1236
1237  void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
1238    assert(N == 1 && "Invalid number of operands!");
1239    Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
1240  }
1241
1242  void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
1243    assert(N == 1 && "Invalid number of operands!");
1244    Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
1245  }
1246
1247  virtual void print(raw_ostream &OS) const;
1248
1249  static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
1250    ARMOperand *Op = new ARMOperand(ITCondMask);
1251    Op->ITMask.Mask = Mask;
1252    Op->StartLoc = S;
1253    Op->EndLoc = S;
1254    return Op;
1255  }
1256
1257  static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
1258    ARMOperand *Op = new ARMOperand(CondCode);
1259    Op->CC.Val = CC;
1260    Op->StartLoc = S;
1261    Op->EndLoc = S;
1262    return Op;
1263  }
1264
1265  static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
1266    ARMOperand *Op = new ARMOperand(CoprocNum);
1267    Op->Cop.Val = CopVal;
1268    Op->StartLoc = S;
1269    Op->EndLoc = S;
1270    return Op;
1271  }
1272
1273  static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
1274    ARMOperand *Op = new ARMOperand(CoprocReg);
1275    Op->Cop.Val = CopVal;
1276    Op->StartLoc = S;
1277    Op->EndLoc = S;
1278    return Op;
1279  }
1280
1281  static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
1282    ARMOperand *Op = new ARMOperand(CCOut);
1283    Op->Reg.RegNum = RegNum;
1284    Op->StartLoc = S;
1285    Op->EndLoc = S;
1286    return Op;
1287  }
1288
1289  static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
1290    ARMOperand *Op = new ARMOperand(Token);
1291    Op->Tok.Data = Str.data();
1292    Op->Tok.Length = Str.size();
1293    Op->StartLoc = S;
1294    Op->EndLoc = S;
1295    return Op;
1296  }
1297
1298  static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
1299    ARMOperand *Op = new ARMOperand(Register);
1300    Op->Reg.RegNum = RegNum;
1301    Op->StartLoc = S;
1302    Op->EndLoc = E;
1303    return Op;
1304  }
1305
1306  static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
1307                                           unsigned SrcReg,
1308                                           unsigned ShiftReg,
1309                                           unsigned ShiftImm,
1310                                           SMLoc S, SMLoc E) {
1311    ARMOperand *Op = new ARMOperand(ShiftedRegister);
1312    Op->RegShiftedReg.ShiftTy = ShTy;
1313    Op->RegShiftedReg.SrcReg = SrcReg;
1314    Op->RegShiftedReg.ShiftReg = ShiftReg;
1315    Op->RegShiftedReg.ShiftImm = ShiftImm;
1316    Op->StartLoc = S;
1317    Op->EndLoc = E;
1318    return Op;
1319  }
1320
1321  static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
1322                                            unsigned SrcReg,
1323                                            unsigned ShiftImm,
1324                                            SMLoc S, SMLoc E) {
1325    ARMOperand *Op = new ARMOperand(ShiftedImmediate);
1326    Op->RegShiftedImm.ShiftTy = ShTy;
1327    Op->RegShiftedImm.SrcReg = SrcReg;
1328    Op->RegShiftedImm.ShiftImm = ShiftImm;
1329    Op->StartLoc = S;
1330    Op->EndLoc = E;
1331    return Op;
1332  }
1333
1334  static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
1335                                   SMLoc S, SMLoc E) {
1336    ARMOperand *Op = new ARMOperand(ShifterImmediate);
1337    Op->ShifterImm.isASR = isASR;
1338    Op->ShifterImm.Imm = Imm;
1339    Op->StartLoc = S;
1340    Op->EndLoc = E;
1341    return Op;
1342  }
1343
1344  static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
1345    ARMOperand *Op = new ARMOperand(RotateImmediate);
1346    Op->RotImm.Imm = Imm;
1347    Op->StartLoc = S;
1348    Op->EndLoc = E;
1349    return Op;
1350  }
1351
1352  static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
1353                                    SMLoc S, SMLoc E) {
1354    ARMOperand *Op = new ARMOperand(BitfieldDescriptor);
1355    Op->Bitfield.LSB = LSB;
1356    Op->Bitfield.Width = Width;
1357    Op->StartLoc = S;
1358    Op->EndLoc = E;
1359    return Op;
1360  }
1361
1362  static ARMOperand *
1363  CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
1364                SMLoc StartLoc, SMLoc EndLoc) {
1365    KindTy Kind = RegisterList;
1366
1367    if (llvm::ARMMCRegisterClasses[ARM::DPRRegClassID].
1368        contains(Regs.front().first))
1369      Kind = DPRRegisterList;
1370    else if (llvm::ARMMCRegisterClasses[ARM::SPRRegClassID].
1371             contains(Regs.front().first))
1372      Kind = SPRRegisterList;
1373
1374    ARMOperand *Op = new ARMOperand(Kind);
1375    for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
1376           I = Regs.begin(), E = Regs.end(); I != E; ++I)
1377      Op->Registers.push_back(I->first);
1378    array_pod_sort(Op->Registers.begin(), Op->Registers.end());
1379    Op->StartLoc = StartLoc;
1380    Op->EndLoc = EndLoc;
1381    return Op;
1382  }
1383
1384  static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
1385    ARMOperand *Op = new ARMOperand(Immediate);
1386    Op->Imm.Val = Val;
1387    Op->StartLoc = S;
1388    Op->EndLoc = E;
1389    return Op;
1390  }
1391
1392  static ARMOperand *CreateMem(unsigned BaseRegNum,
1393                               const MCConstantExpr *OffsetImm,
1394                               unsigned OffsetRegNum,
1395                               ARM_AM::ShiftOpc ShiftType,
1396                               unsigned ShiftImm,
1397                               bool isNegative,
1398                               SMLoc S, SMLoc E) {
1399    ARMOperand *Op = new ARMOperand(Memory);
1400    Op->Mem.BaseRegNum = BaseRegNum;
1401    Op->Mem.OffsetImm = OffsetImm;
1402    Op->Mem.OffsetRegNum = OffsetRegNum;
1403    Op->Mem.ShiftType = ShiftType;
1404    Op->Mem.ShiftImm = ShiftImm;
1405    Op->Mem.isNegative = isNegative;
1406    Op->StartLoc = S;
1407    Op->EndLoc = E;
1408    return Op;
1409  }
1410
1411  static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
1412                                      ARM_AM::ShiftOpc ShiftTy,
1413                                      unsigned ShiftImm,
1414                                      SMLoc S, SMLoc E) {
1415    ARMOperand *Op = new ARMOperand(PostIndexRegister);
1416    Op->PostIdxReg.RegNum = RegNum;
1417    Op->PostIdxReg.isAdd = isAdd;
1418    Op->PostIdxReg.ShiftTy = ShiftTy;
1419    Op->PostIdxReg.ShiftImm = ShiftImm;
1420    Op->StartLoc = S;
1421    Op->EndLoc = E;
1422    return Op;
1423  }
1424
1425  static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
1426    ARMOperand *Op = new ARMOperand(MemBarrierOpt);
1427    Op->MBOpt.Val = Opt;
1428    Op->StartLoc = S;
1429    Op->EndLoc = S;
1430    return Op;
1431  }
1432
1433  static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
1434    ARMOperand *Op = new ARMOperand(ProcIFlags);
1435    Op->IFlags.Val = IFlags;
1436    Op->StartLoc = S;
1437    Op->EndLoc = S;
1438    return Op;
1439  }
1440
1441  static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
1442    ARMOperand *Op = new ARMOperand(MSRMask);
1443    Op->MMask.Val = MMask;
1444    Op->StartLoc = S;
1445    Op->EndLoc = S;
1446    return Op;
1447  }
1448};
1449
1450} // end anonymous namespace.
1451
1452void ARMOperand::print(raw_ostream &OS) const {
1453  switch (Kind) {
1454  case CondCode:
1455    OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
1456    break;
1457  case CCOut:
1458    OS << "<ccout " << getReg() << ">";
1459    break;
1460  case ITCondMask: {
1461    static char MaskStr[][6] = { "()", "(t)", "(e)", "(tt)", "(et)", "(te)",
1462      "(ee)", "(ttt)", "(ett)", "(tet)", "(eet)", "(tte)", "(ete)",
1463      "(tee)", "(eee)" };
1464    assert((ITMask.Mask & 0xf) == ITMask.Mask);
1465    OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
1466    break;
1467  }
1468  case CoprocNum:
1469    OS << "<coprocessor number: " << getCoproc() << ">";
1470    break;
1471  case CoprocReg:
1472    OS << "<coprocessor register: " << getCoproc() << ">";
1473    break;
1474  case MSRMask:
1475    OS << "<mask: " << getMSRMask() << ">";
1476    break;
1477  case Immediate:
1478    getImm()->print(OS);
1479    break;
1480  case MemBarrierOpt:
1481    OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
1482    break;
1483  case Memory:
1484    OS << "<memory "
1485       << " base:" << Mem.BaseRegNum;
1486    OS << ">";
1487    break;
1488  case PostIndexRegister:
1489    OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
1490       << PostIdxReg.RegNum;
1491    if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
1492      OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
1493         << PostIdxReg.ShiftImm;
1494    OS << ">";
1495    break;
1496  case ProcIFlags: {
1497    OS << "<ARM_PROC::";
1498    unsigned IFlags = getProcIFlags();
1499    for (int i=2; i >= 0; --i)
1500      if (IFlags & (1 << i))
1501        OS << ARM_PROC::IFlagsToString(1 << i);
1502    OS << ">";
1503    break;
1504  }
1505  case Register:
1506    OS << "<register " << getReg() << ">";
1507    break;
1508  case ShifterImmediate:
1509    OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
1510       << " #" << ShifterImm.Imm << ">";
1511    break;
1512  case ShiftedRegister:
1513    OS << "<so_reg_reg "
1514       << RegShiftedReg.SrcReg
1515       << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedReg.ShiftImm))
1516       << ", " << RegShiftedReg.ShiftReg << ", "
1517       << ARM_AM::getSORegOffset(RegShiftedReg.ShiftImm)
1518       << ">";
1519    break;
1520  case ShiftedImmediate:
1521    OS << "<so_reg_imm "
1522       << RegShiftedImm.SrcReg
1523       << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedImm.ShiftImm))
1524       << ", " << ARM_AM::getSORegOffset(RegShiftedImm.ShiftImm)
1525       << ">";
1526    break;
1527  case RotateImmediate:
1528    OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
1529    break;
1530  case BitfieldDescriptor:
1531    OS << "<bitfield " << "lsb: " << Bitfield.LSB
1532       << ", width: " << Bitfield.Width << ">";
1533    break;
1534  case RegisterList:
1535  case DPRRegisterList:
1536  case SPRRegisterList: {
1537    OS << "<register_list ";
1538
1539    const SmallVectorImpl<unsigned> &RegList = getRegList();
1540    for (SmallVectorImpl<unsigned>::const_iterator
1541           I = RegList.begin(), E = RegList.end(); I != E; ) {
1542      OS << *I;
1543      if (++I < E) OS << ", ";
1544    }
1545
1546    OS << ">";
1547    break;
1548  }
1549  case Token:
1550    OS << "'" << getToken() << "'";
1551    break;
1552  }
1553}
1554
1555/// @name Auto-generated Match Functions
1556/// {
1557
1558static unsigned MatchRegisterName(StringRef Name);
1559
1560/// }
1561
1562bool ARMAsmParser::ParseRegister(unsigned &RegNo,
1563                                 SMLoc &StartLoc, SMLoc &EndLoc) {
1564  RegNo = tryParseRegister();
1565
1566  return (RegNo == (unsigned)-1);
1567}
1568
1569/// Try to parse a register name.  The token must be an Identifier when called,
1570/// and if it is a register name the token is eaten and the register number is
1571/// returned.  Otherwise return -1.
1572///
1573int ARMAsmParser::tryParseRegister() {
1574  const AsmToken &Tok = Parser.getTok();
1575  if (Tok.isNot(AsmToken::Identifier)) return -1;
1576
1577  // FIXME: Validate register for the current architecture; we have to do
1578  // validation later, so maybe there is no need for this here.
1579  std::string upperCase = Tok.getString().str();
1580  std::string lowerCase = LowercaseString(upperCase);
1581  unsigned RegNum = MatchRegisterName(lowerCase);
1582  if (!RegNum) {
1583    RegNum = StringSwitch<unsigned>(lowerCase)
1584      .Case("r13", ARM::SP)
1585      .Case("r14", ARM::LR)
1586      .Case("r15", ARM::PC)
1587      .Case("ip", ARM::R12)
1588      .Default(0);
1589  }
1590  if (!RegNum) return -1;
1591
1592  Parser.Lex(); // Eat identifier token.
1593  return RegNum;
1594}
1595
1596// Try to parse a shifter  (e.g., "lsl <amt>"). On success, return 0.
1597// If a recoverable error occurs, return 1. If an irrecoverable error
1598// occurs, return -1. An irrecoverable error is one where tokens have been
1599// consumed in the process of trying to parse the shifter (i.e., when it is
1600// indeed a shifter operand, but malformed).
1601int ARMAsmParser::tryParseShiftRegister(
1602                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1603  SMLoc S = Parser.getTok().getLoc();
1604  const AsmToken &Tok = Parser.getTok();
1605  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1606
1607  std::string upperCase = Tok.getString().str();
1608  std::string lowerCase = LowercaseString(upperCase);
1609  ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
1610      .Case("lsl", ARM_AM::lsl)
1611      .Case("lsr", ARM_AM::lsr)
1612      .Case("asr", ARM_AM::asr)
1613      .Case("ror", ARM_AM::ror)
1614      .Case("rrx", ARM_AM::rrx)
1615      .Default(ARM_AM::no_shift);
1616
1617  if (ShiftTy == ARM_AM::no_shift)
1618    return 1;
1619
1620  Parser.Lex(); // Eat the operator.
1621
1622  // The source register for the shift has already been added to the
1623  // operand list, so we need to pop it off and combine it into the shifted
1624  // register operand instead.
1625  OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
1626  if (!PrevOp->isReg())
1627    return Error(PrevOp->getStartLoc(), "shift must be of a register");
1628  int SrcReg = PrevOp->getReg();
1629  int64_t Imm = 0;
1630  int ShiftReg = 0;
1631  if (ShiftTy == ARM_AM::rrx) {
1632    // RRX Doesn't have an explicit shift amount. The encoder expects
1633    // the shift register to be the same as the source register. Seems odd,
1634    // but OK.
1635    ShiftReg = SrcReg;
1636  } else {
1637    // Figure out if this is shifted by a constant or a register (for non-RRX).
1638    if (Parser.getTok().is(AsmToken::Hash)) {
1639      Parser.Lex(); // Eat hash.
1640      SMLoc ImmLoc = Parser.getTok().getLoc();
1641      const MCExpr *ShiftExpr = 0;
1642      if (getParser().ParseExpression(ShiftExpr)) {
1643        Error(ImmLoc, "invalid immediate shift value");
1644        return -1;
1645      }
1646      // The expression must be evaluatable as an immediate.
1647      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
1648      if (!CE) {
1649        Error(ImmLoc, "invalid immediate shift value");
1650        return -1;
1651      }
1652      // Range check the immediate.
1653      // lsl, ror: 0 <= imm <= 31
1654      // lsr, asr: 0 <= imm <= 32
1655      Imm = CE->getValue();
1656      if (Imm < 0 ||
1657          ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
1658          ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
1659        Error(ImmLoc, "immediate shift value out of range");
1660        return -1;
1661      }
1662    } else if (Parser.getTok().is(AsmToken::Identifier)) {
1663      ShiftReg = tryParseRegister();
1664      SMLoc L = Parser.getTok().getLoc();
1665      if (ShiftReg == -1) {
1666        Error (L, "expected immediate or register in shift operand");
1667        return -1;
1668      }
1669    } else {
1670      Error (Parser.getTok().getLoc(),
1671                    "expected immediate or register in shift operand");
1672      return -1;
1673    }
1674  }
1675
1676  if (ShiftReg && ShiftTy != ARM_AM::rrx)
1677    Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
1678                                                         ShiftReg, Imm,
1679                                               S, Parser.getTok().getLoc()));
1680  else
1681    Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
1682                                               S, Parser.getTok().getLoc()));
1683
1684  return 0;
1685}
1686
1687
1688/// Try to parse a register name.  The token must be an Identifier when called.
1689/// If it's a register, an AsmOperand is created. Another AsmOperand is created
1690/// if there is a "writeback". 'true' if it's not a register.
1691///
1692/// TODO this is likely to change to allow different register types and or to
1693/// parse for a specific register type.
1694bool ARMAsmParser::
1695tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1696  SMLoc S = Parser.getTok().getLoc();
1697  int RegNo = tryParseRegister();
1698  if (RegNo == -1)
1699    return true;
1700
1701  Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
1702
1703  const AsmToken &ExclaimTok = Parser.getTok();
1704  if (ExclaimTok.is(AsmToken::Exclaim)) {
1705    Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
1706                                               ExclaimTok.getLoc()));
1707    Parser.Lex(); // Eat exclaim token
1708  }
1709
1710  return false;
1711}
1712
1713/// MatchCoprocessorOperandName - Try to parse an coprocessor related
1714/// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
1715/// "c5", ...
1716static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
1717  // Use the same layout as the tablegen'erated register name matcher. Ugly,
1718  // but efficient.
1719  switch (Name.size()) {
1720  default: break;
1721  case 2:
1722    if (Name[0] != CoprocOp)
1723      return -1;
1724    switch (Name[1]) {
1725    default:  return -1;
1726    case '0': return 0;
1727    case '1': return 1;
1728    case '2': return 2;
1729    case '3': return 3;
1730    case '4': return 4;
1731    case '5': return 5;
1732    case '6': return 6;
1733    case '7': return 7;
1734    case '8': return 8;
1735    case '9': return 9;
1736    }
1737    break;
1738  case 3:
1739    if (Name[0] != CoprocOp || Name[1] != '1')
1740      return -1;
1741    switch (Name[2]) {
1742    default:  return -1;
1743    case '0': return 10;
1744    case '1': return 11;
1745    case '2': return 12;
1746    case '3': return 13;
1747    case '4': return 14;
1748    case '5': return 15;
1749    }
1750    break;
1751  }
1752
1753  return -1;
1754}
1755
1756/// parseITCondCode - Try to parse a condition code for an IT instruction.
1757ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1758parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1759  SMLoc S = Parser.getTok().getLoc();
1760  const AsmToken &Tok = Parser.getTok();
1761  if (!Tok.is(AsmToken::Identifier))
1762    return MatchOperand_NoMatch;
1763  unsigned CC = StringSwitch<unsigned>(Tok.getString())
1764    .Case("eq", ARMCC::EQ)
1765    .Case("ne", ARMCC::NE)
1766    .Case("hs", ARMCC::HS)
1767    .Case("cs", ARMCC::HS)
1768    .Case("lo", ARMCC::LO)
1769    .Case("cc", ARMCC::LO)
1770    .Case("mi", ARMCC::MI)
1771    .Case("pl", ARMCC::PL)
1772    .Case("vs", ARMCC::VS)
1773    .Case("vc", ARMCC::VC)
1774    .Case("hi", ARMCC::HI)
1775    .Case("ls", ARMCC::LS)
1776    .Case("ge", ARMCC::GE)
1777    .Case("lt", ARMCC::LT)
1778    .Case("gt", ARMCC::GT)
1779    .Case("le", ARMCC::LE)
1780    .Case("al", ARMCC::AL)
1781    .Default(~0U);
1782  if (CC == ~0U)
1783    return MatchOperand_NoMatch;
1784  Parser.Lex(); // Eat the token.
1785
1786  Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
1787
1788  return MatchOperand_Success;
1789}
1790
1791/// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
1792/// token must be an Identifier when called, and if it is a coprocessor
1793/// number, the token is eaten and the operand is added to the operand list.
1794ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1795parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1796  SMLoc S = Parser.getTok().getLoc();
1797  const AsmToken &Tok = Parser.getTok();
1798  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1799
1800  int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
1801  if (Num == -1)
1802    return MatchOperand_NoMatch;
1803
1804  Parser.Lex(); // Eat identifier token.
1805  Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
1806  return MatchOperand_Success;
1807}
1808
1809/// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
1810/// token must be an Identifier when called, and if it is a coprocessor
1811/// number, the token is eaten and the operand is added to the operand list.
1812ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1813parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1814  SMLoc S = Parser.getTok().getLoc();
1815  const AsmToken &Tok = Parser.getTok();
1816  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1817
1818  int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
1819  if (Reg == -1)
1820    return MatchOperand_NoMatch;
1821
1822  Parser.Lex(); // Eat identifier token.
1823  Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
1824  return MatchOperand_Success;
1825}
1826
1827/// Parse a register list, return it if successful else return null.  The first
1828/// token must be a '{' when called.
1829bool ARMAsmParser::
1830parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1831  assert(Parser.getTok().is(AsmToken::LCurly) &&
1832         "Token is not a Left Curly Brace");
1833  SMLoc S = Parser.getTok().getLoc();
1834
1835  // Read the rest of the registers in the list.
1836  unsigned PrevRegNum = 0;
1837  SmallVector<std::pair<unsigned, SMLoc>, 32> Registers;
1838
1839  do {
1840    bool IsRange = Parser.getTok().is(AsmToken::Minus);
1841    Parser.Lex(); // Eat non-identifier token.
1842
1843    const AsmToken &RegTok = Parser.getTok();
1844    SMLoc RegLoc = RegTok.getLoc();
1845    if (RegTok.isNot(AsmToken::Identifier)) {
1846      Error(RegLoc, "register expected");
1847      return true;
1848    }
1849
1850    int RegNum = tryParseRegister();
1851    if (RegNum == -1) {
1852      Error(RegLoc, "register expected");
1853      return true;
1854    }
1855
1856    if (IsRange) {
1857      int Reg = PrevRegNum;
1858      do {
1859        ++Reg;
1860        Registers.push_back(std::make_pair(Reg, RegLoc));
1861      } while (Reg != RegNum);
1862    } else {
1863      Registers.push_back(std::make_pair(RegNum, RegLoc));
1864    }
1865
1866    PrevRegNum = RegNum;
1867  } while (Parser.getTok().is(AsmToken::Comma) ||
1868           Parser.getTok().is(AsmToken::Minus));
1869
1870  // Process the right curly brace of the list.
1871  const AsmToken &RCurlyTok = Parser.getTok();
1872  if (RCurlyTok.isNot(AsmToken::RCurly)) {
1873    Error(RCurlyTok.getLoc(), "'}' expected");
1874    return true;
1875  }
1876
1877  SMLoc E = RCurlyTok.getLoc();
1878  Parser.Lex(); // Eat right curly brace token.
1879
1880  // Verify the register list.
1881  bool EmittedWarning = false;
1882  unsigned HighRegNum = 0;
1883  BitVector RegMap(32);
1884  for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
1885    const std::pair<unsigned, SMLoc> &RegInfo = Registers[i];
1886    unsigned Reg = getARMRegisterNumbering(RegInfo.first);
1887
1888    if (RegMap[Reg]) {
1889      Error(RegInfo.second, "register duplicated in register list");
1890      return true;
1891    }
1892
1893    if (!EmittedWarning && Reg < HighRegNum)
1894      Warning(RegInfo.second,
1895              "register not in ascending order in register list");
1896
1897    RegMap.set(Reg);
1898    HighRegNum = std::max(Reg, HighRegNum);
1899  }
1900
1901  Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
1902  return false;
1903}
1904
1905/// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
1906ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1907parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1908  SMLoc S = Parser.getTok().getLoc();
1909  const AsmToken &Tok = Parser.getTok();
1910  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1911  StringRef OptStr = Tok.getString();
1912
1913  unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()))
1914    .Case("sy",    ARM_MB::SY)
1915    .Case("st",    ARM_MB::ST)
1916    .Case("sh",    ARM_MB::ISH)
1917    .Case("ish",   ARM_MB::ISH)
1918    .Case("shst",  ARM_MB::ISHST)
1919    .Case("ishst", ARM_MB::ISHST)
1920    .Case("nsh",   ARM_MB::NSH)
1921    .Case("un",    ARM_MB::NSH)
1922    .Case("nshst", ARM_MB::NSHST)
1923    .Case("unst",  ARM_MB::NSHST)
1924    .Case("osh",   ARM_MB::OSH)
1925    .Case("oshst", ARM_MB::OSHST)
1926    .Default(~0U);
1927
1928  if (Opt == ~0U)
1929    return MatchOperand_NoMatch;
1930
1931  Parser.Lex(); // Eat identifier token.
1932  Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
1933  return MatchOperand_Success;
1934}
1935
1936/// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
1937ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1938parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1939  SMLoc S = Parser.getTok().getLoc();
1940  const AsmToken &Tok = Parser.getTok();
1941  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1942  StringRef IFlagsStr = Tok.getString();
1943
1944  unsigned IFlags = 0;
1945  for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
1946    unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
1947    .Case("a", ARM_PROC::A)
1948    .Case("i", ARM_PROC::I)
1949    .Case("f", ARM_PROC::F)
1950    .Default(~0U);
1951
1952    // If some specific iflag is already set, it means that some letter is
1953    // present more than once, this is not acceptable.
1954    if (Flag == ~0U || (IFlags & Flag))
1955      return MatchOperand_NoMatch;
1956
1957    IFlags |= Flag;
1958  }
1959
1960  Parser.Lex(); // Eat identifier token.
1961  Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
1962  return MatchOperand_Success;
1963}
1964
1965/// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
1966ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1967parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1968  SMLoc S = Parser.getTok().getLoc();
1969  const AsmToken &Tok = Parser.getTok();
1970  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1971  StringRef Mask = Tok.getString();
1972
1973  // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
1974  size_t Start = 0, Next = Mask.find('_');
1975  StringRef Flags = "";
1976  std::string SpecReg = LowercaseString(Mask.slice(Start, Next));
1977  if (Next != StringRef::npos)
1978    Flags = Mask.slice(Next+1, Mask.size());
1979
1980  // FlagsVal contains the complete mask:
1981  // 3-0: Mask
1982  // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
1983  unsigned FlagsVal = 0;
1984
1985  if (SpecReg == "apsr") {
1986    FlagsVal = StringSwitch<unsigned>(Flags)
1987    .Case("nzcvq",  0x8) // same as CPSR_f
1988    .Case("g",      0x4) // same as CPSR_s
1989    .Case("nzcvqg", 0xc) // same as CPSR_fs
1990    .Default(~0U);
1991
1992    if (FlagsVal == ~0U) {
1993      if (!Flags.empty())
1994        return MatchOperand_NoMatch;
1995      else
1996        FlagsVal = 0; // No flag
1997    }
1998  } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
1999    if (Flags == "all") // cpsr_all is an alias for cpsr_fc
2000      Flags = "fc";
2001    for (int i = 0, e = Flags.size(); i != e; ++i) {
2002      unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
2003      .Case("c", 1)
2004      .Case("x", 2)
2005      .Case("s", 4)
2006      .Case("f", 8)
2007      .Default(~0U);
2008
2009      // If some specific flag is already set, it means that some letter is
2010      // present more than once, this is not acceptable.
2011      if (FlagsVal == ~0U || (FlagsVal & Flag))
2012        return MatchOperand_NoMatch;
2013      FlagsVal |= Flag;
2014    }
2015  } else // No match for special register.
2016    return MatchOperand_NoMatch;
2017
2018  // Special register without flags are equivalent to "fc" flags.
2019  if (!FlagsVal)
2020    FlagsVal = 0x9;
2021
2022  // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
2023  if (SpecReg == "spsr")
2024    FlagsVal |= 16;
2025
2026  Parser.Lex(); // Eat identifier token.
2027  Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
2028  return MatchOperand_Success;
2029}
2030
2031ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2032parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
2033            int Low, int High) {
2034  const AsmToken &Tok = Parser.getTok();
2035  if (Tok.isNot(AsmToken::Identifier)) {
2036    Error(Parser.getTok().getLoc(), Op + " operand expected.");
2037    return MatchOperand_ParseFail;
2038  }
2039  StringRef ShiftName = Tok.getString();
2040  std::string LowerOp = LowercaseString(Op);
2041  std::string UpperOp = UppercaseString(Op);
2042  if (ShiftName != LowerOp && ShiftName != UpperOp) {
2043    Error(Parser.getTok().getLoc(), Op + " operand expected.");
2044    return MatchOperand_ParseFail;
2045  }
2046  Parser.Lex(); // Eat shift type token.
2047
2048  // There must be a '#' and a shift amount.
2049  if (Parser.getTok().isNot(AsmToken::Hash)) {
2050    Error(Parser.getTok().getLoc(), "'#' expected");
2051    return MatchOperand_ParseFail;
2052  }
2053  Parser.Lex(); // Eat hash token.
2054
2055  const MCExpr *ShiftAmount;
2056  SMLoc Loc = Parser.getTok().getLoc();
2057  if (getParser().ParseExpression(ShiftAmount)) {
2058    Error(Loc, "illegal expression");
2059    return MatchOperand_ParseFail;
2060  }
2061  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
2062  if (!CE) {
2063    Error(Loc, "constant expression expected");
2064    return MatchOperand_ParseFail;
2065  }
2066  int Val = CE->getValue();
2067  if (Val < Low || Val > High) {
2068    Error(Loc, "immediate value out of range");
2069    return MatchOperand_ParseFail;
2070  }
2071
2072  Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc()));
2073
2074  return MatchOperand_Success;
2075}
2076
2077ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2078parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2079  const AsmToken &Tok = Parser.getTok();
2080  SMLoc S = Tok.getLoc();
2081  if (Tok.isNot(AsmToken::Identifier)) {
2082    Error(Tok.getLoc(), "'be' or 'le' operand expected");
2083    return MatchOperand_ParseFail;
2084  }
2085  int Val = StringSwitch<int>(Tok.getString())
2086    .Case("be", 1)
2087    .Case("le", 0)
2088    .Default(-1);
2089  Parser.Lex(); // Eat the token.
2090
2091  if (Val == -1) {
2092    Error(Tok.getLoc(), "'be' or 'le' operand expected");
2093    return MatchOperand_ParseFail;
2094  }
2095  Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
2096                                                                  getContext()),
2097                                           S, Parser.getTok().getLoc()));
2098  return MatchOperand_Success;
2099}
2100
2101/// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
2102/// instructions. Legal values are:
2103///     lsl #n  'n' in [0,31]
2104///     asr #n  'n' in [1,32]
2105///             n == 32 encoded as n == 0.
2106ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2107parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2108  const AsmToken &Tok = Parser.getTok();
2109  SMLoc S = Tok.getLoc();
2110  if (Tok.isNot(AsmToken::Identifier)) {
2111    Error(S, "shift operator 'asr' or 'lsl' expected");
2112    return MatchOperand_ParseFail;
2113  }
2114  StringRef ShiftName = Tok.getString();
2115  bool isASR;
2116  if (ShiftName == "lsl" || ShiftName == "LSL")
2117    isASR = false;
2118  else if (ShiftName == "asr" || ShiftName == "ASR")
2119    isASR = true;
2120  else {
2121    Error(S, "shift operator 'asr' or 'lsl' expected");
2122    return MatchOperand_ParseFail;
2123  }
2124  Parser.Lex(); // Eat the operator.
2125
2126  // A '#' and a shift amount.
2127  if (Parser.getTok().isNot(AsmToken::Hash)) {
2128    Error(Parser.getTok().getLoc(), "'#' expected");
2129    return MatchOperand_ParseFail;
2130  }
2131  Parser.Lex(); // Eat hash token.
2132
2133  const MCExpr *ShiftAmount;
2134  SMLoc E = Parser.getTok().getLoc();
2135  if (getParser().ParseExpression(ShiftAmount)) {
2136    Error(E, "malformed shift expression");
2137    return MatchOperand_ParseFail;
2138  }
2139  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
2140  if (!CE) {
2141    Error(E, "shift amount must be an immediate");
2142    return MatchOperand_ParseFail;
2143  }
2144
2145  int64_t Val = CE->getValue();
2146  if (isASR) {
2147    // Shift amount must be in [1,32]
2148    if (Val < 1 || Val > 32) {
2149      Error(E, "'asr' shift amount must be in range [1,32]");
2150      return MatchOperand_ParseFail;
2151    }
2152    // asr #32 encoded as asr #0.
2153    if (Val == 32) Val = 0;
2154  } else {
2155    // Shift amount must be in [1,32]
2156    if (Val < 0 || Val > 31) {
2157      Error(E, "'lsr' shift amount must be in range [0,31]");
2158      return MatchOperand_ParseFail;
2159    }
2160  }
2161
2162  E = Parser.getTok().getLoc();
2163  Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E));
2164
2165  return MatchOperand_Success;
2166}
2167
2168/// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
2169/// of instructions. Legal values are:
2170///     ror #n  'n' in {0, 8, 16, 24}
2171ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2172parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2173  const AsmToken &Tok = Parser.getTok();
2174  SMLoc S = Tok.getLoc();
2175  if (Tok.isNot(AsmToken::Identifier)) {
2176    Error(S, "rotate operator 'ror' expected");
2177    return MatchOperand_ParseFail;
2178  }
2179  StringRef ShiftName = Tok.getString();
2180  if (ShiftName != "ror" && ShiftName != "ROR") {
2181    Error(S, "rotate operator 'ror' expected");
2182    return MatchOperand_ParseFail;
2183  }
2184  Parser.Lex(); // Eat the operator.
2185
2186  // A '#' and a rotate amount.
2187  if (Parser.getTok().isNot(AsmToken::Hash)) {
2188    Error(Parser.getTok().getLoc(), "'#' expected");
2189    return MatchOperand_ParseFail;
2190  }
2191  Parser.Lex(); // Eat hash token.
2192
2193  const MCExpr *ShiftAmount;
2194  SMLoc E = Parser.getTok().getLoc();
2195  if (getParser().ParseExpression(ShiftAmount)) {
2196    Error(E, "malformed rotate expression");
2197    return MatchOperand_ParseFail;
2198  }
2199  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
2200  if (!CE) {
2201    Error(E, "rotate amount must be an immediate");
2202    return MatchOperand_ParseFail;
2203  }
2204
2205  int64_t Val = CE->getValue();
2206  // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
2207  // normally, zero is represented in asm by omitting the rotate operand
2208  // entirely.
2209  if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
2210    Error(E, "'ror' rotate amount must be 8, 16, or 24");
2211    return MatchOperand_ParseFail;
2212  }
2213
2214  E = Parser.getTok().getLoc();
2215  Operands.push_back(ARMOperand::CreateRotImm(Val, S, E));
2216
2217  return MatchOperand_Success;
2218}
2219
2220ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2221parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2222  SMLoc S = Parser.getTok().getLoc();
2223  // The bitfield descriptor is really two operands, the LSB and the width.
2224  if (Parser.getTok().isNot(AsmToken::Hash)) {
2225    Error(Parser.getTok().getLoc(), "'#' expected");
2226    return MatchOperand_ParseFail;
2227  }
2228  Parser.Lex(); // Eat hash token.
2229
2230  const MCExpr *LSBExpr;
2231  SMLoc E = Parser.getTok().getLoc();
2232  if (getParser().ParseExpression(LSBExpr)) {
2233    Error(E, "malformed immediate expression");
2234    return MatchOperand_ParseFail;
2235  }
2236  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
2237  if (!CE) {
2238    Error(E, "'lsb' operand must be an immediate");
2239    return MatchOperand_ParseFail;
2240  }
2241
2242  int64_t LSB = CE->getValue();
2243  // The LSB must be in the range [0,31]
2244  if (LSB < 0 || LSB > 31) {
2245    Error(E, "'lsb' operand must be in the range [0,31]");
2246    return MatchOperand_ParseFail;
2247  }
2248  E = Parser.getTok().getLoc();
2249
2250  // Expect another immediate operand.
2251  if (Parser.getTok().isNot(AsmToken::Comma)) {
2252    Error(Parser.getTok().getLoc(), "too few operands");
2253    return MatchOperand_ParseFail;
2254  }
2255  Parser.Lex(); // Eat hash token.
2256  if (Parser.getTok().isNot(AsmToken::Hash)) {
2257    Error(Parser.getTok().getLoc(), "'#' expected");
2258    return MatchOperand_ParseFail;
2259  }
2260  Parser.Lex(); // Eat hash token.
2261
2262  const MCExpr *WidthExpr;
2263  if (getParser().ParseExpression(WidthExpr)) {
2264    Error(E, "malformed immediate expression");
2265    return MatchOperand_ParseFail;
2266  }
2267  CE = dyn_cast<MCConstantExpr>(WidthExpr);
2268  if (!CE) {
2269    Error(E, "'width' operand must be an immediate");
2270    return MatchOperand_ParseFail;
2271  }
2272
2273  int64_t Width = CE->getValue();
2274  // The LSB must be in the range [1,32-lsb]
2275  if (Width < 1 || Width > 32 - LSB) {
2276    Error(E, "'width' operand must be in the range [1,32-lsb]");
2277    return MatchOperand_ParseFail;
2278  }
2279  E = Parser.getTok().getLoc();
2280
2281  Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E));
2282
2283  return MatchOperand_Success;
2284}
2285
2286ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2287parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2288  // Check for a post-index addressing register operand. Specifically:
2289  // postidx_reg := '+' register {, shift}
2290  //              | '-' register {, shift}
2291  //              | register {, shift}
2292
2293  // This method must return MatchOperand_NoMatch without consuming any tokens
2294  // in the case where there is no match, as other alternatives take other
2295  // parse methods.
2296  AsmToken Tok = Parser.getTok();
2297  SMLoc S = Tok.getLoc();
2298  bool haveEaten = false;
2299  bool isAdd = true;
2300  int Reg = -1;
2301  if (Tok.is(AsmToken::Plus)) {
2302    Parser.Lex(); // Eat the '+' token.
2303    haveEaten = true;
2304  } else if (Tok.is(AsmToken::Minus)) {
2305    Parser.Lex(); // Eat the '-' token.
2306    isAdd = false;
2307    haveEaten = true;
2308  }
2309  if (Parser.getTok().is(AsmToken::Identifier))
2310    Reg = tryParseRegister();
2311  if (Reg == -1) {
2312    if (!haveEaten)
2313      return MatchOperand_NoMatch;
2314    Error(Parser.getTok().getLoc(), "register expected");
2315    return MatchOperand_ParseFail;
2316  }
2317  SMLoc E = Parser.getTok().getLoc();
2318
2319  ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
2320  unsigned ShiftImm = 0;
2321  if (Parser.getTok().is(AsmToken::Comma)) {
2322    Parser.Lex(); // Eat the ','.
2323    if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
2324      return MatchOperand_ParseFail;
2325  }
2326
2327  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
2328                                                  ShiftImm, S, E));
2329
2330  return MatchOperand_Success;
2331}
2332
2333ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2334parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2335  // Check for a post-index addressing register operand. Specifically:
2336  // am3offset := '+' register
2337  //              | '-' register
2338  //              | register
2339  //              | # imm
2340  //              | # + imm
2341  //              | # - imm
2342
2343  // This method must return MatchOperand_NoMatch without consuming any tokens
2344  // in the case where there is no match, as other alternatives take other
2345  // parse methods.
2346  AsmToken Tok = Parser.getTok();
2347  SMLoc S = Tok.getLoc();
2348
2349  // Do immediates first, as we always parse those if we have a '#'.
2350  if (Parser.getTok().is(AsmToken::Hash)) {
2351    Parser.Lex(); // Eat the '#'.
2352    // Explicitly look for a '-', as we need to encode negative zero
2353    // differently.
2354    bool isNegative = Parser.getTok().is(AsmToken::Minus);
2355    const MCExpr *Offset;
2356    if (getParser().ParseExpression(Offset))
2357      return MatchOperand_ParseFail;
2358    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
2359    if (!CE) {
2360      Error(S, "constant expression expected");
2361      return MatchOperand_ParseFail;
2362    }
2363    SMLoc E = Tok.getLoc();
2364    // Negative zero is encoded as the flag value INT32_MIN.
2365    int32_t Val = CE->getValue();
2366    if (isNegative && Val == 0)
2367      Val = INT32_MIN;
2368
2369    Operands.push_back(
2370      ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
2371
2372    return MatchOperand_Success;
2373  }
2374
2375
2376  bool haveEaten = false;
2377  bool isAdd = true;
2378  int Reg = -1;
2379  if (Tok.is(AsmToken::Plus)) {
2380    Parser.Lex(); // Eat the '+' token.
2381    haveEaten = true;
2382  } else if (Tok.is(AsmToken::Minus)) {
2383    Parser.Lex(); // Eat the '-' token.
2384    isAdd = false;
2385    haveEaten = true;
2386  }
2387  if (Parser.getTok().is(AsmToken::Identifier))
2388    Reg = tryParseRegister();
2389  if (Reg == -1) {
2390    if (!haveEaten)
2391      return MatchOperand_NoMatch;
2392    Error(Parser.getTok().getLoc(), "register expected");
2393    return MatchOperand_ParseFail;
2394  }
2395  SMLoc E = Parser.getTok().getLoc();
2396
2397  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
2398                                                  0, S, E));
2399
2400  return MatchOperand_Success;
2401}
2402
2403/// cvtLdWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
2404/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2405/// when they refer multiple MIOperands inside a single one.
2406bool ARMAsmParser::
2407cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
2408                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2409  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2410
2411  // Create a writeback register dummy placeholder.
2412  Inst.addOperand(MCOperand::CreateImm(0));
2413
2414  ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
2415  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2416  return true;
2417}
2418
2419/// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
2420/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2421/// when they refer multiple MIOperands inside a single one.
2422bool ARMAsmParser::
2423cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
2424                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2425  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2426
2427  // Create a writeback register dummy placeholder.
2428  Inst.addOperand(MCOperand::CreateImm(0));
2429
2430  ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
2431  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2432  return true;
2433}
2434
2435/// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
2436/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2437/// when they refer multiple MIOperands inside a single one.
2438bool ARMAsmParser::
2439cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
2440                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2441  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2442
2443  // Create a writeback register dummy placeholder.
2444  Inst.addOperand(MCOperand::CreateImm(0));
2445
2446  ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
2447  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2448  return true;
2449}
2450
2451
2452/// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
2453/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2454/// when they refer multiple MIOperands inside a single one.
2455bool ARMAsmParser::
2456cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
2457                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2458  // Create a writeback register dummy placeholder.
2459  Inst.addOperand(MCOperand::CreateImm(0));
2460  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2461  ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
2462  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2463  return true;
2464}
2465
2466/// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
2467/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2468/// when they refer multiple MIOperands inside a single one.
2469bool ARMAsmParser::
2470cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
2471                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2472  // Create a writeback register dummy placeholder.
2473  Inst.addOperand(MCOperand::CreateImm(0));
2474  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2475  ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
2476  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2477  return true;
2478}
2479
2480/// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
2481/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2482/// when they refer multiple MIOperands inside a single one.
2483bool ARMAsmParser::
2484cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
2485                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2486  // Create a writeback register dummy placeholder.
2487  Inst.addOperand(MCOperand::CreateImm(0));
2488  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2489  ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
2490  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2491  return true;
2492}
2493
2494/// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst.
2495/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2496/// when they refer multiple MIOperands inside a single one.
2497bool ARMAsmParser::
2498cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
2499                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2500  // Rt
2501  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2502  // Create a writeback register dummy placeholder.
2503  Inst.addOperand(MCOperand::CreateImm(0));
2504  // addr
2505  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2506  // offset
2507  ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
2508  // pred
2509  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2510  return true;
2511}
2512
2513/// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst.
2514/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2515/// when they refer multiple MIOperands inside a single one.
2516bool ARMAsmParser::
2517cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
2518                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2519  // Rt
2520  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2521  // Create a writeback register dummy placeholder.
2522  Inst.addOperand(MCOperand::CreateImm(0));
2523  // addr
2524  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2525  // offset
2526  ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
2527  // pred
2528  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2529  return true;
2530}
2531
2532/// cvtStExtTWriteBackImm - Convert parsed operands to MCInst.
2533/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2534/// when they refer multiple MIOperands inside a single one.
2535bool ARMAsmParser::
2536cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
2537                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2538  // Create a writeback register dummy placeholder.
2539  Inst.addOperand(MCOperand::CreateImm(0));
2540  // Rt
2541  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2542  // addr
2543  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2544  // offset
2545  ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
2546  // pred
2547  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2548  return true;
2549}
2550
2551/// cvtStExtTWriteBackReg - Convert parsed operands to MCInst.
2552/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2553/// when they refer multiple MIOperands inside a single one.
2554bool ARMAsmParser::
2555cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
2556                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2557  // Create a writeback register dummy placeholder.
2558  Inst.addOperand(MCOperand::CreateImm(0));
2559  // Rt
2560  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2561  // addr
2562  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2563  // offset
2564  ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
2565  // pred
2566  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2567  return true;
2568}
2569
2570/// cvtLdrdPre - Convert parsed operands to MCInst.
2571/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2572/// when they refer multiple MIOperands inside a single one.
2573bool ARMAsmParser::
2574cvtLdrdPre(MCInst &Inst, unsigned Opcode,
2575           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2576  // Rt, Rt2
2577  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2578  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2579  // Create a writeback register dummy placeholder.
2580  Inst.addOperand(MCOperand::CreateImm(0));
2581  // addr
2582  ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
2583  // pred
2584  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2585  return true;
2586}
2587
2588/// cvtStrdPre - Convert parsed operands to MCInst.
2589/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2590/// when they refer multiple MIOperands inside a single one.
2591bool ARMAsmParser::
2592cvtStrdPre(MCInst &Inst, unsigned Opcode,
2593           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2594  // Create a writeback register dummy placeholder.
2595  Inst.addOperand(MCOperand::CreateImm(0));
2596  // Rt, Rt2
2597  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2598  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2599  // addr
2600  ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
2601  // pred
2602  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2603  return true;
2604}
2605
2606/// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
2607/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2608/// when they refer multiple MIOperands inside a single one.
2609bool ARMAsmParser::
2610cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
2611                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2612  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2613  // Create a writeback register dummy placeholder.
2614  Inst.addOperand(MCOperand::CreateImm(0));
2615  ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
2616  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2617  return true;
2618}
2619
2620/// cvtThumbMultiple- Convert parsed operands to MCInst.
2621/// Needed here because the Asm Gen Matcher can't handle properly tied operands
2622/// when they refer multiple MIOperands inside a single one.
2623bool ARMAsmParser::
2624cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
2625           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2626  // The second source operand must be the same register as the destination
2627  // operand.
2628  if (Operands.size() == 6 &&
2629      (((ARMOperand*)Operands[3])->getReg() !=
2630       ((ARMOperand*)Operands[5])->getReg()) &&
2631      (((ARMOperand*)Operands[3])->getReg() !=
2632       ((ARMOperand*)Operands[4])->getReg())) {
2633    Error(Operands[3]->getStartLoc(),
2634          "destination register must match source register");
2635    return false;
2636  }
2637  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2638  ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
2639  ((ARMOperand*)Operands[4])->addRegOperands(Inst, 1);
2640  // If we have a three-operand form, use that, else the second source operand
2641  // is just the destination operand again.
2642  if (Operands.size() == 6)
2643    ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
2644  else
2645    Inst.addOperand(Inst.getOperand(0));
2646  ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
2647
2648  return true;
2649}
2650
2651/// Parse an ARM memory expression, return false if successful else return true
2652/// or an error.  The first token must be a '[' when called.
2653bool ARMAsmParser::
2654parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2655  SMLoc S, E;
2656  assert(Parser.getTok().is(AsmToken::LBrac) &&
2657         "Token is not a Left Bracket");
2658  S = Parser.getTok().getLoc();
2659  Parser.Lex(); // Eat left bracket token.
2660
2661  const AsmToken &BaseRegTok = Parser.getTok();
2662  int BaseRegNum = tryParseRegister();
2663  if (BaseRegNum == -1)
2664    return Error(BaseRegTok.getLoc(), "register expected");
2665
2666  // The next token must either be a comma or a closing bracket.
2667  const AsmToken &Tok = Parser.getTok();
2668  if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac))
2669    return Error(Tok.getLoc(), "malformed memory operand");
2670
2671  if (Tok.is(AsmToken::RBrac)) {
2672    E = Tok.getLoc();
2673    Parser.Lex(); // Eat right bracket token.
2674
2675    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
2676                                             0, false, S, E));
2677
2678    return false;
2679  }
2680
2681  assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!");
2682  Parser.Lex(); // Eat the comma.
2683
2684  // If we have a '#' it's an immediate offset, else assume it's a register
2685  // offset.
2686  if (Parser.getTok().is(AsmToken::Hash)) {
2687    Parser.Lex(); // Eat the '#'.
2688    E = Parser.getTok().getLoc();
2689
2690    bool isNegative = getParser().getTok().is(AsmToken::Minus);
2691    const MCExpr *Offset;
2692    if (getParser().ParseExpression(Offset))
2693     return true;
2694
2695    // The expression has to be a constant. Memory references with relocations
2696    // don't come through here, as they use the <label> forms of the relevant
2697    // instructions.
2698    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
2699    if (!CE)
2700      return Error (E, "constant expression expected");
2701
2702    // If the constant was #-0, represent it as INT32_MIN.
2703    int32_t Val = CE->getValue();
2704    if (isNegative && Val == 0)
2705      CE = MCConstantExpr::Create(INT32_MIN, getContext());
2706
2707    // Now we should have the closing ']'
2708    E = Parser.getTok().getLoc();
2709    if (Parser.getTok().isNot(AsmToken::RBrac))
2710      return Error(E, "']' expected");
2711    Parser.Lex(); // Eat right bracket token.
2712
2713    // Don't worry about range checking the value here. That's handled by
2714    // the is*() predicates.
2715    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
2716                                             ARM_AM::no_shift, 0, false, S,E));
2717
2718    // If there's a pre-indexing writeback marker, '!', just add it as a token
2719    // operand.
2720    if (Parser.getTok().is(AsmToken::Exclaim)) {
2721      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
2722      Parser.Lex(); // Eat the '!'.
2723    }
2724
2725    return false;
2726  }
2727
2728  // The register offset is optionally preceded by a '+' or '-'
2729  bool isNegative = false;
2730  if (Parser.getTok().is(AsmToken::Minus)) {
2731    isNegative = true;
2732    Parser.Lex(); // Eat the '-'.
2733  } else if (Parser.getTok().is(AsmToken::Plus)) {
2734    // Nothing to do.
2735    Parser.Lex(); // Eat the '+'.
2736  }
2737
2738  E = Parser.getTok().getLoc();
2739  int OffsetRegNum = tryParseRegister();
2740  if (OffsetRegNum == -1)
2741    return Error(E, "register expected");
2742
2743  // If there's a shift operator, handle it.
2744  ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
2745  unsigned ShiftImm = 0;
2746  if (Parser.getTok().is(AsmToken::Comma)) {
2747    Parser.Lex(); // Eat the ','.
2748    if (parseMemRegOffsetShift(ShiftType, ShiftImm))
2749      return true;
2750  }
2751
2752  // Now we should have the closing ']'
2753  E = Parser.getTok().getLoc();
2754  if (Parser.getTok().isNot(AsmToken::RBrac))
2755    return Error(E, "']' expected");
2756  Parser.Lex(); // Eat right bracket token.
2757
2758  Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
2759                                           ShiftType, ShiftImm, isNegative,
2760                                           S, E));
2761
2762  // If there's a pre-indexing writeback marker, '!', just add it as a token
2763  // operand.
2764  if (Parser.getTok().is(AsmToken::Exclaim)) {
2765    Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
2766    Parser.Lex(); // Eat the '!'.
2767  }
2768
2769  return false;
2770}
2771
2772/// parseMemRegOffsetShift - one of these two:
2773///   ( lsl | lsr | asr | ror ) , # shift_amount
2774///   rrx
2775/// return true if it parses a shift otherwise it returns false.
2776bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
2777                                          unsigned &Amount) {
2778  SMLoc Loc = Parser.getTok().getLoc();
2779  const AsmToken &Tok = Parser.getTok();
2780  if (Tok.isNot(AsmToken::Identifier))
2781    return true;
2782  StringRef ShiftName = Tok.getString();
2783  if (ShiftName == "lsl" || ShiftName == "LSL")
2784    St = ARM_AM::lsl;
2785  else if (ShiftName == "lsr" || ShiftName == "LSR")
2786    St = ARM_AM::lsr;
2787  else if (ShiftName == "asr" || ShiftName == "ASR")
2788    St = ARM_AM::asr;
2789  else if (ShiftName == "ror" || ShiftName == "ROR")
2790    St = ARM_AM::ror;
2791  else if (ShiftName == "rrx" || ShiftName == "RRX")
2792    St = ARM_AM::rrx;
2793  else
2794    return Error(Loc, "illegal shift operator");
2795  Parser.Lex(); // Eat shift type token.
2796
2797  // rrx stands alone.
2798  Amount = 0;
2799  if (St != ARM_AM::rrx) {
2800    Loc = Parser.getTok().getLoc();
2801    // A '#' and a shift amount.
2802    const AsmToken &HashTok = Parser.getTok();
2803    if (HashTok.isNot(AsmToken::Hash))
2804      return Error(HashTok.getLoc(), "'#' expected");
2805    Parser.Lex(); // Eat hash token.
2806
2807    const MCExpr *Expr;
2808    if (getParser().ParseExpression(Expr))
2809      return true;
2810    // Range check the immediate.
2811    // lsl, ror: 0 <= imm <= 31
2812    // lsr, asr: 0 <= imm <= 32
2813    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2814    if (!CE)
2815      return Error(Loc, "shift amount must be an immediate");
2816    int64_t Imm = CE->getValue();
2817    if (Imm < 0 ||
2818        ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
2819        ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
2820      return Error(Loc, "immediate shift value out of range");
2821    Amount = Imm;
2822  }
2823
2824  return false;
2825}
2826
2827/// Parse a arm instruction operand.  For now this parses the operand regardless
2828/// of the mnemonic.
2829bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
2830                                StringRef Mnemonic) {
2831  SMLoc S, E;
2832
2833  // Check if the current operand has a custom associated parser, if so, try to
2834  // custom parse the operand, or fallback to the general approach.
2835  OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
2836  if (ResTy == MatchOperand_Success)
2837    return false;
2838  // If there wasn't a custom match, try the generic matcher below. Otherwise,
2839  // there was a match, but an error occurred, in which case, just return that
2840  // the operand parsing failed.
2841  if (ResTy == MatchOperand_ParseFail)
2842    return true;
2843
2844  switch (getLexer().getKind()) {
2845  default:
2846    Error(Parser.getTok().getLoc(), "unexpected token in operand");
2847    return true;
2848  case AsmToken::Identifier: {
2849    if (!tryParseRegisterWithWriteBack(Operands))
2850      return false;
2851    int Res = tryParseShiftRegister(Operands);
2852    if (Res == 0) // success
2853      return false;
2854    else if (Res == -1) // irrecoverable error
2855      return true;
2856
2857    // Fall though for the Identifier case that is not a register or a
2858    // special name.
2859  }
2860  case AsmToken::Integer: // things like 1f and 2b as a branch targets
2861  case AsmToken::Dot: {   // . as a branch target
2862    // This was not a register so parse other operands that start with an
2863    // identifier (like labels) as expressions and create them as immediates.
2864    const MCExpr *IdVal;
2865    S = Parser.getTok().getLoc();
2866    if (getParser().ParseExpression(IdVal))
2867      return true;
2868    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2869    Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
2870    return false;
2871  }
2872  case AsmToken::LBrac:
2873    return parseMemory(Operands);
2874  case AsmToken::LCurly:
2875    return parseRegisterList(Operands);
2876  case AsmToken::Hash: {
2877    // #42 -> immediate.
2878    // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
2879    S = Parser.getTok().getLoc();
2880    Parser.Lex();
2881    bool isNegative = Parser.getTok().is(AsmToken::Minus);
2882    const MCExpr *ImmVal;
2883    if (getParser().ParseExpression(ImmVal))
2884      return true;
2885    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
2886    if (!CE) {
2887      Error(S, "constant expression expected");
2888      return MatchOperand_ParseFail;
2889    }
2890    int32_t Val = CE->getValue();
2891    if (isNegative && Val == 0)
2892      ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
2893    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2894    Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
2895    return false;
2896  }
2897  case AsmToken::Colon: {
2898    // ":lower16:" and ":upper16:" expression prefixes
2899    // FIXME: Check it's an expression prefix,
2900    // e.g. (FOO - :lower16:BAR) isn't legal.
2901    ARMMCExpr::VariantKind RefKind;
2902    if (parsePrefix(RefKind))
2903      return true;
2904
2905    const MCExpr *SubExprVal;
2906    if (getParser().ParseExpression(SubExprVal))
2907      return true;
2908
2909    const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
2910                                                   getContext());
2911    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2912    Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
2913    return false;
2914  }
2915  }
2916}
2917
2918// parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
2919//  :lower16: and :upper16:.
2920bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
2921  RefKind = ARMMCExpr::VK_ARM_None;
2922
2923  // :lower16: and :upper16: modifiers
2924  assert(getLexer().is(AsmToken::Colon) && "expected a :");
2925  Parser.Lex(); // Eat ':'
2926
2927  if (getLexer().isNot(AsmToken::Identifier)) {
2928    Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
2929    return true;
2930  }
2931
2932  StringRef IDVal = Parser.getTok().getIdentifier();
2933  if (IDVal == "lower16") {
2934    RefKind = ARMMCExpr::VK_ARM_LO16;
2935  } else if (IDVal == "upper16") {
2936    RefKind = ARMMCExpr::VK_ARM_HI16;
2937  } else {
2938    Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
2939    return true;
2940  }
2941  Parser.Lex();
2942
2943  if (getLexer().isNot(AsmToken::Colon)) {
2944    Error(Parser.getTok().getLoc(), "unexpected token after prefix");
2945    return true;
2946  }
2947  Parser.Lex(); // Eat the last ':'
2948  return false;
2949}
2950
2951const MCExpr *
2952ARMAsmParser::applyPrefixToExpr(const MCExpr *E,
2953                                MCSymbolRefExpr::VariantKind Variant) {
2954  // Recurse over the given expression, rebuilding it to apply the given variant
2955  // to the leftmost symbol.
2956  if (Variant == MCSymbolRefExpr::VK_None)
2957    return E;
2958
2959  switch (E->getKind()) {
2960  case MCExpr::Target:
2961    llvm_unreachable("Can't handle target expr yet");
2962  case MCExpr::Constant:
2963    llvm_unreachable("Can't handle lower16/upper16 of constant yet");
2964
2965  case MCExpr::SymbolRef: {
2966    const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
2967
2968    if (SRE->getKind() != MCSymbolRefExpr::VK_None)
2969      return 0;
2970
2971    return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, getContext());
2972  }
2973
2974  case MCExpr::Unary:
2975    llvm_unreachable("Can't handle unary expressions yet");
2976
2977  case MCExpr::Binary: {
2978    const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
2979    const MCExpr *LHS = applyPrefixToExpr(BE->getLHS(), Variant);
2980    const MCExpr *RHS = BE->getRHS();
2981    if (!LHS)
2982      return 0;
2983
2984    return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, getContext());
2985  }
2986  }
2987
2988  assert(0 && "Invalid expression kind!");
2989  return 0;
2990}
2991
2992/// \brief Given a mnemonic, split out possible predication code and carry
2993/// setting letters to form a canonical mnemonic and flags.
2994//
2995// FIXME: Would be nice to autogen this.
2996// FIXME: This is a bit of a maze of special cases.
2997StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
2998                                      unsigned &PredicationCode,
2999                                      bool &CarrySetting,
3000                                      unsigned &ProcessorIMod,
3001                                      StringRef &ITMask) {
3002  PredicationCode = ARMCC::AL;
3003  CarrySetting = false;
3004  ProcessorIMod = 0;
3005
3006  // Ignore some mnemonics we know aren't predicated forms.
3007  //
3008  // FIXME: Would be nice to autogen this.
3009  if ((Mnemonic == "movs" && isThumb()) ||
3010      Mnemonic == "teq"   || Mnemonic == "vceq"   || Mnemonic == "svc"   ||
3011      Mnemonic == "mls"   || Mnemonic == "smmls"  || Mnemonic == "vcls"  ||
3012      Mnemonic == "vmls"  || Mnemonic == "vnmls"  || Mnemonic == "vacge" ||
3013      Mnemonic == "vcge"  || Mnemonic == "vclt"   || Mnemonic == "vacgt" ||
3014      Mnemonic == "vcgt"  || Mnemonic == "vcle"   || Mnemonic == "smlal" ||
3015      Mnemonic == "umaal" || Mnemonic == "umlal"  || Mnemonic == "vabal" ||
3016      Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal")
3017    return Mnemonic;
3018
3019  // First, split out any predication code. Ignore mnemonics we know aren't
3020  // predicated but do have a carry-set and so weren't caught above.
3021  if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
3022      Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
3023      Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
3024      Mnemonic != "sbcs" && Mnemonic != "rscs") {
3025    unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
3026      .Case("eq", ARMCC::EQ)
3027      .Case("ne", ARMCC::NE)
3028      .Case("hs", ARMCC::HS)
3029      .Case("cs", ARMCC::HS)
3030      .Case("lo", ARMCC::LO)
3031      .Case("cc", ARMCC::LO)
3032      .Case("mi", ARMCC::MI)
3033      .Case("pl", ARMCC::PL)
3034      .Case("vs", ARMCC::VS)
3035      .Case("vc", ARMCC::VC)
3036      .Case("hi", ARMCC::HI)
3037      .Case("ls", ARMCC::LS)
3038      .Case("ge", ARMCC::GE)
3039      .Case("lt", ARMCC::LT)
3040      .Case("gt", ARMCC::GT)
3041      .Case("le", ARMCC::LE)
3042      .Case("al", ARMCC::AL)
3043      .Default(~0U);
3044    if (CC != ~0U) {
3045      Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
3046      PredicationCode = CC;
3047    }
3048  }
3049
3050  // Next, determine if we have a carry setting bit. We explicitly ignore all
3051  // the instructions we know end in 's'.
3052  if (Mnemonic.endswith("s") &&
3053      !(Mnemonic == "cps" || Mnemonic == "mls" ||
3054        Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
3055        Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
3056        Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
3057        Mnemonic == "vrsqrts" || Mnemonic == "srs" ||
3058        (Mnemonic == "movs" && isThumb()))) {
3059    Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
3060    CarrySetting = true;
3061  }
3062
3063  // The "cps" instruction can have a interrupt mode operand which is glued into
3064  // the mnemonic. Check if this is the case, split it and parse the imod op
3065  if (Mnemonic.startswith("cps")) {
3066    // Split out any imod code.
3067    unsigned IMod =
3068      StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
3069      .Case("ie", ARM_PROC::IE)
3070      .Case("id", ARM_PROC::ID)
3071      .Default(~0U);
3072    if (IMod != ~0U) {
3073      Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
3074      ProcessorIMod = IMod;
3075    }
3076  }
3077
3078  // The "it" instruction has the condition mask on the end of the mnemonic.
3079  if (Mnemonic.startswith("it")) {
3080    ITMask = Mnemonic.slice(2, Mnemonic.size());
3081    Mnemonic = Mnemonic.slice(0, 2);
3082  }
3083
3084  return Mnemonic;
3085}
3086
3087/// \brief Given a canonical mnemonic, determine if the instruction ever allows
3088/// inclusion of carry set or predication code operands.
3089//
3090// FIXME: It would be nice to autogen this.
3091void ARMAsmParser::
3092getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
3093                      bool &CanAcceptPredicationCode) {
3094  if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
3095      Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
3096      Mnemonic == "smull" || Mnemonic == "add" || Mnemonic == "adc" ||
3097      Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
3098      Mnemonic == "umlal" || Mnemonic == "orr" || Mnemonic == "mvn" ||
3099      Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
3100      Mnemonic == "sbc" || Mnemonic == "mla" || Mnemonic == "umull" ||
3101      Mnemonic == "eor" || Mnemonic == "smlal" || Mnemonic == "neg" ||
3102      (Mnemonic == "mov" && !isThumb())) {
3103    CanAcceptCarrySet = true;
3104  } else {
3105    CanAcceptCarrySet = false;
3106  }
3107
3108  if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
3109      Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
3110      Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
3111      Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
3112      Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "setend" ||
3113      (Mnemonic == "clrex" && !isThumb()) ||
3114      (Mnemonic == "nop" && isThumbOne()) ||
3115      ((Mnemonic == "pld" || Mnemonic == "pli" || Mnemonic == "pldw") &&
3116       !isThumb()) ||
3117      ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs")) &&
3118       !isThumb()) ||
3119      Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumb())) {
3120    CanAcceptPredicationCode = false;
3121  } else {
3122    CanAcceptPredicationCode = true;
3123  }
3124
3125  if (isThumb())
3126    if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
3127        Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
3128      CanAcceptPredicationCode = false;
3129}
3130
3131bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
3132                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3133  // FIXME: This is all horribly hacky. We really need a better way to deal
3134  // with optional operands like this in the matcher table.
3135
3136  // The 'mov' mnemonic is special. One variant has a cc_out operand, while
3137  // another does not. Specifically, the MOVW instruction does not. So we
3138  // special case it here and remove the defaulted (non-setting) cc_out
3139  // operand if that's the instruction we're trying to match.
3140  //
3141  // We do this as post-processing of the explicit operands rather than just
3142  // conditionally adding the cc_out in the first place because we need
3143  // to check the type of the parsed immediate operand.
3144  if (Mnemonic == "mov" && Operands.size() > 4 &&
3145      !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
3146      static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
3147      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
3148    return true;
3149
3150  // Register-register 'add' for thumb does not have a cc_out operand
3151  // when there are only two register operands.
3152  if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
3153      static_cast<ARMOperand*>(Operands[3])->isReg() &&
3154      static_cast<ARMOperand*>(Operands[4])->isReg() &&
3155      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
3156    return true;
3157  // Register-register 'add' for thumb does not have a cc_out operand
3158  // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
3159  // have to check the immediate range here since Thumb2 has a variant
3160  // that can handle a different range and has a cc_out operand.
3161  if (isThumb() && Mnemonic == "add" && Operands.size() == 6 &&
3162      static_cast<ARMOperand*>(Operands[3])->isReg() &&
3163      static_cast<ARMOperand*>(Operands[4])->isReg() &&
3164      static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
3165      static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
3166      (static_cast<ARMOperand*>(Operands[5])->isReg() ||
3167       static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
3168    return true;
3169  // For Thumb2, add immediate does not have a cc_out operand for the
3170  // imm0_4096 variant. That's the least-preferred variant when
3171  // selecting via the generic "add" mnemonic, so to know that we
3172  // should remove the cc_out operand, we have to explicitly check that
3173  // it's not one of the other variants. Ugh.
3174  if (isThumbTwo() && Mnemonic == "add" && Operands.size() == 6 &&
3175      static_cast<ARMOperand*>(Operands[3])->isReg() &&
3176      static_cast<ARMOperand*>(Operands[4])->isReg() &&
3177      static_cast<ARMOperand*>(Operands[5])->isImm()) {
3178    // Nest conditions rather than one big 'if' statement for readability.
3179    //
3180    // If either register is a high reg, it's either one of the SP
3181    // variants (handled above) or a 32-bit encoding, so we just
3182    // check against T3.
3183    if ((!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
3184         !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg())) &&
3185        static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
3186      return false;
3187    // If both registers are low, we're in an IT block, and the immediate is
3188    // in range, we should use encoding T1 instead, which has a cc_out.
3189    if (inITBlock() &&
3190        isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
3191        isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
3192        static_cast<ARMOperand*>(Operands[5])->isImm0_7())
3193      return false;
3194
3195    // Otherwise, we use encoding T4, which does not have a cc_out
3196    // operand.
3197    return true;
3198  }
3199
3200
3201  // Register-register 'add/sub' for thumb does not have a cc_out operand
3202  // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
3203  // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
3204  // right, this will result in better diagnostics (which operand is off)
3205  // anyway.
3206  if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
3207      (Operands.size() == 5 || Operands.size() == 6) &&
3208      static_cast<ARMOperand*>(Operands[3])->isReg() &&
3209      static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
3210      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
3211    return true;
3212
3213  return false;
3214}
3215
3216/// Parse an arm instruction mnemonic followed by its operands.
3217bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
3218                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3219  // Create the leading tokens for the mnemonic, split by '.' characters.
3220  size_t Start = 0, Next = Name.find('.');
3221  StringRef Mnemonic = Name.slice(Start, Next);
3222
3223  // Split out the predication code and carry setting flag from the mnemonic.
3224  unsigned PredicationCode;
3225  unsigned ProcessorIMod;
3226  bool CarrySetting;
3227  StringRef ITMask;
3228  Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
3229                           ProcessorIMod, ITMask);
3230
3231  // In Thumb1, only the branch (B) instruction can be predicated.
3232  if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
3233    Parser.EatToEndOfStatement();
3234    return Error(NameLoc, "conditional execution not supported in Thumb1");
3235  }
3236
3237  Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
3238
3239  // Handle the IT instruction ITMask. Convert it to a bitmask. This
3240  // is the mask as it will be for the IT encoding if the conditional
3241  // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
3242  // where the conditional bit0 is zero, the instruction post-processing
3243  // will adjust the mask accordingly.
3244  if (Mnemonic == "it") {
3245    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
3246    if (ITMask.size() > 3) {
3247      Parser.EatToEndOfStatement();
3248      return Error(Loc, "too many conditions on IT instruction");
3249    }
3250    unsigned Mask = 8;
3251    for (unsigned i = ITMask.size(); i != 0; --i) {
3252      char pos = ITMask[i - 1];
3253      if (pos != 't' && pos != 'e') {
3254        Parser.EatToEndOfStatement();
3255        return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
3256      }
3257      Mask >>= 1;
3258      if (ITMask[i - 1] == 't')
3259        Mask |= 8;
3260    }
3261    Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
3262  }
3263
3264  // FIXME: This is all a pretty gross hack. We should automatically handle
3265  // optional operands like this via tblgen.
3266
3267  // Next, add the CCOut and ConditionCode operands, if needed.
3268  //
3269  // For mnemonics which can ever incorporate a carry setting bit or predication
3270  // code, our matching model involves us always generating CCOut and
3271  // ConditionCode operands to match the mnemonic "as written" and then we let
3272  // the matcher deal with finding the right instruction or generating an
3273  // appropriate error.
3274  bool CanAcceptCarrySet, CanAcceptPredicationCode;
3275  getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
3276
3277  // If we had a carry-set on an instruction that can't do that, issue an
3278  // error.
3279  if (!CanAcceptCarrySet && CarrySetting) {
3280    Parser.EatToEndOfStatement();
3281    return Error(NameLoc, "instruction '" + Mnemonic +
3282                 "' can not set flags, but 's' suffix specified");
3283  }
3284  // If we had a predication code on an instruction that can't do that, issue an
3285  // error.
3286  if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
3287    Parser.EatToEndOfStatement();
3288    return Error(NameLoc, "instruction '" + Mnemonic +
3289                 "' is not predicable, but condition code specified");
3290  }
3291
3292  // Add the carry setting operand, if necessary.
3293  if (CanAcceptCarrySet) {
3294    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
3295    Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
3296                                               Loc));
3297  }
3298
3299  // Add the predication code operand, if necessary.
3300  if (CanAcceptPredicationCode) {
3301    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
3302                                      CarrySetting);
3303    Operands.push_back(ARMOperand::CreateCondCode(
3304                         ARMCC::CondCodes(PredicationCode), Loc));
3305  }
3306
3307  // Add the processor imod operand, if necessary.
3308  if (ProcessorIMod) {
3309    Operands.push_back(ARMOperand::CreateImm(
3310          MCConstantExpr::Create(ProcessorIMod, getContext()),
3311                                 NameLoc, NameLoc));
3312  }
3313
3314  // Add the remaining tokens in the mnemonic.
3315  while (Next != StringRef::npos) {
3316    Start = Next;
3317    Next = Name.find('.', Start + 1);
3318    StringRef ExtraToken = Name.slice(Start, Next);
3319
3320    // For now, we're only parsing Thumb1 (for the most part), so
3321    // just ignore ".n" qualifiers. We'll use them to restrict
3322    // matching when we do Thumb2.
3323    if (ExtraToken != ".n") {
3324      SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
3325      Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
3326    }
3327  }
3328
3329  // Read the remaining operands.
3330  if (getLexer().isNot(AsmToken::EndOfStatement)) {
3331    // Read the first operand.
3332    if (parseOperand(Operands, Mnemonic)) {
3333      Parser.EatToEndOfStatement();
3334      return true;
3335    }
3336
3337    while (getLexer().is(AsmToken::Comma)) {
3338      Parser.Lex();  // Eat the comma.
3339
3340      // Parse and remember the operand.
3341      if (parseOperand(Operands, Mnemonic)) {
3342        Parser.EatToEndOfStatement();
3343        return true;
3344      }
3345    }
3346  }
3347
3348  if (getLexer().isNot(AsmToken::EndOfStatement)) {
3349    Parser.EatToEndOfStatement();
3350    return TokError("unexpected token in argument list");
3351  }
3352
3353  Parser.Lex(); // Consume the EndOfStatement
3354
3355  // Some instructions, mostly Thumb, have forms for the same mnemonic that
3356  // do and don't have a cc_out optional-def operand. With some spot-checks
3357  // of the operand list, we can figure out which variant we're trying to
3358  // parse and adjust accordingly before actually matching. We shouldn't ever
3359  // try to remove a cc_out operand that was explicitly set on the the
3360  // mnemonic, of course (CarrySetting == true). Reason number #317 the
3361  // table driven matcher doesn't fit well with the ARM instruction set.
3362  if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
3363    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
3364    Operands.erase(Operands.begin() + 1);
3365    delete Op;
3366  }
3367
3368  // ARM mode 'blx' need special handling, as the register operand version
3369  // is predicable, but the label operand version is not. So, we can't rely
3370  // on the Mnemonic based checking to correctly figure out when to put
3371  // a CondCode operand in the list. If we're trying to match the label
3372  // version, remove the CondCode operand here.
3373  if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
3374      static_cast<ARMOperand*>(Operands[2])->isImm()) {
3375    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
3376    Operands.erase(Operands.begin() + 1);
3377    delete Op;
3378  }
3379
3380  // The vector-compare-to-zero instructions have a literal token "#0" at
3381  // the end that comes to here as an immediate operand. Convert it to a
3382  // token to play nicely with the matcher.
3383  if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" ||
3384      Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 &&
3385      static_cast<ARMOperand*>(Operands[5])->isImm()) {
3386    ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
3387    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
3388    if (CE && CE->getValue() == 0) {
3389      Operands.erase(Operands.begin() + 5);
3390      Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
3391      delete Op;
3392    }
3393  }
3394  // Similarly, the Thumb1 "RSB" instruction has a literal "#0" on the
3395  // end. Convert it to a token here.
3396  if (Mnemonic == "rsb" && isThumb() && Operands.size() == 6 &&
3397      static_cast<ARMOperand*>(Operands[5])->isImm()) {
3398    ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
3399    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
3400    if (CE && CE->getValue() == 0) {
3401      Operands.erase(Operands.begin() + 5);
3402      Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
3403      delete Op;
3404    }
3405  }
3406
3407  return false;
3408}
3409
3410// Validate context-sensitive operand constraints.
3411
3412// return 'true' if register list contains non-low GPR registers,
3413// 'false' otherwise. If Reg is in the register list or is HiReg, set
3414// 'containsReg' to true.
3415static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
3416                                 unsigned HiReg, bool &containsReg) {
3417  containsReg = false;
3418  for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
3419    unsigned OpReg = Inst.getOperand(i).getReg();
3420    if (OpReg == Reg)
3421      containsReg = true;
3422    // Anything other than a low register isn't legal here.
3423    if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
3424      return true;
3425  }
3426  return false;
3427}
3428
3429// Check if the specified regisgter is in the register list of the inst,
3430// starting at the indicated operand number.
3431static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
3432  for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
3433    unsigned OpReg = Inst.getOperand(i).getReg();
3434    if (OpReg == Reg)
3435      return true;
3436  }
3437  return false;
3438}
3439
3440// FIXME: We would really prefer to have MCInstrInfo (the wrapper around
3441// the ARMInsts array) instead. Getting that here requires awkward
3442// API changes, though. Better way?
3443namespace llvm {
3444extern MCInstrDesc ARMInsts[];
3445}
3446static MCInstrDesc &getInstDesc(unsigned Opcode) {
3447  return ARMInsts[Opcode];
3448}
3449
3450// FIXME: We would really like to be able to tablegen'erate this.
3451bool ARMAsmParser::
3452validateInstruction(MCInst &Inst,
3453                    const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3454  MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
3455  SMLoc Loc = Operands[0]->getStartLoc();
3456  // Check the IT block state first.
3457  if (inITBlock()) {
3458    unsigned bit = 1;
3459    if (ITState.FirstCond)
3460      ITState.FirstCond = false;
3461    else
3462      bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
3463    // The instruction must be predicable.
3464    if (!MCID.isPredicable())
3465      return Error(Loc, "instructions in IT block must be predicable");
3466    unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
3467    unsigned ITCond = bit ? ITState.Cond :
3468      ARMCC::getOppositeCondition(ITState.Cond);
3469    if (Cond != ITCond) {
3470      // Find the condition code Operand to get its SMLoc information.
3471      SMLoc CondLoc;
3472      for (unsigned i = 1; i < Operands.size(); ++i)
3473        if (static_cast<ARMOperand*>(Operands[i])->isCondCode())
3474          CondLoc = Operands[i]->getStartLoc();
3475      return Error(CondLoc, "incorrect condition in IT block; got '" +
3476                   StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
3477                   "', but expected '" +
3478                   ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
3479    }
3480  // Check for non-'al' condition codes outside of the IT block.
3481  } else if (isThumbTwo() && MCID.isPredicable() &&
3482             Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
3483             ARMCC::AL && Inst.getOpcode() != ARM::tBcc &&
3484             Inst.getOpcode() != ARM::t2Bcc)
3485    return Error(Loc, "predicated instructions must be in IT block");
3486
3487  switch (Inst.getOpcode()) {
3488  case ARM::LDRD:
3489  case ARM::LDRD_PRE:
3490  case ARM::LDRD_POST:
3491  case ARM::LDREXD: {
3492    // Rt2 must be Rt + 1.
3493    unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
3494    unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
3495    if (Rt2 != Rt + 1)
3496      return Error(Operands[3]->getStartLoc(),
3497                   "destination operands must be sequential");
3498    return false;
3499  }
3500  case ARM::STRD: {
3501    // Rt2 must be Rt + 1.
3502    unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
3503    unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
3504    if (Rt2 != Rt + 1)
3505      return Error(Operands[3]->getStartLoc(),
3506                   "source operands must be sequential");
3507    return false;
3508  }
3509  case ARM::STRD_PRE:
3510  case ARM::STRD_POST:
3511  case ARM::STREXD: {
3512    // Rt2 must be Rt + 1.
3513    unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg());
3514    unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(2).getReg());
3515    if (Rt2 != Rt + 1)
3516      return Error(Operands[3]->getStartLoc(),
3517                   "source operands must be sequential");
3518    return false;
3519  }
3520  case ARM::SBFX:
3521  case ARM::UBFX: {
3522    // width must be in range [1, 32-lsb]
3523    unsigned lsb = Inst.getOperand(2).getImm();
3524    unsigned widthm1 = Inst.getOperand(3).getImm();
3525    if (widthm1 >= 32 - lsb)
3526      return Error(Operands[5]->getStartLoc(),
3527                   "bitfield width must be in range [1,32-lsb]");
3528    return false;
3529  }
3530  case ARM::tLDMIA: {
3531    // If we're parsing Thumb2, the .w variant is available and handles
3532    // most cases that are normally illegal for a Thumb1 LDM
3533    // instruction. We'll make the transformation in processInstruction()
3534    // if necessary.
3535    //
3536    // Thumb LDM instructions are writeback iff the base register is not
3537    // in the register list.
3538    unsigned Rn = Inst.getOperand(0).getReg();
3539    bool hasWritebackToken =
3540      (static_cast<ARMOperand*>(Operands[3])->isToken() &&
3541       static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
3542    bool listContainsBase;
3543    if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo())
3544      return Error(Operands[3 + hasWritebackToken]->getStartLoc(),
3545                   "registers must be in range r0-r7");
3546    // If we should have writeback, then there should be a '!' token.
3547    if (!listContainsBase && !hasWritebackToken && !isThumbTwo())
3548      return Error(Operands[2]->getStartLoc(),
3549                   "writeback operator '!' expected");
3550    // If we should not have writeback, there must not be a '!'. This is
3551    // true even for the 32-bit wide encodings.
3552    if (listContainsBase && hasWritebackToken)
3553      return Error(Operands[3]->getStartLoc(),
3554                   "writeback operator '!' not allowed when base register "
3555                   "in register list");
3556
3557    break;
3558  }
3559  case ARM::t2LDMIA_UPD: {
3560    if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
3561      return Error(Operands[4]->getStartLoc(),
3562                   "writeback operator '!' not allowed when base register "
3563                   "in register list");
3564    break;
3565  }
3566  case ARM::tPOP: {
3567    bool listContainsBase;
3568    if (checkLowRegisterList(Inst, 3, 0, ARM::PC, listContainsBase))
3569      return Error(Operands[2]->getStartLoc(),
3570                   "registers must be in range r0-r7 or pc");
3571    break;
3572  }
3573  case ARM::tPUSH: {
3574    bool listContainsBase;
3575    if (checkLowRegisterList(Inst, 3, 0, ARM::LR, listContainsBase))
3576      return Error(Operands[2]->getStartLoc(),
3577                   "registers must be in range r0-r7 or lr");
3578    break;
3579  }
3580  case ARM::tSTMIA_UPD: {
3581    bool listContainsBase;
3582    if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase))
3583      return Error(Operands[4]->getStartLoc(),
3584                   "registers must be in range r0-r7");
3585    break;
3586  }
3587  }
3588
3589  return false;
3590}
3591
3592void ARMAsmParser::
3593processInstruction(MCInst &Inst,
3594                   const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3595  switch (Inst.getOpcode()) {
3596  case ARM::LDMIA_UPD:
3597    // If this is a load of a single register via a 'pop', then we should use
3598    // a post-indexed LDR instruction instead, per the ARM ARM.
3599    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
3600        Inst.getNumOperands() == 5) {
3601      MCInst TmpInst;
3602      TmpInst.setOpcode(ARM::LDR_POST_IMM);
3603      TmpInst.addOperand(Inst.getOperand(4)); // Rt
3604      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
3605      TmpInst.addOperand(Inst.getOperand(1)); // Rn
3606      TmpInst.addOperand(MCOperand::CreateReg(0));  // am2offset
3607      TmpInst.addOperand(MCOperand::CreateImm(4));
3608      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
3609      TmpInst.addOperand(Inst.getOperand(3));
3610      Inst = TmpInst;
3611    }
3612    break;
3613  case ARM::STMDB_UPD:
3614    // If this is a store of a single register via a 'push', then we should use
3615    // a pre-indexed STR instruction instead, per the ARM ARM.
3616    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
3617        Inst.getNumOperands() == 5) {
3618      MCInst TmpInst;
3619      TmpInst.setOpcode(ARM::STR_PRE_IMM);
3620      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
3621      TmpInst.addOperand(Inst.getOperand(4)); // Rt
3622      TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
3623      TmpInst.addOperand(MCOperand::CreateImm(-4));
3624      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
3625      TmpInst.addOperand(Inst.getOperand(3));
3626      Inst = TmpInst;
3627    }
3628    break;
3629  case ARM::tADDi8:
3630    // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
3631    // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
3632    // to encoding T2 if <Rd> is specified and encoding T2 is preferred
3633    // to encoding T1 if <Rd> is omitted."
3634    if (Inst.getOperand(3).getImm() < 8 && Operands.size() == 6)
3635      Inst.setOpcode(ARM::tADDi3);
3636    break;
3637  case ARM::t2Bcc:
3638    // If the conditional is AL or we're in an IT block, we really want t2B.
3639    if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock())
3640      Inst.setOpcode(ARM::t2B);
3641    break;
3642  case ARM::tBcc:
3643    // If the conditional is AL, we really want tB.
3644    if (Inst.getOperand(1).getImm() == ARMCC::AL)
3645      Inst.setOpcode(ARM::tB);
3646    break;
3647  case ARM::tLDMIA: {
3648    // If the register list contains any high registers, or if the writeback
3649    // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
3650    // instead if we're in Thumb2. Otherwise, this should have generated
3651    // an error in validateInstruction().
3652    unsigned Rn = Inst.getOperand(0).getReg();
3653    bool hasWritebackToken =
3654      (static_cast<ARMOperand*>(Operands[3])->isToken() &&
3655       static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
3656    bool listContainsBase;
3657    if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
3658        (!listContainsBase && !hasWritebackToken) ||
3659        (listContainsBase && hasWritebackToken)) {
3660      // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
3661      assert (isThumbTwo());
3662      Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
3663      // If we're switching to the updating version, we need to insert
3664      // the writeback tied operand.
3665      if (hasWritebackToken)
3666        Inst.insert(Inst.begin(),
3667                    MCOperand::CreateReg(Inst.getOperand(0).getReg()));
3668    }
3669    break;
3670  }
3671  case ARM::t2IT: {
3672    // The mask bits for all but the first condition are represented as
3673    // the low bit of the condition code value implies 't'. We currently
3674    // always have 1 implies 't', so XOR toggle the bits if the low bit
3675    // of the condition code is zero. The encoding also expects the low
3676    // bit of the condition to be encoded as bit 4 of the mask operand,
3677    // so mask that in if needed
3678    MCOperand &MO = Inst.getOperand(1);
3679    unsigned Mask = MO.getImm();
3680    unsigned OrigMask = Mask;
3681    unsigned TZ = CountTrailingZeros_32(Mask);
3682    if ((Inst.getOperand(0).getImm() & 1) == 0) {
3683      assert(Mask && TZ <= 3 && "illegal IT mask value!");
3684      for (unsigned i = 3; i != TZ; --i)
3685        Mask ^= 1 << i;
3686    } else
3687      Mask |= 0x10;
3688    MO.setImm(Mask);
3689
3690    // Set up the IT block state according to the IT instruction we just
3691    // matched.
3692    assert(!inITBlock() && "nested IT blocks?!");
3693    ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
3694    ITState.Mask = OrigMask; // Use the original mask, not the updated one.
3695    ITState.CurPosition = 0;
3696    ITState.FirstCond = true;
3697    break;
3698  }
3699  }
3700}
3701
3702unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
3703  // 16-bit thumb arithmetic instructions either require or preclude the 'S'
3704  // suffix depending on whether they're in an IT block or not.
3705  unsigned Opc = Inst.getOpcode();
3706  MCInstrDesc &MCID = getInstDesc(Opc);
3707  if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
3708    assert(MCID.hasOptionalDef() &&
3709           "optionally flag setting instruction missing optional def operand");
3710    assert(MCID.NumOperands == Inst.getNumOperands() &&
3711           "operand count mismatch!");
3712    // Find the optional-def operand (cc_out).
3713    unsigned OpNo;
3714    for (OpNo = 0;
3715         !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
3716         ++OpNo)
3717      ;
3718    // If we're parsing Thumb1, reject it completely.
3719    if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
3720      return Match_MnemonicFail;
3721    // If we're parsing Thumb2, which form is legal depends on whether we're
3722    // in an IT block.
3723    if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
3724        !inITBlock())
3725      return Match_RequiresITBlock;
3726    if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
3727        inITBlock())
3728      return Match_RequiresNotITBlock;
3729  }
3730  // Some high-register supporting Thumb1 encodings only allow both registers
3731  // to be from r0-r7 when in Thumb2.
3732  else if (Opc == ARM::tADDhirr && isThumbOne() &&
3733           isARMLowRegister(Inst.getOperand(1).getReg()) &&
3734           isARMLowRegister(Inst.getOperand(2).getReg()))
3735    return Match_RequiresThumb2;
3736  // Others only require ARMv6 or later.
3737  else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
3738           isARMLowRegister(Inst.getOperand(0).getReg()) &&
3739           isARMLowRegister(Inst.getOperand(1).getReg()))
3740    return Match_RequiresV6;
3741  return Match_Success;
3742}
3743
3744bool ARMAsmParser::
3745MatchAndEmitInstruction(SMLoc IDLoc,
3746                        SmallVectorImpl<MCParsedAsmOperand*> &Operands,
3747                        MCStreamer &Out) {
3748  MCInst Inst;
3749  unsigned ErrorInfo;
3750  unsigned MatchResult;
3751  MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo);
3752  switch (MatchResult) {
3753  default: break;
3754  case Match_Success:
3755    // Context sensitive operand constraints aren't handled by the matcher,
3756    // so check them here.
3757    if (validateInstruction(Inst, Operands)) {
3758      // Still progress the IT block, otherwise one wrong condition causes
3759      // nasty cascading errors.
3760      forwardITPosition();
3761      return true;
3762    }
3763
3764    // Some instructions need post-processing to, for example, tweak which
3765    // encoding is selected.
3766    processInstruction(Inst, Operands);
3767
3768    // Only move forward at the very end so that everything in validate
3769    // and process gets a consistent answer about whether we're in an IT
3770    // block.
3771    forwardITPosition();
3772
3773    Out.EmitInstruction(Inst);
3774    return false;
3775  case Match_MissingFeature:
3776    Error(IDLoc, "instruction requires a CPU feature not currently enabled");
3777    return true;
3778  case Match_InvalidOperand: {
3779    SMLoc ErrorLoc = IDLoc;
3780    if (ErrorInfo != ~0U) {
3781      if (ErrorInfo >= Operands.size())
3782        return Error(IDLoc, "too few operands for instruction");
3783
3784      ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
3785      if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
3786    }
3787
3788    return Error(ErrorLoc, "invalid operand for instruction");
3789  }
3790  case Match_MnemonicFail:
3791    return Error(IDLoc, "invalid instruction");
3792  case Match_ConversionFail:
3793    // The converter function will have already emited a diagnostic.
3794    return true;
3795  case Match_RequiresNotITBlock:
3796    return Error(IDLoc, "flag setting instruction only valid outside IT block");
3797  case Match_RequiresITBlock:
3798    return Error(IDLoc, "instruction only valid inside IT block");
3799  case Match_RequiresV6:
3800    return Error(IDLoc, "instruction variant requires ARMv6 or later");
3801  case Match_RequiresThumb2:
3802    return Error(IDLoc, "instruction variant requires Thumb2");
3803  }
3804
3805  llvm_unreachable("Implement any new match types added!");
3806  return true;
3807}
3808
3809/// parseDirective parses the arm specific directives
3810bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
3811  StringRef IDVal = DirectiveID.getIdentifier();
3812  if (IDVal == ".word")
3813    return parseDirectiveWord(4, DirectiveID.getLoc());
3814  else if (IDVal == ".thumb")
3815    return parseDirectiveThumb(DirectiveID.getLoc());
3816  else if (IDVal == ".thumb_func")
3817    return parseDirectiveThumbFunc(DirectiveID.getLoc());
3818  else if (IDVal == ".code")
3819    return parseDirectiveCode(DirectiveID.getLoc());
3820  else if (IDVal == ".syntax")
3821    return parseDirectiveSyntax(DirectiveID.getLoc());
3822  return true;
3823}
3824
3825/// parseDirectiveWord
3826///  ::= .word [ expression (, expression)* ]
3827bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
3828  if (getLexer().isNot(AsmToken::EndOfStatement)) {
3829    for (;;) {
3830      const MCExpr *Value;
3831      if (getParser().ParseExpression(Value))
3832        return true;
3833
3834      getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
3835
3836      if (getLexer().is(AsmToken::EndOfStatement))
3837        break;
3838
3839      // FIXME: Improve diagnostic.
3840      if (getLexer().isNot(AsmToken::Comma))
3841        return Error(L, "unexpected token in directive");
3842      Parser.Lex();
3843    }
3844  }
3845
3846  Parser.Lex();
3847  return false;
3848}
3849
3850/// parseDirectiveThumb
3851///  ::= .thumb
3852bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
3853  if (getLexer().isNot(AsmToken::EndOfStatement))
3854    return Error(L, "unexpected token in directive");
3855  Parser.Lex();
3856
3857  // TODO: set thumb mode
3858  // TODO: tell the MC streamer the mode
3859  // getParser().getStreamer().Emit???();
3860  return false;
3861}
3862
3863/// parseDirectiveThumbFunc
3864///  ::= .thumbfunc symbol_name
3865bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
3866  const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
3867  bool isMachO = MAI.hasSubsectionsViaSymbols();
3868  StringRef Name;
3869
3870  // Darwin asm has function name after .thumb_func direction
3871  // ELF doesn't
3872  if (isMachO) {
3873    const AsmToken &Tok = Parser.getTok();
3874    if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
3875      return Error(L, "unexpected token in .thumb_func directive");
3876    Name = Tok.getString();
3877    Parser.Lex(); // Consume the identifier token.
3878  }
3879
3880  if (getLexer().isNot(AsmToken::EndOfStatement))
3881    return Error(L, "unexpected token in directive");
3882  Parser.Lex();
3883
3884  // FIXME: assuming function name will be the line following .thumb_func
3885  if (!isMachO) {
3886    Name = Parser.getTok().getString();
3887  }
3888
3889  // Mark symbol as a thumb symbol.
3890  MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
3891  getParser().getStreamer().EmitThumbFunc(Func);
3892  return false;
3893}
3894
3895/// parseDirectiveSyntax
3896///  ::= .syntax unified | divided
3897bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
3898  const AsmToken &Tok = Parser.getTok();
3899  if (Tok.isNot(AsmToken::Identifier))
3900    return Error(L, "unexpected token in .syntax directive");
3901  StringRef Mode = Tok.getString();
3902  if (Mode == "unified" || Mode == "UNIFIED")
3903    Parser.Lex();
3904  else if (Mode == "divided" || Mode == "DIVIDED")
3905    return Error(L, "'.syntax divided' arm asssembly not supported");
3906  else
3907    return Error(L, "unrecognized syntax mode in .syntax directive");
3908
3909  if (getLexer().isNot(AsmToken::EndOfStatement))
3910    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
3911  Parser.Lex();
3912
3913  // TODO tell the MC streamer the mode
3914  // getParser().getStreamer().Emit???();
3915  return false;
3916}
3917
3918/// parseDirectiveCode
3919///  ::= .code 16 | 32
3920bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
3921  const AsmToken &Tok = Parser.getTok();
3922  if (Tok.isNot(AsmToken::Integer))
3923    return Error(L, "unexpected token in .code directive");
3924  int64_t Val = Parser.getTok().getIntVal();
3925  if (Val == 16)
3926    Parser.Lex();
3927  else if (Val == 32)
3928    Parser.Lex();
3929  else
3930    return Error(L, "invalid operand to .code directive");
3931
3932  if (getLexer().isNot(AsmToken::EndOfStatement))
3933    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
3934  Parser.Lex();
3935
3936  if (Val == 16) {
3937    if (!isThumb())
3938      SwitchMode();
3939    getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
3940  } else {
3941    if (isThumb())
3942      SwitchMode();
3943    getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
3944  }
3945
3946  return false;
3947}
3948
3949extern "C" void LLVMInitializeARMAsmLexer();
3950
3951/// Force static initialization.
3952extern "C" void LLVMInitializeARMAsmParser() {
3953  RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
3954  RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
3955  LLVMInitializeARMAsmLexer();
3956}
3957
3958#define GET_REGISTER_MATCHER
3959#define GET_MATCHER_IMPLEMENTATION
3960#include "ARMGenAsmMatcher.inc"
3961