1f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard//===-- SIRegisterInfo.cpp - SI Register Information ---------------------===// 2f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// 3f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// The LLVM Compiler Infrastructure 4f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// 5f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// This file is distributed under the University of Illinois Open Source 6f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// License. See LICENSE.TXT for details. 7f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// 8f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard//===----------------------------------------------------------------------===// 9f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// 10f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard/// \file 11f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard/// \brief SI implementation of the TargetRegisterInfo class. 12f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// 13f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard//===----------------------------------------------------------------------===// 14f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 15f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 16f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#include "SIRegisterInfo.h" 17cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines#include "AMDGPUSubtarget.h" 18a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard#include "SIInstrInfo.h" 19f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 20f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardusing namespace llvm; 21f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 22cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen HinesSIRegisterInfo::SIRegisterInfo(const AMDGPUSubtarget &st) 23cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines: AMDGPURegisterInfo(st) 24f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard { } 25f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 26f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardBitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 27f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard BitVector Reserved(getNumRegs()); 28219e788dc6e38120266d366a51286739fa33123bTom Stellard Reserved.set(AMDGPU::EXEC); 29a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard Reserved.set(AMDGPU::INDIRECT_BASE_ADDR); 30cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines const SIInstrInfo *TII = static_cast<const SIInstrInfo*>(ST.getInstrInfo()); 31a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard TII->reserveIndirectRegisters(Reserved, MF); 32f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return Reserved; 33f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 34f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 35c53270f885e8d778cfe0e741e07d7def2b66884aChristian Konigunsigned SIRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, 36c53270f885e8d778cfe0e741e07d7def2b66884aChristian Konig MachineFunction &MF) const { 37c53270f885e8d778cfe0e741e07d7def2b66884aChristian Konig return RC->getNumRegs(); 38c53270f885e8d778cfe0e741e07d7def2b66884aChristian Konig} 39c53270f885e8d778cfe0e741e07d7def2b66884aChristian Konig 40f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardconst TargetRegisterClass * SIRegisterInfo::getCFGStructurizerRegClass( 41f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard MVT VT) const { 42f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard switch(VT.SimpleTy) { 43f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard default: 44f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard case MVT::i32: return &AMDGPU::VReg_32RegClass; 45f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard } 46f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 473406d882c02a6cd1e16f4636351c23dcb68d785fTom Stellard 48a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellardunsigned SIRegisterInfo::getHWRegIndex(unsigned Reg) const { 4936b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines return getEncodingValue(Reg) & 0xff; 50a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard} 51a2b4eb6d15a13de257319ac6231b5ab622cd02b1Tom Stellard 523406d882c02a6cd1e16f4636351c23dcb68d785fTom Stellardconst TargetRegisterClass *SIRegisterInfo::getPhysRegClass(unsigned Reg) const { 533406d882c02a6cd1e16f4636351c23dcb68d785fTom Stellard assert(!TargetRegisterInfo::isVirtualRegister(Reg)); 543406d882c02a6cd1e16f4636351c23dcb68d785fTom Stellard 553406d882c02a6cd1e16f4636351c23dcb68d785fTom Stellard const TargetRegisterClass *BaseClasses[] = { 563406d882c02a6cd1e16f4636351c23dcb68d785fTom Stellard &AMDGPU::VReg_32RegClass, 573406d882c02a6cd1e16f4636351c23dcb68d785fTom Stellard &AMDGPU::SReg_32RegClass, 583406d882c02a6cd1e16f4636351c23dcb68d785fTom Stellard &AMDGPU::VReg_64RegClass, 593406d882c02a6cd1e16f4636351c23dcb68d785fTom Stellard &AMDGPU::SReg_64RegClass, 603406d882c02a6cd1e16f4636351c23dcb68d785fTom Stellard &AMDGPU::SReg_128RegClass, 613406d882c02a6cd1e16f4636351c23dcb68d785fTom Stellard &AMDGPU::SReg_256RegClass 623406d882c02a6cd1e16f4636351c23dcb68d785fTom Stellard }; 633406d882c02a6cd1e16f4636351c23dcb68d785fTom Stellard 64dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines for (const TargetRegisterClass *BaseClass : BaseClasses) { 65dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines if (BaseClass->contains(Reg)) { 66dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return BaseClass; 673406d882c02a6cd1e16f4636351c23dcb68d785fTom Stellard } 683406d882c02a6cd1e16f4636351c23dcb68d785fTom Stellard } 69dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return nullptr; 703406d882c02a6cd1e16f4636351c23dcb68d785fTom Stellard} 71636298ba64fd07d4ddcae6005e7fc1db43eb5335Tom Stellard 72b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellardbool SIRegisterInfo::isSGPRClass(const TargetRegisterClass *RC) const { 73636298ba64fd07d4ddcae6005e7fc1db43eb5335Tom Stellard if (!RC) { 74636298ba64fd07d4ddcae6005e7fc1db43eb5335Tom Stellard return false; 75636298ba64fd07d4ddcae6005e7fc1db43eb5335Tom Stellard } 76b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard return !hasVGPRs(RC); 77b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard} 78b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard 79b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellardbool SIRegisterInfo::hasVGPRs(const TargetRegisterClass *RC) const { 80b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard return getCommonSubClass(&AMDGPU::VReg_32RegClass, RC) || 81b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard getCommonSubClass(&AMDGPU::VReg_64RegClass, RC) || 825cddda6d13ab66c462ccbd61255ad6e6f95e9f6fTom Stellard getCommonSubClass(&AMDGPU::VReg_96RegClass, RC) || 83b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard getCommonSubClass(&AMDGPU::VReg_128RegClass, RC) || 84b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard getCommonSubClass(&AMDGPU::VReg_256RegClass, RC) || 85b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard getCommonSubClass(&AMDGPU::VReg_512RegClass, RC); 86b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard} 87b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard 88b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellardconst TargetRegisterClass *SIRegisterInfo::getEquivalentVGPRClass( 89b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard const TargetRegisterClass *SRC) const { 90b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard if (hasVGPRs(SRC)) { 91b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard return SRC; 923560dd2dcd67d42eeb8e59975581d598d71669dfMatt Arsenault } else if (SRC == &AMDGPU::SCCRegRegClass) { 933560dd2dcd67d42eeb8e59975581d598d71669dfMatt Arsenault return &AMDGPU::VCCRegRegClass; 94b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard } else if (getCommonSubClass(SRC, &AMDGPU::SGPR_32RegClass)) { 95b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard return &AMDGPU::VReg_32RegClass; 96b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard } else if (getCommonSubClass(SRC, &AMDGPU::SGPR_64RegClass)) { 97b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard return &AMDGPU::VReg_64RegClass; 98b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard } else if (getCommonSubClass(SRC, &AMDGPU::SReg_128RegClass)) { 99b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard return &AMDGPU::VReg_128RegClass; 100b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard } else if (getCommonSubClass(SRC, &AMDGPU::SReg_256RegClass)) { 101b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard return &AMDGPU::VReg_256RegClass; 102b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard } else if (getCommonSubClass(SRC, &AMDGPU::SReg_512RegClass)) { 103b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard return &AMDGPU::VReg_512RegClass; 104b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard } 105dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return nullptr; 106b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard} 107b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard 108b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellardconst TargetRegisterClass *SIRegisterInfo::getSubRegClass( 109b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard const TargetRegisterClass *RC, unsigned SubIdx) const { 110b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard if (SubIdx == AMDGPU::NoSubRegister) 111b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard return RC; 112b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard 113b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard // If this register has a sub-register, we can safely assume it is a 32-bit 11436b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines // register, because all of SI's sub-registers are 32-bit. 115b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard if (isSGPRClass(RC)) { 116b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard return &AMDGPU::SGPR_32RegClass; 117b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard } else { 118b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard return &AMDGPU::VGPR_32RegClass; 119b52bf6a3b31596a309f4b12884522e9b4a344654Tom Stellard } 120636298ba64fd07d4ddcae6005e7fc1db43eb5335Tom Stellard} 121dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 122dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesunsigned SIRegisterInfo::getPhysRegSubReg(unsigned Reg, 123dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines const TargetRegisterClass *SubRC, 124dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines unsigned Channel) const { 125dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines unsigned Index = getHWRegIndex(Reg); 126dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return SubRC->getRegister(Index + Channel); 127dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines} 128cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines 129cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hinesbool SIRegisterInfo::regClassCanUseImmediate(int RCID) const { 130cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines switch (RCID) { 131cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines default: return false; 132cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines case AMDGPU::SSrc_32RegClassID: 133cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines case AMDGPU::SSrc_64RegClassID: 134cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines case AMDGPU::VSrc_32RegClassID: 135cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines case AMDGPU::VSrc_64RegClassID: 136cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines return true; 137cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines } 138cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines} 139cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines 140cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hinesbool SIRegisterInfo::regClassCanUseImmediate( 141cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines const TargetRegisterClass *RC) const { 142cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines return regClassCanUseImmediate(RC->getID()); 143cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines} 144