SparcRegisterInfo.cpp revision 7ce45783531cfa81bfd7be561ea7e4738e8c6ca8 
1//===- SparcRegisterInfo.cpp - SPARC Register Information -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the SPARC implementation of the MRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "Sparc.h"
15#include "SparcRegisterInfo.h"
16#include "SparcSubtarget.h"
17#include "llvm/CodeGen/MachineInstrBuilder.h"
18#include "llvm/CodeGen/MachineFunction.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineLocation.h"
21#include "llvm/Type.h"
22#include "llvm/ADT/STLExtras.h"
23#include <iostream>
24using namespace llvm;
25
26SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st,
27                                     const TargetInstrInfo &tii)
28  : SparcGenRegisterInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
29    Subtarget(st), TII(tii) {
30}
31
32void SparcRegisterInfo::
33storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
34                    unsigned SrcReg, int FI,
35                    const TargetRegisterClass *RC) const {
36  // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
37  if (RC == SP::IntRegsRegisterClass)
38    BuildMI(MBB, I, SP::STri, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg);
39  else if (RC == SP::FPRegsRegisterClass)
40    BuildMI(MBB, I, SP::STFri, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg);
41  else if (RC == SP::DFPRegsRegisterClass)
42    BuildMI(MBB, I, SP::STDFri, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg);
43  else
44    assert(0 && "Can't store this register to stack slot");
45}
46
47void SparcRegisterInfo::
48loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
49                     unsigned DestReg, int FI,
50                     const TargetRegisterClass *RC) const {
51  if (RC == SP::IntRegsRegisterClass)
52    BuildMI(MBB, I, SP::LDri, 2, DestReg).addFrameIndex(FI).addImm(0);
53  else if (RC == SP::FPRegsRegisterClass)
54    BuildMI(MBB, I, SP::LDFri, 2, DestReg).addFrameIndex(FI).addImm (0);
55  else if (RC == SP::DFPRegsRegisterClass)
56    BuildMI(MBB, I, SP::LDDFri, 2, DestReg).addFrameIndex(FI).addImm(0);
57  else
58    assert(0 && "Can't load this register from stack slot");
59}
60
61void SparcRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
62                                     MachineBasicBlock::iterator I,
63                                     unsigned DestReg, unsigned SrcReg,
64                                     const TargetRegisterClass *RC) const {
65  if (RC == SP::IntRegsRegisterClass)
66    BuildMI(MBB, I, SP::ORrr, 2, DestReg).addReg(SP::G0).addReg(SrcReg);
67  else if (RC == SP::FPRegsRegisterClass)
68    BuildMI(MBB, I, SP::FMOVS, 1, DestReg).addReg(SrcReg);
69  else if (RC == SP::DFPRegsRegisterClass)
70    BuildMI(MBB, I, Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD,
71            1, DestReg).addReg(SrcReg);
72  else
73    assert (0 && "Can't copy this register");
74}
75
76MachineInstr *SparcRegisterInfo::foldMemoryOperand(MachineInstr* MI,
77                                                   unsigned OpNum,
78                                                   int FI) const {
79  bool isFloat = false;
80  switch (MI->getOpcode()) {
81  case SP::ORrr:
82    if (MI->getOperand(1).isRegister() && MI->getOperand(1).getReg() == SP::G0&&
83        MI->getOperand(0).isRegister() && MI->getOperand(2).isRegister()) {
84      if (OpNum == 0)    // COPY -> STORE
85        return BuildMI(TII, SP::STri, 3).addFrameIndex(FI).addImm(0)
86                                   .addReg(MI->getOperand(2).getReg());
87      else               // COPY -> LOAD
88        return BuildMI(TII, SP::LDri, 2, MI->getOperand(0).getReg())
89                      .addFrameIndex(FI).addImm(0);
90    }
91    break;
92  case SP::FMOVS:
93    isFloat = true;
94    // FALLTHROUGH
95  case SP::FMOVD:
96    if (OpNum == 0)  // COPY -> STORE
97      return BuildMI(TII, isFloat ? SP::STFri : SP::STDFri, 3)
98               .addFrameIndex(FI).addImm(0).addReg(MI->getOperand(1).getReg());
99    else             // COPY -> LOAD
100      return BuildMI(TII, isFloat ? SP::LDFri : SP::LDDFri, 2,
101                     MI->getOperand(0).getReg()).addFrameIndex(FI).addImm(0);
102    break;
103  }
104  return 0;
105}
106
107const unsigned* SparcRegisterInfo::getCalleeSaveRegs() const {
108  static const unsigned CalleeSaveRegs[] = { 0 };
109  return CalleeSaveRegs;
110}
111
112const TargetRegisterClass* const*
113SparcRegisterInfo::getCalleeSaveRegClasses() const {
114  static const TargetRegisterClass * const CalleeSaveRegClasses[] = { 0 };
115  return CalleeSaveRegClasses;
116}
117
118
119void SparcRegisterInfo::
120eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
121                              MachineBasicBlock::iterator I) const {
122  MachineInstr &MI = *I;
123  int Size = MI.getOperand(0).getImmedValue();
124  if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
125    Size = -Size;
126  if (Size)
127    BuildMI(MBB, I, SP::ADDri, 2, SP::O6).addReg(SP::O6).addImm(Size);
128  MBB.erase(I);
129}
130
131void
132SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
133  unsigned i = 0;
134  MachineInstr &MI = *II;
135  while (!MI.getOperand(i).isFrameIndex()) {
136    ++i;
137    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
138  }
139
140  int FrameIndex = MI.getOperand(i).getFrameIndex();
141
142  // Addressable stack objects are accessed using neg. offsets from %fp
143  MachineFunction &MF = *MI.getParent()->getParent();
144  int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
145               MI.getOperand(i+1).getImmedValue();
146
147  // Replace frame index with a frame pointer reference.
148  if (Offset >= -4096 && Offset <= 4095) {
149    // If the offset is small enough to fit in the immediate field, directly
150    // encode it.
151    MI.getOperand(i).ChangeToRegister(SP::I6, false);
152    MI.getOperand(i+1).ChangeToImmediate(Offset);
153  } else {
154    // Otherwise, emit a G1 = SETHI %hi(offset).  FIXME: it would be better to
155    // scavenge a register here instead of reserving G1 all of the time.
156    unsigned OffHi = (unsigned)Offset >> 10U;
157    BuildMI(*MI.getParent(), II, SP::SETHIi, 1, SP::G1).addImm(OffHi);
158    // Emit G1 = G1 + I6
159    BuildMI(*MI.getParent(), II, SP::ADDrr, 2,
160            SP::G1).addReg(SP::G1).addReg(SP::I6);
161    // Insert: G1+%lo(offset) into the user.
162    MI.getOperand(i).ChangeToRegister(SP::G1, false);
163    MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1));
164  }
165}
166
167void SparcRegisterInfo::
168processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
169
170void SparcRegisterInfo::emitPrologue(MachineFunction &MF) const {
171  MachineBasicBlock &MBB = MF.front();
172  MachineFrameInfo *MFI = MF.getFrameInfo();
173
174  // Get the number of bytes to allocate from the FrameInfo
175  int NumBytes = (int) MFI->getStackSize();
176
177  // Emit the correct save instruction based on the number of bytes in
178  // the frame. Minimum stack frame size according to V8 ABI is:
179  //   16 words for register window spill
180  //    1 word for address of returned aggregate-value
181  // +  6 words for passing parameters on the stack
182  // ----------
183  //   23 words * 4 bytes per word = 92 bytes
184  NumBytes += 92;
185  // Round up to next doubleword boundary -- a double-word boundary
186  // is required by the ABI.
187  NumBytes = (NumBytes + 7) & ~7;
188  NumBytes = -NumBytes;
189
190  if (NumBytes >= -4096) {
191    BuildMI(MBB, MBB.begin(), SP::SAVEri, 2,
192            SP::O6).addImm(NumBytes).addReg(SP::O6);
193  } else {
194    MachineBasicBlock::iterator InsertPt = MBB.begin();
195    // Emit this the hard way.  This clobbers G1 which we always know is
196    // available here.
197    unsigned OffHi = (unsigned)NumBytes >> 10U;
198    BuildMI(MBB, InsertPt, SP::SETHIi, 1, SP::G1).addImm(OffHi);
199    // Emit G1 = G1 + I6
200    BuildMI(MBB, InsertPt, SP::ORri, 2, SP::G1)
201      .addReg(SP::G1).addImm(NumBytes & ((1 << 10)-1));
202    BuildMI(MBB, InsertPt, SP::SAVErr, 2,
203            SP::O6).addReg(SP::O6).addReg(SP::G1);
204  }
205}
206
207void SparcRegisterInfo::emitEpilogue(MachineFunction &MF,
208                                     MachineBasicBlock &MBB) const {
209  MachineBasicBlock::iterator MBBI = prior(MBB.end());
210  assert(MBBI->getOpcode() == SP::RETL &&
211         "Can only put epilog before 'retl' instruction!");
212  BuildMI(MBB, MBBI, SP::RESTORErr, 2, SP::G0).addReg(SP::G0).addReg(SP::G0);
213}
214
215unsigned SparcRegisterInfo::getRARegister() const {
216  assert(0 && "What is the return address register");
217  return 0;
218}
219
220unsigned SparcRegisterInfo::getFrameRegister(MachineFunction &MF) const {
221  assert(0 && "What is the frame register");
222  return SP::G1;
223}
224
225#include "SparcGenRegisterInfo.inc"
226
227