SparcRegisterInfo.cpp revision 88ddd4a07de81a14a6c768fe5ac4c6a7481f838d 
1//===- SparcV8RegisterInfo.cpp - SparcV8 Register Information ---*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the SparcV8 implementation of the MRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "SparcV8.h"
15#include "SparcV8RegisterInfo.h"
16#include "llvm/CodeGen/MachineInstrBuilder.h"
17#include "llvm/CodeGen/MachineFunction.h"
18#include "llvm/CodeGen/MachineFrameInfo.h"
19#include "llvm/Type.h"
20#include "Support/STLExtras.h"
21using namespace llvm;
22
23SparcV8RegisterInfo::SparcV8RegisterInfo()
24  : SparcV8GenRegisterInfo(V8::ADJCALLSTACKDOWN,
25                           V8::ADJCALLSTACKUP) {}
26
27int SparcV8RegisterInfo::storeRegToStackSlot(
28  MachineBasicBlock &MBB,
29  MachineBasicBlock::iterator MBBI,
30  unsigned SrcReg, int FrameIdx,
31  const TargetRegisterClass *RC) const
32{
33  assert (RC == SparcV8::IntRegsRegisterClass
34          && "Can only store 32-bit values to stack slots");
35  MachineInstr *I =
36    BuildMI (V8::STrm, 3).addFrameIndex (FrameIdx).addSImm (0).addReg (SrcReg);
37  MBB.insert(MBBI, I);
38  return 1;
39}
40
41int SparcV8RegisterInfo::loadRegFromStackSlot(
42  MachineBasicBlock &MBB,
43  MachineBasicBlock::iterator I,
44  unsigned DestReg, int FrameIdx,
45  const TargetRegisterClass *RC) const
46{
47  assert (RC == SparcV8::IntRegsRegisterClass
48          && "Can only load 32-bit registers from stack slots");
49  BuildMI (MBB, I, V8::LDmr, 2, DestReg).addFrameIndex (FrameIdx).addSImm (0);
50  return 1;
51}
52
53int SparcV8RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
54                                      MachineBasicBlock::iterator I,
55                                      unsigned DestReg, unsigned SrcReg,
56                                      const TargetRegisterClass *RC) const {
57  assert (RC == SparcV8::IntRegsRegisterClass
58          && "Can only copy 32-bit registers");
59  BuildMI (MBB, I, V8::ORrr, 2, DestReg).addReg (V8::G0).addReg (SrcReg);
60  return -1;
61}
62
63void SparcV8RegisterInfo::
64eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
65                              MachineBasicBlock::iterator I) const {
66  std::cerr
67    << "Sorry, I don't know how to eliminate call frame pseudo instrs yet, in\n"
68    << __FUNCTION__ << " at " << __FILE__ << ":" << __LINE__ << "\n";
69  abort();
70}
71
72void
73SparcV8RegisterInfo::eliminateFrameIndex(MachineFunction &MF,
74                                         MachineBasicBlock::iterator II) const {
75  unsigned i = 0;
76  MachineInstr &MI = *II;
77  while (!MI.getOperand(i).isFrameIndex()) {
78    ++i;
79    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
80  }
81
82  int FrameIndex = MI.getOperand(i).getFrameIndex();
83
84  // Replace frame index with a frame pointer reference
85  MI.SetMachineOperandReg (i, V8::FP);
86
87  // Addressable stack objects are accessed using neg. offsets from %fp
88  int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
89               MI.getOperand(i+1).getImmedValue();
90  // note: Offset < 0
91  MI.SetMachineOperandConst (i+1, MachineOperand::MO_SignExtendedImmed, Offset);
92}
93
94void SparcV8RegisterInfo::
95processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
96
97void SparcV8RegisterInfo::emitPrologue(MachineFunction &MF) const {
98  MachineBasicBlock &MBB = MF.front();
99  MachineFrameInfo *MFI = MF.getFrameInfo();
100
101  // Get the number of bytes to allocate from the FrameInfo
102  int NumBytes = (int) MFI->getStackSize() + 4;
103
104  // Emit the correct save instruction based on the number of bytes in the frame.
105  // Minimum stack frame size according to V8 ABI is:
106  //   16 words for register window spill
107  //    1 word for address of returned aggregate-value
108  // +  6 words for passing parameters on the stack
109  // ----------
110  //   23 words * 4 bytes per word = 92 bytes
111  NumBytes += 92;
112  NumBytes = (NumBytes + 3) & ~3;  // Round up to next word boundary
113  BuildMI(MBB, MBB.begin(), V8::SAVEri, 2,
114          V8::SP).addImm(-NumBytes).addReg(V8::SP);
115}
116
117void SparcV8RegisterInfo::emitEpilogue(MachineFunction &MF,
118                                       MachineBasicBlock &MBB) const {
119  MachineBasicBlock::iterator MBBI = prior(MBB.end());
120  assert(MBBI->getOpcode() == V8::RETL &&
121         "Can only put epilog before 'retl' instruction!");
122  BuildMI(MBB, MBBI, V8::RESTORErr, 2, V8::G0).addReg(V8::G0).addReg(V8::G0);
123}
124
125#include "SparcV8GenRegisterInfo.inc"
126
127const TargetRegisterClass*
128SparcV8RegisterInfo::getRegClassForType(const Type* Ty) const {
129  switch (Ty->getPrimitiveID()) {
130  case Type::FloatTyID:  return &FPRegsInstance;
131  case Type::DoubleTyID: return &DFPRegsInstance;
132  case Type::LongTyID:
133  case Type::ULongTyID: assert(0 && "Long values can't fit in registers!");
134  default:              assert(0 && "Invalid type to getClass!");
135  case Type::BoolTyID:
136  case Type::SByteTyID:
137  case Type::UByteTyID:
138  case Type::ShortTyID:
139  case Type::UShortTyID:
140  case Type::IntTyID:
141  case Type::UIntTyID:
142  case Type::PointerTyID: return &IntRegsInstance;
143  }
144}
145
146