X86ISelDAGToDAG.cpp revision 518bb53485df640d7b7e3f6b0544099020c42aa7
1//===- X86ISelDAGToDAG.cpp - A DAG pattern matching inst selector for X86 -===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines a DAG pattern matching instruction selector for X86, 11// converting from a legalized dag to a X86 dag. 12// 13//===----------------------------------------------------------------------===// 14 15// Force NDEBUG on in any optimized build on Darwin. 16// 17// FIXME: This is a huge hack, to work around ridiculously awful compile times 18// on this file with gcc-4.2 on Darwin, in Release mode. 19#if (!defined(__llvm__) && defined(__APPLE__) && \ 20 defined(__OPTIMIZE__) && !defined(NDEBUG)) 21#define NDEBUG 22#endif 23 24#define DEBUG_TYPE "x86-isel" 25#include "X86.h" 26#include "X86InstrBuilder.h" 27#include "X86ISelLowering.h" 28#include "X86MachineFunctionInfo.h" 29#include "X86RegisterInfo.h" 30#include "X86Subtarget.h" 31#include "X86TargetMachine.h" 32#include "llvm/GlobalValue.h" 33#include "llvm/Instructions.h" 34#include "llvm/Intrinsics.h" 35#include "llvm/Support/CFG.h" 36#include "llvm/Type.h" 37#include "llvm/CodeGen/MachineConstantPool.h" 38#include "llvm/CodeGen/MachineFunction.h" 39#include "llvm/CodeGen/MachineFrameInfo.h" 40#include "llvm/CodeGen/MachineInstrBuilder.h" 41#include "llvm/CodeGen/MachineRegisterInfo.h" 42#include "llvm/CodeGen/SelectionDAGISel.h" 43#include "llvm/Target/TargetMachine.h" 44#include "llvm/Target/TargetOptions.h" 45#include "llvm/Support/Debug.h" 46#include "llvm/Support/ErrorHandling.h" 47#include "llvm/Support/MathExtras.h" 48#include "llvm/Support/raw_ostream.h" 49#include "llvm/ADT/SmallPtrSet.h" 50#include "llvm/ADT/Statistic.h" 51using namespace llvm; 52 53STATISTIC(NumLoadMoved, "Number of loads moved below TokenFactor"); 54 55//===----------------------------------------------------------------------===// 56// Pattern Matcher Implementation 57//===----------------------------------------------------------------------===// 58 59namespace { 60 /// X86ISelAddressMode - This corresponds to X86AddressMode, but uses 61 /// SDValue's instead of register numbers for the leaves of the matched 62 /// tree. 63 struct X86ISelAddressMode { 64 enum { 65 RegBase, 66 FrameIndexBase 67 } BaseType; 68 69 struct { // This is really a union, discriminated by BaseType! 70 SDValue Reg; 71 int FrameIndex; 72 } Base; 73 74 unsigned Scale; 75 SDValue IndexReg; 76 int32_t Disp; 77 SDValue Segment; 78 GlobalValue *GV; 79 Constant *CP; 80 BlockAddress *BlockAddr; 81 const char *ES; 82 int JT; 83 unsigned Align; // CP alignment. 84 unsigned char SymbolFlags; // X86II::MO_* 85 86 X86ISelAddressMode() 87 : BaseType(RegBase), Scale(1), IndexReg(), Disp(0), 88 Segment(), GV(0), CP(0), BlockAddr(0), ES(0), JT(-1), Align(0), 89 SymbolFlags(X86II::MO_NO_FLAG) { 90 } 91 92 bool hasSymbolicDisplacement() const { 93 return GV != 0 || CP != 0 || ES != 0 || JT != -1 || BlockAddr != 0; 94 } 95 96 bool hasBaseOrIndexReg() const { 97 return IndexReg.getNode() != 0 || Base.Reg.getNode() != 0; 98 } 99 100 /// isRIPRelative - Return true if this addressing mode is already RIP 101 /// relative. 102 bool isRIPRelative() const { 103 if (BaseType != RegBase) return false; 104 if (RegisterSDNode *RegNode = 105 dyn_cast_or_null<RegisterSDNode>(Base.Reg.getNode())) 106 return RegNode->getReg() == X86::RIP; 107 return false; 108 } 109 110 void setBaseReg(SDValue Reg) { 111 BaseType = RegBase; 112 Base.Reg = Reg; 113 } 114 115 void dump() { 116 dbgs() << "X86ISelAddressMode " << this << '\n'; 117 dbgs() << "Base.Reg "; 118 if (Base.Reg.getNode() != 0) 119 Base.Reg.getNode()->dump(); 120 else 121 dbgs() << "nul"; 122 dbgs() << " Base.FrameIndex " << Base.FrameIndex << '\n' 123 << " Scale" << Scale << '\n' 124 << "IndexReg "; 125 if (IndexReg.getNode() != 0) 126 IndexReg.getNode()->dump(); 127 else 128 dbgs() << "nul"; 129 dbgs() << " Disp " << Disp << '\n' 130 << "GV "; 131 if (GV) 132 GV->dump(); 133 else 134 dbgs() << "nul"; 135 dbgs() << " CP "; 136 if (CP) 137 CP->dump(); 138 else 139 dbgs() << "nul"; 140 dbgs() << '\n' 141 << "ES "; 142 if (ES) 143 dbgs() << ES; 144 else 145 dbgs() << "nul"; 146 dbgs() << " JT" << JT << " Align" << Align << '\n'; 147 } 148 }; 149} 150 151namespace { 152 //===--------------------------------------------------------------------===// 153 /// ISel - X86 specific code to select X86 machine instructions for 154 /// SelectionDAG operations. 155 /// 156 class X86DAGToDAGISel : public SelectionDAGISel { 157 /// X86Lowering - This object fully describes how to lower LLVM code to an 158 /// X86-specific SelectionDAG. 159 X86TargetLowering &X86Lowering; 160 161 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can 162 /// make the right decision when generating code for different targets. 163 const X86Subtarget *Subtarget; 164 165 /// OptForSize - If true, selector should try to optimize for code size 166 /// instead of performance. 167 bool OptForSize; 168 169 public: 170 explicit X86DAGToDAGISel(X86TargetMachine &tm, CodeGenOpt::Level OptLevel) 171 : SelectionDAGISel(tm, OptLevel), 172 X86Lowering(*tm.getTargetLowering()), 173 Subtarget(&tm.getSubtarget<X86Subtarget>()), 174 OptForSize(false) {} 175 176 virtual const char *getPassName() const { 177 return "X86 DAG->DAG Instruction Selection"; 178 } 179 180 /// InstructionSelect - This callback is invoked by 181 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. 182 virtual void InstructionSelect(); 183 184 virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF); 185 186 virtual 187 bool IsLegalAndProfitableToFold(SDNode *N, SDNode *U, SDNode *Root) const; 188 189// Include the pieces autogenerated from the target description. 190#include "X86GenDAGISel.inc" 191 192 private: 193 SDNode *Select(SDNode *N); 194 SDNode *SelectAtomic64(SDNode *Node, unsigned Opc); 195 SDNode *SelectAtomicLoadAdd(SDNode *Node, EVT NVT); 196 197 bool MatchSegmentBaseAddress(SDValue N, X86ISelAddressMode &AM); 198 bool MatchLoad(SDValue N, X86ISelAddressMode &AM); 199 bool MatchWrapper(SDValue N, X86ISelAddressMode &AM); 200 bool MatchAddress(SDValue N, X86ISelAddressMode &AM); 201 bool MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM, 202 unsigned Depth); 203 bool MatchAddressBase(SDValue N, X86ISelAddressMode &AM); 204 bool SelectAddr(SDNode *Op, SDValue N, SDValue &Base, 205 SDValue &Scale, SDValue &Index, SDValue &Disp, 206 SDValue &Segment); 207 bool SelectLEAAddr(SDNode *Op, SDValue N, SDValue &Base, 208 SDValue &Scale, SDValue &Index, SDValue &Disp); 209 bool SelectTLSADDRAddr(SDNode *Op, SDValue N, SDValue &Base, 210 SDValue &Scale, SDValue &Index, SDValue &Disp); 211 bool SelectScalarSSELoad(SDNode *Op, SDValue Pred, 212 SDValue N, SDValue &Base, SDValue &Scale, 213 SDValue &Index, SDValue &Disp, 214 SDValue &Segment, 215 SDValue &InChain, SDValue &OutChain); 216 bool TryFoldLoad(SDNode *P, SDValue N, 217 SDValue &Base, SDValue &Scale, 218 SDValue &Index, SDValue &Disp, 219 SDValue &Segment); 220 void PreprocessForRMW(); 221 void PreprocessForFPConvert(); 222 223 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for 224 /// inline asm expressions. 225 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, 226 char ConstraintCode, 227 std::vector<SDValue> &OutOps); 228 229 void EmitSpecialCodeForMain(MachineBasicBlock *BB, MachineFrameInfo *MFI); 230 231 inline void getAddressOperands(X86ISelAddressMode &AM, SDValue &Base, 232 SDValue &Scale, SDValue &Index, 233 SDValue &Disp, SDValue &Segment) { 234 Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase) ? 235 CurDAG->getTargetFrameIndex(AM.Base.FrameIndex, TLI.getPointerTy()) : 236 AM.Base.Reg; 237 Scale = getI8Imm(AM.Scale); 238 Index = AM.IndexReg; 239 // These are 32-bit even in 64-bit mode since RIP relative offset 240 // is 32-bit. 241 if (AM.GV) 242 Disp = CurDAG->getTargetGlobalAddress(AM.GV, MVT::i32, AM.Disp, 243 AM.SymbolFlags); 244 else if (AM.CP) 245 Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i32, 246 AM.Align, AM.Disp, AM.SymbolFlags); 247 else if (AM.ES) 248 Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i32, AM.SymbolFlags); 249 else if (AM.JT != -1) 250 Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i32, AM.SymbolFlags); 251 else if (AM.BlockAddr) 252 Disp = CurDAG->getBlockAddress(AM.BlockAddr, MVT::i32, 253 true, AM.SymbolFlags); 254 else 255 Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i32); 256 257 if (AM.Segment.getNode()) 258 Segment = AM.Segment; 259 else 260 Segment = CurDAG->getRegister(0, MVT::i32); 261 } 262 263 /// getI8Imm - Return a target constant with the specified value, of type 264 /// i8. 265 inline SDValue getI8Imm(unsigned Imm) { 266 return CurDAG->getTargetConstant(Imm, MVT::i8); 267 } 268 269 /// getI16Imm - Return a target constant with the specified value, of type 270 /// i16. 271 inline SDValue getI16Imm(unsigned Imm) { 272 return CurDAG->getTargetConstant(Imm, MVT::i16); 273 } 274 275 /// getI32Imm - Return a target constant with the specified value, of type 276 /// i32. 277 inline SDValue getI32Imm(unsigned Imm) { 278 return CurDAG->getTargetConstant(Imm, MVT::i32); 279 } 280 281 /// getGlobalBaseReg - Return an SDNode that returns the value of 282 /// the global base register. Output instructions required to 283 /// initialize the global base register, if necessary. 284 /// 285 SDNode *getGlobalBaseReg(); 286 287 /// getTargetMachine - Return a reference to the TargetMachine, casted 288 /// to the target-specific type. 289 const X86TargetMachine &getTargetMachine() { 290 return static_cast<const X86TargetMachine &>(TM); 291 } 292 293 /// getInstrInfo - Return a reference to the TargetInstrInfo, casted 294 /// to the target-specific type. 295 const X86InstrInfo *getInstrInfo() { 296 return getTargetMachine().getInstrInfo(); 297 } 298 299#ifndef NDEBUG 300 unsigned Indent; 301#endif 302 }; 303} 304 305 306bool X86DAGToDAGISel::IsLegalAndProfitableToFold(SDNode *N, SDNode *U, 307 SDNode *Root) const { 308 if (OptLevel == CodeGenOpt::None) return false; 309 310 if (U == Root) 311 switch (U->getOpcode()) { 312 default: break; 313 case X86ISD::ADD: 314 case X86ISD::SUB: 315 case X86ISD::AND: 316 case X86ISD::XOR: 317 case X86ISD::OR: 318 case ISD::ADD: 319 case ISD::ADDC: 320 case ISD::ADDE: 321 case ISD::AND: 322 case ISD::OR: 323 case ISD::XOR: { 324 SDValue Op1 = U->getOperand(1); 325 326 // If the other operand is a 8-bit immediate we should fold the immediate 327 // instead. This reduces code size. 328 // e.g. 329 // movl 4(%esp), %eax 330 // addl $4, %eax 331 // vs. 332 // movl $4, %eax 333 // addl 4(%esp), %eax 334 // The former is 2 bytes shorter. In case where the increment is 1, then 335 // the saving can be 4 bytes (by using incl %eax). 336 if (ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(Op1)) 337 if (Imm->getAPIntValue().isSignedIntN(8)) 338 return false; 339 340 // If the other operand is a TLS address, we should fold it instead. 341 // This produces 342 // movl %gs:0, %eax 343 // leal i@NTPOFF(%eax), %eax 344 // instead of 345 // movl $i@NTPOFF, %eax 346 // addl %gs:0, %eax 347 // if the block also has an access to a second TLS address this will save 348 // a load. 349 // FIXME: This is probably also true for non TLS addresses. 350 if (Op1.getOpcode() == X86ISD::Wrapper) { 351 SDValue Val = Op1.getOperand(0); 352 if (Val.getOpcode() == ISD::TargetGlobalTLSAddress) 353 return false; 354 } 355 } 356 } 357 358 // Proceed to 'generic' cycle finder code 359 return SelectionDAGISel::IsLegalAndProfitableToFold(N, U, Root); 360} 361 362/// MoveBelowTokenFactor - Replace TokenFactor operand with load's chain operand 363/// and move load below the TokenFactor. Replace store's chain operand with 364/// load's chain result. 365static void MoveBelowTokenFactor(SelectionDAG *CurDAG, SDValue Load, 366 SDValue Store, SDValue TF) { 367 SmallVector<SDValue, 4> Ops; 368 for (unsigned i = 0, e = TF.getNode()->getNumOperands(); i != e; ++i) 369 if (Load.getNode() == TF.getOperand(i).getNode()) 370 Ops.push_back(Load.getOperand(0)); 371 else 372 Ops.push_back(TF.getOperand(i)); 373 SDValue NewTF = CurDAG->UpdateNodeOperands(TF, &Ops[0], Ops.size()); 374 SDValue NewLoad = CurDAG->UpdateNodeOperands(Load, NewTF, 375 Load.getOperand(1), 376 Load.getOperand(2)); 377 CurDAG->UpdateNodeOperands(Store, NewLoad.getValue(1), Store.getOperand(1), 378 Store.getOperand(2), Store.getOperand(3)); 379} 380 381/// isRMWLoad - Return true if N is a load that's part of RMW sub-DAG. The 382/// chain produced by the load must only be used by the store's chain operand, 383/// otherwise this may produce a cycle in the DAG. 384/// 385static bool isRMWLoad(SDValue N, SDValue Chain, SDValue Address, 386 SDValue &Load) { 387 if (N.getOpcode() == ISD::BIT_CONVERT) { 388 if (!N.hasOneUse()) 389 return false; 390 N = N.getOperand(0); 391 } 392 393 LoadSDNode *LD = dyn_cast<LoadSDNode>(N); 394 if (!LD || LD->isVolatile()) 395 return false; 396 if (LD->getAddressingMode() != ISD::UNINDEXED) 397 return false; 398 399 ISD::LoadExtType ExtType = LD->getExtensionType(); 400 if (ExtType != ISD::NON_EXTLOAD && ExtType != ISD::EXTLOAD) 401 return false; 402 403 if (N.hasOneUse() && 404 LD->hasNUsesOfValue(1, 1) && 405 N.getOperand(1) == Address && 406 LD->isOperandOf(Chain.getNode())) { 407 Load = N; 408 return true; 409 } 410 return false; 411} 412 413/// MoveBelowCallSeqStart - Replace CALLSEQ_START operand with load's chain 414/// operand and move load below the call's chain operand. 415static void MoveBelowCallSeqStart(SelectionDAG *CurDAG, SDValue Load, 416 SDValue Call, SDValue CallSeqStart) { 417 SmallVector<SDValue, 8> Ops; 418 SDValue Chain = CallSeqStart.getOperand(0); 419 if (Chain.getNode() == Load.getNode()) 420 Ops.push_back(Load.getOperand(0)); 421 else { 422 assert(Chain.getOpcode() == ISD::TokenFactor && 423 "Unexpected CallSeqStart chain operand"); 424 for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i) 425 if (Chain.getOperand(i).getNode() == Load.getNode()) 426 Ops.push_back(Load.getOperand(0)); 427 else 428 Ops.push_back(Chain.getOperand(i)); 429 SDValue NewChain = 430 CurDAG->getNode(ISD::TokenFactor, Load.getDebugLoc(), 431 MVT::Other, &Ops[0], Ops.size()); 432 Ops.clear(); 433 Ops.push_back(NewChain); 434 } 435 for (unsigned i = 1, e = CallSeqStart.getNumOperands(); i != e; ++i) 436 Ops.push_back(CallSeqStart.getOperand(i)); 437 CurDAG->UpdateNodeOperands(CallSeqStart, &Ops[0], Ops.size()); 438 CurDAG->UpdateNodeOperands(Load, Call.getOperand(0), 439 Load.getOperand(1), Load.getOperand(2)); 440 Ops.clear(); 441 Ops.push_back(SDValue(Load.getNode(), 1)); 442 for (unsigned i = 1, e = Call.getNode()->getNumOperands(); i != e; ++i) 443 Ops.push_back(Call.getOperand(i)); 444 CurDAG->UpdateNodeOperands(Call, &Ops[0], Ops.size()); 445} 446 447/// isCalleeLoad - Return true if call address is a load and it can be 448/// moved below CALLSEQ_START and the chains leading up to the call. 449/// Return the CALLSEQ_START by reference as a second output. 450static bool isCalleeLoad(SDValue Callee, SDValue &Chain) { 451 if (Callee.getNode() == Chain.getNode() || !Callee.hasOneUse()) 452 return false; 453 LoadSDNode *LD = dyn_cast<LoadSDNode>(Callee.getNode()); 454 if (!LD || 455 LD->isVolatile() || 456 LD->getAddressingMode() != ISD::UNINDEXED || 457 LD->getExtensionType() != ISD::NON_EXTLOAD) 458 return false; 459 460 // Now let's find the callseq_start. 461 while (Chain.getOpcode() != ISD::CALLSEQ_START) { 462 if (!Chain.hasOneUse()) 463 return false; 464 Chain = Chain.getOperand(0); 465 } 466 467 if (Chain.getOperand(0).getNode() == Callee.getNode()) 468 return true; 469 if (Chain.getOperand(0).getOpcode() == ISD::TokenFactor && 470 Callee.getValue(1).isOperandOf(Chain.getOperand(0).getNode()) && 471 Callee.getValue(1).hasOneUse()) 472 return true; 473 return false; 474} 475 476 477/// PreprocessForRMW - Preprocess the DAG to make instruction selection better. 478/// This is only run if not in -O0 mode. 479/// This allows the instruction selector to pick more read-modify-write 480/// instructions. This is a common case: 481/// 482/// [Load chain] 483/// ^ 484/// | 485/// [Load] 486/// ^ ^ 487/// | | 488/// / \- 489/// / | 490/// [TokenFactor] [Op] 491/// ^ ^ 492/// | | 493/// \ / 494/// \ / 495/// [Store] 496/// 497/// The fact the store's chain operand != load's chain will prevent the 498/// (store (op (load))) instruction from being selected. We can transform it to: 499/// 500/// [Load chain] 501/// ^ 502/// | 503/// [TokenFactor] 504/// ^ 505/// | 506/// [Load] 507/// ^ ^ 508/// | | 509/// | \- 510/// | | 511/// | [Op] 512/// | ^ 513/// | | 514/// \ / 515/// \ / 516/// [Store] 517void X86DAGToDAGISel::PreprocessForRMW() { 518 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(), 519 E = CurDAG->allnodes_end(); I != E; ++I) { 520 if (I->getOpcode() == X86ISD::CALL) { 521 /// Also try moving call address load from outside callseq_start to just 522 /// before the call to allow it to be folded. 523 /// 524 /// [Load chain] 525 /// ^ 526 /// | 527 /// [Load] 528 /// ^ ^ 529 /// | | 530 /// / \-- 531 /// / | 532 ///[CALLSEQ_START] | 533 /// ^ | 534 /// | | 535 /// [LOAD/C2Reg] | 536 /// | | 537 /// \ / 538 /// \ / 539 /// [CALL] 540 SDValue Chain = I->getOperand(0); 541 SDValue Load = I->getOperand(1); 542 if (!isCalleeLoad(Load, Chain)) 543 continue; 544 MoveBelowCallSeqStart(CurDAG, Load, SDValue(I, 0), Chain); 545 ++NumLoadMoved; 546 continue; 547 } 548 549 if (!ISD::isNON_TRUNCStore(I)) 550 continue; 551 SDValue Chain = I->getOperand(0); 552 553 if (Chain.getNode()->getOpcode() != ISD::TokenFactor) 554 continue; 555 556 SDValue N1 = I->getOperand(1); 557 SDValue N2 = I->getOperand(2); 558 if ((N1.getValueType().isFloatingPoint() && 559 !N1.getValueType().isVector()) || 560 !N1.hasOneUse()) 561 continue; 562 563 bool RModW = false; 564 SDValue Load; 565 unsigned Opcode = N1.getNode()->getOpcode(); 566 switch (Opcode) { 567 case ISD::ADD: 568 case ISD::MUL: 569 case ISD::AND: 570 case ISD::OR: 571 case ISD::XOR: 572 case ISD::ADDC: 573 case ISD::ADDE: 574 case ISD::VECTOR_SHUFFLE: { 575 SDValue N10 = N1.getOperand(0); 576 SDValue N11 = N1.getOperand(1); 577 RModW = isRMWLoad(N10, Chain, N2, Load); 578 if (!RModW) 579 RModW = isRMWLoad(N11, Chain, N2, Load); 580 break; 581 } 582 case ISD::SUB: 583 case ISD::SHL: 584 case ISD::SRA: 585 case ISD::SRL: 586 case ISD::ROTL: 587 case ISD::ROTR: 588 case ISD::SUBC: 589 case ISD::SUBE: 590 case X86ISD::SHLD: 591 case X86ISD::SHRD: { 592 SDValue N10 = N1.getOperand(0); 593 RModW = isRMWLoad(N10, Chain, N2, Load); 594 break; 595 } 596 } 597 598 if (RModW) { 599 MoveBelowTokenFactor(CurDAG, Load, SDValue(I, 0), Chain); 600 ++NumLoadMoved; 601 checkForCycles(I); 602 } 603 } 604} 605 606 607/// PreprocessForFPConvert - Walk over the dag lowering fpround and fpextend 608/// nodes that target the FP stack to be store and load to the stack. This is a 609/// gross hack. We would like to simply mark these as being illegal, but when 610/// we do that, legalize produces these when it expands calls, then expands 611/// these in the same legalize pass. We would like dag combine to be able to 612/// hack on these between the call expansion and the node legalization. As such 613/// this pass basically does "really late" legalization of these inline with the 614/// X86 isel pass. 615void X86DAGToDAGISel::PreprocessForFPConvert() { 616 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(), 617 E = CurDAG->allnodes_end(); I != E; ) { 618 SDNode *N = I++; // Preincrement iterator to avoid invalidation issues. 619 if (N->getOpcode() != ISD::FP_ROUND && N->getOpcode() != ISD::FP_EXTEND) 620 continue; 621 622 // If the source and destination are SSE registers, then this is a legal 623 // conversion that should not be lowered. 624 EVT SrcVT = N->getOperand(0).getValueType(); 625 EVT DstVT = N->getValueType(0); 626 bool SrcIsSSE = X86Lowering.isScalarFPTypeInSSEReg(SrcVT); 627 bool DstIsSSE = X86Lowering.isScalarFPTypeInSSEReg(DstVT); 628 if (SrcIsSSE && DstIsSSE) 629 continue; 630 631 if (!SrcIsSSE && !DstIsSSE) { 632 // If this is an FPStack extension, it is a noop. 633 if (N->getOpcode() == ISD::FP_EXTEND) 634 continue; 635 // If this is a value-preserving FPStack truncation, it is a noop. 636 if (N->getConstantOperandVal(1)) 637 continue; 638 } 639 640 // Here we could have an FP stack truncation or an FPStack <-> SSE convert. 641 // FPStack has extload and truncstore. SSE can fold direct loads into other 642 // operations. Based on this, decide what we want to do. 643 EVT MemVT; 644 if (N->getOpcode() == ISD::FP_ROUND) 645 MemVT = DstVT; // FP_ROUND must use DstVT, we can't do a 'trunc load'. 646 else 647 MemVT = SrcIsSSE ? SrcVT : DstVT; 648 649 SDValue MemTmp = CurDAG->CreateStackTemporary(MemVT); 650 DebugLoc dl = N->getDebugLoc(); 651 652 // FIXME: optimize the case where the src/dest is a load or store? 653 SDValue Store = CurDAG->getTruncStore(CurDAG->getEntryNode(), dl, 654 N->getOperand(0), 655 MemTmp, NULL, 0, MemVT); 656 SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, dl, DstVT, Store, MemTmp, 657 NULL, 0, MemVT); 658 659 // We're about to replace all uses of the FP_ROUND/FP_EXTEND with the 660 // extload we created. This will cause general havok on the dag because 661 // anything below the conversion could be folded into other existing nodes. 662 // To avoid invalidating 'I', back it up to the convert node. 663 --I; 664 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), Result); 665 666 // Now that we did that, the node is dead. Increment the iterator to the 667 // next node to process, then delete N. 668 ++I; 669 CurDAG->DeleteNode(N); 670 } 671} 672 673/// InstructionSelectBasicBlock - This callback is invoked by SelectionDAGISel 674/// when it has created a SelectionDAG for us to codegen. 675void X86DAGToDAGISel::InstructionSelect() { 676 const Function *F = MF->getFunction(); 677 OptForSize = F->hasFnAttr(Attribute::OptimizeForSize); 678 679 if (OptLevel != CodeGenOpt::None) 680 PreprocessForRMW(); 681 682 // FIXME: This should only happen when not compiled with -O0. 683 PreprocessForFPConvert(); 684 685 // Codegen the basic block. 686#ifndef NDEBUG 687 DEBUG(dbgs() << "===== Instruction selection begins:\n"); 688 Indent = 0; 689#endif 690 SelectRoot(*CurDAG); 691#ifndef NDEBUG 692 DEBUG(dbgs() << "===== Instruction selection ends:\n"); 693#endif 694 695 CurDAG->RemoveDeadNodes(); 696} 697 698/// EmitSpecialCodeForMain - Emit any code that needs to be executed only in 699/// the main function. 700void X86DAGToDAGISel::EmitSpecialCodeForMain(MachineBasicBlock *BB, 701 MachineFrameInfo *MFI) { 702 const TargetInstrInfo *TII = TM.getInstrInfo(); 703 if (Subtarget->isTargetCygMing()) 704 BuildMI(BB, DebugLoc::getUnknownLoc(), 705 TII->get(X86::CALLpcrel32)).addExternalSymbol("__main"); 706} 707 708void X86DAGToDAGISel::EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) { 709 // If this is main, emit special code for main. 710 MachineBasicBlock *BB = MF.begin(); 711 if (Fn.hasExternalLinkage() && Fn.getName() == "main") 712 EmitSpecialCodeForMain(BB, MF.getFrameInfo()); 713} 714 715 716bool X86DAGToDAGISel::MatchSegmentBaseAddress(SDValue N, 717 X86ISelAddressMode &AM) { 718 assert(N.getOpcode() == X86ISD::SegmentBaseAddress); 719 SDValue Segment = N.getOperand(0); 720 721 if (AM.Segment.getNode() == 0) { 722 AM.Segment = Segment; 723 return false; 724 } 725 726 return true; 727} 728 729bool X86DAGToDAGISel::MatchLoad(SDValue N, X86ISelAddressMode &AM) { 730 // This optimization is valid because the GNU TLS model defines that 731 // gs:0 (or fs:0 on X86-64) contains its own address. 732 // For more information see http://people.redhat.com/drepper/tls.pdf 733 734 SDValue Address = N.getOperand(1); 735 if (Address.getOpcode() == X86ISD::SegmentBaseAddress && 736 !MatchSegmentBaseAddress (Address, AM)) 737 return false; 738 739 return true; 740} 741 742/// MatchWrapper - Try to match X86ISD::Wrapper and X86ISD::WrapperRIP nodes 743/// into an addressing mode. These wrap things that will resolve down into a 744/// symbol reference. If no match is possible, this returns true, otherwise it 745/// returns false. 746bool X86DAGToDAGISel::MatchWrapper(SDValue N, X86ISelAddressMode &AM) { 747 // If the addressing mode already has a symbol as the displacement, we can 748 // never match another symbol. 749 if (AM.hasSymbolicDisplacement()) 750 return true; 751 752 SDValue N0 = N.getOperand(0); 753 CodeModel::Model M = TM.getCodeModel(); 754 755 // Handle X86-64 rip-relative addresses. We check this before checking direct 756 // folding because RIP is preferable to non-RIP accesses. 757 if (Subtarget->is64Bit() && 758 // Under X86-64 non-small code model, GV (and friends) are 64-bits, so 759 // they cannot be folded into immediate fields. 760 // FIXME: This can be improved for kernel and other models? 761 (M == CodeModel::Small || M == CodeModel::Kernel) && 762 // Base and index reg must be 0 in order to use %rip as base and lowering 763 // must allow RIP. 764 !AM.hasBaseOrIndexReg() && N.getOpcode() == X86ISD::WrapperRIP) { 765 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) { 766 int64_t Offset = AM.Disp + G->getOffset(); 767 if (!X86::isOffsetSuitableForCodeModel(Offset, M)) return true; 768 AM.GV = G->getGlobal(); 769 AM.Disp = Offset; 770 AM.SymbolFlags = G->getTargetFlags(); 771 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) { 772 int64_t Offset = AM.Disp + CP->getOffset(); 773 if (!X86::isOffsetSuitableForCodeModel(Offset, M)) return true; 774 AM.CP = CP->getConstVal(); 775 AM.Align = CP->getAlignment(); 776 AM.Disp = Offset; 777 AM.SymbolFlags = CP->getTargetFlags(); 778 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) { 779 AM.ES = S->getSymbol(); 780 AM.SymbolFlags = S->getTargetFlags(); 781 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) { 782 AM.JT = J->getIndex(); 783 AM.SymbolFlags = J->getTargetFlags(); 784 } else { 785 AM.BlockAddr = cast<BlockAddressSDNode>(N0)->getBlockAddress(); 786 AM.SymbolFlags = cast<BlockAddressSDNode>(N0)->getTargetFlags(); 787 } 788 789 if (N.getOpcode() == X86ISD::WrapperRIP) 790 AM.setBaseReg(CurDAG->getRegister(X86::RIP, MVT::i64)); 791 return false; 792 } 793 794 // Handle the case when globals fit in our immediate field: This is true for 795 // X86-32 always and X86-64 when in -static -mcmodel=small mode. In 64-bit 796 // mode, this results in a non-RIP-relative computation. 797 if (!Subtarget->is64Bit() || 798 ((M == CodeModel::Small || M == CodeModel::Kernel) && 799 TM.getRelocationModel() == Reloc::Static)) { 800 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) { 801 AM.GV = G->getGlobal(); 802 AM.Disp += G->getOffset(); 803 AM.SymbolFlags = G->getTargetFlags(); 804 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) { 805 AM.CP = CP->getConstVal(); 806 AM.Align = CP->getAlignment(); 807 AM.Disp += CP->getOffset(); 808 AM.SymbolFlags = CP->getTargetFlags(); 809 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) { 810 AM.ES = S->getSymbol(); 811 AM.SymbolFlags = S->getTargetFlags(); 812 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) { 813 AM.JT = J->getIndex(); 814 AM.SymbolFlags = J->getTargetFlags(); 815 } else { 816 AM.BlockAddr = cast<BlockAddressSDNode>(N0)->getBlockAddress(); 817 AM.SymbolFlags = cast<BlockAddressSDNode>(N0)->getTargetFlags(); 818 } 819 return false; 820 } 821 822 return true; 823} 824 825/// MatchAddress - Add the specified node to the specified addressing mode, 826/// returning true if it cannot be done. This just pattern matches for the 827/// addressing mode. 828bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM) { 829 if (MatchAddressRecursively(N, AM, 0)) 830 return true; 831 832 // Post-processing: Convert lea(,%reg,2) to lea(%reg,%reg), which has 833 // a smaller encoding and avoids a scaled-index. 834 if (AM.Scale == 2 && 835 AM.BaseType == X86ISelAddressMode::RegBase && 836 AM.Base.Reg.getNode() == 0) { 837 AM.Base.Reg = AM.IndexReg; 838 AM.Scale = 1; 839 } 840 841 // Post-processing: Convert foo to foo(%rip), even in non-PIC mode, 842 // because it has a smaller encoding. 843 // TODO: Which other code models can use this? 844 if (TM.getCodeModel() == CodeModel::Small && 845 Subtarget->is64Bit() && 846 AM.Scale == 1 && 847 AM.BaseType == X86ISelAddressMode::RegBase && 848 AM.Base.Reg.getNode() == 0 && 849 AM.IndexReg.getNode() == 0 && 850 AM.SymbolFlags == X86II::MO_NO_FLAG && 851 AM.hasSymbolicDisplacement()) 852 AM.Base.Reg = CurDAG->getRegister(X86::RIP, MVT::i64); 853 854 return false; 855} 856 857bool X86DAGToDAGISel::MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM, 858 unsigned Depth) { 859 bool is64Bit = Subtarget->is64Bit(); 860 DebugLoc dl = N.getDebugLoc(); 861 DEBUG({ 862 dbgs() << "MatchAddress: "; 863 AM.dump(); 864 }); 865 // Limit recursion. 866 if (Depth > 5) 867 return MatchAddressBase(N, AM); 868 869 CodeModel::Model M = TM.getCodeModel(); 870 871 // If this is already a %rip relative address, we can only merge immediates 872 // into it. Instead of handling this in every case, we handle it here. 873 // RIP relative addressing: %rip + 32-bit displacement! 874 if (AM.isRIPRelative()) { 875 // FIXME: JumpTable and ExternalSymbol address currently don't like 876 // displacements. It isn't very important, but this should be fixed for 877 // consistency. 878 if (!AM.ES && AM.JT != -1) return true; 879 880 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N)) { 881 int64_t Val = AM.Disp + Cst->getSExtValue(); 882 if (X86::isOffsetSuitableForCodeModel(Val, M, 883 AM.hasSymbolicDisplacement())) { 884 AM.Disp = Val; 885 return false; 886 } 887 } 888 return true; 889 } 890 891 switch (N.getOpcode()) { 892 default: break; 893 case ISD::Constant: { 894 uint64_t Val = cast<ConstantSDNode>(N)->getSExtValue(); 895 if (!is64Bit || 896 X86::isOffsetSuitableForCodeModel(AM.Disp + Val, M, 897 AM.hasSymbolicDisplacement())) { 898 AM.Disp += Val; 899 return false; 900 } 901 break; 902 } 903 904 case X86ISD::SegmentBaseAddress: 905 if (!MatchSegmentBaseAddress(N, AM)) 906 return false; 907 break; 908 909 case X86ISD::Wrapper: 910 case X86ISD::WrapperRIP: 911 if (!MatchWrapper(N, AM)) 912 return false; 913 break; 914 915 case ISD::LOAD: 916 if (!MatchLoad(N, AM)) 917 return false; 918 break; 919 920 case ISD::FrameIndex: 921 if (AM.BaseType == X86ISelAddressMode::RegBase 922 && AM.Base.Reg.getNode() == 0) { 923 AM.BaseType = X86ISelAddressMode::FrameIndexBase; 924 AM.Base.FrameIndex = cast<FrameIndexSDNode>(N)->getIndex(); 925 return false; 926 } 927 break; 928 929 case ISD::SHL: 930 if (AM.IndexReg.getNode() != 0 || AM.Scale != 1) 931 break; 932 933 if (ConstantSDNode 934 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1))) { 935 unsigned Val = CN->getZExtValue(); 936 // Note that we handle x<<1 as (,x,2) rather than (x,x) here so 937 // that the base operand remains free for further matching. If 938 // the base doesn't end up getting used, a post-processing step 939 // in MatchAddress turns (,x,2) into (x,x), which is cheaper. 940 if (Val == 1 || Val == 2 || Val == 3) { 941 AM.Scale = 1 << Val; 942 SDValue ShVal = N.getNode()->getOperand(0); 943 944 // Okay, we know that we have a scale by now. However, if the scaled 945 // value is an add of something and a constant, we can fold the 946 // constant into the disp field here. 947 if (ShVal.getNode()->getOpcode() == ISD::ADD && 948 isa<ConstantSDNode>(ShVal.getNode()->getOperand(1))) { 949 AM.IndexReg = ShVal.getNode()->getOperand(0); 950 ConstantSDNode *AddVal = 951 cast<ConstantSDNode>(ShVal.getNode()->getOperand(1)); 952 uint64_t Disp = AM.Disp + (AddVal->getSExtValue() << Val); 953 if (!is64Bit || 954 X86::isOffsetSuitableForCodeModel(Disp, M, 955 AM.hasSymbolicDisplacement())) 956 AM.Disp = Disp; 957 else 958 AM.IndexReg = ShVal; 959 } else { 960 AM.IndexReg = ShVal; 961 } 962 return false; 963 } 964 break; 965 } 966 967 case ISD::SMUL_LOHI: 968 case ISD::UMUL_LOHI: 969 // A mul_lohi where we need the low part can be folded as a plain multiply. 970 if (N.getResNo() != 0) break; 971 // FALL THROUGH 972 case ISD::MUL: 973 case X86ISD::MUL_IMM: 974 // X*[3,5,9] -> X+X*[2,4,8] 975 if (AM.BaseType == X86ISelAddressMode::RegBase && 976 AM.Base.Reg.getNode() == 0 && 977 AM.IndexReg.getNode() == 0) { 978 if (ConstantSDNode 979 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1))) 980 if (CN->getZExtValue() == 3 || CN->getZExtValue() == 5 || 981 CN->getZExtValue() == 9) { 982 AM.Scale = unsigned(CN->getZExtValue())-1; 983 984 SDValue MulVal = N.getNode()->getOperand(0); 985 SDValue Reg; 986 987 // Okay, we know that we have a scale by now. However, if the scaled 988 // value is an add of something and a constant, we can fold the 989 // constant into the disp field here. 990 if (MulVal.getNode()->getOpcode() == ISD::ADD && MulVal.hasOneUse() && 991 isa<ConstantSDNode>(MulVal.getNode()->getOperand(1))) { 992 Reg = MulVal.getNode()->getOperand(0); 993 ConstantSDNode *AddVal = 994 cast<ConstantSDNode>(MulVal.getNode()->getOperand(1)); 995 uint64_t Disp = AM.Disp + AddVal->getSExtValue() * 996 CN->getZExtValue(); 997 if (!is64Bit || 998 X86::isOffsetSuitableForCodeModel(Disp, M, 999 AM.hasSymbolicDisplacement())) 1000 AM.Disp = Disp; 1001 else 1002 Reg = N.getNode()->getOperand(0); 1003 } else { 1004 Reg = N.getNode()->getOperand(0); 1005 } 1006 1007 AM.IndexReg = AM.Base.Reg = Reg; 1008 return false; 1009 } 1010 } 1011 break; 1012 1013 case ISD::SUB: { 1014 // Given A-B, if A can be completely folded into the address and 1015 // the index field with the index field unused, use -B as the index. 1016 // This is a win if a has multiple parts that can be folded into 1017 // the address. Also, this saves a mov if the base register has 1018 // other uses, since it avoids a two-address sub instruction, however 1019 // it costs an additional mov if the index register has other uses. 1020 1021 // Test if the LHS of the sub can be folded. 1022 X86ISelAddressMode Backup = AM; 1023 if (MatchAddressRecursively(N.getNode()->getOperand(0), AM, Depth+1)) { 1024 AM = Backup; 1025 break; 1026 } 1027 // Test if the index field is free for use. 1028 if (AM.IndexReg.getNode() || AM.isRIPRelative()) { 1029 AM = Backup; 1030 break; 1031 } 1032 int Cost = 0; 1033 SDValue RHS = N.getNode()->getOperand(1); 1034 // If the RHS involves a register with multiple uses, this 1035 // transformation incurs an extra mov, due to the neg instruction 1036 // clobbering its operand. 1037 if (!RHS.getNode()->hasOneUse() || 1038 RHS.getNode()->getOpcode() == ISD::CopyFromReg || 1039 RHS.getNode()->getOpcode() == ISD::TRUNCATE || 1040 RHS.getNode()->getOpcode() == ISD::ANY_EXTEND || 1041 (RHS.getNode()->getOpcode() == ISD::ZERO_EXTEND && 1042 RHS.getNode()->getOperand(0).getValueType() == MVT::i32)) 1043 ++Cost; 1044 // If the base is a register with multiple uses, this 1045 // transformation may save a mov. 1046 if ((AM.BaseType == X86ISelAddressMode::RegBase && 1047 AM.Base.Reg.getNode() && 1048 !AM.Base.Reg.getNode()->hasOneUse()) || 1049 AM.BaseType == X86ISelAddressMode::FrameIndexBase) 1050 --Cost; 1051 // If the folded LHS was interesting, this transformation saves 1052 // address arithmetic. 1053 if ((AM.hasSymbolicDisplacement() && !Backup.hasSymbolicDisplacement()) + 1054 ((AM.Disp != 0) && (Backup.Disp == 0)) + 1055 (AM.Segment.getNode() && !Backup.Segment.getNode()) >= 2) 1056 --Cost; 1057 // If it doesn't look like it may be an overall win, don't do it. 1058 if (Cost >= 0) { 1059 AM = Backup; 1060 break; 1061 } 1062 1063 // Ok, the transformation is legal and appears profitable. Go for it. 1064 SDValue Zero = CurDAG->getConstant(0, N.getValueType()); 1065 SDValue Neg = CurDAG->getNode(ISD::SUB, dl, N.getValueType(), Zero, RHS); 1066 AM.IndexReg = Neg; 1067 AM.Scale = 1; 1068 1069 // Insert the new nodes into the topological ordering. 1070 if (Zero.getNode()->getNodeId() == -1 || 1071 Zero.getNode()->getNodeId() > N.getNode()->getNodeId()) { 1072 CurDAG->RepositionNode(N.getNode(), Zero.getNode()); 1073 Zero.getNode()->setNodeId(N.getNode()->getNodeId()); 1074 } 1075 if (Neg.getNode()->getNodeId() == -1 || 1076 Neg.getNode()->getNodeId() > N.getNode()->getNodeId()) { 1077 CurDAG->RepositionNode(N.getNode(), Neg.getNode()); 1078 Neg.getNode()->setNodeId(N.getNode()->getNodeId()); 1079 } 1080 return false; 1081 } 1082 1083 case ISD::ADD: { 1084 X86ISelAddressMode Backup = AM; 1085 if (!MatchAddressRecursively(N.getNode()->getOperand(0), AM, Depth+1) && 1086 !MatchAddressRecursively(N.getNode()->getOperand(1), AM, Depth+1)) 1087 return false; 1088 AM = Backup; 1089 if (!MatchAddressRecursively(N.getNode()->getOperand(1), AM, Depth+1) && 1090 !MatchAddressRecursively(N.getNode()->getOperand(0), AM, Depth+1)) 1091 return false; 1092 AM = Backup; 1093 1094 // If we couldn't fold both operands into the address at the same time, 1095 // see if we can just put each operand into a register and fold at least 1096 // the add. 1097 if (AM.BaseType == X86ISelAddressMode::RegBase && 1098 !AM.Base.Reg.getNode() && 1099 !AM.IndexReg.getNode()) { 1100 AM.Base.Reg = N.getNode()->getOperand(0); 1101 AM.IndexReg = N.getNode()->getOperand(1); 1102 AM.Scale = 1; 1103 return false; 1104 } 1105 break; 1106 } 1107 1108 case ISD::OR: 1109 // Handle "X | C" as "X + C" iff X is known to have C bits clear. 1110 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 1111 X86ISelAddressMode Backup = AM; 1112 uint64_t Offset = CN->getSExtValue(); 1113 // Start with the LHS as an addr mode. 1114 if (!MatchAddressRecursively(N.getOperand(0), AM, Depth+1) && 1115 // Address could not have picked a GV address for the displacement. 1116 AM.GV == NULL && 1117 // On x86-64, the resultant disp must fit in 32-bits. 1118 (!is64Bit || 1119 X86::isOffsetSuitableForCodeModel(AM.Disp + Offset, M, 1120 AM.hasSymbolicDisplacement())) && 1121 // Check to see if the LHS & C is zero. 1122 CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getAPIntValue())) { 1123 AM.Disp += Offset; 1124 return false; 1125 } 1126 AM = Backup; 1127 } 1128 break; 1129 1130 case ISD::AND: { 1131 // Perform some heroic transforms on an and of a constant-count shift 1132 // with a constant to enable use of the scaled offset field. 1133 1134 SDValue Shift = N.getOperand(0); 1135 if (Shift.getNumOperands() != 2) break; 1136 1137 // Scale must not be used already. 1138 if (AM.IndexReg.getNode() != 0 || AM.Scale != 1) break; 1139 1140 SDValue X = Shift.getOperand(0); 1141 ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N.getOperand(1)); 1142 ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(Shift.getOperand(1)); 1143 if (!C1 || !C2) break; 1144 1145 // Handle "(X >> (8-C1)) & C2" as "(X >> 8) & 0xff)" if safe. This 1146 // allows us to convert the shift and and into an h-register extract and 1147 // a scaled index. 1148 if (Shift.getOpcode() == ISD::SRL && Shift.hasOneUse()) { 1149 unsigned ScaleLog = 8 - C1->getZExtValue(); 1150 if (ScaleLog > 0 && ScaleLog < 4 && 1151 C2->getZExtValue() == (UINT64_C(0xff) << ScaleLog)) { 1152 SDValue Eight = CurDAG->getConstant(8, MVT::i8); 1153 SDValue Mask = CurDAG->getConstant(0xff, N.getValueType()); 1154 SDValue Srl = CurDAG->getNode(ISD::SRL, dl, N.getValueType(), 1155 X, Eight); 1156 SDValue And = CurDAG->getNode(ISD::AND, dl, N.getValueType(), 1157 Srl, Mask); 1158 SDValue ShlCount = CurDAG->getConstant(ScaleLog, MVT::i8); 1159 SDValue Shl = CurDAG->getNode(ISD::SHL, dl, N.getValueType(), 1160 And, ShlCount); 1161 1162 // Insert the new nodes into the topological ordering. 1163 if (Eight.getNode()->getNodeId() == -1 || 1164 Eight.getNode()->getNodeId() > X.getNode()->getNodeId()) { 1165 CurDAG->RepositionNode(X.getNode(), Eight.getNode()); 1166 Eight.getNode()->setNodeId(X.getNode()->getNodeId()); 1167 } 1168 if (Mask.getNode()->getNodeId() == -1 || 1169 Mask.getNode()->getNodeId() > X.getNode()->getNodeId()) { 1170 CurDAG->RepositionNode(X.getNode(), Mask.getNode()); 1171 Mask.getNode()->setNodeId(X.getNode()->getNodeId()); 1172 } 1173 if (Srl.getNode()->getNodeId() == -1 || 1174 Srl.getNode()->getNodeId() > Shift.getNode()->getNodeId()) { 1175 CurDAG->RepositionNode(Shift.getNode(), Srl.getNode()); 1176 Srl.getNode()->setNodeId(Shift.getNode()->getNodeId()); 1177 } 1178 if (And.getNode()->getNodeId() == -1 || 1179 And.getNode()->getNodeId() > N.getNode()->getNodeId()) { 1180 CurDAG->RepositionNode(N.getNode(), And.getNode()); 1181 And.getNode()->setNodeId(N.getNode()->getNodeId()); 1182 } 1183 if (ShlCount.getNode()->getNodeId() == -1 || 1184 ShlCount.getNode()->getNodeId() > X.getNode()->getNodeId()) { 1185 CurDAG->RepositionNode(X.getNode(), ShlCount.getNode()); 1186 ShlCount.getNode()->setNodeId(N.getNode()->getNodeId()); 1187 } 1188 if (Shl.getNode()->getNodeId() == -1 || 1189 Shl.getNode()->getNodeId() > N.getNode()->getNodeId()) { 1190 CurDAG->RepositionNode(N.getNode(), Shl.getNode()); 1191 Shl.getNode()->setNodeId(N.getNode()->getNodeId()); 1192 } 1193 CurDAG->ReplaceAllUsesWith(N, Shl); 1194 AM.IndexReg = And; 1195 AM.Scale = (1 << ScaleLog); 1196 return false; 1197 } 1198 } 1199 1200 // Handle "(X << C1) & C2" as "(X & (C2>>C1)) << C1" if safe and if this 1201 // allows us to fold the shift into this addressing mode. 1202 if (Shift.getOpcode() != ISD::SHL) break; 1203 1204 // Not likely to be profitable if either the AND or SHIFT node has more 1205 // than one use (unless all uses are for address computation). Besides, 1206 // isel mechanism requires their node ids to be reused. 1207 if (!N.hasOneUse() || !Shift.hasOneUse()) 1208 break; 1209 1210 // Verify that the shift amount is something we can fold. 1211 unsigned ShiftCst = C1->getZExtValue(); 1212 if (ShiftCst != 1 && ShiftCst != 2 && ShiftCst != 3) 1213 break; 1214 1215 // Get the new AND mask, this folds to a constant. 1216 SDValue NewANDMask = CurDAG->getNode(ISD::SRL, dl, N.getValueType(), 1217 SDValue(C2, 0), SDValue(C1, 0)); 1218 SDValue NewAND = CurDAG->getNode(ISD::AND, dl, N.getValueType(), X, 1219 NewANDMask); 1220 SDValue NewSHIFT = CurDAG->getNode(ISD::SHL, dl, N.getValueType(), 1221 NewAND, SDValue(C1, 0)); 1222 1223 // Insert the new nodes into the topological ordering. 1224 if (C1->getNodeId() > X.getNode()->getNodeId()) { 1225 CurDAG->RepositionNode(X.getNode(), C1); 1226 C1->setNodeId(X.getNode()->getNodeId()); 1227 } 1228 if (NewANDMask.getNode()->getNodeId() == -1 || 1229 NewANDMask.getNode()->getNodeId() > X.getNode()->getNodeId()) { 1230 CurDAG->RepositionNode(X.getNode(), NewANDMask.getNode()); 1231 NewANDMask.getNode()->setNodeId(X.getNode()->getNodeId()); 1232 } 1233 if (NewAND.getNode()->getNodeId() == -1 || 1234 NewAND.getNode()->getNodeId() > Shift.getNode()->getNodeId()) { 1235 CurDAG->RepositionNode(Shift.getNode(), NewAND.getNode()); 1236 NewAND.getNode()->setNodeId(Shift.getNode()->getNodeId()); 1237 } 1238 if (NewSHIFT.getNode()->getNodeId() == -1 || 1239 NewSHIFT.getNode()->getNodeId() > N.getNode()->getNodeId()) { 1240 CurDAG->RepositionNode(N.getNode(), NewSHIFT.getNode()); 1241 NewSHIFT.getNode()->setNodeId(N.getNode()->getNodeId()); 1242 } 1243 1244 CurDAG->ReplaceAllUsesWith(N, NewSHIFT); 1245 1246 AM.Scale = 1 << ShiftCst; 1247 AM.IndexReg = NewAND; 1248 return false; 1249 } 1250 } 1251 1252 return MatchAddressBase(N, AM); 1253} 1254 1255/// MatchAddressBase - Helper for MatchAddress. Add the specified node to the 1256/// specified addressing mode without any further recursion. 1257bool X86DAGToDAGISel::MatchAddressBase(SDValue N, X86ISelAddressMode &AM) { 1258 // Is the base register already occupied? 1259 if (AM.BaseType != X86ISelAddressMode::RegBase || AM.Base.Reg.getNode()) { 1260 // If so, check to see if the scale index register is set. 1261 if (AM.IndexReg.getNode() == 0) { 1262 AM.IndexReg = N; 1263 AM.Scale = 1; 1264 return false; 1265 } 1266 1267 // Otherwise, we cannot select it. 1268 return true; 1269 } 1270 1271 // Default, generate it as a register. 1272 AM.BaseType = X86ISelAddressMode::RegBase; 1273 AM.Base.Reg = N; 1274 return false; 1275} 1276 1277/// SelectAddr - returns true if it is able pattern match an addressing mode. 1278/// It returns the operands which make up the maximal addressing mode it can 1279/// match by reference. 1280bool X86DAGToDAGISel::SelectAddr(SDNode *Op, SDValue N, SDValue &Base, 1281 SDValue &Scale, SDValue &Index, 1282 SDValue &Disp, SDValue &Segment) { 1283 X86ISelAddressMode AM; 1284 if (MatchAddress(N, AM)) 1285 return false; 1286 1287 EVT VT = N.getValueType(); 1288 if (AM.BaseType == X86ISelAddressMode::RegBase) { 1289 if (!AM.Base.Reg.getNode()) 1290 AM.Base.Reg = CurDAG->getRegister(0, VT); 1291 } 1292 1293 if (!AM.IndexReg.getNode()) 1294 AM.IndexReg = CurDAG->getRegister(0, VT); 1295 1296 getAddressOperands(AM, Base, Scale, Index, Disp, Segment); 1297 return true; 1298} 1299 1300/// SelectScalarSSELoad - Match a scalar SSE load. In particular, we want to 1301/// match a load whose top elements are either undef or zeros. The load flavor 1302/// is derived from the type of N, which is either v4f32 or v2f64. 1303bool X86DAGToDAGISel::SelectScalarSSELoad(SDNode *Op, SDValue Pred, 1304 SDValue N, SDValue &Base, 1305 SDValue &Scale, SDValue &Index, 1306 SDValue &Disp, SDValue &Segment, 1307 SDValue &InChain, 1308 SDValue &OutChain) { 1309 if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) { 1310 InChain = N.getOperand(0).getValue(1); 1311 if (ISD::isNON_EXTLoad(InChain.getNode()) && 1312 InChain.getValue(0).hasOneUse() && 1313 N.hasOneUse() && 1314 IsLegalAndProfitableToFold(N.getNode(), Pred.getNode(), Op)) { 1315 LoadSDNode *LD = cast<LoadSDNode>(InChain); 1316 if (!SelectAddr(Op, LD->getBasePtr(), Base, Scale, Index, Disp, Segment)) 1317 return false; 1318 OutChain = LD->getChain(); 1319 return true; 1320 } 1321 } 1322 1323 // Also handle the case where we explicitly require zeros in the top 1324 // elements. This is a vector shuffle from the zero vector. 1325 if (N.getOpcode() == X86ISD::VZEXT_MOVL && N.getNode()->hasOneUse() && 1326 // Check to see if the top elements are all zeros (or bitcast of zeros). 1327 N.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR && 1328 N.getOperand(0).getNode()->hasOneUse() && 1329 ISD::isNON_EXTLoad(N.getOperand(0).getOperand(0).getNode()) && 1330 N.getOperand(0).getOperand(0).hasOneUse()) { 1331 // Okay, this is a zero extending load. Fold it. 1332 LoadSDNode *LD = cast<LoadSDNode>(N.getOperand(0).getOperand(0)); 1333 if (!SelectAddr(Op, LD->getBasePtr(), Base, Scale, Index, Disp, Segment)) 1334 return false; 1335 OutChain = LD->getChain(); 1336 InChain = SDValue(LD, 1); 1337 return true; 1338 } 1339 return false; 1340} 1341 1342 1343/// SelectLEAAddr - it calls SelectAddr and determines if the maximal addressing 1344/// mode it matches can be cost effectively emitted as an LEA instruction. 1345bool X86DAGToDAGISel::SelectLEAAddr(SDNode *Op, SDValue N, 1346 SDValue &Base, SDValue &Scale, 1347 SDValue &Index, SDValue &Disp) { 1348 X86ISelAddressMode AM; 1349 1350 // Set AM.Segment to prevent MatchAddress from using one. LEA doesn't support 1351 // segments. 1352 SDValue Copy = AM.Segment; 1353 SDValue T = CurDAG->getRegister(0, MVT::i32); 1354 AM.Segment = T; 1355 if (MatchAddress(N, AM)) 1356 return false; 1357 assert (T == AM.Segment); 1358 AM.Segment = Copy; 1359 1360 EVT VT = N.getValueType(); 1361 unsigned Complexity = 0; 1362 if (AM.BaseType == X86ISelAddressMode::RegBase) 1363 if (AM.Base.Reg.getNode()) 1364 Complexity = 1; 1365 else 1366 AM.Base.Reg = CurDAG->getRegister(0, VT); 1367 else if (AM.BaseType == X86ISelAddressMode::FrameIndexBase) 1368 Complexity = 4; 1369 1370 if (AM.IndexReg.getNode()) 1371 Complexity++; 1372 else 1373 AM.IndexReg = CurDAG->getRegister(0, VT); 1374 1375 // Don't match just leal(,%reg,2). It's cheaper to do addl %reg, %reg, or with 1376 // a simple shift. 1377 if (AM.Scale > 1) 1378 Complexity++; 1379 1380 // FIXME: We are artificially lowering the criteria to turn ADD %reg, $GA 1381 // to a LEA. This is determined with some expermentation but is by no means 1382 // optimal (especially for code size consideration). LEA is nice because of 1383 // its three-address nature. Tweak the cost function again when we can run 1384 // convertToThreeAddress() at register allocation time. 1385 if (AM.hasSymbolicDisplacement()) { 1386 // For X86-64, we should always use lea to materialize RIP relative 1387 // addresses. 1388 if (Subtarget->is64Bit()) 1389 Complexity = 4; 1390 else 1391 Complexity += 2; 1392 } 1393 1394 if (AM.Disp && (AM.Base.Reg.getNode() || AM.IndexReg.getNode())) 1395 Complexity++; 1396 1397 // If it isn't worth using an LEA, reject it. 1398 if (Complexity <= 2) 1399 return false; 1400 1401 SDValue Segment; 1402 getAddressOperands(AM, Base, Scale, Index, Disp, Segment); 1403 return true; 1404} 1405 1406/// SelectTLSADDRAddr - This is only run on TargetGlobalTLSAddress nodes. 1407bool X86DAGToDAGISel::SelectTLSADDRAddr(SDNode *Op, SDValue N, SDValue &Base, 1408 SDValue &Scale, SDValue &Index, 1409 SDValue &Disp) { 1410 assert(Op->getOpcode() == X86ISD::TLSADDR); 1411 assert(N.getOpcode() == ISD::TargetGlobalTLSAddress); 1412 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N); 1413 1414 X86ISelAddressMode AM; 1415 AM.GV = GA->getGlobal(); 1416 AM.Disp += GA->getOffset(); 1417 AM.Base.Reg = CurDAG->getRegister(0, N.getValueType()); 1418 AM.SymbolFlags = GA->getTargetFlags(); 1419 1420 if (N.getValueType() == MVT::i32) { 1421 AM.Scale = 1; 1422 AM.IndexReg = CurDAG->getRegister(X86::EBX, MVT::i32); 1423 } else { 1424 AM.IndexReg = CurDAG->getRegister(0, MVT::i64); 1425 } 1426 1427 SDValue Segment; 1428 getAddressOperands(AM, Base, Scale, Index, Disp, Segment); 1429 return true; 1430} 1431 1432 1433bool X86DAGToDAGISel::TryFoldLoad(SDNode *P, SDValue N, 1434 SDValue &Base, SDValue &Scale, 1435 SDValue &Index, SDValue &Disp, 1436 SDValue &Segment) { 1437 if (ISD::isNON_EXTLoad(N.getNode()) && 1438 N.hasOneUse() && 1439 IsLegalAndProfitableToFold(N.getNode(), P, P)) 1440 return SelectAddr(P, N.getOperand(1), Base, Scale, Index, Disp, Segment); 1441 return false; 1442} 1443 1444/// getGlobalBaseReg - Return an SDNode that returns the value of 1445/// the global base register. Output instructions required to 1446/// initialize the global base register, if necessary. 1447/// 1448SDNode *X86DAGToDAGISel::getGlobalBaseReg() { 1449 unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF); 1450 return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode(); 1451} 1452 1453static SDNode *FindCallStartFromCall(SDNode *Node) { 1454 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 1455 assert(Node->getOperand(0).getValueType() == MVT::Other && 1456 "Node doesn't have a token chain argument!"); 1457 return FindCallStartFromCall(Node->getOperand(0).getNode()); 1458} 1459 1460SDNode *X86DAGToDAGISel::SelectAtomic64(SDNode *Node, unsigned Opc) { 1461 SDValue Chain = Node->getOperand(0); 1462 SDValue In1 = Node->getOperand(1); 1463 SDValue In2L = Node->getOperand(2); 1464 SDValue In2H = Node->getOperand(3); 1465 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; 1466 if (!SelectAddr(In1.getNode(), In1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) 1467 return NULL; 1468 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1); 1469 MemOp[0] = cast<MemSDNode>(Node)->getMemOperand(); 1470 const SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, In2L, In2H, Chain}; 1471 SDNode *ResNode = CurDAG->getMachineNode(Opc, Node->getDebugLoc(), 1472 MVT::i32, MVT::i32, MVT::Other, Ops, 1473 array_lengthof(Ops)); 1474 cast<MachineSDNode>(ResNode)->setMemRefs(MemOp, MemOp + 1); 1475 return ResNode; 1476} 1477 1478SDNode *X86DAGToDAGISel::SelectAtomicLoadAdd(SDNode *Node, EVT NVT) { 1479 if (Node->hasAnyUseOfValue(0)) 1480 return 0; 1481 1482 // Optimize common patterns for __sync_add_and_fetch and 1483 // __sync_sub_and_fetch where the result is not used. This allows us 1484 // to use "lock" version of add, sub, inc, dec instructions. 1485 // FIXME: Do not use special instructions but instead add the "lock" 1486 // prefix to the target node somehow. The extra information will then be 1487 // transferred to machine instruction and it denotes the prefix. 1488 SDValue Chain = Node->getOperand(0); 1489 SDValue Ptr = Node->getOperand(1); 1490 SDValue Val = Node->getOperand(2); 1491 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; 1492 if (!SelectAddr(Ptr.getNode(), Ptr, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) 1493 return 0; 1494 1495 bool isInc = false, isDec = false, isSub = false, isCN = false; 1496 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val); 1497 if (CN) { 1498 isCN = true; 1499 int64_t CNVal = CN->getSExtValue(); 1500 if (CNVal == 1) 1501 isInc = true; 1502 else if (CNVal == -1) 1503 isDec = true; 1504 else if (CNVal >= 0) 1505 Val = CurDAG->getTargetConstant(CNVal, NVT); 1506 else { 1507 isSub = true; 1508 Val = CurDAG->getTargetConstant(-CNVal, NVT); 1509 } 1510 } else if (Val.hasOneUse() && 1511 Val.getOpcode() == ISD::SUB && 1512 X86::isZeroNode(Val.getOperand(0))) { 1513 isSub = true; 1514 Val = Val.getOperand(1); 1515 } 1516 1517 unsigned Opc = 0; 1518 switch (NVT.getSimpleVT().SimpleTy) { 1519 default: return 0; 1520 case MVT::i8: 1521 if (isInc) 1522 Opc = X86::LOCK_INC8m; 1523 else if (isDec) 1524 Opc = X86::LOCK_DEC8m; 1525 else if (isSub) { 1526 if (isCN) 1527 Opc = X86::LOCK_SUB8mi; 1528 else 1529 Opc = X86::LOCK_SUB8mr; 1530 } else { 1531 if (isCN) 1532 Opc = X86::LOCK_ADD8mi; 1533 else 1534 Opc = X86::LOCK_ADD8mr; 1535 } 1536 break; 1537 case MVT::i16: 1538 if (isInc) 1539 Opc = X86::LOCK_INC16m; 1540 else if (isDec) 1541 Opc = X86::LOCK_DEC16m; 1542 else if (isSub) { 1543 if (isCN) { 1544 if (Predicate_i16immSExt8(Val.getNode())) 1545 Opc = X86::LOCK_SUB16mi8; 1546 else 1547 Opc = X86::LOCK_SUB16mi; 1548 } else 1549 Opc = X86::LOCK_SUB16mr; 1550 } else { 1551 if (isCN) { 1552 if (Predicate_i16immSExt8(Val.getNode())) 1553 Opc = X86::LOCK_ADD16mi8; 1554 else 1555 Opc = X86::LOCK_ADD16mi; 1556 } else 1557 Opc = X86::LOCK_ADD16mr; 1558 } 1559 break; 1560 case MVT::i32: 1561 if (isInc) 1562 Opc = X86::LOCK_INC32m; 1563 else if (isDec) 1564 Opc = X86::LOCK_DEC32m; 1565 else if (isSub) { 1566 if (isCN) { 1567 if (Predicate_i32immSExt8(Val.getNode())) 1568 Opc = X86::LOCK_SUB32mi8; 1569 else 1570 Opc = X86::LOCK_SUB32mi; 1571 } else 1572 Opc = X86::LOCK_SUB32mr; 1573 } else { 1574 if (isCN) { 1575 if (Predicate_i32immSExt8(Val.getNode())) 1576 Opc = X86::LOCK_ADD32mi8; 1577 else 1578 Opc = X86::LOCK_ADD32mi; 1579 } else 1580 Opc = X86::LOCK_ADD32mr; 1581 } 1582 break; 1583 case MVT::i64: 1584 if (isInc) 1585 Opc = X86::LOCK_INC64m; 1586 else if (isDec) 1587 Opc = X86::LOCK_DEC64m; 1588 else if (isSub) { 1589 Opc = X86::LOCK_SUB64mr; 1590 if (isCN) { 1591 if (Predicate_i64immSExt8(Val.getNode())) 1592 Opc = X86::LOCK_SUB64mi8; 1593 else if (Predicate_i64immSExt32(Val.getNode())) 1594 Opc = X86::LOCK_SUB64mi32; 1595 } 1596 } else { 1597 Opc = X86::LOCK_ADD64mr; 1598 if (isCN) { 1599 if (Predicate_i64immSExt8(Val.getNode())) 1600 Opc = X86::LOCK_ADD64mi8; 1601 else if (Predicate_i64immSExt32(Val.getNode())) 1602 Opc = X86::LOCK_ADD64mi32; 1603 } 1604 } 1605 break; 1606 } 1607 1608 DebugLoc dl = Node->getDebugLoc(); 1609 SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, 1610 dl, NVT), 0); 1611 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1); 1612 MemOp[0] = cast<MemSDNode>(Node)->getMemOperand(); 1613 if (isInc || isDec) { 1614 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Chain }; 1615 SDValue Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 6), 0); 1616 cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1); 1617 SDValue RetVals[] = { Undef, Ret }; 1618 return CurDAG->getMergeValues(RetVals, 2, dl).getNode(); 1619 } else { 1620 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Val, Chain }; 1621 SDValue Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 7), 0); 1622 cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1); 1623 SDValue RetVals[] = { Undef, Ret }; 1624 return CurDAG->getMergeValues(RetVals, 2, dl).getNode(); 1625 } 1626} 1627 1628/// HasNoSignedComparisonUses - Test whether the given X86ISD::CMP node has 1629/// any uses which require the SF or OF bits to be accurate. 1630static bool HasNoSignedComparisonUses(SDNode *N) { 1631 // Examine each user of the node. 1632 for (SDNode::use_iterator UI = N->use_begin(), 1633 UE = N->use_end(); UI != UE; ++UI) { 1634 // Only examine CopyToReg uses. 1635 if (UI->getOpcode() != ISD::CopyToReg) 1636 return false; 1637 // Only examine CopyToReg uses that copy to EFLAGS. 1638 if (cast<RegisterSDNode>(UI->getOperand(1))->getReg() != 1639 X86::EFLAGS) 1640 return false; 1641 // Examine each user of the CopyToReg use. 1642 for (SDNode::use_iterator FlagUI = UI->use_begin(), 1643 FlagUE = UI->use_end(); FlagUI != FlagUE; ++FlagUI) { 1644 // Only examine the Flag result. 1645 if (FlagUI.getUse().getResNo() != 1) continue; 1646 // Anything unusual: assume conservatively. 1647 if (!FlagUI->isMachineOpcode()) return false; 1648 // Examine the opcode of the user. 1649 switch (FlagUI->getMachineOpcode()) { 1650 // These comparisons don't treat the most significant bit specially. 1651 case X86::SETAr: case X86::SETAEr: case X86::SETBr: case X86::SETBEr: 1652 case X86::SETEr: case X86::SETNEr: case X86::SETPr: case X86::SETNPr: 1653 case X86::SETAm: case X86::SETAEm: case X86::SETBm: case X86::SETBEm: 1654 case X86::SETEm: case X86::SETNEm: case X86::SETPm: case X86::SETNPm: 1655 case X86::JA: case X86::JAE: case X86::JB: case X86::JBE: 1656 case X86::JE: case X86::JNE: case X86::JP: case X86::JNP: 1657 case X86::CMOVA16rr: case X86::CMOVA16rm: 1658 case X86::CMOVA32rr: case X86::CMOVA32rm: 1659 case X86::CMOVA64rr: case X86::CMOVA64rm: 1660 case X86::CMOVAE16rr: case X86::CMOVAE16rm: 1661 case X86::CMOVAE32rr: case X86::CMOVAE32rm: 1662 case X86::CMOVAE64rr: case X86::CMOVAE64rm: 1663 case X86::CMOVB16rr: case X86::CMOVB16rm: 1664 case X86::CMOVB32rr: case X86::CMOVB32rm: 1665 case X86::CMOVB64rr: case X86::CMOVB64rm: 1666 case X86::CMOVBE16rr: case X86::CMOVBE16rm: 1667 case X86::CMOVBE32rr: case X86::CMOVBE32rm: 1668 case X86::CMOVBE64rr: case X86::CMOVBE64rm: 1669 case X86::CMOVE16rr: case X86::CMOVE16rm: 1670 case X86::CMOVE32rr: case X86::CMOVE32rm: 1671 case X86::CMOVE64rr: case X86::CMOVE64rm: 1672 case X86::CMOVNE16rr: case X86::CMOVNE16rm: 1673 case X86::CMOVNE32rr: case X86::CMOVNE32rm: 1674 case X86::CMOVNE64rr: case X86::CMOVNE64rm: 1675 case X86::CMOVNP16rr: case X86::CMOVNP16rm: 1676 case X86::CMOVNP32rr: case X86::CMOVNP32rm: 1677 case X86::CMOVNP64rr: case X86::CMOVNP64rm: 1678 case X86::CMOVP16rr: case X86::CMOVP16rm: 1679 case X86::CMOVP32rr: case X86::CMOVP32rm: 1680 case X86::CMOVP64rr: case X86::CMOVP64rm: 1681 continue; 1682 // Anything else: assume conservatively. 1683 default: return false; 1684 } 1685 } 1686 } 1687 return true; 1688} 1689 1690SDNode *X86DAGToDAGISel::Select(SDNode *Node) { 1691 EVT NVT = Node->getValueType(0); 1692 unsigned Opc, MOpc; 1693 unsigned Opcode = Node->getOpcode(); 1694 DebugLoc dl = Node->getDebugLoc(); 1695 1696#ifndef NDEBUG 1697 DEBUG({ 1698 dbgs() << std::string(Indent, ' ') << "Selecting: "; 1699 Node->dump(CurDAG); 1700 dbgs() << '\n'; 1701 }); 1702 Indent += 2; 1703#endif 1704 1705 if (Node->isMachineOpcode()) { 1706#ifndef NDEBUG 1707 DEBUG({ 1708 dbgs() << std::string(Indent-2, ' ') << "== "; 1709 Node->dump(CurDAG); 1710 dbgs() << '\n'; 1711 }); 1712 Indent -= 2; 1713#endif 1714 return NULL; // Already selected. 1715 } 1716 1717 switch (Opcode) { 1718 default: break; 1719 case X86ISD::GlobalBaseReg: 1720 return getGlobalBaseReg(); 1721 1722 case X86ISD::ATOMOR64_DAG: 1723 return SelectAtomic64(Node, X86::ATOMOR6432); 1724 case X86ISD::ATOMXOR64_DAG: 1725 return SelectAtomic64(Node, X86::ATOMXOR6432); 1726 case X86ISD::ATOMADD64_DAG: 1727 return SelectAtomic64(Node, X86::ATOMADD6432); 1728 case X86ISD::ATOMSUB64_DAG: 1729 return SelectAtomic64(Node, X86::ATOMSUB6432); 1730 case X86ISD::ATOMNAND64_DAG: 1731 return SelectAtomic64(Node, X86::ATOMNAND6432); 1732 case X86ISD::ATOMAND64_DAG: 1733 return SelectAtomic64(Node, X86::ATOMAND6432); 1734 case X86ISD::ATOMSWAP64_DAG: 1735 return SelectAtomic64(Node, X86::ATOMSWAP6432); 1736 1737 case ISD::ATOMIC_LOAD_ADD: { 1738 SDNode *RetVal = SelectAtomicLoadAdd(Node, NVT); 1739 if (RetVal) 1740 return RetVal; 1741 break; 1742 } 1743 1744 case ISD::SMUL_LOHI: 1745 case ISD::UMUL_LOHI: { 1746 SDValue N0 = Node->getOperand(0); 1747 SDValue N1 = Node->getOperand(1); 1748 1749 bool isSigned = Opcode == ISD::SMUL_LOHI; 1750 if (!isSigned) { 1751 switch (NVT.getSimpleVT().SimpleTy) { 1752 default: llvm_unreachable("Unsupported VT!"); 1753 case MVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break; 1754 case MVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break; 1755 case MVT::i32: Opc = X86::MUL32r; MOpc = X86::MUL32m; break; 1756 case MVT::i64: Opc = X86::MUL64r; MOpc = X86::MUL64m; break; 1757 } 1758 } else { 1759 switch (NVT.getSimpleVT().SimpleTy) { 1760 default: llvm_unreachable("Unsupported VT!"); 1761 case MVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break; 1762 case MVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break; 1763 case MVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break; 1764 case MVT::i64: Opc = X86::IMUL64r; MOpc = X86::IMUL64m; break; 1765 } 1766 } 1767 1768 unsigned LoReg, HiReg; 1769 switch (NVT.getSimpleVT().SimpleTy) { 1770 default: llvm_unreachable("Unsupported VT!"); 1771 case MVT::i8: LoReg = X86::AL; HiReg = X86::AH; break; 1772 case MVT::i16: LoReg = X86::AX; HiReg = X86::DX; break; 1773 case MVT::i32: LoReg = X86::EAX; HiReg = X86::EDX; break; 1774 case MVT::i64: LoReg = X86::RAX; HiReg = X86::RDX; break; 1775 } 1776 1777 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; 1778 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4); 1779 // Multiply is commmutative. 1780 if (!foldedLoad) { 1781 foldedLoad = TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4); 1782 if (foldedLoad) 1783 std::swap(N0, N1); 1784 } 1785 1786 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, LoReg, 1787 N0, SDValue()).getValue(1); 1788 1789 if (foldedLoad) { 1790 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0), 1791 InFlag }; 1792 SDNode *CNode = 1793 CurDAG->getMachineNode(MOpc, dl, MVT::Other, MVT::Flag, Ops, 1794 array_lengthof(Ops)); 1795 InFlag = SDValue(CNode, 1); 1796 // Update the chain. 1797 ReplaceUses(N1.getValue(1), SDValue(CNode, 0)); 1798 } else { 1799 InFlag = 1800 SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Flag, N1, InFlag), 0); 1801 } 1802 1803 // Copy the low half of the result, if it is needed. 1804 if (!SDValue(Node, 0).use_empty()) { 1805 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, 1806 LoReg, NVT, InFlag); 1807 InFlag = Result.getValue(2); 1808 ReplaceUses(SDValue(Node, 0), Result); 1809#ifndef NDEBUG 1810 DEBUG({ 1811 dbgs() << std::string(Indent-2, ' ') << "=> "; 1812 Result.getNode()->dump(CurDAG); 1813 dbgs() << '\n'; 1814 }); 1815#endif 1816 } 1817 // Copy the high half of the result, if it is needed. 1818 if (!SDValue(Node, 1).use_empty()) { 1819 SDValue Result; 1820 if (HiReg == X86::AH && Subtarget->is64Bit()) { 1821 // Prevent use of AH in a REX instruction by referencing AX instead. 1822 // Shift it down 8 bits. 1823 Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, 1824 X86::AX, MVT::i16, InFlag); 1825 InFlag = Result.getValue(2); 1826 Result = SDValue(CurDAG->getMachineNode(X86::SHR16ri, dl, MVT::i16, 1827 Result, 1828 CurDAG->getTargetConstant(8, MVT::i8)), 0); 1829 // Then truncate it down to i8. 1830 Result = CurDAG->getTargetExtractSubreg(X86::SUBREG_8BIT, dl, 1831 MVT::i8, Result); 1832 } else { 1833 Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, 1834 HiReg, NVT, InFlag); 1835 InFlag = Result.getValue(2); 1836 } 1837 ReplaceUses(SDValue(Node, 1), Result); 1838#ifndef NDEBUG 1839 DEBUG({ 1840 dbgs() << std::string(Indent-2, ' ') << "=> "; 1841 Result.getNode()->dump(CurDAG); 1842 dbgs() << '\n'; 1843 }); 1844#endif 1845 } 1846 1847#ifndef NDEBUG 1848 Indent -= 2; 1849#endif 1850 1851 return NULL; 1852 } 1853 1854 case ISD::SDIVREM: 1855 case ISD::UDIVREM: { 1856 SDValue N0 = Node->getOperand(0); 1857 SDValue N1 = Node->getOperand(1); 1858 1859 bool isSigned = Opcode == ISD::SDIVREM; 1860 if (!isSigned) { 1861 switch (NVT.getSimpleVT().SimpleTy) { 1862 default: llvm_unreachable("Unsupported VT!"); 1863 case MVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break; 1864 case MVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break; 1865 case MVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break; 1866 case MVT::i64: Opc = X86::DIV64r; MOpc = X86::DIV64m; break; 1867 } 1868 } else { 1869 switch (NVT.getSimpleVT().SimpleTy) { 1870 default: llvm_unreachable("Unsupported VT!"); 1871 case MVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break; 1872 case MVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break; 1873 case MVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break; 1874 case MVT::i64: Opc = X86::IDIV64r; MOpc = X86::IDIV64m; break; 1875 } 1876 } 1877 1878 unsigned LoReg, HiReg, ClrReg; 1879 unsigned ClrOpcode, SExtOpcode; 1880 switch (NVT.getSimpleVT().SimpleTy) { 1881 default: llvm_unreachable("Unsupported VT!"); 1882 case MVT::i8: 1883 LoReg = X86::AL; ClrReg = HiReg = X86::AH; 1884 ClrOpcode = 0; 1885 SExtOpcode = X86::CBW; 1886 break; 1887 case MVT::i16: 1888 LoReg = X86::AX; HiReg = X86::DX; 1889 ClrOpcode = X86::MOV16r0; ClrReg = X86::DX; 1890 SExtOpcode = X86::CWD; 1891 break; 1892 case MVT::i32: 1893 LoReg = X86::EAX; ClrReg = HiReg = X86::EDX; 1894 ClrOpcode = X86::MOV32r0; 1895 SExtOpcode = X86::CDQ; 1896 break; 1897 case MVT::i64: 1898 LoReg = X86::RAX; ClrReg = HiReg = X86::RDX; 1899 ClrOpcode = X86::MOV64r0; 1900 SExtOpcode = X86::CQO; 1901 break; 1902 } 1903 1904 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; 1905 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4); 1906 bool signBitIsZero = CurDAG->SignBitIsZero(N0); 1907 1908 SDValue InFlag; 1909 if (NVT == MVT::i8 && (!isSigned || signBitIsZero)) { 1910 // Special case for div8, just use a move with zero extension to AX to 1911 // clear the upper 8 bits (AH). 1912 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Move, Chain; 1913 if (TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) { 1914 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N0.getOperand(0) }; 1915 Move = 1916 SDValue(CurDAG->getMachineNode(X86::MOVZX16rm8, dl, MVT::i16, 1917 MVT::Other, Ops, 1918 array_lengthof(Ops)), 0); 1919 Chain = Move.getValue(1); 1920 ReplaceUses(N0.getValue(1), Chain); 1921 } else { 1922 Move = 1923 SDValue(CurDAG->getMachineNode(X86::MOVZX16rr8, dl, MVT::i16, N0),0); 1924 Chain = CurDAG->getEntryNode(); 1925 } 1926 Chain = CurDAG->getCopyToReg(Chain, dl, X86::AX, Move, SDValue()); 1927 InFlag = Chain.getValue(1); 1928 } else { 1929 InFlag = 1930 CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, 1931 LoReg, N0, SDValue()).getValue(1); 1932 if (isSigned && !signBitIsZero) { 1933 // Sign extend the low part into the high part. 1934 InFlag = 1935 SDValue(CurDAG->getMachineNode(SExtOpcode, dl, MVT::Flag, InFlag),0); 1936 } else { 1937 // Zero out the high part, effectively zero extending the input. 1938 SDValue ClrNode = 1939 SDValue(CurDAG->getMachineNode(ClrOpcode, dl, NVT), 0); 1940 InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, ClrReg, 1941 ClrNode, InFlag).getValue(1); 1942 } 1943 } 1944 1945 if (foldedLoad) { 1946 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0), 1947 InFlag }; 1948 SDNode *CNode = 1949 CurDAG->getMachineNode(MOpc, dl, MVT::Other, MVT::Flag, Ops, 1950 array_lengthof(Ops)); 1951 InFlag = SDValue(CNode, 1); 1952 // Update the chain. 1953 ReplaceUses(N1.getValue(1), SDValue(CNode, 0)); 1954 } else { 1955 InFlag = 1956 SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Flag, N1, InFlag), 0); 1957 } 1958 1959 // Copy the division (low) result, if it is needed. 1960 if (!SDValue(Node, 0).use_empty()) { 1961 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, 1962 LoReg, NVT, InFlag); 1963 InFlag = Result.getValue(2); 1964 ReplaceUses(SDValue(Node, 0), Result); 1965#ifndef NDEBUG 1966 DEBUG({ 1967 dbgs() << std::string(Indent-2, ' ') << "=> "; 1968 Result.getNode()->dump(CurDAG); 1969 dbgs() << '\n'; 1970 }); 1971#endif 1972 } 1973 // Copy the remainder (high) result, if it is needed. 1974 if (!SDValue(Node, 1).use_empty()) { 1975 SDValue Result; 1976 if (HiReg == X86::AH && Subtarget->is64Bit()) { 1977 // Prevent use of AH in a REX instruction by referencing AX instead. 1978 // Shift it down 8 bits. 1979 Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, 1980 X86::AX, MVT::i16, InFlag); 1981 InFlag = Result.getValue(2); 1982 Result = SDValue(CurDAG->getMachineNode(X86::SHR16ri, dl, MVT::i16, 1983 Result, 1984 CurDAG->getTargetConstant(8, MVT::i8)), 1985 0); 1986 // Then truncate it down to i8. 1987 Result = CurDAG->getTargetExtractSubreg(X86::SUBREG_8BIT, dl, 1988 MVT::i8, Result); 1989 } else { 1990 Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, 1991 HiReg, NVT, InFlag); 1992 InFlag = Result.getValue(2); 1993 } 1994 ReplaceUses(SDValue(Node, 1), Result); 1995#ifndef NDEBUG 1996 DEBUG({ 1997 dbgs() << std::string(Indent-2, ' ') << "=> "; 1998 Result.getNode()->dump(CurDAG); 1999 dbgs() << '\n'; 2000 }); 2001#endif 2002 } 2003 2004#ifndef NDEBUG 2005 Indent -= 2; 2006#endif 2007 2008 return NULL; 2009 } 2010 2011 case X86ISD::CMP: { 2012 SDValue N0 = Node->getOperand(0); 2013 SDValue N1 = Node->getOperand(1); 2014 2015 // Look for (X86cmp (and $op, $imm), 0) and see if we can convert it to 2016 // use a smaller encoding. 2017 if (N0.getNode()->getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 2018 N0.getValueType() != MVT::i8 && 2019 X86::isZeroNode(N1)) { 2020 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getNode()->getOperand(1)); 2021 if (!C) break; 2022 2023 // For example, convert "testl %eax, $8" to "testb %al, $8" 2024 if ((C->getZExtValue() & ~UINT64_C(0xff)) == 0 && 2025 (!(C->getZExtValue() & 0x80) || 2026 HasNoSignedComparisonUses(Node))) { 2027 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i8); 2028 SDValue Reg = N0.getNode()->getOperand(0); 2029 2030 // On x86-32, only the ABCD registers have 8-bit subregisters. 2031 if (!Subtarget->is64Bit()) { 2032 TargetRegisterClass *TRC = 0; 2033 switch (N0.getValueType().getSimpleVT().SimpleTy) { 2034 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break; 2035 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break; 2036 default: llvm_unreachable("Unsupported TEST operand type!"); 2037 } 2038 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32); 2039 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl, 2040 Reg.getValueType(), Reg, RC), 0); 2041 } 2042 2043 // Extract the l-register. 2044 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::SUBREG_8BIT, dl, 2045 MVT::i8, Reg); 2046 2047 // Emit a testb. 2048 return CurDAG->getMachineNode(X86::TEST8ri, dl, MVT::i32, Subreg, Imm); 2049 } 2050 2051 // For example, "testl %eax, $2048" to "testb %ah, $8". 2052 if ((C->getZExtValue() & ~UINT64_C(0xff00)) == 0 && 2053 (!(C->getZExtValue() & 0x8000) || 2054 HasNoSignedComparisonUses(Node))) { 2055 // Shift the immediate right by 8 bits. 2056 SDValue ShiftedImm = CurDAG->getTargetConstant(C->getZExtValue() >> 8, 2057 MVT::i8); 2058 SDValue Reg = N0.getNode()->getOperand(0); 2059 2060 // Put the value in an ABCD register. 2061 TargetRegisterClass *TRC = 0; 2062 switch (N0.getValueType().getSimpleVT().SimpleTy) { 2063 case MVT::i64: TRC = &X86::GR64_ABCDRegClass; break; 2064 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break; 2065 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break; 2066 default: llvm_unreachable("Unsupported TEST operand type!"); 2067 } 2068 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32); 2069 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl, 2070 Reg.getValueType(), Reg, RC), 0); 2071 2072 // Extract the h-register. 2073 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::SUBREG_8BIT_HI, dl, 2074 MVT::i8, Reg); 2075 2076 // Emit a testb. No special NOREX tricks are needed since there's 2077 // only one GPR operand! 2078 return CurDAG->getMachineNode(X86::TEST8ri, dl, MVT::i32, 2079 Subreg, ShiftedImm); 2080 } 2081 2082 // For example, "testl %eax, $32776" to "testw %ax, $32776". 2083 if ((C->getZExtValue() & ~UINT64_C(0xffff)) == 0 && 2084 N0.getValueType() != MVT::i16 && 2085 (!(C->getZExtValue() & 0x8000) || 2086 HasNoSignedComparisonUses(Node))) { 2087 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i16); 2088 SDValue Reg = N0.getNode()->getOperand(0); 2089 2090 // Extract the 16-bit subregister. 2091 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::SUBREG_16BIT, dl, 2092 MVT::i16, Reg); 2093 2094 // Emit a testw. 2095 return CurDAG->getMachineNode(X86::TEST16ri, dl, MVT::i32, Subreg, Imm); 2096 } 2097 2098 // For example, "testq %rax, $268468232" to "testl %eax, $268468232". 2099 if ((C->getZExtValue() & ~UINT64_C(0xffffffff)) == 0 && 2100 N0.getValueType() == MVT::i64 && 2101 (!(C->getZExtValue() & 0x80000000) || 2102 HasNoSignedComparisonUses(Node))) { 2103 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32); 2104 SDValue Reg = N0.getNode()->getOperand(0); 2105 2106 // Extract the 32-bit subregister. 2107 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::SUBREG_32BIT, dl, 2108 MVT::i32, Reg); 2109 2110 // Emit a testl. 2111 return CurDAG->getMachineNode(X86::TEST32ri, dl, MVT::i32, Subreg, Imm); 2112 } 2113 } 2114 break; 2115 } 2116 } 2117 2118 SDNode *ResNode = SelectCode(Node); 2119 2120#ifndef NDEBUG 2121 DEBUG({ 2122 dbgs() << std::string(Indent-2, ' ') << "=> "; 2123 if (ResNode == NULL || ResNode == Node) 2124 Node->dump(CurDAG); 2125 else 2126 ResNode->dump(CurDAG); 2127 dbgs() << '\n'; 2128 }); 2129 Indent -= 2; 2130#endif 2131 2132 return ResNode; 2133} 2134 2135bool X86DAGToDAGISel:: 2136SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode, 2137 std::vector<SDValue> &OutOps) { 2138 SDValue Op0, Op1, Op2, Op3, Op4; 2139 switch (ConstraintCode) { 2140 case 'o': // offsetable ?? 2141 case 'v': // not offsetable ?? 2142 default: return true; 2143 case 'm': // memory 2144 if (!SelectAddr(Op.getNode(), Op, Op0, Op1, Op2, Op3, Op4)) 2145 return true; 2146 break; 2147 } 2148 2149 OutOps.push_back(Op0); 2150 OutOps.push_back(Op1); 2151 OutOps.push_back(Op2); 2152 OutOps.push_back(Op3); 2153 OutOps.push_back(Op4); 2154 return false; 2155} 2156 2157/// createX86ISelDag - This pass converts a legalized DAG into a 2158/// X86-specific DAG, ready for instruction scheduling. 2159/// 2160FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM, 2161 llvm::CodeGenOpt::Level OptLevel) { 2162 return new X86DAGToDAGISel(TM, OptLevel); 2163} 2164