X86ISelDAGToDAG.cpp revision f103b3d1b99db0ae314c36d8b4ae71427816379e
1//===- X86ISelDAGToDAG.cpp - A DAG pattern matching inst selector for X86 -===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines a DAG pattern matching instruction selector for X86, 11// converting from a legalized dag to a X86 dag. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "x86-isel" 16#include "X86.h" 17#include "X86InstrBuilder.h" 18#include "X86MachineFunctionInfo.h" 19#include "X86RegisterInfo.h" 20#include "X86Subtarget.h" 21#include "X86TargetMachine.h" 22#include "llvm/Instructions.h" 23#include "llvm/Intrinsics.h" 24#include "llvm/Support/CFG.h" 25#include "llvm/Type.h" 26#include "llvm/CodeGen/FunctionLoweringInfo.h" 27#include "llvm/CodeGen/MachineConstantPool.h" 28#include "llvm/CodeGen/MachineFunction.h" 29#include "llvm/CodeGen/MachineFrameInfo.h" 30#include "llvm/CodeGen/MachineInstrBuilder.h" 31#include "llvm/CodeGen/MachineRegisterInfo.h" 32#include "llvm/CodeGen/SelectionDAGISel.h" 33#include "llvm/Target/TargetMachine.h" 34#include "llvm/Target/TargetOptions.h" 35#include "llvm/Support/Debug.h" 36#include "llvm/Support/ErrorHandling.h" 37#include "llvm/Support/MathExtras.h" 38#include "llvm/Support/raw_ostream.h" 39#include "llvm/ADT/SmallPtrSet.h" 40#include "llvm/ADT/Statistic.h" 41using namespace llvm; 42 43STATISTIC(NumLoadMoved, "Number of loads moved below TokenFactor"); 44 45//===----------------------------------------------------------------------===// 46// Pattern Matcher Implementation 47//===----------------------------------------------------------------------===// 48 49namespace { 50 /// X86ISelAddressMode - This corresponds to X86AddressMode, but uses 51 /// SDValue's instead of register numbers for the leaves of the matched 52 /// tree. 53 struct X86ISelAddressMode { 54 enum { 55 RegBase, 56 FrameIndexBase 57 } BaseType; 58 59 // This is really a union, discriminated by BaseType! 60 SDValue Base_Reg; 61 int Base_FrameIndex; 62 63 unsigned Scale; 64 SDValue IndexReg; 65 int32_t Disp; 66 SDValue Segment; 67 const GlobalValue *GV; 68 const Constant *CP; 69 const BlockAddress *BlockAddr; 70 const char *ES; 71 int JT; 72 unsigned Align; // CP alignment. 73 unsigned char SymbolFlags; // X86II::MO_* 74 75 X86ISelAddressMode() 76 : BaseType(RegBase), Base_FrameIndex(0), Scale(1), IndexReg(), Disp(0), 77 Segment(), GV(0), CP(0), BlockAddr(0), ES(0), JT(-1), Align(0), 78 SymbolFlags(X86II::MO_NO_FLAG) { 79 } 80 81 bool hasSymbolicDisplacement() const { 82 return GV != 0 || CP != 0 || ES != 0 || JT != -1 || BlockAddr != 0; 83 } 84 85 bool hasBaseOrIndexReg() const { 86 return IndexReg.getNode() != 0 || Base_Reg.getNode() != 0; 87 } 88 89 /// isRIPRelative - Return true if this addressing mode is already RIP 90 /// relative. 91 bool isRIPRelative() const { 92 if (BaseType != RegBase) return false; 93 if (RegisterSDNode *RegNode = 94 dyn_cast_or_null<RegisterSDNode>(Base_Reg.getNode())) 95 return RegNode->getReg() == X86::RIP; 96 return false; 97 } 98 99 void setBaseReg(SDValue Reg) { 100 BaseType = RegBase; 101 Base_Reg = Reg; 102 } 103 104 void dump() { 105 dbgs() << "X86ISelAddressMode " << this << '\n'; 106 dbgs() << "Base_Reg "; 107 if (Base_Reg.getNode() != 0) 108 Base_Reg.getNode()->dump(); 109 else 110 dbgs() << "nul"; 111 dbgs() << " Base.FrameIndex " << Base_FrameIndex << '\n' 112 << " Scale" << Scale << '\n' 113 << "IndexReg "; 114 if (IndexReg.getNode() != 0) 115 IndexReg.getNode()->dump(); 116 else 117 dbgs() << "nul"; 118 dbgs() << " Disp " << Disp << '\n' 119 << "GV "; 120 if (GV) 121 GV->dump(); 122 else 123 dbgs() << "nul"; 124 dbgs() << " CP "; 125 if (CP) 126 CP->dump(); 127 else 128 dbgs() << "nul"; 129 dbgs() << '\n' 130 << "ES "; 131 if (ES) 132 dbgs() << ES; 133 else 134 dbgs() << "nul"; 135 dbgs() << " JT" << JT << " Align" << Align << '\n'; 136 } 137 }; 138} 139 140namespace { 141 //===--------------------------------------------------------------------===// 142 /// ISel - X86 specific code to select X86 machine instructions for 143 /// SelectionDAG operations. 144 /// 145 class X86DAGToDAGISel : public SelectionDAGISel { 146 /// X86Lowering - This object fully describes how to lower LLVM code to an 147 /// X86-specific SelectionDAG. 148 const X86TargetLowering &X86Lowering; 149 150 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can 151 /// make the right decision when generating code for different targets. 152 const X86Subtarget *Subtarget; 153 154 /// OptForSize - If true, selector should try to optimize for code size 155 /// instead of performance. 156 bool OptForSize; 157 158 public: 159 explicit X86DAGToDAGISel(X86TargetMachine &tm, CodeGenOpt::Level OptLevel) 160 : SelectionDAGISel(tm, OptLevel), 161 X86Lowering(*tm.getTargetLowering()), 162 Subtarget(&tm.getSubtarget<X86Subtarget>()), 163 OptForSize(false) {} 164 165 virtual const char *getPassName() const { 166 return "X86 DAG->DAG Instruction Selection"; 167 } 168 169 virtual void EmitFunctionEntryCode(); 170 171 virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const; 172 173 virtual void PreprocessISelDAG(); 174 175 inline bool immSext8(SDNode *N) const { 176 return isInt<8>(cast<ConstantSDNode>(N)->getSExtValue()); 177 } 178 179 // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit 180 // sign extended field. 181 inline bool i64immSExt32(SDNode *N) const { 182 uint64_t v = cast<ConstantSDNode>(N)->getZExtValue(); 183 return (int64_t)v == (int32_t)v; 184 } 185 186// Include the pieces autogenerated from the target description. 187#include "X86GenDAGISel.inc" 188 189 private: 190 SDNode *Select(SDNode *N); 191 SDNode *SelectAtomic64(SDNode *Node, unsigned Opc); 192 SDNode *SelectAtomicLoadAdd(SDNode *Node, EVT NVT); 193 SDNode *SelectAtomicLoadArith(SDNode *Node, EVT NVT); 194 195 bool FoldOffsetIntoAddress(uint64_t Offset, X86ISelAddressMode &AM); 196 bool MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM); 197 bool MatchWrapper(SDValue N, X86ISelAddressMode &AM); 198 bool MatchAddress(SDValue N, X86ISelAddressMode &AM); 199 bool MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM, 200 unsigned Depth); 201 bool MatchAddressBase(SDValue N, X86ISelAddressMode &AM); 202 bool SelectAddr(SDNode *Parent, SDValue N, SDValue &Base, 203 SDValue &Scale, SDValue &Index, SDValue &Disp, 204 SDValue &Segment); 205 bool SelectLEAAddr(SDValue N, SDValue &Base, 206 SDValue &Scale, SDValue &Index, SDValue &Disp, 207 SDValue &Segment); 208 bool SelectTLSADDRAddr(SDValue N, SDValue &Base, 209 SDValue &Scale, SDValue &Index, SDValue &Disp, 210 SDValue &Segment); 211 bool SelectScalarSSELoad(SDNode *Root, SDValue N, 212 SDValue &Base, SDValue &Scale, 213 SDValue &Index, SDValue &Disp, 214 SDValue &Segment, 215 SDValue &NodeWithChain); 216 217 bool TryFoldLoad(SDNode *P, SDValue N, 218 SDValue &Base, SDValue &Scale, 219 SDValue &Index, SDValue &Disp, 220 SDValue &Segment); 221 222 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for 223 /// inline asm expressions. 224 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, 225 char ConstraintCode, 226 std::vector<SDValue> &OutOps); 227 228 void EmitSpecialCodeForMain(MachineBasicBlock *BB, MachineFrameInfo *MFI); 229 230 inline void getAddressOperands(X86ISelAddressMode &AM, SDValue &Base, 231 SDValue &Scale, SDValue &Index, 232 SDValue &Disp, SDValue &Segment) { 233 Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase) ? 234 CurDAG->getTargetFrameIndex(AM.Base_FrameIndex, TLI.getPointerTy()) : 235 AM.Base_Reg; 236 Scale = getI8Imm(AM.Scale); 237 Index = AM.IndexReg; 238 // These are 32-bit even in 64-bit mode since RIP relative offset 239 // is 32-bit. 240 if (AM.GV) 241 Disp = CurDAG->getTargetGlobalAddress(AM.GV, DebugLoc(), 242 MVT::i32, AM.Disp, 243 AM.SymbolFlags); 244 else if (AM.CP) 245 Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i32, 246 AM.Align, AM.Disp, AM.SymbolFlags); 247 else if (AM.ES) 248 Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i32, AM.SymbolFlags); 249 else if (AM.JT != -1) 250 Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i32, AM.SymbolFlags); 251 else if (AM.BlockAddr) 252 Disp = CurDAG->getBlockAddress(AM.BlockAddr, MVT::i32, 253 true, AM.SymbolFlags); 254 else 255 Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i32); 256 257 if (AM.Segment.getNode()) 258 Segment = AM.Segment; 259 else 260 Segment = CurDAG->getRegister(0, MVT::i32); 261 } 262 263 /// getI8Imm - Return a target constant with the specified value, of type 264 /// i8. 265 inline SDValue getI8Imm(unsigned Imm) { 266 return CurDAG->getTargetConstant(Imm, MVT::i8); 267 } 268 269 /// getI32Imm - Return a target constant with the specified value, of type 270 /// i32. 271 inline SDValue getI32Imm(unsigned Imm) { 272 return CurDAG->getTargetConstant(Imm, MVT::i32); 273 } 274 275 /// getGlobalBaseReg - Return an SDNode that returns the value of 276 /// the global base register. Output instructions required to 277 /// initialize the global base register, if necessary. 278 /// 279 SDNode *getGlobalBaseReg(); 280 281 /// getTargetMachine - Return a reference to the TargetMachine, casted 282 /// to the target-specific type. 283 const X86TargetMachine &getTargetMachine() { 284 return static_cast<const X86TargetMachine &>(TM); 285 } 286 287 /// getInstrInfo - Return a reference to the TargetInstrInfo, casted 288 /// to the target-specific type. 289 const X86InstrInfo *getInstrInfo() { 290 return getTargetMachine().getInstrInfo(); 291 } 292 }; 293} 294 295 296bool 297X86DAGToDAGISel::IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const { 298 if (OptLevel == CodeGenOpt::None) return false; 299 300 if (!N.hasOneUse()) 301 return false; 302 303 if (N.getOpcode() != ISD::LOAD) 304 return true; 305 306 // If N is a load, do additional profitability checks. 307 if (U == Root) { 308 switch (U->getOpcode()) { 309 default: break; 310 case X86ISD::ADD: 311 case X86ISD::SUB: 312 case X86ISD::AND: 313 case X86ISD::XOR: 314 case X86ISD::OR: 315 case ISD::ADD: 316 case ISD::ADDC: 317 case ISD::ADDE: 318 case ISD::AND: 319 case ISD::OR: 320 case ISD::XOR: { 321 SDValue Op1 = U->getOperand(1); 322 323 // If the other operand is a 8-bit immediate we should fold the immediate 324 // instead. This reduces code size. 325 // e.g. 326 // movl 4(%esp), %eax 327 // addl $4, %eax 328 // vs. 329 // movl $4, %eax 330 // addl 4(%esp), %eax 331 // The former is 2 bytes shorter. In case where the increment is 1, then 332 // the saving can be 4 bytes (by using incl %eax). 333 if (ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(Op1)) 334 if (Imm->getAPIntValue().isSignedIntN(8)) 335 return false; 336 337 // If the other operand is a TLS address, we should fold it instead. 338 // This produces 339 // movl %gs:0, %eax 340 // leal i@NTPOFF(%eax), %eax 341 // instead of 342 // movl $i@NTPOFF, %eax 343 // addl %gs:0, %eax 344 // if the block also has an access to a second TLS address this will save 345 // a load. 346 // FIXME: This is probably also true for non TLS addresses. 347 if (Op1.getOpcode() == X86ISD::Wrapper) { 348 SDValue Val = Op1.getOperand(0); 349 if (Val.getOpcode() == ISD::TargetGlobalTLSAddress) 350 return false; 351 } 352 } 353 } 354 } 355 356 return true; 357} 358 359/// MoveBelowCallOrigChain - Replace the original chain operand of the call with 360/// load's chain operand and move load below the call's chain operand. 361static void MoveBelowOrigChain(SelectionDAG *CurDAG, SDValue Load, 362 SDValue Call, SDValue OrigChain) { 363 SmallVector<SDValue, 8> Ops; 364 SDValue Chain = OrigChain.getOperand(0); 365 if (Chain.getNode() == Load.getNode()) 366 Ops.push_back(Load.getOperand(0)); 367 else { 368 assert(Chain.getOpcode() == ISD::TokenFactor && 369 "Unexpected chain operand"); 370 for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i) 371 if (Chain.getOperand(i).getNode() == Load.getNode()) 372 Ops.push_back(Load.getOperand(0)); 373 else 374 Ops.push_back(Chain.getOperand(i)); 375 SDValue NewChain = 376 CurDAG->getNode(ISD::TokenFactor, Load.getDebugLoc(), 377 MVT::Other, &Ops[0], Ops.size()); 378 Ops.clear(); 379 Ops.push_back(NewChain); 380 } 381 for (unsigned i = 1, e = OrigChain.getNumOperands(); i != e; ++i) 382 Ops.push_back(OrigChain.getOperand(i)); 383 CurDAG->UpdateNodeOperands(OrigChain.getNode(), &Ops[0], Ops.size()); 384 CurDAG->UpdateNodeOperands(Load.getNode(), Call.getOperand(0), 385 Load.getOperand(1), Load.getOperand(2)); 386 Ops.clear(); 387 Ops.push_back(SDValue(Load.getNode(), 1)); 388 for (unsigned i = 1, e = Call.getNode()->getNumOperands(); i != e; ++i) 389 Ops.push_back(Call.getOperand(i)); 390 CurDAG->UpdateNodeOperands(Call.getNode(), &Ops[0], Ops.size()); 391} 392 393/// isCalleeLoad - Return true if call address is a load and it can be 394/// moved below CALLSEQ_START and the chains leading up to the call. 395/// Return the CALLSEQ_START by reference as a second output. 396/// In the case of a tail call, there isn't a callseq node between the call 397/// chain and the load. 398static bool isCalleeLoad(SDValue Callee, SDValue &Chain, bool HasCallSeq) { 399 if (Callee.getNode() == Chain.getNode() || !Callee.hasOneUse()) 400 return false; 401 LoadSDNode *LD = dyn_cast<LoadSDNode>(Callee.getNode()); 402 if (!LD || 403 LD->isVolatile() || 404 LD->getAddressingMode() != ISD::UNINDEXED || 405 LD->getExtensionType() != ISD::NON_EXTLOAD) 406 return false; 407 408 // Now let's find the callseq_start. 409 while (HasCallSeq && Chain.getOpcode() != ISD::CALLSEQ_START) { 410 if (!Chain.hasOneUse()) 411 return false; 412 Chain = Chain.getOperand(0); 413 } 414 415 if (!Chain.getNumOperands()) 416 return false; 417 if (Chain.getOperand(0).getNode() == Callee.getNode()) 418 return true; 419 if (Chain.getOperand(0).getOpcode() == ISD::TokenFactor && 420 Callee.getValue(1).isOperandOf(Chain.getOperand(0).getNode()) && 421 Callee.getValue(1).hasOneUse()) 422 return true; 423 return false; 424} 425 426void X86DAGToDAGISel::PreprocessISelDAG() { 427 // OptForSize is used in pattern predicates that isel is matching. 428 OptForSize = MF->getFunction()->hasFnAttr(Attribute::OptimizeForSize); 429 430 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(), 431 E = CurDAG->allnodes_end(); I != E; ) { 432 SDNode *N = I++; // Preincrement iterator to avoid invalidation issues. 433 434 if (OptLevel != CodeGenOpt::None && 435 (N->getOpcode() == X86ISD::CALL || 436 N->getOpcode() == X86ISD::TC_RETURN)) { 437 /// Also try moving call address load from outside callseq_start to just 438 /// before the call to allow it to be folded. 439 /// 440 /// [Load chain] 441 /// ^ 442 /// | 443 /// [Load] 444 /// ^ ^ 445 /// | | 446 /// / \-- 447 /// / | 448 ///[CALLSEQ_START] | 449 /// ^ | 450 /// | | 451 /// [LOAD/C2Reg] | 452 /// | | 453 /// \ / 454 /// \ / 455 /// [CALL] 456 bool HasCallSeq = N->getOpcode() == X86ISD::CALL; 457 SDValue Chain = N->getOperand(0); 458 SDValue Load = N->getOperand(1); 459 if (!isCalleeLoad(Load, Chain, HasCallSeq)) 460 continue; 461 MoveBelowOrigChain(CurDAG, Load, SDValue(N, 0), Chain); 462 ++NumLoadMoved; 463 continue; 464 } 465 466 // Lower fpround and fpextend nodes that target the FP stack to be store and 467 // load to the stack. This is a gross hack. We would like to simply mark 468 // these as being illegal, but when we do that, legalize produces these when 469 // it expands calls, then expands these in the same legalize pass. We would 470 // like dag combine to be able to hack on these between the call expansion 471 // and the node legalization. As such this pass basically does "really 472 // late" legalization of these inline with the X86 isel pass. 473 // FIXME: This should only happen when not compiled with -O0. 474 if (N->getOpcode() != ISD::FP_ROUND && N->getOpcode() != ISD::FP_EXTEND) 475 continue; 476 477 EVT SrcVT = N->getOperand(0).getValueType(); 478 EVT DstVT = N->getValueType(0); 479 480 // If any of the sources are vectors, no fp stack involved. 481 if (SrcVT.isVector() || DstVT.isVector()) 482 continue; 483 484 // If the source and destination are SSE registers, then this is a legal 485 // conversion that should not be lowered. 486 bool SrcIsSSE = X86Lowering.isScalarFPTypeInSSEReg(SrcVT); 487 bool DstIsSSE = X86Lowering.isScalarFPTypeInSSEReg(DstVT); 488 if (SrcIsSSE && DstIsSSE) 489 continue; 490 491 if (!SrcIsSSE && !DstIsSSE) { 492 // If this is an FPStack extension, it is a noop. 493 if (N->getOpcode() == ISD::FP_EXTEND) 494 continue; 495 // If this is a value-preserving FPStack truncation, it is a noop. 496 if (N->getConstantOperandVal(1)) 497 continue; 498 } 499 500 // Here we could have an FP stack truncation or an FPStack <-> SSE convert. 501 // FPStack has extload and truncstore. SSE can fold direct loads into other 502 // operations. Based on this, decide what we want to do. 503 EVT MemVT; 504 if (N->getOpcode() == ISD::FP_ROUND) 505 MemVT = DstVT; // FP_ROUND must use DstVT, we can't do a 'trunc load'. 506 else 507 MemVT = SrcIsSSE ? SrcVT : DstVT; 508 509 SDValue MemTmp = CurDAG->CreateStackTemporary(MemVT); 510 DebugLoc dl = N->getDebugLoc(); 511 512 // FIXME: optimize the case where the src/dest is a load or store? 513 SDValue Store = CurDAG->getTruncStore(CurDAG->getEntryNode(), dl, 514 N->getOperand(0), 515 MemTmp, MachinePointerInfo(), MemVT, 516 false, false, 0); 517 SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, dl, DstVT, Store, MemTmp, 518 MachinePointerInfo(), 519 MemVT, false, false, 0); 520 521 // We're about to replace all uses of the FP_ROUND/FP_EXTEND with the 522 // extload we created. This will cause general havok on the dag because 523 // anything below the conversion could be folded into other existing nodes. 524 // To avoid invalidating 'I', back it up to the convert node. 525 --I; 526 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), Result); 527 528 // Now that we did that, the node is dead. Increment the iterator to the 529 // next node to process, then delete N. 530 ++I; 531 CurDAG->DeleteNode(N); 532 } 533} 534 535 536/// EmitSpecialCodeForMain - Emit any code that needs to be executed only in 537/// the main function. 538void X86DAGToDAGISel::EmitSpecialCodeForMain(MachineBasicBlock *BB, 539 MachineFrameInfo *MFI) { 540 const TargetInstrInfo *TII = TM.getInstrInfo(); 541 if (Subtarget->isTargetCygMing()) { 542 unsigned CallOp = 543 Subtarget->is64Bit() ? X86::WINCALL64pcrel32 : X86::CALLpcrel32; 544 BuildMI(BB, DebugLoc(), 545 TII->get(CallOp)).addExternalSymbol("__main"); 546 } 547} 548 549void X86DAGToDAGISel::EmitFunctionEntryCode() { 550 // If this is main, emit special code for main. 551 if (const Function *Fn = MF->getFunction()) 552 if (Fn->hasExternalLinkage() && Fn->getName() == "main") 553 EmitSpecialCodeForMain(MF->begin(), MF->getFrameInfo()); 554} 555 556static bool isDispSafeForFrameIndex(int64_t Val) { 557 // On 64-bit platforms, we can run into an issue where a frame index 558 // includes a displacement that, when added to the explicit displacement, 559 // will overflow the displacement field. Assuming that the frame index 560 // displacement fits into a 31-bit integer (which is only slightly more 561 // aggressive than the current fundamental assumption that it fits into 562 // a 32-bit integer), a 31-bit disp should always be safe. 563 return isInt<31>(Val); 564} 565 566bool X86DAGToDAGISel::FoldOffsetIntoAddress(uint64_t Offset, 567 X86ISelAddressMode &AM) { 568 int64_t Val = AM.Disp + Offset; 569 CodeModel::Model M = TM.getCodeModel(); 570 if (Subtarget->is64Bit()) { 571 if (!X86::isOffsetSuitableForCodeModel(Val, M, 572 AM.hasSymbolicDisplacement())) 573 return true; 574 // In addition to the checks required for a register base, check that 575 // we do not try to use an unsafe Disp with a frame index. 576 if (AM.BaseType == X86ISelAddressMode::FrameIndexBase && 577 !isDispSafeForFrameIndex(Val)) 578 return true; 579 } 580 AM.Disp = Val; 581 return false; 582 583} 584 585bool X86DAGToDAGISel::MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM){ 586 SDValue Address = N->getOperand(1); 587 588 // load gs:0 -> GS segment register. 589 // load fs:0 -> FS segment register. 590 // 591 // This optimization is valid because the GNU TLS model defines that 592 // gs:0 (or fs:0 on X86-64) contains its own address. 593 // For more information see http://people.redhat.com/drepper/tls.pdf 594 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Address)) 595 if (C->getSExtValue() == 0 && AM.Segment.getNode() == 0 && 596 Subtarget->isTargetELF()) 597 switch (N->getPointerInfo().getAddrSpace()) { 598 case 256: 599 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16); 600 return false; 601 case 257: 602 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16); 603 return false; 604 } 605 606 return true; 607} 608 609/// MatchWrapper - Try to match X86ISD::Wrapper and X86ISD::WrapperRIP nodes 610/// into an addressing mode. These wrap things that will resolve down into a 611/// symbol reference. If no match is possible, this returns true, otherwise it 612/// returns false. 613bool X86DAGToDAGISel::MatchWrapper(SDValue N, X86ISelAddressMode &AM) { 614 // If the addressing mode already has a symbol as the displacement, we can 615 // never match another symbol. 616 if (AM.hasSymbolicDisplacement()) 617 return true; 618 619 SDValue N0 = N.getOperand(0); 620 CodeModel::Model M = TM.getCodeModel(); 621 622 // Handle X86-64 rip-relative addresses. We check this before checking direct 623 // folding because RIP is preferable to non-RIP accesses. 624 if (Subtarget->is64Bit() && 625 // Under X86-64 non-small code model, GV (and friends) are 64-bits, so 626 // they cannot be folded into immediate fields. 627 // FIXME: This can be improved for kernel and other models? 628 (M == CodeModel::Small || M == CodeModel::Kernel) && 629 // Base and index reg must be 0 in order to use %rip as base and lowering 630 // must allow RIP. 631 !AM.hasBaseOrIndexReg() && N.getOpcode() == X86ISD::WrapperRIP) { 632 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) { 633 X86ISelAddressMode Backup = AM; 634 AM.GV = G->getGlobal(); 635 AM.SymbolFlags = G->getTargetFlags(); 636 if (FoldOffsetIntoAddress(G->getOffset(), AM)) { 637 AM = Backup; 638 return true; 639 } 640 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) { 641 X86ISelAddressMode Backup = AM; 642 AM.CP = CP->getConstVal(); 643 AM.Align = CP->getAlignment(); 644 AM.SymbolFlags = CP->getTargetFlags(); 645 if (FoldOffsetIntoAddress(CP->getOffset(), AM)) { 646 AM = Backup; 647 return true; 648 } 649 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) { 650 AM.ES = S->getSymbol(); 651 AM.SymbolFlags = S->getTargetFlags(); 652 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) { 653 AM.JT = J->getIndex(); 654 AM.SymbolFlags = J->getTargetFlags(); 655 } else { 656 AM.BlockAddr = cast<BlockAddressSDNode>(N0)->getBlockAddress(); 657 AM.SymbolFlags = cast<BlockAddressSDNode>(N0)->getTargetFlags(); 658 } 659 660 if (N.getOpcode() == X86ISD::WrapperRIP) 661 AM.setBaseReg(CurDAG->getRegister(X86::RIP, MVT::i64)); 662 return false; 663 } 664 665 // Handle the case when globals fit in our immediate field: This is true for 666 // X86-32 always and X86-64 when in -static -mcmodel=small mode. In 64-bit 667 // mode, this results in a non-RIP-relative computation. 668 if (!Subtarget->is64Bit() || 669 ((M == CodeModel::Small || M == CodeModel::Kernel) && 670 TM.getRelocationModel() == Reloc::Static)) { 671 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) { 672 AM.GV = G->getGlobal(); 673 AM.Disp += G->getOffset(); 674 AM.SymbolFlags = G->getTargetFlags(); 675 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) { 676 AM.CP = CP->getConstVal(); 677 AM.Align = CP->getAlignment(); 678 AM.Disp += CP->getOffset(); 679 AM.SymbolFlags = CP->getTargetFlags(); 680 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) { 681 AM.ES = S->getSymbol(); 682 AM.SymbolFlags = S->getTargetFlags(); 683 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) { 684 AM.JT = J->getIndex(); 685 AM.SymbolFlags = J->getTargetFlags(); 686 } else { 687 AM.BlockAddr = cast<BlockAddressSDNode>(N0)->getBlockAddress(); 688 AM.SymbolFlags = cast<BlockAddressSDNode>(N0)->getTargetFlags(); 689 } 690 return false; 691 } 692 693 return true; 694} 695 696/// MatchAddress - Add the specified node to the specified addressing mode, 697/// returning true if it cannot be done. This just pattern matches for the 698/// addressing mode. 699bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM) { 700 if (MatchAddressRecursively(N, AM, 0)) 701 return true; 702 703 // Post-processing: Convert lea(,%reg,2) to lea(%reg,%reg), which has 704 // a smaller encoding and avoids a scaled-index. 705 if (AM.Scale == 2 && 706 AM.BaseType == X86ISelAddressMode::RegBase && 707 AM.Base_Reg.getNode() == 0) { 708 AM.Base_Reg = AM.IndexReg; 709 AM.Scale = 1; 710 } 711 712 // Post-processing: Convert foo to foo(%rip), even in non-PIC mode, 713 // because it has a smaller encoding. 714 // TODO: Which other code models can use this? 715 if (TM.getCodeModel() == CodeModel::Small && 716 Subtarget->is64Bit() && 717 AM.Scale == 1 && 718 AM.BaseType == X86ISelAddressMode::RegBase && 719 AM.Base_Reg.getNode() == 0 && 720 AM.IndexReg.getNode() == 0 && 721 AM.SymbolFlags == X86II::MO_NO_FLAG && 722 AM.hasSymbolicDisplacement()) 723 AM.Base_Reg = CurDAG->getRegister(X86::RIP, MVT::i64); 724 725 return false; 726} 727 728// Implement some heroics to detect shifts of masked values where the mask can 729// be replaced by extending the shift and undoing that in the addressing mode 730// scale. Patterns such as (shl (srl x, c1), c2) are canonicalized into (and 731// (srl x, SHIFT), MASK) by DAGCombines that don't know the shl can be done in 732// the addressing mode. This results in code such as: 733// 734// int f(short *y, int *lookup_table) { 735// ... 736// return *y + lookup_table[*y >> 11]; 737// } 738// 739// Turning into: 740// movzwl (%rdi), %eax 741// movl %eax, %ecx 742// shrl $11, %ecx 743// addl (%rsi,%rcx,4), %eax 744// 745// Instead of: 746// movzwl (%rdi), %eax 747// movl %eax, %ecx 748// shrl $9, %ecx 749// andl $124, %rcx 750// addl (%rsi,%rcx), %eax 751// 752static bool FoldMaskAndShiftToScale(SelectionDAG &DAG, SDValue N, 753 X86ISelAddressMode &AM) { 754 // Scale must not be used already. 755 if (AM.IndexReg.getNode() != 0 || AM.Scale != 1) return true; 756 757 SDValue Shift = N; 758 SDValue And = N.getOperand(0); 759 if (N.getOpcode() != ISD::SRL) 760 std::swap(Shift, And); 761 if (Shift.getOpcode() != ISD::SRL || And.getOpcode() != ISD::AND || 762 !Shift.hasOneUse() || 763 !isa<ConstantSDNode>(Shift.getOperand(1)) || 764 !isa<ConstantSDNode>(And.getOperand(1))) 765 return true; 766 SDValue X = (N == Shift ? And.getOperand(0) : Shift.getOperand(0)); 767 768 // We only handle up to 64-bit values here as those are what matter for 769 // addressing mode optimizations. 770 if (X.getValueSizeInBits() > 64) return true; 771 772 uint64_t Mask = And.getConstantOperandVal(1); 773 unsigned ShiftAmt = Shift.getConstantOperandVal(1); 774 unsigned MaskLZ = CountLeadingZeros_64(Mask); 775 unsigned MaskTZ = CountTrailingZeros_64(Mask); 776 777 // The amount of shift we're trying to fit into the addressing mode is taken 778 // from the trailing zeros of the mask. If the mask is pre-shift, we subtract 779 // the shift amount. 780 int AMShiftAmt = MaskTZ - (N == Shift ? ShiftAmt : 0); 781 782 // There is nothing we can do here unless the mask is removing some bits. 783 // Also, the addressing mode can only represent shifts of 1, 2, or 3 bits. 784 if (AMShiftAmt <= 0 || AMShiftAmt > 3) return true; 785 786 // We also need to ensure that mask is a continuous run of bits. 787 if (CountTrailingOnes_64(Mask >> MaskTZ) + MaskTZ + MaskLZ != 64) return true; 788 789 // Scale the leading zero count down based on the actual size of the value. 790 // Also scale it down based on the size of the shift if it was applied 791 // before the mask. 792 MaskLZ -= (64 - X.getValueSizeInBits()) + (N == Shift ? 0 : ShiftAmt); 793 794 // The final check is to ensure that any masked out high bits of X are 795 // already known to be zero. Otherwise, the mask has a semantic impact 796 // other than masking out a couple of low bits. Unfortunately, because of 797 // the mask, zero extensions will be removed from operands in some cases. 798 // This code works extra hard to look through extensions because we can 799 // replace them with zero extensions cheaply if necessary. 800 bool ReplacingAnyExtend = false; 801 if (X.getOpcode() == ISD::ANY_EXTEND) { 802 unsigned ExtendBits = 803 X.getValueSizeInBits() - X.getOperand(0).getValueSizeInBits(); 804 // Assume that we'll replace the any-extend with a zero-extend, and 805 // narrow the search to the extended value. 806 X = X.getOperand(0); 807 MaskLZ = ExtendBits > MaskLZ ? 0 : MaskLZ - ExtendBits; 808 ReplacingAnyExtend = true; 809 } 810 APInt MaskedHighBits = APInt::getHighBitsSet(X.getValueSizeInBits(), 811 MaskLZ); 812 APInt KnownZero, KnownOne; 813 DAG.ComputeMaskedBits(X, MaskedHighBits, KnownZero, KnownOne); 814 if (MaskedHighBits != KnownZero) return true; 815 816 // We've identified a pattern that can be transformed into a single shift 817 // and an addressing mode. Make it so. 818 EVT VT = N.getValueType(); 819 if (ReplacingAnyExtend) { 820 assert(X.getValueType() != VT); 821 // We looked through an ANY_EXTEND node, insert a ZERO_EXTEND. 822 SDValue NewX = DAG.getNode(ISD::ZERO_EXTEND, X.getDebugLoc(), VT, X); 823 if (NewX.getNode()->getNodeId() == -1 || 824 NewX.getNode()->getNodeId() > N.getNode()->getNodeId()) { 825 DAG.RepositionNode(N.getNode(), NewX.getNode()); 826 NewX.getNode()->setNodeId(N.getNode()->getNodeId()); 827 } 828 X = NewX; 829 } 830 DebugLoc DL = N.getDebugLoc(); 831 SDValue NewSRLAmt = DAG.getConstant(ShiftAmt + AMShiftAmt, MVT::i8); 832 SDValue NewSRL = DAG.getNode(ISD::SRL, DL, VT, X, NewSRLAmt); 833 SDValue NewSHLAmt = DAG.getConstant(AMShiftAmt, MVT::i8); 834 SDValue NewSHL = DAG.getNode(ISD::SHL, DL, VT, NewSRL, NewSHLAmt); 835 if (NewSRLAmt.getNode()->getNodeId() == -1 || 836 NewSRLAmt.getNode()->getNodeId() > N.getNode()->getNodeId()) { 837 DAG.RepositionNode(N.getNode(), NewSRLAmt.getNode()); 838 NewSRLAmt.getNode()->setNodeId(N.getNode()->getNodeId()); 839 } 840 if (NewSRL.getNode()->getNodeId() == -1 || 841 NewSRL.getNode()->getNodeId() > N.getNode()->getNodeId()) { 842 DAG.RepositionNode(N.getNode(), NewSRL.getNode()); 843 NewSRL.getNode()->setNodeId(N.getNode()->getNodeId()); 844 } 845 if (NewSHLAmt.getNode()->getNodeId() == -1 || 846 NewSHLAmt.getNode()->getNodeId() > N.getNode()->getNodeId()) { 847 DAG.RepositionNode(N.getNode(), NewSHLAmt.getNode()); 848 NewSHLAmt.getNode()->setNodeId(N.getNode()->getNodeId()); 849 } 850 if (NewSHL.getNode()->getNodeId() == -1 || 851 NewSHL.getNode()->getNodeId() > N.getNode()->getNodeId()) { 852 DAG.RepositionNode(N.getNode(), NewSHL.getNode()); 853 NewSHL.getNode()->setNodeId(N.getNode()->getNodeId()); 854 } 855 DAG.ReplaceAllUsesWith(N, NewSHL); 856 857 AM.Scale = 1 << AMShiftAmt; 858 AM.IndexReg = NewSRL; 859 return false; 860} 861 862bool X86DAGToDAGISel::MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM, 863 unsigned Depth) { 864 DebugLoc dl = N.getDebugLoc(); 865 DEBUG({ 866 dbgs() << "MatchAddress: "; 867 AM.dump(); 868 }); 869 // Limit recursion. 870 if (Depth > 5) 871 return MatchAddressBase(N, AM); 872 873 // If this is already a %rip relative address, we can only merge immediates 874 // into it. Instead of handling this in every case, we handle it here. 875 // RIP relative addressing: %rip + 32-bit displacement! 876 if (AM.isRIPRelative()) { 877 // FIXME: JumpTable and ExternalSymbol address currently don't like 878 // displacements. It isn't very important, but this should be fixed for 879 // consistency. 880 if (!AM.ES && AM.JT != -1) return true; 881 882 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N)) 883 if (!FoldOffsetIntoAddress(Cst->getSExtValue(), AM)) 884 return false; 885 return true; 886 } 887 888 switch (N.getOpcode()) { 889 default: break; 890 case ISD::Constant: { 891 uint64_t Val = cast<ConstantSDNode>(N)->getSExtValue(); 892 if (!FoldOffsetIntoAddress(Val, AM)) 893 return false; 894 break; 895 } 896 897 case X86ISD::Wrapper: 898 case X86ISD::WrapperRIP: 899 if (!MatchWrapper(N, AM)) 900 return false; 901 break; 902 903 case ISD::LOAD: 904 if (!MatchLoadInAddress(cast<LoadSDNode>(N), AM)) 905 return false; 906 break; 907 908 case ISD::FrameIndex: 909 if (AM.BaseType == X86ISelAddressMode::RegBase && 910 AM.Base_Reg.getNode() == 0 && 911 (!Subtarget->is64Bit() || isDispSafeForFrameIndex(AM.Disp))) { 912 AM.BaseType = X86ISelAddressMode::FrameIndexBase; 913 AM.Base_FrameIndex = cast<FrameIndexSDNode>(N)->getIndex(); 914 return false; 915 } 916 break; 917 918 case ISD::SHL: 919 if (AM.IndexReg.getNode() != 0 || AM.Scale != 1) 920 break; 921 922 if (ConstantSDNode 923 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1))) { 924 unsigned Val = CN->getZExtValue(); 925 // Note that we handle x<<1 as (,x,2) rather than (x,x) here so 926 // that the base operand remains free for further matching. If 927 // the base doesn't end up getting used, a post-processing step 928 // in MatchAddress turns (,x,2) into (x,x), which is cheaper. 929 if (Val == 1 || Val == 2 || Val == 3) { 930 AM.Scale = 1 << Val; 931 SDValue ShVal = N.getNode()->getOperand(0); 932 933 // Okay, we know that we have a scale by now. However, if the scaled 934 // value is an add of something and a constant, we can fold the 935 // constant into the disp field here. 936 if (CurDAG->isBaseWithConstantOffset(ShVal)) { 937 AM.IndexReg = ShVal.getNode()->getOperand(0); 938 ConstantSDNode *AddVal = 939 cast<ConstantSDNode>(ShVal.getNode()->getOperand(1)); 940 uint64_t Disp = AddVal->getSExtValue() << Val; 941 if (!FoldOffsetIntoAddress(Disp, AM)) 942 return false; 943 } 944 945 AM.IndexReg = ShVal; 946 return false; 947 } 948 break; 949 } 950 951 case ISD::SRL: 952 // Try to fold the mask and shift into the scale, and return false if we 953 // succeed. 954 if (!FoldMaskAndShiftToScale(*CurDAG, N, AM)) 955 return false; 956 break; 957 958 case ISD::SMUL_LOHI: 959 case ISD::UMUL_LOHI: 960 // A mul_lohi where we need the low part can be folded as a plain multiply. 961 if (N.getResNo() != 0) break; 962 // FALL THROUGH 963 case ISD::MUL: 964 case X86ISD::MUL_IMM: 965 // X*[3,5,9] -> X+X*[2,4,8] 966 if (AM.BaseType == X86ISelAddressMode::RegBase && 967 AM.Base_Reg.getNode() == 0 && 968 AM.IndexReg.getNode() == 0) { 969 if (ConstantSDNode 970 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1))) 971 if (CN->getZExtValue() == 3 || CN->getZExtValue() == 5 || 972 CN->getZExtValue() == 9) { 973 AM.Scale = unsigned(CN->getZExtValue())-1; 974 975 SDValue MulVal = N.getNode()->getOperand(0); 976 SDValue Reg; 977 978 // Okay, we know that we have a scale by now. However, if the scaled 979 // value is an add of something and a constant, we can fold the 980 // constant into the disp field here. 981 if (MulVal.getNode()->getOpcode() == ISD::ADD && MulVal.hasOneUse() && 982 isa<ConstantSDNode>(MulVal.getNode()->getOperand(1))) { 983 Reg = MulVal.getNode()->getOperand(0); 984 ConstantSDNode *AddVal = 985 cast<ConstantSDNode>(MulVal.getNode()->getOperand(1)); 986 uint64_t Disp = AddVal->getSExtValue() * CN->getZExtValue(); 987 if (FoldOffsetIntoAddress(Disp, AM)) 988 Reg = N.getNode()->getOperand(0); 989 } else { 990 Reg = N.getNode()->getOperand(0); 991 } 992 993 AM.IndexReg = AM.Base_Reg = Reg; 994 return false; 995 } 996 } 997 break; 998 999 case ISD::SUB: { 1000 // Given A-B, if A can be completely folded into the address and 1001 // the index field with the index field unused, use -B as the index. 1002 // This is a win if a has multiple parts that can be folded into 1003 // the address. Also, this saves a mov if the base register has 1004 // other uses, since it avoids a two-address sub instruction, however 1005 // it costs an additional mov if the index register has other uses. 1006 1007 // Add an artificial use to this node so that we can keep track of 1008 // it if it gets CSE'd with a different node. 1009 HandleSDNode Handle(N); 1010 1011 // Test if the LHS of the sub can be folded. 1012 X86ISelAddressMode Backup = AM; 1013 if (MatchAddressRecursively(N.getNode()->getOperand(0), AM, Depth+1)) { 1014 AM = Backup; 1015 break; 1016 } 1017 // Test if the index field is free for use. 1018 if (AM.IndexReg.getNode() || AM.isRIPRelative()) { 1019 AM = Backup; 1020 break; 1021 } 1022 1023 int Cost = 0; 1024 SDValue RHS = Handle.getValue().getNode()->getOperand(1); 1025 // If the RHS involves a register with multiple uses, this 1026 // transformation incurs an extra mov, due to the neg instruction 1027 // clobbering its operand. 1028 if (!RHS.getNode()->hasOneUse() || 1029 RHS.getNode()->getOpcode() == ISD::CopyFromReg || 1030 RHS.getNode()->getOpcode() == ISD::TRUNCATE || 1031 RHS.getNode()->getOpcode() == ISD::ANY_EXTEND || 1032 (RHS.getNode()->getOpcode() == ISD::ZERO_EXTEND && 1033 RHS.getNode()->getOperand(0).getValueType() == MVT::i32)) 1034 ++Cost; 1035 // If the base is a register with multiple uses, this 1036 // transformation may save a mov. 1037 if ((AM.BaseType == X86ISelAddressMode::RegBase && 1038 AM.Base_Reg.getNode() && 1039 !AM.Base_Reg.getNode()->hasOneUse()) || 1040 AM.BaseType == X86ISelAddressMode::FrameIndexBase) 1041 --Cost; 1042 // If the folded LHS was interesting, this transformation saves 1043 // address arithmetic. 1044 if ((AM.hasSymbolicDisplacement() && !Backup.hasSymbolicDisplacement()) + 1045 ((AM.Disp != 0) && (Backup.Disp == 0)) + 1046 (AM.Segment.getNode() && !Backup.Segment.getNode()) >= 2) 1047 --Cost; 1048 // If it doesn't look like it may be an overall win, don't do it. 1049 if (Cost >= 0) { 1050 AM = Backup; 1051 break; 1052 } 1053 1054 // Ok, the transformation is legal and appears profitable. Go for it. 1055 SDValue Zero = CurDAG->getConstant(0, N.getValueType()); 1056 SDValue Neg = CurDAG->getNode(ISD::SUB, dl, N.getValueType(), Zero, RHS); 1057 AM.IndexReg = Neg; 1058 AM.Scale = 1; 1059 1060 // Insert the new nodes into the topological ordering. 1061 if (Zero.getNode()->getNodeId() == -1 || 1062 Zero.getNode()->getNodeId() > N.getNode()->getNodeId()) { 1063 CurDAG->RepositionNode(N.getNode(), Zero.getNode()); 1064 Zero.getNode()->setNodeId(N.getNode()->getNodeId()); 1065 } 1066 if (Neg.getNode()->getNodeId() == -1 || 1067 Neg.getNode()->getNodeId() > N.getNode()->getNodeId()) { 1068 CurDAG->RepositionNode(N.getNode(), Neg.getNode()); 1069 Neg.getNode()->setNodeId(N.getNode()->getNodeId()); 1070 } 1071 return false; 1072 } 1073 1074 case ISD::ADD: { 1075 // Add an artificial use to this node so that we can keep track of 1076 // it if it gets CSE'd with a different node. 1077 HandleSDNode Handle(N); 1078 1079 X86ISelAddressMode Backup = AM; 1080 if (!MatchAddressRecursively(N.getOperand(0), AM, Depth+1) && 1081 !MatchAddressRecursively(Handle.getValue().getOperand(1), AM, Depth+1)) 1082 return false; 1083 AM = Backup; 1084 1085 // Try again after commuting the operands. 1086 if (!MatchAddressRecursively(Handle.getValue().getOperand(1), AM, Depth+1)&& 1087 !MatchAddressRecursively(Handle.getValue().getOperand(0), AM, Depth+1)) 1088 return false; 1089 AM = Backup; 1090 1091 // If we couldn't fold both operands into the address at the same time, 1092 // see if we can just put each operand into a register and fold at least 1093 // the add. 1094 if (AM.BaseType == X86ISelAddressMode::RegBase && 1095 !AM.Base_Reg.getNode() && 1096 !AM.IndexReg.getNode()) { 1097 N = Handle.getValue(); 1098 AM.Base_Reg = N.getOperand(0); 1099 AM.IndexReg = N.getOperand(1); 1100 AM.Scale = 1; 1101 return false; 1102 } 1103 N = Handle.getValue(); 1104 break; 1105 } 1106 1107 case ISD::OR: 1108 // Handle "X | C" as "X + C" iff X is known to have C bits clear. 1109 if (CurDAG->isBaseWithConstantOffset(N)) { 1110 X86ISelAddressMode Backup = AM; 1111 ConstantSDNode *CN = cast<ConstantSDNode>(N.getOperand(1)); 1112 1113 // Start with the LHS as an addr mode. 1114 if (!MatchAddressRecursively(N.getOperand(0), AM, Depth+1) && 1115 !FoldOffsetIntoAddress(CN->getSExtValue(), AM)) 1116 return false; 1117 AM = Backup; 1118 } 1119 break; 1120 1121 case ISD::AND: { 1122 // Perform some heroic transforms on an and of a constant-count shift 1123 // with a constant to enable use of the scaled offset field. 1124 1125 SDValue Shift = N.getOperand(0); 1126 if (Shift.getNumOperands() != 2) break; 1127 1128 // Scale must not be used already. 1129 if (AM.IndexReg.getNode() != 0 || AM.Scale != 1) break; 1130 1131 SDValue X = Shift.getOperand(0); 1132 ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N.getOperand(1)); 1133 ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(Shift.getOperand(1)); 1134 if (!C1 || !C2) break; 1135 1136 // Handle "(X >> (8-C1)) & C2" as "(X >> 8) & 0xff)" if safe. This 1137 // allows us to convert the shift and and into an h-register extract and 1138 // a scaled index. 1139 if (Shift.getOpcode() == ISD::SRL && Shift.hasOneUse()) { 1140 int ScaleLog = 8 - C1->getZExtValue(); 1141 if (ScaleLog > 0 && ScaleLog < 4 && 1142 C2->getZExtValue() == (UINT64_C(0xff) << ScaleLog)) { 1143 SDValue Eight = CurDAG->getConstant(8, MVT::i8); 1144 SDValue Mask = CurDAG->getConstant(0xff, N.getValueType()); 1145 SDValue Srl = CurDAG->getNode(ISD::SRL, dl, N.getValueType(), 1146 X, Eight); 1147 SDValue And = CurDAG->getNode(ISD::AND, dl, N.getValueType(), 1148 Srl, Mask); 1149 SDValue ShlCount = CurDAG->getConstant(ScaleLog, MVT::i8); 1150 SDValue Shl = CurDAG->getNode(ISD::SHL, dl, N.getValueType(), 1151 And, ShlCount); 1152 1153 // Insert the new nodes into the topological ordering. 1154 if (Eight.getNode()->getNodeId() == -1 || 1155 Eight.getNode()->getNodeId() > X.getNode()->getNodeId()) { 1156 CurDAG->RepositionNode(X.getNode(), Eight.getNode()); 1157 Eight.getNode()->setNodeId(X.getNode()->getNodeId()); 1158 } 1159 if (Mask.getNode()->getNodeId() == -1 || 1160 Mask.getNode()->getNodeId() > X.getNode()->getNodeId()) { 1161 CurDAG->RepositionNode(X.getNode(), Mask.getNode()); 1162 Mask.getNode()->setNodeId(X.getNode()->getNodeId()); 1163 } 1164 if (Srl.getNode()->getNodeId() == -1 || 1165 Srl.getNode()->getNodeId() > Shift.getNode()->getNodeId()) { 1166 CurDAG->RepositionNode(Shift.getNode(), Srl.getNode()); 1167 Srl.getNode()->setNodeId(Shift.getNode()->getNodeId()); 1168 } 1169 if (And.getNode()->getNodeId() == -1 || 1170 And.getNode()->getNodeId() > N.getNode()->getNodeId()) { 1171 CurDAG->RepositionNode(N.getNode(), And.getNode()); 1172 And.getNode()->setNodeId(N.getNode()->getNodeId()); 1173 } 1174 if (ShlCount.getNode()->getNodeId() == -1 || 1175 ShlCount.getNode()->getNodeId() > X.getNode()->getNodeId()) { 1176 CurDAG->RepositionNode(X.getNode(), ShlCount.getNode()); 1177 ShlCount.getNode()->setNodeId(N.getNode()->getNodeId()); 1178 } 1179 if (Shl.getNode()->getNodeId() == -1 || 1180 Shl.getNode()->getNodeId() > N.getNode()->getNodeId()) { 1181 CurDAG->RepositionNode(N.getNode(), Shl.getNode()); 1182 Shl.getNode()->setNodeId(N.getNode()->getNodeId()); 1183 } 1184 CurDAG->ReplaceAllUsesWith(N, Shl); 1185 AM.IndexReg = And; 1186 AM.Scale = (1 << ScaleLog); 1187 return false; 1188 } 1189 } 1190 1191 // Try to fold the mask and shift into the scale, and return false if we 1192 // succeed. 1193 if (!FoldMaskAndShiftToScale(*CurDAG, N, AM)) 1194 return false; 1195 1196 // Handle "(X << C1) & C2" as "(X & (C2>>C1)) << C1" if safe and if this 1197 // allows us to fold the shift into this addressing mode. 1198 if (Shift.getOpcode() != ISD::SHL) break; 1199 1200 // Not likely to be profitable if either the AND or SHIFT node has more 1201 // than one use (unless all uses are for address computation). Besides, 1202 // isel mechanism requires their node ids to be reused. 1203 if (!N.hasOneUse() || !Shift.hasOneUse()) 1204 break; 1205 1206 // Verify that the shift amount is something we can fold. 1207 unsigned ShiftCst = C1->getZExtValue(); 1208 if (ShiftCst != 1 && ShiftCst != 2 && ShiftCst != 3) 1209 break; 1210 1211 // Get the new AND mask, this folds to a constant. 1212 SDValue NewANDMask = CurDAG->getNode(ISD::SRL, dl, N.getValueType(), 1213 SDValue(C2, 0), SDValue(C1, 0)); 1214 SDValue NewAND = CurDAG->getNode(ISD::AND, dl, N.getValueType(), X, 1215 NewANDMask); 1216 SDValue NewSHIFT = CurDAG->getNode(ISD::SHL, dl, N.getValueType(), 1217 NewAND, SDValue(C1, 0)); 1218 1219 // Insert the new nodes into the topological ordering. 1220 if (C1->getNodeId() > X.getNode()->getNodeId()) { 1221 CurDAG->RepositionNode(X.getNode(), C1); 1222 C1->setNodeId(X.getNode()->getNodeId()); 1223 } 1224 if (NewANDMask.getNode()->getNodeId() == -1 || 1225 NewANDMask.getNode()->getNodeId() > X.getNode()->getNodeId()) { 1226 CurDAG->RepositionNode(X.getNode(), NewANDMask.getNode()); 1227 NewANDMask.getNode()->setNodeId(X.getNode()->getNodeId()); 1228 } 1229 if (NewAND.getNode()->getNodeId() == -1 || 1230 NewAND.getNode()->getNodeId() > Shift.getNode()->getNodeId()) { 1231 CurDAG->RepositionNode(Shift.getNode(), NewAND.getNode()); 1232 NewAND.getNode()->setNodeId(Shift.getNode()->getNodeId()); 1233 } 1234 if (NewSHIFT.getNode()->getNodeId() == -1 || 1235 NewSHIFT.getNode()->getNodeId() > N.getNode()->getNodeId()) { 1236 CurDAG->RepositionNode(N.getNode(), NewSHIFT.getNode()); 1237 NewSHIFT.getNode()->setNodeId(N.getNode()->getNodeId()); 1238 } 1239 1240 CurDAG->ReplaceAllUsesWith(N, NewSHIFT); 1241 1242 AM.Scale = 1 << ShiftCst; 1243 AM.IndexReg = NewAND; 1244 return false; 1245 } 1246 } 1247 1248 return MatchAddressBase(N, AM); 1249} 1250 1251/// MatchAddressBase - Helper for MatchAddress. Add the specified node to the 1252/// specified addressing mode without any further recursion. 1253bool X86DAGToDAGISel::MatchAddressBase(SDValue N, X86ISelAddressMode &AM) { 1254 // Is the base register already occupied? 1255 if (AM.BaseType != X86ISelAddressMode::RegBase || AM.Base_Reg.getNode()) { 1256 // If so, check to see if the scale index register is set. 1257 if (AM.IndexReg.getNode() == 0) { 1258 AM.IndexReg = N; 1259 AM.Scale = 1; 1260 return false; 1261 } 1262 1263 // Otherwise, we cannot select it. 1264 return true; 1265 } 1266 1267 // Default, generate it as a register. 1268 AM.BaseType = X86ISelAddressMode::RegBase; 1269 AM.Base_Reg = N; 1270 return false; 1271} 1272 1273/// SelectAddr - returns true if it is able pattern match an addressing mode. 1274/// It returns the operands which make up the maximal addressing mode it can 1275/// match by reference. 1276/// 1277/// Parent is the parent node of the addr operand that is being matched. It 1278/// is always a load, store, atomic node, or null. It is only null when 1279/// checking memory operands for inline asm nodes. 1280bool X86DAGToDAGISel::SelectAddr(SDNode *Parent, SDValue N, SDValue &Base, 1281 SDValue &Scale, SDValue &Index, 1282 SDValue &Disp, SDValue &Segment) { 1283 X86ISelAddressMode AM; 1284 1285 if (Parent && 1286 // This list of opcodes are all the nodes that have an "addr:$ptr" operand 1287 // that are not a MemSDNode, and thus don't have proper addrspace info. 1288 Parent->getOpcode() != ISD::INTRINSIC_W_CHAIN && // unaligned loads, fixme 1289 Parent->getOpcode() != ISD::INTRINSIC_VOID && // nontemporal stores 1290 Parent->getOpcode() != X86ISD::TLSCALL) { // Fixme 1291 unsigned AddrSpace = 1292 cast<MemSDNode>(Parent)->getPointerInfo().getAddrSpace(); 1293 // AddrSpace 256 -> GS, 257 -> FS. 1294 if (AddrSpace == 256) 1295 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16); 1296 if (AddrSpace == 257) 1297 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16); 1298 } 1299 1300 if (MatchAddress(N, AM)) 1301 return false; 1302 1303 EVT VT = N.getValueType(); 1304 if (AM.BaseType == X86ISelAddressMode::RegBase) { 1305 if (!AM.Base_Reg.getNode()) 1306 AM.Base_Reg = CurDAG->getRegister(0, VT); 1307 } 1308 1309 if (!AM.IndexReg.getNode()) 1310 AM.IndexReg = CurDAG->getRegister(0, VT); 1311 1312 getAddressOperands(AM, Base, Scale, Index, Disp, Segment); 1313 return true; 1314} 1315 1316/// SelectScalarSSELoad - Match a scalar SSE load. In particular, we want to 1317/// match a load whose top elements are either undef or zeros. The load flavor 1318/// is derived from the type of N, which is either v4f32 or v2f64. 1319/// 1320/// We also return: 1321/// PatternChainNode: this is the matched node that has a chain input and 1322/// output. 1323bool X86DAGToDAGISel::SelectScalarSSELoad(SDNode *Root, 1324 SDValue N, SDValue &Base, 1325 SDValue &Scale, SDValue &Index, 1326 SDValue &Disp, SDValue &Segment, 1327 SDValue &PatternNodeWithChain) { 1328 if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) { 1329 PatternNodeWithChain = N.getOperand(0); 1330 if (ISD::isNON_EXTLoad(PatternNodeWithChain.getNode()) && 1331 PatternNodeWithChain.hasOneUse() && 1332 IsProfitableToFold(N.getOperand(0), N.getNode(), Root) && 1333 IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) { 1334 LoadSDNode *LD = cast<LoadSDNode>(PatternNodeWithChain); 1335 if (!SelectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp, Segment)) 1336 return false; 1337 return true; 1338 } 1339 } 1340 1341 // Also handle the case where we explicitly require zeros in the top 1342 // elements. This is a vector shuffle from the zero vector. 1343 if (N.getOpcode() == X86ISD::VZEXT_MOVL && N.getNode()->hasOneUse() && 1344 // Check to see if the top elements are all zeros (or bitcast of zeros). 1345 N.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR && 1346 N.getOperand(0).getNode()->hasOneUse() && 1347 ISD::isNON_EXTLoad(N.getOperand(0).getOperand(0).getNode()) && 1348 N.getOperand(0).getOperand(0).hasOneUse() && 1349 IsProfitableToFold(N.getOperand(0), N.getNode(), Root) && 1350 IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) { 1351 // Okay, this is a zero extending load. Fold it. 1352 LoadSDNode *LD = cast<LoadSDNode>(N.getOperand(0).getOperand(0)); 1353 if (!SelectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp, Segment)) 1354 return false; 1355 PatternNodeWithChain = SDValue(LD, 0); 1356 return true; 1357 } 1358 return false; 1359} 1360 1361 1362/// SelectLEAAddr - it calls SelectAddr and determines if the maximal addressing 1363/// mode it matches can be cost effectively emitted as an LEA instruction. 1364bool X86DAGToDAGISel::SelectLEAAddr(SDValue N, 1365 SDValue &Base, SDValue &Scale, 1366 SDValue &Index, SDValue &Disp, 1367 SDValue &Segment) { 1368 X86ISelAddressMode AM; 1369 1370 // Set AM.Segment to prevent MatchAddress from using one. LEA doesn't support 1371 // segments. 1372 SDValue Copy = AM.Segment; 1373 SDValue T = CurDAG->getRegister(0, MVT::i32); 1374 AM.Segment = T; 1375 if (MatchAddress(N, AM)) 1376 return false; 1377 assert (T == AM.Segment); 1378 AM.Segment = Copy; 1379 1380 EVT VT = N.getValueType(); 1381 unsigned Complexity = 0; 1382 if (AM.BaseType == X86ISelAddressMode::RegBase) 1383 if (AM.Base_Reg.getNode()) 1384 Complexity = 1; 1385 else 1386 AM.Base_Reg = CurDAG->getRegister(0, VT); 1387 else if (AM.BaseType == X86ISelAddressMode::FrameIndexBase) 1388 Complexity = 4; 1389 1390 if (AM.IndexReg.getNode()) 1391 Complexity++; 1392 else 1393 AM.IndexReg = CurDAG->getRegister(0, VT); 1394 1395 // Don't match just leal(,%reg,2). It's cheaper to do addl %reg, %reg, or with 1396 // a simple shift. 1397 if (AM.Scale > 1) 1398 Complexity++; 1399 1400 // FIXME: We are artificially lowering the criteria to turn ADD %reg, $GA 1401 // to a LEA. This is determined with some expermentation but is by no means 1402 // optimal (especially for code size consideration). LEA is nice because of 1403 // its three-address nature. Tweak the cost function again when we can run 1404 // convertToThreeAddress() at register allocation time. 1405 if (AM.hasSymbolicDisplacement()) { 1406 // For X86-64, we should always use lea to materialize RIP relative 1407 // addresses. 1408 if (Subtarget->is64Bit()) 1409 Complexity = 4; 1410 else 1411 Complexity += 2; 1412 } 1413 1414 if (AM.Disp && (AM.Base_Reg.getNode() || AM.IndexReg.getNode())) 1415 Complexity++; 1416 1417 // If it isn't worth using an LEA, reject it. 1418 if (Complexity <= 2) 1419 return false; 1420 1421 getAddressOperands(AM, Base, Scale, Index, Disp, Segment); 1422 return true; 1423} 1424 1425/// SelectTLSADDRAddr - This is only run on TargetGlobalTLSAddress nodes. 1426bool X86DAGToDAGISel::SelectTLSADDRAddr(SDValue N, SDValue &Base, 1427 SDValue &Scale, SDValue &Index, 1428 SDValue &Disp, SDValue &Segment) { 1429 assert(N.getOpcode() == ISD::TargetGlobalTLSAddress); 1430 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N); 1431 1432 X86ISelAddressMode AM; 1433 AM.GV = GA->getGlobal(); 1434 AM.Disp += GA->getOffset(); 1435 AM.Base_Reg = CurDAG->getRegister(0, N.getValueType()); 1436 AM.SymbolFlags = GA->getTargetFlags(); 1437 1438 if (N.getValueType() == MVT::i32) { 1439 AM.Scale = 1; 1440 AM.IndexReg = CurDAG->getRegister(X86::EBX, MVT::i32); 1441 } else { 1442 AM.IndexReg = CurDAG->getRegister(0, MVT::i64); 1443 } 1444 1445 getAddressOperands(AM, Base, Scale, Index, Disp, Segment); 1446 return true; 1447} 1448 1449 1450bool X86DAGToDAGISel::TryFoldLoad(SDNode *P, SDValue N, 1451 SDValue &Base, SDValue &Scale, 1452 SDValue &Index, SDValue &Disp, 1453 SDValue &Segment) { 1454 if (!ISD::isNON_EXTLoad(N.getNode()) || 1455 !IsProfitableToFold(N, P, P) || 1456 !IsLegalToFold(N, P, P, OptLevel)) 1457 return false; 1458 1459 return SelectAddr(N.getNode(), 1460 N.getOperand(1), Base, Scale, Index, Disp, Segment); 1461} 1462 1463/// getGlobalBaseReg - Return an SDNode that returns the value of 1464/// the global base register. Output instructions required to 1465/// initialize the global base register, if necessary. 1466/// 1467SDNode *X86DAGToDAGISel::getGlobalBaseReg() { 1468 unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF); 1469 return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode(); 1470} 1471 1472SDNode *X86DAGToDAGISel::SelectAtomic64(SDNode *Node, unsigned Opc) { 1473 SDValue Chain = Node->getOperand(0); 1474 SDValue In1 = Node->getOperand(1); 1475 SDValue In2L = Node->getOperand(2); 1476 SDValue In2H = Node->getOperand(3); 1477 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; 1478 if (!SelectAddr(Node, In1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) 1479 return NULL; 1480 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1); 1481 MemOp[0] = cast<MemSDNode>(Node)->getMemOperand(); 1482 const SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, In2L, In2H, Chain}; 1483 SDNode *ResNode = CurDAG->getMachineNode(Opc, Node->getDebugLoc(), 1484 MVT::i32, MVT::i32, MVT::Other, Ops, 1485 array_lengthof(Ops)); 1486 cast<MachineSDNode>(ResNode)->setMemRefs(MemOp, MemOp + 1); 1487 return ResNode; 1488} 1489 1490// FIXME: Figure out some way to unify this with the 'or' and other code 1491// below. 1492SDNode *X86DAGToDAGISel::SelectAtomicLoadAdd(SDNode *Node, EVT NVT) { 1493 if (Node->hasAnyUseOfValue(0)) 1494 return 0; 1495 1496 // Optimize common patterns for __sync_add_and_fetch and 1497 // __sync_sub_and_fetch where the result is not used. This allows us 1498 // to use "lock" version of add, sub, inc, dec instructions. 1499 // FIXME: Do not use special instructions but instead add the "lock" 1500 // prefix to the target node somehow. The extra information will then be 1501 // transferred to machine instruction and it denotes the prefix. 1502 SDValue Chain = Node->getOperand(0); 1503 SDValue Ptr = Node->getOperand(1); 1504 SDValue Val = Node->getOperand(2); 1505 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; 1506 if (!SelectAddr(Node, Ptr, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) 1507 return 0; 1508 1509 bool isInc = false, isDec = false, isSub = false, isCN = false; 1510 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val); 1511 if (CN && CN->getSExtValue() == (int32_t)CN->getSExtValue()) { 1512 isCN = true; 1513 int64_t CNVal = CN->getSExtValue(); 1514 if (CNVal == 1) 1515 isInc = true; 1516 else if (CNVal == -1) 1517 isDec = true; 1518 else if (CNVal >= 0) 1519 Val = CurDAG->getTargetConstant(CNVal, NVT); 1520 else { 1521 isSub = true; 1522 Val = CurDAG->getTargetConstant(-CNVal, NVT); 1523 } 1524 } else if (Val.hasOneUse() && 1525 Val.getOpcode() == ISD::SUB && 1526 X86::isZeroNode(Val.getOperand(0))) { 1527 isSub = true; 1528 Val = Val.getOperand(1); 1529 } 1530 1531 DebugLoc dl = Node->getDebugLoc(); 1532 unsigned Opc = 0; 1533 switch (NVT.getSimpleVT().SimpleTy) { 1534 default: return 0; 1535 case MVT::i8: 1536 if (isInc) 1537 Opc = X86::LOCK_INC8m; 1538 else if (isDec) 1539 Opc = X86::LOCK_DEC8m; 1540 else if (isSub) { 1541 if (isCN) 1542 Opc = X86::LOCK_SUB8mi; 1543 else 1544 Opc = X86::LOCK_SUB8mr; 1545 } else { 1546 if (isCN) 1547 Opc = X86::LOCK_ADD8mi; 1548 else 1549 Opc = X86::LOCK_ADD8mr; 1550 } 1551 break; 1552 case MVT::i16: 1553 if (isInc) 1554 Opc = X86::LOCK_INC16m; 1555 else if (isDec) 1556 Opc = X86::LOCK_DEC16m; 1557 else if (isSub) { 1558 if (isCN) { 1559 if (immSext8(Val.getNode())) 1560 Opc = X86::LOCK_SUB16mi8; 1561 else 1562 Opc = X86::LOCK_SUB16mi; 1563 } else 1564 Opc = X86::LOCK_SUB16mr; 1565 } else { 1566 if (isCN) { 1567 if (immSext8(Val.getNode())) 1568 Opc = X86::LOCK_ADD16mi8; 1569 else 1570 Opc = X86::LOCK_ADD16mi; 1571 } else 1572 Opc = X86::LOCK_ADD16mr; 1573 } 1574 break; 1575 case MVT::i32: 1576 if (isInc) 1577 Opc = X86::LOCK_INC32m; 1578 else if (isDec) 1579 Opc = X86::LOCK_DEC32m; 1580 else if (isSub) { 1581 if (isCN) { 1582 if (immSext8(Val.getNode())) 1583 Opc = X86::LOCK_SUB32mi8; 1584 else 1585 Opc = X86::LOCK_SUB32mi; 1586 } else 1587 Opc = X86::LOCK_SUB32mr; 1588 } else { 1589 if (isCN) { 1590 if (immSext8(Val.getNode())) 1591 Opc = X86::LOCK_ADD32mi8; 1592 else 1593 Opc = X86::LOCK_ADD32mi; 1594 } else 1595 Opc = X86::LOCK_ADD32mr; 1596 } 1597 break; 1598 case MVT::i64: 1599 if (isInc) 1600 Opc = X86::LOCK_INC64m; 1601 else if (isDec) 1602 Opc = X86::LOCK_DEC64m; 1603 else if (isSub) { 1604 Opc = X86::LOCK_SUB64mr; 1605 if (isCN) { 1606 if (immSext8(Val.getNode())) 1607 Opc = X86::LOCK_SUB64mi8; 1608 else if (i64immSExt32(Val.getNode())) 1609 Opc = X86::LOCK_SUB64mi32; 1610 } 1611 } else { 1612 Opc = X86::LOCK_ADD64mr; 1613 if (isCN) { 1614 if (immSext8(Val.getNode())) 1615 Opc = X86::LOCK_ADD64mi8; 1616 else if (i64immSExt32(Val.getNode())) 1617 Opc = X86::LOCK_ADD64mi32; 1618 } 1619 } 1620 break; 1621 } 1622 1623 SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, 1624 dl, NVT), 0); 1625 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1); 1626 MemOp[0] = cast<MemSDNode>(Node)->getMemOperand(); 1627 if (isInc || isDec) { 1628 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Chain }; 1629 SDValue Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 6), 0); 1630 cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1); 1631 SDValue RetVals[] = { Undef, Ret }; 1632 return CurDAG->getMergeValues(RetVals, 2, dl).getNode(); 1633 } else { 1634 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Val, Chain }; 1635 SDValue Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 7), 0); 1636 cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1); 1637 SDValue RetVals[] = { Undef, Ret }; 1638 return CurDAG->getMergeValues(RetVals, 2, dl).getNode(); 1639 } 1640} 1641 1642enum AtomicOpc { 1643 OR, 1644 AND, 1645 XOR, 1646 AtomicOpcEnd 1647}; 1648 1649enum AtomicSz { 1650 ConstantI8, 1651 I8, 1652 SextConstantI16, 1653 ConstantI16, 1654 I16, 1655 SextConstantI32, 1656 ConstantI32, 1657 I32, 1658 SextConstantI64, 1659 ConstantI64, 1660 I64, 1661 AtomicSzEnd 1662}; 1663 1664static const unsigned int AtomicOpcTbl[AtomicOpcEnd][AtomicSzEnd] = { 1665 { 1666 X86::LOCK_OR8mi, 1667 X86::LOCK_OR8mr, 1668 X86::LOCK_OR16mi8, 1669 X86::LOCK_OR16mi, 1670 X86::LOCK_OR16mr, 1671 X86::LOCK_OR32mi8, 1672 X86::LOCK_OR32mi, 1673 X86::LOCK_OR32mr, 1674 X86::LOCK_OR64mi8, 1675 X86::LOCK_OR64mi32, 1676 X86::LOCK_OR64mr 1677 }, 1678 { 1679 X86::LOCK_AND8mi, 1680 X86::LOCK_AND8mr, 1681 X86::LOCK_AND16mi8, 1682 X86::LOCK_AND16mi, 1683 X86::LOCK_AND16mr, 1684 X86::LOCK_AND32mi8, 1685 X86::LOCK_AND32mi, 1686 X86::LOCK_AND32mr, 1687 X86::LOCK_AND64mi8, 1688 X86::LOCK_AND64mi32, 1689 X86::LOCK_AND64mr 1690 }, 1691 { 1692 X86::LOCK_XOR8mi, 1693 X86::LOCK_XOR8mr, 1694 X86::LOCK_XOR16mi8, 1695 X86::LOCK_XOR16mi, 1696 X86::LOCK_XOR16mr, 1697 X86::LOCK_XOR32mi8, 1698 X86::LOCK_XOR32mi, 1699 X86::LOCK_XOR32mr, 1700 X86::LOCK_XOR64mi8, 1701 X86::LOCK_XOR64mi32, 1702 X86::LOCK_XOR64mr 1703 } 1704}; 1705 1706SDNode *X86DAGToDAGISel::SelectAtomicLoadArith(SDNode *Node, EVT NVT) { 1707 if (Node->hasAnyUseOfValue(0)) 1708 return 0; 1709 1710 // Optimize common patterns for __sync_or_and_fetch and similar arith 1711 // operations where the result is not used. This allows us to use the "lock" 1712 // version of the arithmetic instruction. 1713 // FIXME: Same as for 'add' and 'sub', try to merge those down here. 1714 SDValue Chain = Node->getOperand(0); 1715 SDValue Ptr = Node->getOperand(1); 1716 SDValue Val = Node->getOperand(2); 1717 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; 1718 if (!SelectAddr(Node, Ptr, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) 1719 return 0; 1720 1721 // Which index into the table. 1722 enum AtomicOpc Op; 1723 switch (Node->getOpcode()) { 1724 case ISD::ATOMIC_LOAD_OR: 1725 Op = OR; 1726 break; 1727 case ISD::ATOMIC_LOAD_AND: 1728 Op = AND; 1729 break; 1730 case ISD::ATOMIC_LOAD_XOR: 1731 Op = XOR; 1732 break; 1733 default: 1734 return 0; 1735 } 1736 1737 bool isCN = false; 1738 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val); 1739 if (CN && (int32_t)CN->getSExtValue() == CN->getSExtValue()) { 1740 isCN = true; 1741 Val = CurDAG->getTargetConstant(CN->getSExtValue(), NVT); 1742 } 1743 1744 unsigned Opc = 0; 1745 switch (NVT.getSimpleVT().SimpleTy) { 1746 default: return 0; 1747 case MVT::i8: 1748 if (isCN) 1749 Opc = AtomicOpcTbl[Op][ConstantI8]; 1750 else 1751 Opc = AtomicOpcTbl[Op][I8]; 1752 break; 1753 case MVT::i16: 1754 if (isCN) { 1755 if (immSext8(Val.getNode())) 1756 Opc = AtomicOpcTbl[Op][SextConstantI16]; 1757 else 1758 Opc = AtomicOpcTbl[Op][ConstantI16]; 1759 } else 1760 Opc = AtomicOpcTbl[Op][I16]; 1761 break; 1762 case MVT::i32: 1763 if (isCN) { 1764 if (immSext8(Val.getNode())) 1765 Opc = AtomicOpcTbl[Op][SextConstantI32]; 1766 else 1767 Opc = AtomicOpcTbl[Op][ConstantI32]; 1768 } else 1769 Opc = AtomicOpcTbl[Op][I32]; 1770 break; 1771 case MVT::i64: 1772 Opc = AtomicOpcTbl[Op][I64]; 1773 if (isCN) { 1774 if (immSext8(Val.getNode())) 1775 Opc = AtomicOpcTbl[Op][SextConstantI64]; 1776 else if (i64immSExt32(Val.getNode())) 1777 Opc = AtomicOpcTbl[Op][ConstantI64]; 1778 } 1779 break; 1780 } 1781 1782 assert(Opc != 0 && "Invalid arith lock transform!"); 1783 1784 DebugLoc dl = Node->getDebugLoc(); 1785 SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, 1786 dl, NVT), 0); 1787 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1); 1788 MemOp[0] = cast<MemSDNode>(Node)->getMemOperand(); 1789 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Val, Chain }; 1790 SDValue Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 7), 0); 1791 cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1); 1792 SDValue RetVals[] = { Undef, Ret }; 1793 return CurDAG->getMergeValues(RetVals, 2, dl).getNode(); 1794} 1795 1796/// HasNoSignedComparisonUses - Test whether the given X86ISD::CMP node has 1797/// any uses which require the SF or OF bits to be accurate. 1798static bool HasNoSignedComparisonUses(SDNode *N) { 1799 // Examine each user of the node. 1800 for (SDNode::use_iterator UI = N->use_begin(), 1801 UE = N->use_end(); UI != UE; ++UI) { 1802 // Only examine CopyToReg uses. 1803 if (UI->getOpcode() != ISD::CopyToReg) 1804 return false; 1805 // Only examine CopyToReg uses that copy to EFLAGS. 1806 if (cast<RegisterSDNode>(UI->getOperand(1))->getReg() != 1807 X86::EFLAGS) 1808 return false; 1809 // Examine each user of the CopyToReg use. 1810 for (SDNode::use_iterator FlagUI = UI->use_begin(), 1811 FlagUE = UI->use_end(); FlagUI != FlagUE; ++FlagUI) { 1812 // Only examine the Flag result. 1813 if (FlagUI.getUse().getResNo() != 1) continue; 1814 // Anything unusual: assume conservatively. 1815 if (!FlagUI->isMachineOpcode()) return false; 1816 // Examine the opcode of the user. 1817 switch (FlagUI->getMachineOpcode()) { 1818 // These comparisons don't treat the most significant bit specially. 1819 case X86::SETAr: case X86::SETAEr: case X86::SETBr: case X86::SETBEr: 1820 case X86::SETEr: case X86::SETNEr: case X86::SETPr: case X86::SETNPr: 1821 case X86::SETAm: case X86::SETAEm: case X86::SETBm: case X86::SETBEm: 1822 case X86::SETEm: case X86::SETNEm: case X86::SETPm: case X86::SETNPm: 1823 case X86::JA_4: case X86::JAE_4: case X86::JB_4: case X86::JBE_4: 1824 case X86::JE_4: case X86::JNE_4: case X86::JP_4: case X86::JNP_4: 1825 case X86::CMOVA16rr: case X86::CMOVA16rm: 1826 case X86::CMOVA32rr: case X86::CMOVA32rm: 1827 case X86::CMOVA64rr: case X86::CMOVA64rm: 1828 case X86::CMOVAE16rr: case X86::CMOVAE16rm: 1829 case X86::CMOVAE32rr: case X86::CMOVAE32rm: 1830 case X86::CMOVAE64rr: case X86::CMOVAE64rm: 1831 case X86::CMOVB16rr: case X86::CMOVB16rm: 1832 case X86::CMOVB32rr: case X86::CMOVB32rm: 1833 case X86::CMOVB64rr: case X86::CMOVB64rm: 1834 case X86::CMOVBE16rr: case X86::CMOVBE16rm: 1835 case X86::CMOVBE32rr: case X86::CMOVBE32rm: 1836 case X86::CMOVBE64rr: case X86::CMOVBE64rm: 1837 case X86::CMOVE16rr: case X86::CMOVE16rm: 1838 case X86::CMOVE32rr: case X86::CMOVE32rm: 1839 case X86::CMOVE64rr: case X86::CMOVE64rm: 1840 case X86::CMOVNE16rr: case X86::CMOVNE16rm: 1841 case X86::CMOVNE32rr: case X86::CMOVNE32rm: 1842 case X86::CMOVNE64rr: case X86::CMOVNE64rm: 1843 case X86::CMOVNP16rr: case X86::CMOVNP16rm: 1844 case X86::CMOVNP32rr: case X86::CMOVNP32rm: 1845 case X86::CMOVNP64rr: case X86::CMOVNP64rm: 1846 case X86::CMOVP16rr: case X86::CMOVP16rm: 1847 case X86::CMOVP32rr: case X86::CMOVP32rm: 1848 case X86::CMOVP64rr: case X86::CMOVP64rm: 1849 continue; 1850 // Anything else: assume conservatively. 1851 default: return false; 1852 } 1853 } 1854 } 1855 return true; 1856} 1857 1858SDNode *X86DAGToDAGISel::Select(SDNode *Node) { 1859 EVT NVT = Node->getValueType(0); 1860 unsigned Opc, MOpc; 1861 unsigned Opcode = Node->getOpcode(); 1862 DebugLoc dl = Node->getDebugLoc(); 1863 1864 DEBUG(dbgs() << "Selecting: "; Node->dump(CurDAG); dbgs() << '\n'); 1865 1866 if (Node->isMachineOpcode()) { 1867 DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << '\n'); 1868 return NULL; // Already selected. 1869 } 1870 1871 switch (Opcode) { 1872 default: break; 1873 case X86ISD::GlobalBaseReg: 1874 return getGlobalBaseReg(); 1875 1876 case X86ISD::ATOMOR64_DAG: 1877 return SelectAtomic64(Node, X86::ATOMOR6432); 1878 case X86ISD::ATOMXOR64_DAG: 1879 return SelectAtomic64(Node, X86::ATOMXOR6432); 1880 case X86ISD::ATOMADD64_DAG: 1881 return SelectAtomic64(Node, X86::ATOMADD6432); 1882 case X86ISD::ATOMSUB64_DAG: 1883 return SelectAtomic64(Node, X86::ATOMSUB6432); 1884 case X86ISD::ATOMNAND64_DAG: 1885 return SelectAtomic64(Node, X86::ATOMNAND6432); 1886 case X86ISD::ATOMAND64_DAG: 1887 return SelectAtomic64(Node, X86::ATOMAND6432); 1888 case X86ISD::ATOMSWAP64_DAG: 1889 return SelectAtomic64(Node, X86::ATOMSWAP6432); 1890 1891 case ISD::ATOMIC_LOAD_ADD: { 1892 SDNode *RetVal = SelectAtomicLoadAdd(Node, NVT); 1893 if (RetVal) 1894 return RetVal; 1895 break; 1896 } 1897 case ISD::ATOMIC_LOAD_XOR: 1898 case ISD::ATOMIC_LOAD_AND: 1899 case ISD::ATOMIC_LOAD_OR: { 1900 SDNode *RetVal = SelectAtomicLoadArith(Node, NVT); 1901 if (RetVal) 1902 return RetVal; 1903 break; 1904 } 1905 case ISD::AND: 1906 case ISD::OR: 1907 case ISD::XOR: { 1908 // For operations of the form (x << C1) op C2, check if we can use a smaller 1909 // encoding for C2 by transforming it into (x op (C2>>C1)) << C1. 1910 SDValue N0 = Node->getOperand(0); 1911 SDValue N1 = Node->getOperand(1); 1912 1913 if (N0->getOpcode() != ISD::SHL || !N0->hasOneUse()) 1914 break; 1915 1916 // i8 is unshrinkable, i16 should be promoted to i32. 1917 if (NVT != MVT::i32 && NVT != MVT::i64) 1918 break; 1919 1920 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N1); 1921 ConstantSDNode *ShlCst = dyn_cast<ConstantSDNode>(N0->getOperand(1)); 1922 if (!Cst || !ShlCst) 1923 break; 1924 1925 int64_t Val = Cst->getSExtValue(); 1926 uint64_t ShlVal = ShlCst->getZExtValue(); 1927 1928 // Make sure that we don't change the operation by removing bits. 1929 // This only matters for OR and XOR, AND is unaffected. 1930 if (Opcode != ISD::AND && ((Val >> ShlVal) << ShlVal) != Val) 1931 break; 1932 1933 unsigned ShlOp, Op = 0; 1934 EVT CstVT = NVT; 1935 1936 // Check the minimum bitwidth for the new constant. 1937 // TODO: AND32ri is the same as AND64ri32 with zext imm. 1938 // TODO: MOV32ri+OR64r is cheaper than MOV64ri64+OR64rr 1939 // TODO: Using 16 and 8 bit operations is also possible for or32 & xor32. 1940 if (!isInt<8>(Val) && isInt<8>(Val >> ShlVal)) 1941 CstVT = MVT::i8; 1942 else if (!isInt<32>(Val) && isInt<32>(Val >> ShlVal)) 1943 CstVT = MVT::i32; 1944 1945 // Bail if there is no smaller encoding. 1946 if (NVT == CstVT) 1947 break; 1948 1949 switch (NVT.getSimpleVT().SimpleTy) { 1950 default: llvm_unreachable("Unsupported VT!"); 1951 case MVT::i32: 1952 assert(CstVT == MVT::i8); 1953 ShlOp = X86::SHL32ri; 1954 1955 switch (Opcode) { 1956 case ISD::AND: Op = X86::AND32ri8; break; 1957 case ISD::OR: Op = X86::OR32ri8; break; 1958 case ISD::XOR: Op = X86::XOR32ri8; break; 1959 } 1960 break; 1961 case MVT::i64: 1962 assert(CstVT == MVT::i8 || CstVT == MVT::i32); 1963 ShlOp = X86::SHL64ri; 1964 1965 switch (Opcode) { 1966 case ISD::AND: Op = CstVT==MVT::i8? X86::AND64ri8 : X86::AND64ri32; break; 1967 case ISD::OR: Op = CstVT==MVT::i8? X86::OR64ri8 : X86::OR64ri32; break; 1968 case ISD::XOR: Op = CstVT==MVT::i8? X86::XOR64ri8 : X86::XOR64ri32; break; 1969 } 1970 break; 1971 } 1972 1973 // Emit the smaller op and the shift. 1974 SDValue NewCst = CurDAG->getTargetConstant(Val >> ShlVal, CstVT); 1975 SDNode *New = CurDAG->getMachineNode(Op, dl, NVT, N0->getOperand(0),NewCst); 1976 return CurDAG->SelectNodeTo(Node, ShlOp, NVT, SDValue(New, 0), 1977 getI8Imm(ShlVal)); 1978 break; 1979 } 1980 case X86ISD::UMUL: { 1981 SDValue N0 = Node->getOperand(0); 1982 SDValue N1 = Node->getOperand(1); 1983 1984 unsigned LoReg; 1985 switch (NVT.getSimpleVT().SimpleTy) { 1986 default: llvm_unreachable("Unsupported VT!"); 1987 case MVT::i8: LoReg = X86::AL; Opc = X86::MUL8r; break; 1988 case MVT::i16: LoReg = X86::AX; Opc = X86::MUL16r; break; 1989 case MVT::i32: LoReg = X86::EAX; Opc = X86::MUL32r; break; 1990 case MVT::i64: LoReg = X86::RAX; Opc = X86::MUL64r; break; 1991 } 1992 1993 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, LoReg, 1994 N0, SDValue()).getValue(1); 1995 1996 SDVTList VTs = CurDAG->getVTList(NVT, NVT, MVT::i32); 1997 SDValue Ops[] = {N1, InFlag}; 1998 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops, 2); 1999 2000 ReplaceUses(SDValue(Node, 0), SDValue(CNode, 0)); 2001 ReplaceUses(SDValue(Node, 1), SDValue(CNode, 1)); 2002 ReplaceUses(SDValue(Node, 2), SDValue(CNode, 2)); 2003 return NULL; 2004 } 2005 2006 case ISD::SMUL_LOHI: 2007 case ISD::UMUL_LOHI: { 2008 SDValue N0 = Node->getOperand(0); 2009 SDValue N1 = Node->getOperand(1); 2010 2011 bool isSigned = Opcode == ISD::SMUL_LOHI; 2012 if (!isSigned) { 2013 switch (NVT.getSimpleVT().SimpleTy) { 2014 default: llvm_unreachable("Unsupported VT!"); 2015 case MVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break; 2016 case MVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break; 2017 case MVT::i32: Opc = X86::MUL32r; MOpc = X86::MUL32m; break; 2018 case MVT::i64: Opc = X86::MUL64r; MOpc = X86::MUL64m; break; 2019 } 2020 } else { 2021 switch (NVT.getSimpleVT().SimpleTy) { 2022 default: llvm_unreachable("Unsupported VT!"); 2023 case MVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break; 2024 case MVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break; 2025 case MVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break; 2026 case MVT::i64: Opc = X86::IMUL64r; MOpc = X86::IMUL64m; break; 2027 } 2028 } 2029 2030 unsigned LoReg, HiReg; 2031 switch (NVT.getSimpleVT().SimpleTy) { 2032 default: llvm_unreachable("Unsupported VT!"); 2033 case MVT::i8: LoReg = X86::AL; HiReg = X86::AH; break; 2034 case MVT::i16: LoReg = X86::AX; HiReg = X86::DX; break; 2035 case MVT::i32: LoReg = X86::EAX; HiReg = X86::EDX; break; 2036 case MVT::i64: LoReg = X86::RAX; HiReg = X86::RDX; break; 2037 } 2038 2039 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; 2040 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4); 2041 // Multiply is commmutative. 2042 if (!foldedLoad) { 2043 foldedLoad = TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4); 2044 if (foldedLoad) 2045 std::swap(N0, N1); 2046 } 2047 2048 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, LoReg, 2049 N0, SDValue()).getValue(1); 2050 2051 if (foldedLoad) { 2052 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0), 2053 InFlag }; 2054 SDNode *CNode = 2055 CurDAG->getMachineNode(MOpc, dl, MVT::Other, MVT::Glue, Ops, 2056 array_lengthof(Ops)); 2057 InFlag = SDValue(CNode, 1); 2058 2059 // Update the chain. 2060 ReplaceUses(N1.getValue(1), SDValue(CNode, 0)); 2061 } else { 2062 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, MVT::Glue, N1, InFlag); 2063 InFlag = SDValue(CNode, 0); 2064 } 2065 2066 // Prevent use of AH in a REX instruction by referencing AX instead. 2067 if (HiReg == X86::AH && Subtarget->is64Bit() && 2068 !SDValue(Node, 1).use_empty()) { 2069 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, 2070 X86::AX, MVT::i16, InFlag); 2071 InFlag = Result.getValue(2); 2072 // Get the low part if needed. Don't use getCopyFromReg for aliasing 2073 // registers. 2074 if (!SDValue(Node, 0).use_empty()) 2075 ReplaceUses(SDValue(Node, 1), 2076 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result)); 2077 2078 // Shift AX down 8 bits. 2079 Result = SDValue(CurDAG->getMachineNode(X86::SHR16ri, dl, MVT::i16, 2080 Result, 2081 CurDAG->getTargetConstant(8, MVT::i8)), 0); 2082 // Then truncate it down to i8. 2083 ReplaceUses(SDValue(Node, 1), 2084 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result)); 2085 } 2086 // Copy the low half of the result, if it is needed. 2087 if (!SDValue(Node, 0).use_empty()) { 2088 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, 2089 LoReg, NVT, InFlag); 2090 InFlag = Result.getValue(2); 2091 ReplaceUses(SDValue(Node, 0), Result); 2092 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n'); 2093 } 2094 // Copy the high half of the result, if it is needed. 2095 if (!SDValue(Node, 1).use_empty()) { 2096 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, 2097 HiReg, NVT, InFlag); 2098 InFlag = Result.getValue(2); 2099 ReplaceUses(SDValue(Node, 1), Result); 2100 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n'); 2101 } 2102 2103 return NULL; 2104 } 2105 2106 case ISD::SDIVREM: 2107 case ISD::UDIVREM: { 2108 SDValue N0 = Node->getOperand(0); 2109 SDValue N1 = Node->getOperand(1); 2110 2111 bool isSigned = Opcode == ISD::SDIVREM; 2112 if (!isSigned) { 2113 switch (NVT.getSimpleVT().SimpleTy) { 2114 default: llvm_unreachable("Unsupported VT!"); 2115 case MVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break; 2116 case MVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break; 2117 case MVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break; 2118 case MVT::i64: Opc = X86::DIV64r; MOpc = X86::DIV64m; break; 2119 } 2120 } else { 2121 switch (NVT.getSimpleVT().SimpleTy) { 2122 default: llvm_unreachable("Unsupported VT!"); 2123 case MVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break; 2124 case MVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break; 2125 case MVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break; 2126 case MVT::i64: Opc = X86::IDIV64r; MOpc = X86::IDIV64m; break; 2127 } 2128 } 2129 2130 unsigned LoReg, HiReg, ClrReg; 2131 unsigned ClrOpcode, SExtOpcode; 2132 switch (NVT.getSimpleVT().SimpleTy) { 2133 default: llvm_unreachable("Unsupported VT!"); 2134 case MVT::i8: 2135 LoReg = X86::AL; ClrReg = HiReg = X86::AH; 2136 ClrOpcode = 0; 2137 SExtOpcode = X86::CBW; 2138 break; 2139 case MVT::i16: 2140 LoReg = X86::AX; HiReg = X86::DX; 2141 ClrOpcode = X86::MOV16r0; ClrReg = X86::DX; 2142 SExtOpcode = X86::CWD; 2143 break; 2144 case MVT::i32: 2145 LoReg = X86::EAX; ClrReg = HiReg = X86::EDX; 2146 ClrOpcode = X86::MOV32r0; 2147 SExtOpcode = X86::CDQ; 2148 break; 2149 case MVT::i64: 2150 LoReg = X86::RAX; ClrReg = HiReg = X86::RDX; 2151 ClrOpcode = X86::MOV64r0; 2152 SExtOpcode = X86::CQO; 2153 break; 2154 } 2155 2156 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; 2157 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4); 2158 bool signBitIsZero = CurDAG->SignBitIsZero(N0); 2159 2160 SDValue InFlag; 2161 if (NVT == MVT::i8 && (!isSigned || signBitIsZero)) { 2162 // Special case for div8, just use a move with zero extension to AX to 2163 // clear the upper 8 bits (AH). 2164 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Move, Chain; 2165 if (TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) { 2166 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N0.getOperand(0) }; 2167 Move = 2168 SDValue(CurDAG->getMachineNode(X86::MOVZX32rm8, dl, MVT::i32, 2169 MVT::Other, Ops, 2170 array_lengthof(Ops)), 0); 2171 Chain = Move.getValue(1); 2172 ReplaceUses(N0.getValue(1), Chain); 2173 } else { 2174 Move = 2175 SDValue(CurDAG->getMachineNode(X86::MOVZX32rr8, dl, MVT::i32, N0),0); 2176 Chain = CurDAG->getEntryNode(); 2177 } 2178 Chain = CurDAG->getCopyToReg(Chain, dl, X86::EAX, Move, SDValue()); 2179 InFlag = Chain.getValue(1); 2180 } else { 2181 InFlag = 2182 CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, 2183 LoReg, N0, SDValue()).getValue(1); 2184 if (isSigned && !signBitIsZero) { 2185 // Sign extend the low part into the high part. 2186 InFlag = 2187 SDValue(CurDAG->getMachineNode(SExtOpcode, dl, MVT::Glue, InFlag),0); 2188 } else { 2189 // Zero out the high part, effectively zero extending the input. 2190 SDValue ClrNode = 2191 SDValue(CurDAG->getMachineNode(ClrOpcode, dl, NVT), 0); 2192 InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, ClrReg, 2193 ClrNode, InFlag).getValue(1); 2194 } 2195 } 2196 2197 if (foldedLoad) { 2198 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0), 2199 InFlag }; 2200 SDNode *CNode = 2201 CurDAG->getMachineNode(MOpc, dl, MVT::Other, MVT::Glue, Ops, 2202 array_lengthof(Ops)); 2203 InFlag = SDValue(CNode, 1); 2204 // Update the chain. 2205 ReplaceUses(N1.getValue(1), SDValue(CNode, 0)); 2206 } else { 2207 InFlag = 2208 SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Glue, N1, InFlag), 0); 2209 } 2210 2211 // Prevent use of AH in a REX instruction by referencing AX instead. 2212 // Shift it down 8 bits. 2213 if (HiReg == X86::AH && Subtarget->is64Bit() && 2214 !SDValue(Node, 1).use_empty()) { 2215 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, 2216 X86::AX, MVT::i16, InFlag); 2217 InFlag = Result.getValue(2); 2218 2219 // If we also need AL (the quotient), get it by extracting a subreg from 2220 // Result. The fast register allocator does not like multiple CopyFromReg 2221 // nodes using aliasing registers. 2222 if (!SDValue(Node, 0).use_empty()) 2223 ReplaceUses(SDValue(Node, 0), 2224 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result)); 2225 2226 // Shift AX right by 8 bits instead of using AH. 2227 Result = SDValue(CurDAG->getMachineNode(X86::SHR16ri, dl, MVT::i16, 2228 Result, 2229 CurDAG->getTargetConstant(8, MVT::i8)), 2230 0); 2231 ReplaceUses(SDValue(Node, 1), 2232 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result)); 2233 } 2234 // Copy the division (low) result, if it is needed. 2235 if (!SDValue(Node, 0).use_empty()) { 2236 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, 2237 LoReg, NVT, InFlag); 2238 InFlag = Result.getValue(2); 2239 ReplaceUses(SDValue(Node, 0), Result); 2240 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n'); 2241 } 2242 // Copy the remainder (high) result, if it is needed. 2243 if (!SDValue(Node, 1).use_empty()) { 2244 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, 2245 HiReg, NVT, InFlag); 2246 InFlag = Result.getValue(2); 2247 ReplaceUses(SDValue(Node, 1), Result); 2248 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n'); 2249 } 2250 return NULL; 2251 } 2252 2253 case X86ISD::CMP: { 2254 SDValue N0 = Node->getOperand(0); 2255 SDValue N1 = Node->getOperand(1); 2256 2257 // Look for (X86cmp (and $op, $imm), 0) and see if we can convert it to 2258 // use a smaller encoding. 2259 if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() && 2260 HasNoSignedComparisonUses(Node)) 2261 // Look past the truncate if CMP is the only use of it. 2262 N0 = N0.getOperand(0); 2263 if ((N0.getNode()->getOpcode() == ISD::AND || 2264 (N0.getResNo() == 0 && N0.getNode()->getOpcode() == X86ISD::AND)) && 2265 N0.getNode()->hasOneUse() && 2266 N0.getValueType() != MVT::i8 && 2267 X86::isZeroNode(N1)) { 2268 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getNode()->getOperand(1)); 2269 if (!C) break; 2270 2271 // For example, convert "testl %eax, $8" to "testb %al, $8" 2272 if ((C->getZExtValue() & ~UINT64_C(0xff)) == 0 && 2273 (!(C->getZExtValue() & 0x80) || 2274 HasNoSignedComparisonUses(Node))) { 2275 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i8); 2276 SDValue Reg = N0.getNode()->getOperand(0); 2277 2278 // On x86-32, only the ABCD registers have 8-bit subregisters. 2279 if (!Subtarget->is64Bit()) { 2280 TargetRegisterClass *TRC = 0; 2281 switch (N0.getValueType().getSimpleVT().SimpleTy) { 2282 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break; 2283 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break; 2284 default: llvm_unreachable("Unsupported TEST operand type!"); 2285 } 2286 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32); 2287 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl, 2288 Reg.getValueType(), Reg, RC), 0); 2289 } 2290 2291 // Extract the l-register. 2292 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, 2293 MVT::i8, Reg); 2294 2295 // Emit a testb. 2296 return CurDAG->getMachineNode(X86::TEST8ri, dl, MVT::i32, Subreg, Imm); 2297 } 2298 2299 // For example, "testl %eax, $2048" to "testb %ah, $8". 2300 if ((C->getZExtValue() & ~UINT64_C(0xff00)) == 0 && 2301 (!(C->getZExtValue() & 0x8000) || 2302 HasNoSignedComparisonUses(Node))) { 2303 // Shift the immediate right by 8 bits. 2304 SDValue ShiftedImm = CurDAG->getTargetConstant(C->getZExtValue() >> 8, 2305 MVT::i8); 2306 SDValue Reg = N0.getNode()->getOperand(0); 2307 2308 // Put the value in an ABCD register. 2309 TargetRegisterClass *TRC = 0; 2310 switch (N0.getValueType().getSimpleVT().SimpleTy) { 2311 case MVT::i64: TRC = &X86::GR64_ABCDRegClass; break; 2312 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break; 2313 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break; 2314 default: llvm_unreachable("Unsupported TEST operand type!"); 2315 } 2316 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32); 2317 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl, 2318 Reg.getValueType(), Reg, RC), 0); 2319 2320 // Extract the h-register. 2321 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit_hi, dl, 2322 MVT::i8, Reg); 2323 2324 // Emit a testb. The EXTRACT_SUBREG becomes a COPY that can only 2325 // target GR8_NOREX registers, so make sure the register class is 2326 // forced. 2327 return CurDAG->getMachineNode(X86::TEST8ri_NOREX, dl, MVT::i32, 2328 Subreg, ShiftedImm); 2329 } 2330 2331 // For example, "testl %eax, $32776" to "testw %ax, $32776". 2332 if ((C->getZExtValue() & ~UINT64_C(0xffff)) == 0 && 2333 N0.getValueType() != MVT::i16 && 2334 (!(C->getZExtValue() & 0x8000) || 2335 HasNoSignedComparisonUses(Node))) { 2336 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i16); 2337 SDValue Reg = N0.getNode()->getOperand(0); 2338 2339 // Extract the 16-bit subregister. 2340 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_16bit, dl, 2341 MVT::i16, Reg); 2342 2343 // Emit a testw. 2344 return CurDAG->getMachineNode(X86::TEST16ri, dl, MVT::i32, Subreg, Imm); 2345 } 2346 2347 // For example, "testq %rax, $268468232" to "testl %eax, $268468232". 2348 if ((C->getZExtValue() & ~UINT64_C(0xffffffff)) == 0 && 2349 N0.getValueType() == MVT::i64 && 2350 (!(C->getZExtValue() & 0x80000000) || 2351 HasNoSignedComparisonUses(Node))) { 2352 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32); 2353 SDValue Reg = N0.getNode()->getOperand(0); 2354 2355 // Extract the 32-bit subregister. 2356 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_32bit, dl, 2357 MVT::i32, Reg); 2358 2359 // Emit a testl. 2360 return CurDAG->getMachineNode(X86::TEST32ri, dl, MVT::i32, Subreg, Imm); 2361 } 2362 } 2363 break; 2364 } 2365 case ISD::STORE: { 2366 // The DEC64m tablegen pattern is currently not able to match the case where 2367 // the EFLAGS on the original DEC are used. 2368 // we'll need to improve tablegen to allow flags to be transferred from a 2369 // node in the pattern to the result node. probably with a new keyword 2370 // for example, we have this 2371 // def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst", 2372 // [(store (add (loadi64 addr:$dst), -1), addr:$dst), 2373 // (implicit EFLAGS)]>; 2374 // but maybe need something like this 2375 // def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst", 2376 // [(store (add (loadi64 addr:$dst), -1), addr:$dst), 2377 // (transferrable EFLAGS)]>; 2378 StoreSDNode *StoreNode = cast<StoreSDNode>(Node); 2379 SDValue Chain = StoreNode->getOperand(0); 2380 SDValue StoredVal = StoreNode->getOperand(1); 2381 SDValue Address = StoreNode->getOperand(2); 2382 SDValue Undef = StoreNode->getOperand(3); 2383 2384 if (StoreNode->getMemOperand()->getSize() != 8 || 2385 Undef->getOpcode() != ISD::UNDEF || 2386 Chain->getOpcode() != ISD::LOAD || 2387 StoredVal->getOpcode() != X86ISD::DEC || 2388 StoredVal.getResNo() != 0 || 2389 StoredVal->getOperand(0).getNode() != Chain.getNode()) 2390 break; 2391 2392 //OPC_CheckPredicate, 1, // Predicate_nontemporalstore 2393 if (StoreNode->isNonTemporal()) 2394 break; 2395 2396 LoadSDNode *LoadNode = cast<LoadSDNode>(Chain.getNode()); 2397 if (LoadNode->getOperand(1) != Address || 2398 LoadNode->getOperand(2) != Undef) 2399 break; 2400 2401 if (!ISD::isNormalLoad(LoadNode)) 2402 break; 2403 2404 if (!ISD::isNormalStore(StoreNode)) 2405 break; 2406 2407 // check load chain has only one use (from the store) 2408 if (!Chain.hasOneUse()) 2409 break; 2410 2411 // Merge the input chains if they are not intra-pattern references. 2412 SDValue InputChain = LoadNode->getOperand(0); 2413 2414 SDValue Base, Scale, Index, Disp, Segment; 2415 if (!SelectAddr(LoadNode, LoadNode->getBasePtr(), 2416 Base, Scale, Index, Disp, Segment)) 2417 break; 2418 2419 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(2); 2420 MemOp[0] = StoreNode->getMemOperand(); 2421 MemOp[1] = LoadNode->getMemOperand(); 2422 const SDValue Ops[] = { Base, Scale, Index, Disp, Segment, InputChain }; 2423 MachineSDNode *Result = CurDAG->getMachineNode(X86::DEC64m, 2424 Node->getDebugLoc(), 2425 MVT::i32, MVT::Other, Ops, 2426 array_lengthof(Ops)); 2427 Result->setMemRefs(MemOp, MemOp + 2); 2428 2429 ReplaceUses(SDValue(StoreNode, 0), SDValue(Result, 1)); 2430 ReplaceUses(SDValue(StoredVal.getNode(), 1), SDValue(Result, 0)); 2431 2432 return Result; 2433 } 2434 } 2435 2436 SDNode *ResNode = SelectCode(Node); 2437 2438 DEBUG(dbgs() << "=> "; 2439 if (ResNode == NULL || ResNode == Node) 2440 Node->dump(CurDAG); 2441 else 2442 ResNode->dump(CurDAG); 2443 dbgs() << '\n'); 2444 2445 return ResNode; 2446} 2447 2448bool X86DAGToDAGISel:: 2449SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode, 2450 std::vector<SDValue> &OutOps) { 2451 SDValue Op0, Op1, Op2, Op3, Op4; 2452 switch (ConstraintCode) { 2453 case 'o': // offsetable ?? 2454 case 'v': // not offsetable ?? 2455 default: return true; 2456 case 'm': // memory 2457 if (!SelectAddr(0, Op, Op0, Op1, Op2, Op3, Op4)) 2458 return true; 2459 break; 2460 } 2461 2462 OutOps.push_back(Op0); 2463 OutOps.push_back(Op1); 2464 OutOps.push_back(Op2); 2465 OutOps.push_back(Op3); 2466 OutOps.push_back(Op4); 2467 return false; 2468} 2469 2470/// createX86ISelDag - This pass converts a legalized DAG into a 2471/// X86-specific DAG, ready for instruction scheduling. 2472/// 2473FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM, 2474 llvm::CodeGenOpt::Level OptLevel) { 2475 return new X86DAGToDAGISel(TM, OptLevel); 2476} 2477