AsmWriterEmitter.cpp revision dce4a407a24b04eebc6a376f8e62b41aaa7b071f
1//===- AsmWriterEmitter.cpp - Generate an assembly writer -----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This tablegen backend is emits an assembly printer for the current target. 11// Note that this is currently fairly skeletal, but will grow over time. 12// 13//===----------------------------------------------------------------------===// 14 15#include "AsmWriterInst.h" 16#include "CodeGenTarget.h" 17#include "SequenceToOffsetTable.h" 18#include "llvm/ADT/SmallString.h" 19#include "llvm/ADT/StringExtras.h" 20#include "llvm/ADT/Twine.h" 21#include "llvm/Support/Debug.h" 22#include "llvm/Support/Format.h" 23#include "llvm/Support/MathExtras.h" 24#include "llvm/TableGen/Error.h" 25#include "llvm/TableGen/Record.h" 26#include "llvm/TableGen/TableGenBackend.h" 27#include <algorithm> 28#include <cassert> 29#include <map> 30#include <vector> 31using namespace llvm; 32 33#define DEBUG_TYPE "asm-writer-emitter" 34 35namespace { 36class AsmWriterEmitter { 37 RecordKeeper &Records; 38 CodeGenTarget Target; 39 std::map<const CodeGenInstruction*, AsmWriterInst*> CGIAWIMap; 40 const std::vector<const CodeGenInstruction*> *NumberedInstructions; 41 std::vector<AsmWriterInst> Instructions; 42 std::vector<std::string> PrintMethods; 43public: 44 AsmWriterEmitter(RecordKeeper &R); 45 46 void run(raw_ostream &o); 47 48private: 49 void EmitPrintInstruction(raw_ostream &o); 50 void EmitGetRegisterName(raw_ostream &o); 51 void EmitPrintAliasInstruction(raw_ostream &O); 52 53 AsmWriterInst *getAsmWriterInstByID(unsigned ID) const { 54 assert(ID < NumberedInstructions->size()); 55 std::map<const CodeGenInstruction*, AsmWriterInst*>::const_iterator I = 56 CGIAWIMap.find(NumberedInstructions->at(ID)); 57 assert(I != CGIAWIMap.end() && "Didn't find inst!"); 58 return I->second; 59 } 60 void FindUniqueOperandCommands(std::vector<std::string> &UOC, 61 std::vector<unsigned> &InstIdxs, 62 std::vector<unsigned> &InstOpsUsed) const; 63}; 64} // end anonymous namespace 65 66static void PrintCases(std::vector<std::pair<std::string, 67 AsmWriterOperand> > &OpsToPrint, raw_ostream &O) { 68 O << " case " << OpsToPrint.back().first << ": "; 69 AsmWriterOperand TheOp = OpsToPrint.back().second; 70 OpsToPrint.pop_back(); 71 72 // Check to see if any other operands are identical in this list, and if so, 73 // emit a case label for them. 74 for (unsigned i = OpsToPrint.size(); i != 0; --i) 75 if (OpsToPrint[i-1].second == TheOp) { 76 O << "\n case " << OpsToPrint[i-1].first << ": "; 77 OpsToPrint.erase(OpsToPrint.begin()+i-1); 78 } 79 80 // Finally, emit the code. 81 O << TheOp.getCode(); 82 O << "break;\n"; 83} 84 85 86/// EmitInstructions - Emit the last instruction in the vector and any other 87/// instructions that are suitably similar to it. 88static void EmitInstructions(std::vector<AsmWriterInst> &Insts, 89 raw_ostream &O) { 90 AsmWriterInst FirstInst = Insts.back(); 91 Insts.pop_back(); 92 93 std::vector<AsmWriterInst> SimilarInsts; 94 unsigned DifferingOperand = ~0; 95 for (unsigned i = Insts.size(); i != 0; --i) { 96 unsigned DiffOp = Insts[i-1].MatchesAllButOneOp(FirstInst); 97 if (DiffOp != ~1U) { 98 if (DifferingOperand == ~0U) // First match! 99 DifferingOperand = DiffOp; 100 101 // If this differs in the same operand as the rest of the instructions in 102 // this class, move it to the SimilarInsts list. 103 if (DifferingOperand == DiffOp || DiffOp == ~0U) { 104 SimilarInsts.push_back(Insts[i-1]); 105 Insts.erase(Insts.begin()+i-1); 106 } 107 } 108 } 109 110 O << " case " << FirstInst.CGI->Namespace << "::" 111 << FirstInst.CGI->TheDef->getName() << ":\n"; 112 for (unsigned i = 0, e = SimilarInsts.size(); i != e; ++i) 113 O << " case " << SimilarInsts[i].CGI->Namespace << "::" 114 << SimilarInsts[i].CGI->TheDef->getName() << ":\n"; 115 for (unsigned i = 0, e = FirstInst.Operands.size(); i != e; ++i) { 116 if (i != DifferingOperand) { 117 // If the operand is the same for all instructions, just print it. 118 O << " " << FirstInst.Operands[i].getCode(); 119 } else { 120 // If this is the operand that varies between all of the instructions, 121 // emit a switch for just this operand now. 122 O << " switch (MI->getOpcode()) {\n"; 123 std::vector<std::pair<std::string, AsmWriterOperand> > OpsToPrint; 124 OpsToPrint.push_back(std::make_pair(FirstInst.CGI->Namespace + "::" + 125 FirstInst.CGI->TheDef->getName(), 126 FirstInst.Operands[i])); 127 128 for (unsigned si = 0, e = SimilarInsts.size(); si != e; ++si) { 129 AsmWriterInst &AWI = SimilarInsts[si]; 130 OpsToPrint.push_back(std::make_pair(AWI.CGI->Namespace+"::"+ 131 AWI.CGI->TheDef->getName(), 132 AWI.Operands[i])); 133 } 134 std::reverse(OpsToPrint.begin(), OpsToPrint.end()); 135 while (!OpsToPrint.empty()) 136 PrintCases(OpsToPrint, O); 137 O << " }"; 138 } 139 O << "\n"; 140 } 141 O << " break;\n"; 142} 143 144void AsmWriterEmitter:: 145FindUniqueOperandCommands(std::vector<std::string> &UniqueOperandCommands, 146 std::vector<unsigned> &InstIdxs, 147 std::vector<unsigned> &InstOpsUsed) const { 148 InstIdxs.assign(NumberedInstructions->size(), ~0U); 149 150 // This vector parallels UniqueOperandCommands, keeping track of which 151 // instructions each case are used for. It is a comma separated string of 152 // enums. 153 std::vector<std::string> InstrsForCase; 154 InstrsForCase.resize(UniqueOperandCommands.size()); 155 InstOpsUsed.assign(UniqueOperandCommands.size(), 0); 156 157 for (unsigned i = 0, e = NumberedInstructions->size(); i != e; ++i) { 158 const AsmWriterInst *Inst = getAsmWriterInstByID(i); 159 if (!Inst) 160 continue; // PHI, INLINEASM, CFI_INSTRUCTION, etc. 161 162 std::string Command; 163 if (Inst->Operands.empty()) 164 continue; // Instruction already done. 165 166 Command = " " + Inst->Operands[0].getCode() + "\n"; 167 168 // Check to see if we already have 'Command' in UniqueOperandCommands. 169 // If not, add it. 170 bool FoundIt = false; 171 for (unsigned idx = 0, e = UniqueOperandCommands.size(); idx != e; ++idx) 172 if (UniqueOperandCommands[idx] == Command) { 173 InstIdxs[i] = idx; 174 InstrsForCase[idx] += ", "; 175 InstrsForCase[idx] += Inst->CGI->TheDef->getName(); 176 FoundIt = true; 177 break; 178 } 179 if (!FoundIt) { 180 InstIdxs[i] = UniqueOperandCommands.size(); 181 UniqueOperandCommands.push_back(Command); 182 InstrsForCase.push_back(Inst->CGI->TheDef->getName()); 183 184 // This command matches one operand so far. 185 InstOpsUsed.push_back(1); 186 } 187 } 188 189 // For each entry of UniqueOperandCommands, there is a set of instructions 190 // that uses it. If the next command of all instructions in the set are 191 // identical, fold it into the command. 192 for (unsigned CommandIdx = 0, e = UniqueOperandCommands.size(); 193 CommandIdx != e; ++CommandIdx) { 194 195 for (unsigned Op = 1; ; ++Op) { 196 // Scan for the first instruction in the set. 197 std::vector<unsigned>::iterator NIT = 198 std::find(InstIdxs.begin(), InstIdxs.end(), CommandIdx); 199 if (NIT == InstIdxs.end()) break; // No commonality. 200 201 // If this instruction has no more operands, we isn't anything to merge 202 // into this command. 203 const AsmWriterInst *FirstInst = 204 getAsmWriterInstByID(NIT-InstIdxs.begin()); 205 if (!FirstInst || FirstInst->Operands.size() == Op) 206 break; 207 208 // Otherwise, scan to see if all of the other instructions in this command 209 // set share the operand. 210 bool AllSame = true; 211 // Keep track of the maximum, number of operands or any 212 // instruction we see in the group. 213 size_t MaxSize = FirstInst->Operands.size(); 214 215 for (NIT = std::find(NIT+1, InstIdxs.end(), CommandIdx); 216 NIT != InstIdxs.end(); 217 NIT = std::find(NIT+1, InstIdxs.end(), CommandIdx)) { 218 // Okay, found another instruction in this command set. If the operand 219 // matches, we're ok, otherwise bail out. 220 const AsmWriterInst *OtherInst = 221 getAsmWriterInstByID(NIT-InstIdxs.begin()); 222 223 if (OtherInst && 224 OtherInst->Operands.size() > FirstInst->Operands.size()) 225 MaxSize = std::max(MaxSize, OtherInst->Operands.size()); 226 227 if (!OtherInst || OtherInst->Operands.size() == Op || 228 OtherInst->Operands[Op] != FirstInst->Operands[Op]) { 229 AllSame = false; 230 break; 231 } 232 } 233 if (!AllSame) break; 234 235 // Okay, everything in this command set has the same next operand. Add it 236 // to UniqueOperandCommands and remember that it was consumed. 237 std::string Command = " " + FirstInst->Operands[Op].getCode() + "\n"; 238 239 UniqueOperandCommands[CommandIdx] += Command; 240 InstOpsUsed[CommandIdx]++; 241 } 242 } 243 244 // Prepend some of the instructions each case is used for onto the case val. 245 for (unsigned i = 0, e = InstrsForCase.size(); i != e; ++i) { 246 std::string Instrs = InstrsForCase[i]; 247 if (Instrs.size() > 70) { 248 Instrs.erase(Instrs.begin()+70, Instrs.end()); 249 Instrs += "..."; 250 } 251 252 if (!Instrs.empty()) 253 UniqueOperandCommands[i] = " // " + Instrs + "\n" + 254 UniqueOperandCommands[i]; 255 } 256} 257 258 259static void UnescapeString(std::string &Str) { 260 for (unsigned i = 0; i != Str.size(); ++i) { 261 if (Str[i] == '\\' && i != Str.size()-1) { 262 switch (Str[i+1]) { 263 default: continue; // Don't execute the code after the switch. 264 case 'a': Str[i] = '\a'; break; 265 case 'b': Str[i] = '\b'; break; 266 case 'e': Str[i] = 27; break; 267 case 'f': Str[i] = '\f'; break; 268 case 'n': Str[i] = '\n'; break; 269 case 'r': Str[i] = '\r'; break; 270 case 't': Str[i] = '\t'; break; 271 case 'v': Str[i] = '\v'; break; 272 case '"': Str[i] = '\"'; break; 273 case '\'': Str[i] = '\''; break; 274 case '\\': Str[i] = '\\'; break; 275 } 276 // Nuke the second character. 277 Str.erase(Str.begin()+i+1); 278 } 279 } 280} 281 282/// EmitPrintInstruction - Generate the code for the "printInstruction" method 283/// implementation. Destroys all instances of AsmWriterInst information, by 284/// clearing the Instructions vector. 285void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) { 286 Record *AsmWriter = Target.getAsmWriter(); 287 std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName"); 288 289 O << 290 "/// printInstruction - This method is automatically generated by tablegen\n" 291 "/// from the instruction set description.\n" 292 "void " << Target.getName() << ClassName 293 << "::printInstruction(const MCInst *MI, raw_ostream &O) {\n"; 294 295 // Build an aggregate string, and build a table of offsets into it. 296 SequenceToOffsetTable<std::string> StringTable; 297 298 /// OpcodeInfo - This encodes the index of the string to use for the first 299 /// chunk of the output as well as indices used for operand printing. 300 /// To reduce the number of unhandled cases, we expand the size from 32-bit 301 /// to 32+16 = 48-bit. 302 std::vector<uint64_t> OpcodeInfo; 303 304 // Add all strings to the string table upfront so it can generate an optimized 305 // representation. 306 for (unsigned i = 0, e = NumberedInstructions->size(); i != e; ++i) { 307 AsmWriterInst *AWI = CGIAWIMap[NumberedInstructions->at(i)]; 308 if (AWI && 309 AWI->Operands[0].OperandType == 310 AsmWriterOperand::isLiteralTextOperand && 311 !AWI->Operands[0].Str.empty()) { 312 std::string Str = AWI->Operands[0].Str; 313 UnescapeString(Str); 314 StringTable.add(Str); 315 } 316 } 317 318 StringTable.layout(); 319 320 unsigned MaxStringIdx = 0; 321 for (unsigned i = 0, e = NumberedInstructions->size(); i != e; ++i) { 322 AsmWriterInst *AWI = CGIAWIMap[NumberedInstructions->at(i)]; 323 unsigned Idx; 324 if (!AWI) { 325 // Something not handled by the asmwriter printer. 326 Idx = ~0U; 327 } else if (AWI->Operands[0].OperandType != 328 AsmWriterOperand::isLiteralTextOperand || 329 AWI->Operands[0].Str.empty()) { 330 // Something handled by the asmwriter printer, but with no leading string. 331 Idx = StringTable.get(""); 332 } else { 333 std::string Str = AWI->Operands[0].Str; 334 UnescapeString(Str); 335 Idx = StringTable.get(Str); 336 MaxStringIdx = std::max(MaxStringIdx, Idx); 337 338 // Nuke the string from the operand list. It is now handled! 339 AWI->Operands.erase(AWI->Operands.begin()); 340 } 341 342 // Bias offset by one since we want 0 as a sentinel. 343 OpcodeInfo.push_back(Idx+1); 344 } 345 346 // Figure out how many bits we used for the string index. 347 unsigned AsmStrBits = Log2_32_Ceil(MaxStringIdx+2); 348 349 // To reduce code size, we compactify common instructions into a few bits 350 // in the opcode-indexed table. 351 unsigned BitsLeft = 64-AsmStrBits; 352 353 std::vector<std::vector<std::string> > TableDrivenOperandPrinters; 354 355 while (1) { 356 std::vector<std::string> UniqueOperandCommands; 357 std::vector<unsigned> InstIdxs; 358 std::vector<unsigned> NumInstOpsHandled; 359 FindUniqueOperandCommands(UniqueOperandCommands, InstIdxs, 360 NumInstOpsHandled); 361 362 // If we ran out of operands to print, we're done. 363 if (UniqueOperandCommands.empty()) break; 364 365 // Compute the number of bits we need to represent these cases, this is 366 // ceil(log2(numentries)). 367 unsigned NumBits = Log2_32_Ceil(UniqueOperandCommands.size()); 368 369 // If we don't have enough bits for this operand, don't include it. 370 if (NumBits > BitsLeft) { 371 DEBUG(errs() << "Not enough bits to densely encode " << NumBits 372 << " more bits\n"); 373 break; 374 } 375 376 // Otherwise, we can include this in the initial lookup table. Add it in. 377 for (unsigned i = 0, e = InstIdxs.size(); i != e; ++i) 378 if (InstIdxs[i] != ~0U) { 379 OpcodeInfo[i] |= (uint64_t)InstIdxs[i] << (64-BitsLeft); 380 } 381 BitsLeft -= NumBits; 382 383 // Remove the info about this operand. 384 for (unsigned i = 0, e = NumberedInstructions->size(); i != e; ++i) { 385 if (AsmWriterInst *Inst = getAsmWriterInstByID(i)) 386 if (!Inst->Operands.empty()) { 387 unsigned NumOps = NumInstOpsHandled[InstIdxs[i]]; 388 assert(NumOps <= Inst->Operands.size() && 389 "Can't remove this many ops!"); 390 Inst->Operands.erase(Inst->Operands.begin(), 391 Inst->Operands.begin()+NumOps); 392 } 393 } 394 395 // Remember the handlers for this set of operands. 396 TableDrivenOperandPrinters.push_back(UniqueOperandCommands); 397 } 398 399 400 // We always emit at least one 32-bit table. A second table is emitted if 401 // more bits are needed. 402 O<<" static const uint32_t OpInfo[] = {\n"; 403 for (unsigned i = 0, e = NumberedInstructions->size(); i != e; ++i) { 404 O << " " << (OpcodeInfo[i] & 0xffffffff) << "U,\t// " 405 << NumberedInstructions->at(i)->TheDef->getName() << "\n"; 406 } 407 // Add a dummy entry so the array init doesn't end with a comma. 408 O << " 0U\n"; 409 O << " };\n\n"; 410 411 if (BitsLeft < 32) { 412 // Add a second OpInfo table only when it is necessary. 413 // Adjust the type of the second table based on the number of bits needed. 414 O << " static const uint" 415 << ((BitsLeft < 16) ? "32" : (BitsLeft < 24) ? "16" : "8") 416 << "_t OpInfo2[] = {\n"; 417 for (unsigned i = 0, e = NumberedInstructions->size(); i != e; ++i) { 418 O << " " << (OpcodeInfo[i] >> 32) << "U,\t// " 419 << NumberedInstructions->at(i)->TheDef->getName() << "\n"; 420 } 421 // Add a dummy entry so the array init doesn't end with a comma. 422 O << " 0U\n"; 423 O << " };\n\n"; 424 } 425 426 // Emit the string itself. 427 O << " const char AsmStrs[] = {\n"; 428 StringTable.emit(O, printChar); 429 O << " };\n\n"; 430 431 O << " O << \"\\t\";\n\n"; 432 433 O << " // Emit the opcode for the instruction.\n"; 434 if (BitsLeft < 32) { 435 // If we have two tables then we need to perform two lookups and combine 436 // the results into a single 64-bit value. 437 O << " uint64_t Bits1 = OpInfo[MI->getOpcode()];\n" 438 << " uint64_t Bits2 = OpInfo2[MI->getOpcode()];\n" 439 << " uint64_t Bits = (Bits2 << 32) | Bits1;\n"; 440 } else { 441 // If only one table is used we just need to perform a single lookup. 442 O << " uint32_t Bits = OpInfo[MI->getOpcode()];\n"; 443 } 444 O << " assert(Bits != 0 && \"Cannot print this instruction.\");\n" 445 << " O << AsmStrs+(Bits & " << (1 << AsmStrBits)-1 << ")-1;\n\n"; 446 447 // Output the table driven operand information. 448 BitsLeft = 64-AsmStrBits; 449 for (unsigned i = 0, e = TableDrivenOperandPrinters.size(); i != e; ++i) { 450 std::vector<std::string> &Commands = TableDrivenOperandPrinters[i]; 451 452 // Compute the number of bits we need to represent these cases, this is 453 // ceil(log2(numentries)). 454 unsigned NumBits = Log2_32_Ceil(Commands.size()); 455 assert(NumBits <= BitsLeft && "consistency error"); 456 457 // Emit code to extract this field from Bits. 458 O << "\n // Fragment " << i << " encoded into " << NumBits 459 << " bits for " << Commands.size() << " unique commands.\n"; 460 461 if (Commands.size() == 2) { 462 // Emit two possibilitys with if/else. 463 O << " if ((Bits >> " 464 << (64-BitsLeft) << ") & " 465 << ((1 << NumBits)-1) << ") {\n" 466 << Commands[1] 467 << " } else {\n" 468 << Commands[0] 469 << " }\n\n"; 470 } else if (Commands.size() == 1) { 471 // Emit a single possibility. 472 O << Commands[0] << "\n\n"; 473 } else { 474 O << " switch ((Bits >> " 475 << (64-BitsLeft) << ") & " 476 << ((1 << NumBits)-1) << ") {\n" 477 << " default: // unreachable.\n"; 478 479 // Print out all the cases. 480 for (unsigned i = 0, e = Commands.size(); i != e; ++i) { 481 O << " case " << i << ":\n"; 482 O << Commands[i]; 483 O << " break;\n"; 484 } 485 O << " }\n\n"; 486 } 487 BitsLeft -= NumBits; 488 } 489 490 // Okay, delete instructions with no operand info left. 491 for (unsigned i = 0, e = Instructions.size(); i != e; ++i) { 492 // Entire instruction has been emitted? 493 AsmWriterInst &Inst = Instructions[i]; 494 if (Inst.Operands.empty()) { 495 Instructions.erase(Instructions.begin()+i); 496 --i; --e; 497 } 498 } 499 500 501 // Because this is a vector, we want to emit from the end. Reverse all of the 502 // elements in the vector. 503 std::reverse(Instructions.begin(), Instructions.end()); 504 505 506 // Now that we've emitted all of the operand info that fit into 32 bits, emit 507 // information for those instructions that are left. This is a less dense 508 // encoding, but we expect the main 32-bit table to handle the majority of 509 // instructions. 510 if (!Instructions.empty()) { 511 // Find the opcode # of inline asm. 512 O << " switch (MI->getOpcode()) {\n"; 513 while (!Instructions.empty()) 514 EmitInstructions(Instructions, O); 515 516 O << " }\n"; 517 O << " return;\n"; 518 } 519 520 O << "}\n"; 521} 522 523static void 524emitRegisterNameString(raw_ostream &O, StringRef AltName, 525 const std::vector<CodeGenRegister*> &Registers) { 526 SequenceToOffsetTable<std::string> StringTable; 527 SmallVector<std::string, 4> AsmNames(Registers.size()); 528 for (unsigned i = 0, e = Registers.size(); i != e; ++i) { 529 const CodeGenRegister &Reg = *Registers[i]; 530 std::string &AsmName = AsmNames[i]; 531 532 // "NoRegAltName" is special. We don't need to do a lookup for that, 533 // as it's just a reference to the default register name. 534 if (AltName == "" || AltName == "NoRegAltName") { 535 AsmName = Reg.TheDef->getValueAsString("AsmName"); 536 if (AsmName.empty()) 537 AsmName = Reg.getName(); 538 } else { 539 // Make sure the register has an alternate name for this index. 540 std::vector<Record*> AltNameList = 541 Reg.TheDef->getValueAsListOfDefs("RegAltNameIndices"); 542 unsigned Idx = 0, e; 543 for (e = AltNameList.size(); 544 Idx < e && (AltNameList[Idx]->getName() != AltName); 545 ++Idx) 546 ; 547 // If the register has an alternate name for this index, use it. 548 // Otherwise, leave it empty as an error flag. 549 if (Idx < e) { 550 std::vector<std::string> AltNames = 551 Reg.TheDef->getValueAsListOfStrings("AltNames"); 552 if (AltNames.size() <= Idx) 553 PrintFatalError(Reg.TheDef->getLoc(), 554 "Register definition missing alt name for '" + 555 AltName + "'."); 556 AsmName = AltNames[Idx]; 557 } 558 } 559 StringTable.add(AsmName); 560 } 561 562 StringTable.layout(); 563 O << " static const char AsmStrs" << AltName << "[] = {\n"; 564 StringTable.emit(O, printChar); 565 O << " };\n\n"; 566 567 O << " static const uint32_t RegAsmOffset" << AltName << "[] = {"; 568 for (unsigned i = 0, e = Registers.size(); i != e; ++i) { 569 if ((i % 14) == 0) 570 O << "\n "; 571 O << StringTable.get(AsmNames[i]) << ", "; 572 } 573 O << "\n };\n" 574 << "\n"; 575} 576 577void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) { 578 Record *AsmWriter = Target.getAsmWriter(); 579 std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName"); 580 const std::vector<CodeGenRegister*> &Registers = 581 Target.getRegBank().getRegisters(); 582 std::vector<Record*> AltNameIndices = Target.getRegAltNameIndices(); 583 bool hasAltNames = AltNameIndices.size() > 1; 584 585 O << 586 "\n\n/// getRegisterName - This method is automatically generated by tblgen\n" 587 "/// from the register set description. This returns the assembler name\n" 588 "/// for the specified register.\n" 589 "const char *" << Target.getName() << ClassName << "::"; 590 if (hasAltNames) 591 O << "\ngetRegisterName(unsigned RegNo, unsigned AltIdx) {\n"; 592 else 593 O << "getRegisterName(unsigned RegNo) {\n"; 594 O << " assert(RegNo && RegNo < " << (Registers.size()+1) 595 << " && \"Invalid register number!\");\n" 596 << "\n"; 597 598 if (hasAltNames) { 599 for (unsigned i = 0, e = AltNameIndices.size(); i < e; ++i) 600 emitRegisterNameString(O, AltNameIndices[i]->getName(), Registers); 601 } else 602 emitRegisterNameString(O, "", Registers); 603 604 if (hasAltNames) { 605 O << " const uint32_t *RegAsmOffset;\n" 606 << " const char *AsmStrs;\n" 607 << " switch(AltIdx) {\n" 608 << " default: llvm_unreachable(\"Invalid register alt name index!\");\n"; 609 for (unsigned i = 0, e = AltNameIndices.size(); i < e; ++i) { 610 std::string Namespace = AltNameIndices[1]->getValueAsString("Namespace"); 611 std::string AltName(AltNameIndices[i]->getName()); 612 O << " case " << Namespace << "::" << AltName 613 << ":\n" 614 << " AsmStrs = AsmStrs" << AltName << ";\n" 615 << " RegAsmOffset = RegAsmOffset" << AltName << ";\n" 616 << " break;\n"; 617 } 618 O << "}\n"; 619 } 620 621 O << " assert (*(AsmStrs+RegAsmOffset[RegNo-1]) &&\n" 622 << " \"Invalid alt name index for register!\");\n" 623 << " return AsmStrs+RegAsmOffset[RegNo-1];\n" 624 << "}\n"; 625} 626 627namespace { 628// IAPrinter - Holds information about an InstAlias. Two InstAliases match if 629// they both have the same conditionals. In which case, we cannot print out the 630// alias for that pattern. 631class IAPrinter { 632 std::vector<std::string> Conds; 633 std::map<StringRef, std::pair<int, int>> OpMap; 634 SmallVector<Record*, 4> ReqFeatures; 635 636 std::string Result; 637 std::string AsmString; 638public: 639 IAPrinter(std::string R, std::string AS) : Result(R), AsmString(AS) {} 640 641 void addCond(const std::string &C) { Conds.push_back(C); } 642 643 void addOperand(StringRef Op, int OpIdx, int PrintMethodIdx = -1) { 644 assert(OpIdx >= 0 && OpIdx < 0xFE && "Idx out of range"); 645 assert(PrintMethodIdx >= -1 && PrintMethodIdx < 0xFF && 646 "Idx out of range"); 647 OpMap[Op] = std::make_pair(OpIdx, PrintMethodIdx); 648 } 649 650 bool isOpMapped(StringRef Op) { return OpMap.find(Op) != OpMap.end(); } 651 int getOpIndex(StringRef Op) { return OpMap[Op].first; } 652 std::pair<int, int> &getOpData(StringRef Op) { return OpMap[Op]; } 653 654 std::pair<StringRef, StringRef::iterator> parseName(StringRef::iterator Start, 655 StringRef::iterator End) { 656 StringRef::iterator I = Start; 657 if (*I == '{') { 658 // ${some_name} 659 Start = ++I; 660 while (I != End && *I != '}') 661 ++I; 662 } else { 663 // $name, just eat the usual suspects. 664 while (I != End && 665 ((*I >= 'a' && *I <= 'z') || (*I >= 'A' && *I <= 'Z') || 666 (*I >= '0' && *I <= '9') || *I == '_')) 667 ++I; 668 } 669 670 return std::make_pair(StringRef(Start, I - Start), I); 671 } 672 673 void print(raw_ostream &O) { 674 if (Conds.empty() && ReqFeatures.empty()) { 675 O.indent(6) << "return true;\n"; 676 return; 677 } 678 679 O << "if ("; 680 681 for (std::vector<std::string>::iterator 682 I = Conds.begin(), E = Conds.end(); I != E; ++I) { 683 if (I != Conds.begin()) { 684 O << " &&\n"; 685 O.indent(8); 686 } 687 688 O << *I; 689 } 690 691 O << ") {\n"; 692 O.indent(6) << "// " << Result << "\n"; 693 694 // Directly mangle mapped operands into the string. Each operand is 695 // identified by a '$' sign followed by a byte identifying the number of the 696 // operand. We add one to the index to avoid zero bytes. 697 StringRef ASM(AsmString); 698 SmallString<128> OutString; 699 raw_svector_ostream OS(OutString); 700 for (StringRef::iterator I = ASM.begin(), E = ASM.end(); I != E;) { 701 OS << *I; 702 if (*I == '$') { 703 StringRef Name; 704 std::tie(Name, I) = parseName(++I, E); 705 assert(isOpMapped(Name) && "Unmapped operand!"); 706 707 int OpIndex, PrintIndex; 708 std::tie(OpIndex, PrintIndex) = getOpData(Name); 709 if (PrintIndex == -1) { 710 // Can use the default printOperand route. 711 OS << format("\\x%02X", (unsigned char)OpIndex + 1); 712 } else 713 // 3 bytes if a PrintMethod is needed: 0xFF, the MCInst operand 714 // number, and which of our pre-detected Methods to call. 715 OS << format("\\xFF\\x%02X\\x%02X", OpIndex + 1, PrintIndex + 1); 716 } else { 717 ++I; 718 } 719 } 720 OS.flush(); 721 722 // Emit the string. 723 O.indent(6) << "AsmString = \"" << OutString.str() << "\";\n"; 724 725 O.indent(6) << "break;\n"; 726 O.indent(4) << '}'; 727 } 728 729 bool operator==(const IAPrinter &RHS) { 730 if (Conds.size() != RHS.Conds.size()) 731 return false; 732 733 unsigned Idx = 0; 734 for (std::vector<std::string>::iterator 735 I = Conds.begin(), E = Conds.end(); I != E; ++I) 736 if (*I != RHS.Conds[Idx++]) 737 return false; 738 739 return true; 740 } 741}; 742 743} // end anonymous namespace 744 745static unsigned CountNumOperands(StringRef AsmString, unsigned Variant) { 746 std::string FlatAsmString = 747 CodeGenInstruction::FlattenAsmStringVariants(AsmString, Variant); 748 AsmString = FlatAsmString; 749 750 return AsmString.count(' ') + AsmString.count('\t'); 751} 752 753namespace { 754struct AliasPriorityComparator { 755 typedef std::pair<CodeGenInstAlias *, int> ValueType; 756 bool operator()(const ValueType &LHS, const ValueType &RHS) { 757 if (LHS.second == RHS.second) { 758 // We don't actually care about the order, but for consistency it 759 // shouldn't depend on pointer comparisons. 760 return LHS.first->TheDef->getName() < RHS.first->TheDef->getName(); 761 } 762 763 // Aliases with larger priorities should be considered first. 764 return LHS.second > RHS.second; 765 } 766}; 767} 768 769 770void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) { 771 Record *AsmWriter = Target.getAsmWriter(); 772 773 O << "\n#ifdef PRINT_ALIAS_INSTR\n"; 774 O << "#undef PRINT_ALIAS_INSTR\n\n"; 775 776 ////////////////////////////// 777 // Gather information about aliases we need to print 778 ////////////////////////////// 779 780 // Emit the method that prints the alias instruction. 781 std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName"); 782 unsigned Variant = AsmWriter->getValueAsInt("Variant"); 783 784 std::vector<Record*> AllInstAliases = 785 Records.getAllDerivedDefinitions("InstAlias"); 786 787 // Create a map from the qualified name to a list of potential matches. 788 typedef std::set<std::pair<CodeGenInstAlias*, int>, AliasPriorityComparator> 789 AliasWithPriority; 790 std::map<std::string, AliasWithPriority> AliasMap; 791 for (std::vector<Record*>::iterator 792 I = AllInstAliases.begin(), E = AllInstAliases.end(); I != E; ++I) { 793 CodeGenInstAlias *Alias = new CodeGenInstAlias(*I, Variant, Target); 794 const Record *R = *I; 795 int Priority = R->getValueAsInt("EmitPriority"); 796 if (Priority < 1) 797 continue; // Aliases with priority 0 are never emitted. 798 799 const DagInit *DI = R->getValueAsDag("ResultInst"); 800 const DefInit *Op = cast<DefInit>(DI->getOperator()); 801 AliasMap[getQualifiedName(Op->getDef())].insert(std::make_pair(Alias, 802 Priority)); 803 } 804 805 // A map of which conditions need to be met for each instruction operand 806 // before it can be matched to the mnemonic. 807 std::map<std::string, std::vector<IAPrinter*> > IAPrinterMap; 808 809 for (auto &Aliases : AliasMap) { 810 for (auto &Alias : Aliases.second) { 811 const CodeGenInstAlias *CGA = Alias.first; 812 unsigned LastOpNo = CGA->ResultInstOperandIndex.size(); 813 unsigned NumResultOps = 814 CountNumOperands(CGA->ResultInst->AsmString, Variant); 815 816 // Don't emit the alias if it has more operands than what it's aliasing. 817 if (NumResultOps < CountNumOperands(CGA->AsmString, Variant)) 818 continue; 819 820 IAPrinter *IAP = new IAPrinter(CGA->Result->getAsString(), 821 CGA->AsmString); 822 823 unsigned NumMIOps = 0; 824 for (auto &Operand : CGA->ResultOperands) 825 NumMIOps += Operand.getMINumOperands(); 826 827 std::string Cond; 828 Cond = std::string("MI->getNumOperands() == ") + llvm::utostr(NumMIOps); 829 IAP->addCond(Cond); 830 831 bool CantHandle = false; 832 833 unsigned MIOpNum = 0; 834 for (unsigned i = 0, e = LastOpNo; i != e; ++i) { 835 const CodeGenInstAlias::ResultOperand &RO = CGA->ResultOperands[i]; 836 837 switch (RO.Kind) { 838 case CodeGenInstAlias::ResultOperand::K_Record: { 839 const Record *Rec = RO.getRecord(); 840 StringRef ROName = RO.getName(); 841 int PrintMethodIdx = -1; 842 843 // These two may have a PrintMethod, which we want to record (if it's 844 // the first time we've seen it) and provide an index for the aliasing 845 // code to use. 846 if (Rec->isSubClassOf("RegisterOperand") || 847 Rec->isSubClassOf("Operand")) { 848 std::string PrintMethod = Rec->getValueAsString("PrintMethod"); 849 if (PrintMethod != "" && PrintMethod != "printOperand") { 850 PrintMethodIdx = std::find(PrintMethods.begin(), 851 PrintMethods.end(), PrintMethod) - 852 PrintMethods.begin(); 853 if (static_cast<unsigned>(PrintMethodIdx) == PrintMethods.size()) 854 PrintMethods.push_back(PrintMethod); 855 } 856 } 857 858 if (Rec->isSubClassOf("RegisterOperand")) 859 Rec = Rec->getValueAsDef("RegClass"); 860 if (Rec->isSubClassOf("RegisterClass")) { 861 Cond = std::string("MI->getOperand(") + llvm::utostr(MIOpNum) + 862 ").isReg()"; 863 IAP->addCond(Cond); 864 865 if (!IAP->isOpMapped(ROName)) { 866 IAP->addOperand(ROName, MIOpNum, PrintMethodIdx); 867 Record *R = CGA->ResultOperands[i].getRecord(); 868 if (R->isSubClassOf("RegisterOperand")) 869 R = R->getValueAsDef("RegClass"); 870 Cond = std::string("MRI.getRegClass(") + Target.getName() + "::" + 871 R->getName() + "RegClassID)" 872 ".contains(MI->getOperand(" + 873 llvm::utostr(MIOpNum) + ").getReg())"; 874 IAP->addCond(Cond); 875 } else { 876 Cond = std::string("MI->getOperand(") + 877 llvm::utostr(MIOpNum) + ").getReg() == MI->getOperand(" + 878 llvm::utostr(IAP->getOpIndex(ROName)) + ").getReg()"; 879 IAP->addCond(Cond); 880 } 881 } else { 882 // Assume all printable operands are desired for now. This can be 883 // overridden in the InstAlias instantiation if necessary. 884 IAP->addOperand(ROName, MIOpNum, PrintMethodIdx); 885 } 886 887 break; 888 } 889 case CodeGenInstAlias::ResultOperand::K_Imm: { 890 std::string Op = "MI->getOperand(" + llvm::utostr(MIOpNum) + ")"; 891 892 // Just because the alias has an immediate result, doesn't mean the 893 // MCInst will. An MCExpr could be present, for example. 894 IAP->addCond(Op + ".isImm()"); 895 896 Cond = Op + ".getImm() == " 897 + llvm::utostr(CGA->ResultOperands[i].getImm()); 898 IAP->addCond(Cond); 899 break; 900 } 901 case CodeGenInstAlias::ResultOperand::K_Reg: 902 // If this is zero_reg, something's playing tricks we're not 903 // equipped to handle. 904 if (!CGA->ResultOperands[i].getRegister()) { 905 CantHandle = true; 906 break; 907 } 908 909 Cond = std::string("MI->getOperand(") + 910 llvm::utostr(MIOpNum) + ").getReg() == " + Target.getName() + 911 "::" + CGA->ResultOperands[i].getRegister()->getName(); 912 IAP->addCond(Cond); 913 break; 914 } 915 916 if (!IAP) break; 917 MIOpNum += RO.getMINumOperands(); 918 } 919 920 if (CantHandle) continue; 921 IAPrinterMap[Aliases.first].push_back(IAP); 922 } 923 } 924 925 ////////////////////////////// 926 // Write out the printAliasInstr function 927 ////////////////////////////// 928 929 std::string Header; 930 raw_string_ostream HeaderO(Header); 931 932 HeaderO << "bool " << Target.getName() << ClassName 933 << "::printAliasInstr(const MCInst" 934 << " *MI, raw_ostream &OS) {\n"; 935 936 std::string Cases; 937 raw_string_ostream CasesO(Cases); 938 939 for (std::map<std::string, std::vector<IAPrinter*> >::iterator 940 I = IAPrinterMap.begin(), E = IAPrinterMap.end(); I != E; ++I) { 941 std::vector<IAPrinter*> &IAPs = I->second; 942 std::vector<IAPrinter*> UniqueIAPs; 943 944 for (std::vector<IAPrinter*>::iterator 945 II = IAPs.begin(), IE = IAPs.end(); II != IE; ++II) { 946 IAPrinter *LHS = *II; 947 bool IsDup = false; 948 for (std::vector<IAPrinter*>::iterator 949 III = IAPs.begin(), IIE = IAPs.end(); III != IIE; ++III) { 950 IAPrinter *RHS = *III; 951 if (LHS != RHS && *LHS == *RHS) { 952 IsDup = true; 953 break; 954 } 955 } 956 957 if (!IsDup) UniqueIAPs.push_back(LHS); 958 } 959 960 if (UniqueIAPs.empty()) continue; 961 962 CasesO.indent(2) << "case " << I->first << ":\n"; 963 964 for (std::vector<IAPrinter*>::iterator 965 II = UniqueIAPs.begin(), IE = UniqueIAPs.end(); II != IE; ++II) { 966 IAPrinter *IAP = *II; 967 CasesO.indent(4); 968 IAP->print(CasesO); 969 CasesO << '\n'; 970 } 971 972 CasesO.indent(4) << "return false;\n"; 973 } 974 975 if (CasesO.str().empty()) { 976 O << HeaderO.str(); 977 O << " return false;\n"; 978 O << "}\n\n"; 979 O << "#endif // PRINT_ALIAS_INSTR\n"; 980 return; 981 } 982 983 O << HeaderO.str(); 984 O.indent(2) << "const char *AsmString;\n"; 985 O.indent(2) << "switch (MI->getOpcode()) {\n"; 986 O.indent(2) << "default: return false;\n"; 987 O << CasesO.str(); 988 O.indent(2) << "}\n\n"; 989 990 // Code that prints the alias, replacing the operands with the ones from the 991 // MCInst. 992 O << " unsigned I = 0;\n"; 993 O << " while (AsmString[I] != ' ' && AsmString[I] != '\t' &&\n"; 994 O << " AsmString[I] != '\\0')\n"; 995 O << " ++I;\n"; 996 O << " OS << '\\t' << StringRef(AsmString, I);\n"; 997 998 O << " if (AsmString[I] != '\\0') {\n"; 999 O << " OS << '\\t';\n"; 1000 O << " do {\n"; 1001 O << " if (AsmString[I] == '$') {\n"; 1002 O << " ++I;\n"; 1003 O << " if (AsmString[I] == (char)0xff) {\n"; 1004 O << " ++I;\n"; 1005 O << " int OpIdx = AsmString[I++] - 1;\n"; 1006 O << " int PrintMethodIdx = AsmString[I++] - 1;\n"; 1007 O << " printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS);\n"; 1008 O << " } else\n"; 1009 O << " printOperand(MI, unsigned(AsmString[I++]) - 1, OS);\n"; 1010 O << " } else {\n"; 1011 O << " OS << AsmString[I++];\n"; 1012 O << " }\n"; 1013 O << " } while (AsmString[I] != '\\0');\n"; 1014 O << " }\n\n"; 1015 1016 O << " return true;\n"; 1017 O << "}\n\n"; 1018 1019 ////////////////////////////// 1020 // Write out the printCustomAliasOperand function 1021 ////////////////////////////// 1022 1023 O << "void " << Target.getName() << ClassName << "::" 1024 << "printCustomAliasOperand(\n" 1025 << " const MCInst *MI, unsigned OpIdx,\n" 1026 << " unsigned PrintMethodIdx, raw_ostream &OS) {\n"; 1027 if (PrintMethods.empty()) 1028 O << " llvm_unreachable(\"Unknown PrintMethod kind\");\n"; 1029 else { 1030 O << " switch (PrintMethodIdx) {\n" 1031 << " default:\n" 1032 << " llvm_unreachable(\"Unknown PrintMethod kind\");\n" 1033 << " break;\n"; 1034 1035 for (unsigned i = 0; i < PrintMethods.size(); ++i) { 1036 O << " case " << i << ":\n" 1037 << " " << PrintMethods[i] << "(MI, OpIdx, OS);\n" 1038 << " break;\n"; 1039 } 1040 O << " }\n"; 1041 } 1042 O << "}\n\n"; 1043 1044 O << "#endif // PRINT_ALIAS_INSTR\n"; 1045} 1046 1047AsmWriterEmitter::AsmWriterEmitter(RecordKeeper &R) : Records(R), Target(R) { 1048 Record *AsmWriter = Target.getAsmWriter(); 1049 for (CodeGenTarget::inst_iterator I = Target.inst_begin(), 1050 E = Target.inst_end(); 1051 I != E; ++I) 1052 if (!(*I)->AsmString.empty() && (*I)->TheDef->getName() != "PHI") 1053 Instructions.push_back( 1054 AsmWriterInst(**I, AsmWriter->getValueAsInt("Variant"), 1055 AsmWriter->getValueAsInt("OperandSpacing"))); 1056 1057 // Get the instruction numbering. 1058 NumberedInstructions = &Target.getInstructionsByEnumValue(); 1059 1060 // Compute the CodeGenInstruction -> AsmWriterInst mapping. Note that not 1061 // all machine instructions are necessarily being printed, so there may be 1062 // target instructions not in this map. 1063 for (unsigned i = 0, e = Instructions.size(); i != e; ++i) 1064 CGIAWIMap.insert(std::make_pair(Instructions[i].CGI, &Instructions[i])); 1065} 1066 1067void AsmWriterEmitter::run(raw_ostream &O) { 1068 EmitPrintInstruction(O); 1069 EmitGetRegisterName(O); 1070 EmitPrintAliasInstruction(O); 1071} 1072 1073 1074namespace llvm { 1075 1076void EmitAsmWriter(RecordKeeper &RK, raw_ostream &OS) { 1077 emitSourceFileHeader("Assembly Writer Source Fragment", OS); 1078 AsmWriterEmitter(RK).run(OS); 1079} 1080 1081} // End llvm namespace 1082