nv50_vbo.c revision 222b3ea653e5525a4afa57e6a2353335953012d4
1/* 2 * Copyright 2010 Christoph Bumiller 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 20 * SOFTWARE. 21 */ 22 23#include "pipe/p_context.h" 24#include "pipe/p_state.h" 25#include "util/u_inlines.h" 26#include "util/u_format.h" 27#include "translate/translate.h" 28 29#include "nv50_context.h" 30#include "nv50_resource.h" 31 32#include "nv50_3d.xml.h" 33 34void 35nv50_vertex_state_delete(struct pipe_context *pipe, 36 void *hwcso) 37{ 38 struct nv50_vertex_stateobj *so = hwcso; 39 40 if (so->translate) 41 so->translate->release(so->translate); 42 FREE(hwcso); 43} 44 45void * 46nv50_vertex_state_create(struct pipe_context *pipe, 47 unsigned num_elements, 48 const struct pipe_vertex_element *elements) 49{ 50 struct nv50_vertex_stateobj *so; 51 struct translate_key transkey; 52 unsigned i; 53 54 so = MALLOC(sizeof(*so) + 55 num_elements * sizeof(struct nv50_vertex_element)); 56 if (!so) 57 return NULL; 58 so->num_elements = num_elements; 59 so->instance_elts = 0; 60 so->instance_bufs = 0; 61 so->need_conversion = FALSE; 62 63 transkey.nr_elements = 0; 64 transkey.output_stride = 0; 65 66 for (i = 0; i < num_elements; ++i) { 67 const struct pipe_vertex_element *ve = &elements[i]; 68 const unsigned vbi = ve->vertex_buffer_index; 69 enum pipe_format fmt = ve->src_format; 70 71 so->element[i].pipe = elements[i]; 72 so->element[i].state = nv50_format_table[fmt].vtx; 73 74 if (!so->element[i].state) { 75 switch (util_format_get_nr_components(fmt)) { 76 case 1: fmt = PIPE_FORMAT_R32_FLOAT; break; 77 case 2: fmt = PIPE_FORMAT_R32G32_FLOAT; break; 78 case 3: fmt = PIPE_FORMAT_R32G32B32_FLOAT; break; 79 case 4: fmt = PIPE_FORMAT_R32G32B32A32_FLOAT; break; 80 default: 81 assert(0); 82 return NULL; 83 } 84 so->element[i].state = nv50_format_table[fmt].vtx; 85 so->need_conversion = TRUE; 86 } 87 so->element[i].state |= i; 88 89 if (1) { 90 unsigned j = transkey.nr_elements++; 91 92 transkey.element[j].type = TRANSLATE_ELEMENT_NORMAL; 93 transkey.element[j].input_format = ve->src_format; 94 transkey.element[j].input_buffer = vbi; 95 transkey.element[j].input_offset = ve->src_offset; 96 transkey.element[j].instance_divisor = ve->instance_divisor; 97 98 transkey.element[j].output_format = fmt; 99 transkey.element[j].output_offset = transkey.output_stride; 100 transkey.output_stride += (util_format_get_stride(fmt, 1) + 3) & ~3; 101 102 if (unlikely(ve->instance_divisor)) { 103 so->instance_elts |= 1 << i; 104 so->instance_bufs |= 1 << vbi; 105 } 106 } 107 } 108 109 so->translate = translate_create(&transkey); 110 so->vertex_size = transkey.output_stride / 4; 111 so->packet_vertex_limit = NV04_PFIFO_MAX_PACKET_LEN / 112 MAX2(so->vertex_size, 1); 113 114 return so; 115} 116 117#define NV50_3D_VERTEX_ATTRIB_INACTIVE \ 118 NV50_3D_VERTEX_ARRAY_ATTRIB_TYPE_FLOAT | \ 119 NV50_3D_VERTEX_ARRAY_ATTRIB_FORMAT_32_32_32_32 | \ 120 NV50_3D_VERTEX_ARRAY_ATTRIB_CONST 121 122static void 123nv50_emit_vtxattr(struct nv50_context *nv50, struct pipe_vertex_buffer *vb, 124 struct pipe_vertex_element *ve, unsigned attr) 125{ 126 const void *data; 127 struct nouveau_channel *chan = nv50->screen->base.channel; 128 struct nv04_resource *res = nv04_resource(vb->buffer); 129 float v[4]; 130 const unsigned nc = util_format_get_nr_components(ve->src_format); 131 132 data = nouveau_resource_map_offset(&nv50->base, res, vb->buffer_offset + 133 ve->src_offset, NOUVEAU_BO_RD); 134 135 util_format_read_4f(ve->src_format, v, 0, data, 0, 0, 0, 1, 1); 136 137 switch (nc) { 138 case 4: 139 BEGIN_RING(chan, RING_3D(VTX_ATTR_4F_X(attr)), 4); 140 OUT_RINGf (chan, v[0]); 141 OUT_RINGf (chan, v[1]); 142 OUT_RINGf (chan, v[2]); 143 OUT_RINGf (chan, v[3]); 144 break; 145 case 3: 146 BEGIN_RING(chan, RING_3D(VTX_ATTR_3F_X(attr)), 3); 147 OUT_RINGf (chan, v[0]); 148 OUT_RINGf (chan, v[1]); 149 OUT_RINGf (chan, v[2]); 150 break; 151 case 2: 152 BEGIN_RING(chan, RING_3D(VTX_ATTR_2F_X(attr)), 2); 153 OUT_RINGf (chan, v[0]); 154 OUT_RINGf (chan, v[1]); 155 break; 156 case 1: 157 if (attr == nv50->vertprog->vp.edgeflag) { 158 BEGIN_RING(chan, RING_3D(EDGEFLAG_ENABLE), 1); 159 OUT_RING (chan, v[0] ? 1 : 0); 160 } 161 BEGIN_RING(chan, RING_3D(VTX_ATTR_1F(attr)), 1); 162 OUT_RINGf (chan, v[0]); 163 break; 164 default: 165 assert(0); 166 break; 167 } 168} 169 170static INLINE void 171nv50_vbuf_range(struct nv50_context *nv50, int vbi, 172 uint32_t *base, uint32_t *size) 173{ 174 if (unlikely(nv50->vertex->instance_bufs & (1 << vbi))) { 175 /* TODO: use min and max instance divisor to get a proper range */ 176 *base = 0; 177 *size = nv50->vtxbuf[vbi].buffer->width0; 178 } else { 179 assert(nv50->vbo_max_index != ~0); 180 *base = nv50->vbo_min_index * nv50->vtxbuf[vbi].stride; 181 *size = (nv50->vbo_max_index - 182 nv50->vbo_min_index + 1) * nv50->vtxbuf[vbi].stride; 183 } 184} 185 186static void 187nv50_prevalidate_vbufs(struct nv50_context *nv50) 188{ 189 struct pipe_vertex_buffer *vb; 190 struct nv04_resource *buf; 191 int i; 192 uint32_t base, size; 193 194 nv50->vbo_fifo = nv50->vbo_user = 0; 195 196 nv50_bufctx_reset(nv50, NV50_BUFCTX_VERTEX); 197 198 for (i = 0; i < nv50->num_vtxbufs; ++i) { 199 vb = &nv50->vtxbuf[i]; 200 if (!vb->stride) 201 continue; 202 buf = nv04_resource(vb->buffer); 203 204 /* NOTE: user buffers with temporary storage count as mapped by GPU */ 205 if (!nouveau_resource_mapped_by_gpu(vb->buffer)) { 206 if (nv50->vbo_push_hint) { 207 nv50->vbo_fifo = ~0; 208 continue; 209 } else { 210 if (buf->status & NOUVEAU_BUFFER_STATUS_USER_MEMORY) { 211 nv50->vbo_user |= 1 << i; 212 assert(vb->stride > vb->buffer_offset); 213 nv50_vbuf_range(nv50, i, &base, &size); 214 nouveau_user_buffer_upload(buf, base, size); 215 } else { 216 nouveau_buffer_migrate(&nv50->base, buf, NOUVEAU_BO_GART); 217 } 218 nv50->base.vbo_dirty = TRUE; 219 } 220 } 221 nv50_bufctx_add_resident(nv50, NV50_BUFCTX_VERTEX, buf, NOUVEAU_BO_RD); 222 nouveau_buffer_adjust_score(&nv50->base, buf, 1); 223 } 224} 225 226static void 227nv50_update_user_vbufs(struct nv50_context *nv50) 228{ 229 struct nouveau_channel *chan = nv50->screen->base.channel; 230 uint32_t base, offset, size; 231 int i; 232 uint32_t written = 0; 233 234 for (i = 0; i < nv50->vertex->num_elements; ++i) { 235 struct pipe_vertex_element *ve = &nv50->vertex->element[i].pipe; 236 const int b = ve->vertex_buffer_index; 237 struct pipe_vertex_buffer *vb = &nv50->vtxbuf[b]; 238 struct nv04_resource *buf = nv04_resource(vb->buffer); 239 240 if (!(nv50->vbo_user & (1 << b))) 241 continue; 242 243 if (!vb->stride) { 244 nv50_emit_vtxattr(nv50, vb, ve, i); 245 continue; 246 } 247 nv50_vbuf_range(nv50, b, &base, &size); 248 249 if (!(written & (1 << b))) { 250 written |= 1 << b; 251 nouveau_user_buffer_upload(buf, base, size); 252 } 253 offset = vb->buffer_offset + ve->src_offset; 254 255 MARK_RING (chan, 6, 4); 256 BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_LIMIT_HIGH(i)), 2); 257 OUT_RESRCh(chan, buf, base + size - 1, NOUVEAU_BO_RD); 258 OUT_RESRCl(chan, buf, base + size - 1, NOUVEAU_BO_RD); 259 BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_START_HIGH(i)), 2); 260 OUT_RESRCh(chan, buf, offset, NOUVEAU_BO_RD); 261 OUT_RESRCl(chan, buf, offset, NOUVEAU_BO_RD); 262 } 263 nv50->base.vbo_dirty = TRUE; 264} 265 266static INLINE void 267nv50_release_user_vbufs(struct nv50_context *nv50) 268{ 269 uint32_t vbo_user = nv50->vbo_user; 270 271 while (vbo_user) { 272 int i = ffs(vbo_user) - 1; 273 vbo_user &= ~(1 << i); 274 275 nouveau_buffer_release_gpu_storage(nv04_resource(nv50->vtxbuf[i].buffer)); 276 } 277} 278 279void 280nv50_vertex_arrays_validate(struct nv50_context *nv50) 281{ 282 struct nouveau_channel *chan = nv50->screen->base.channel; 283 struct nv50_vertex_stateobj *vertex = nv50->vertex; 284 struct pipe_vertex_buffer *vb; 285 struct nv50_vertex_element *ve; 286 unsigned i; 287 288 if (unlikely(vertex->need_conversion)) { 289 nv50->vbo_fifo = ~0; 290 nv50->vbo_user = 0; 291 } else { 292 nv50_prevalidate_vbufs(nv50); 293 } 294 295 BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_ATTRIB(0)), vertex->num_elements); 296 for (i = 0; i < vertex->num_elements; ++i) { 297 ve = &vertex->element[i]; 298 vb = &nv50->vtxbuf[ve->pipe.vertex_buffer_index]; 299 300 if (likely(vb->stride) || nv50->vbo_fifo) { 301 OUT_RING(chan, ve->state); 302 } else { 303 OUT_RING(chan, ve->state | NV50_3D_VERTEX_ARRAY_ATTRIB_CONST); 304 nv50->vbo_fifo &= ~(1 << i); 305 } 306 } 307 308 for (i = 0; i < vertex->num_elements; ++i) { 309 struct nv04_resource *res; 310 unsigned size, offset; 311 312 ve = &vertex->element[i]; 313 vb = &nv50->vtxbuf[ve->pipe.vertex_buffer_index]; 314 315 if (unlikely(ve->pipe.instance_divisor)) { 316 if (!(nv50->state.instance_elts & (1 << i))) { 317 BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_PER_INSTANCE(i)), 1); 318 OUT_RING (chan, 1); 319 } 320 BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_DIVISOR(i)), 1); 321 OUT_RING (chan, ve->pipe.instance_divisor); 322 } else 323 if (unlikely(nv50->state.instance_elts & (1 << i))) { 324 BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_PER_INSTANCE(i)), 1); 325 OUT_RING (chan, 0); 326 } 327 328 res = nv04_resource(vb->buffer); 329 330 if (nv50->vbo_fifo || unlikely(vb->stride == 0)) { 331 if (!nv50->vbo_fifo) 332 nv50_emit_vtxattr(nv50, vb, &ve->pipe, i); 333 BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_FETCH(i)), 1); 334 OUT_RING (chan, 0); 335 continue; 336 } 337 338 size = vb->buffer->width0; 339 offset = ve->pipe.src_offset + vb->buffer_offset; 340 341 MARK_RING (chan, 8, 4); 342 BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_FETCH(i)), 1); 343 OUT_RING (chan, NV50_3D_VERTEX_ARRAY_FETCH_ENABLE | vb->stride); 344 BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_LIMIT_HIGH(i)), 2); 345 OUT_RESRCh(chan, res, size - 1, NOUVEAU_BO_RD); 346 OUT_RESRCl(chan, res, size - 1, NOUVEAU_BO_RD); 347 BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_START_HIGH(i)), 2); 348 OUT_RESRCh(chan, res, offset, NOUVEAU_BO_RD); 349 OUT_RESRCl(chan, res, offset, NOUVEAU_BO_RD); 350 } 351 for (; i < nv50->state.num_vtxelts; ++i) { 352 BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_ATTRIB(i)), 1); 353 OUT_RING (chan, NV50_3D_VERTEX_ATTRIB_INACTIVE); 354 BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_FETCH(i)), 1); 355 OUT_RING (chan, 0); 356 } 357 358 nv50->state.num_vtxelts = vertex->num_elements; 359 nv50->state.instance_elts = vertex->instance_elts; 360} 361 362#define NV50_PRIM_GL_CASE(n) \ 363 case PIPE_PRIM_##n: return NV50_3D_VERTEX_BEGIN_GL_PRIMITIVE_##n 364 365static INLINE unsigned 366nv50_prim_gl(unsigned prim) 367{ 368 switch (prim) { 369 NV50_PRIM_GL_CASE(POINTS); 370 NV50_PRIM_GL_CASE(LINES); 371 NV50_PRIM_GL_CASE(LINE_LOOP); 372 NV50_PRIM_GL_CASE(LINE_STRIP); 373 NV50_PRIM_GL_CASE(TRIANGLES); 374 NV50_PRIM_GL_CASE(TRIANGLE_STRIP); 375 NV50_PRIM_GL_CASE(TRIANGLE_FAN); 376 NV50_PRIM_GL_CASE(QUADS); 377 NV50_PRIM_GL_CASE(QUAD_STRIP); 378 NV50_PRIM_GL_CASE(POLYGON); 379 NV50_PRIM_GL_CASE(LINES_ADJACENCY); 380 NV50_PRIM_GL_CASE(LINE_STRIP_ADJACENCY); 381 NV50_PRIM_GL_CASE(TRIANGLES_ADJACENCY); 382 NV50_PRIM_GL_CASE(TRIANGLE_STRIP_ADJACENCY); 383 default: 384 return NV50_3D_VERTEX_BEGIN_GL_PRIMITIVE_POINTS; 385 break; 386 } 387} 388 389static void 390nv50_draw_vbo_flush_notify(struct nouveau_channel *chan) 391{ 392 struct nv50_screen *screen = chan->user_private; 393 394 nouveau_fence_update(&screen->base, TRUE); 395 396 nv50_bufctx_emit_relocs(screen->cur_ctx); 397} 398 399static void 400nv50_draw_arrays(struct nv50_context *nv50, 401 unsigned mode, unsigned start, unsigned count, 402 unsigned instance_count) 403{ 404 struct nouveau_channel *chan = nv50->screen->base.channel; 405 unsigned prim; 406 407 prim = nv50_prim_gl(mode); 408 409 while (instance_count--) { 410 BEGIN_RING(chan, RING_3D(VERTEX_BEGIN_GL), 1); 411 OUT_RING (chan, prim); 412 BEGIN_RING(chan, RING_3D(VERTEX_BUFFER_FIRST), 2); 413 OUT_RING (chan, start); 414 OUT_RING (chan, count); 415 BEGIN_RING(chan, RING_3D(VERTEX_END_GL), 1); 416 OUT_RING (chan, 0); 417 418 prim |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT; 419 } 420} 421 422static void 423nv50_draw_elements_inline_u08(struct nouveau_channel *chan, uint8_t *map, 424 unsigned start, unsigned count) 425{ 426 map += start; 427 428 if (count & 3) { 429 unsigned i; 430 BEGIN_RING_NI(chan, RING_3D(VB_ELEMENT_U32), count & 3); 431 for (i = 0; i < (count & 3); ++i) 432 OUT_RING(chan, *map++); 433 count &= ~3; 434 } 435 while (count) { 436 unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 4) / 4; 437 438 BEGIN_RING_NI(chan, RING_3D(VB_ELEMENT_U8), nr); 439 for (i = 0; i < nr; ++i) { 440 OUT_RING(chan, 441 (map[3] << 24) | (map[2] << 16) | (map[1] << 8) | map[0]); 442 map += 4; 443 } 444 count -= nr * 4; 445 } 446} 447 448static void 449nv50_draw_elements_inline_u16(struct nouveau_channel *chan, uint16_t *map, 450 unsigned start, unsigned count) 451{ 452 map += start; 453 454 if (count & 1) { 455 count &= ~1; 456 BEGIN_RING(chan, RING_3D(VB_ELEMENT_U32), 1); 457 OUT_RING (chan, *map++); 458 } 459 while (count) { 460 unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2; 461 462 BEGIN_RING_NI(chan, RING_3D(VB_ELEMENT_U16), nr); 463 for (i = 0; i < nr; ++i) { 464 OUT_RING(chan, (map[1] << 16) | map[0]); 465 map += 2; 466 } 467 count -= nr * 2; 468 } 469} 470 471static void 472nv50_draw_elements_inline_u32(struct nouveau_channel *chan, uint32_t *map, 473 unsigned start, unsigned count) 474{ 475 map += start; 476 477 while (count) { 478 const unsigned nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN); 479 480 BEGIN_RING_NI(chan, RING_3D(VB_ELEMENT_U32), nr); 481 OUT_RINGp (chan, map, nr); 482 483 map += nr; 484 count -= nr; 485 } 486} 487 488static void 489nv50_draw_elements_inline_u32_short(struct nouveau_channel *chan, uint32_t *map, 490 unsigned start, unsigned count) 491{ 492 map += start; 493 494 if (count & 1) { 495 count--; 496 BEGIN_RING(chan, RING_3D(VB_ELEMENT_U32), 1); 497 OUT_RING (chan, *map++); 498 } 499 while (count) { 500 unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2; 501 502 BEGIN_RING_NI(chan, RING_3D(VB_ELEMENT_U16), nr); 503 for (i = 0; i < nr; ++i) { 504 OUT_RING(chan, (map[1] << 16) | map[0]); 505 map += 2; 506 } 507 count -= nr * 2; 508 } 509} 510 511static void 512nv50_draw_elements(struct nv50_context *nv50, boolean shorten, 513 unsigned mode, unsigned start, unsigned count, 514 unsigned instance_count, int32_t index_bias) 515{ 516 struct nouveau_channel *chan = nv50->screen->base.channel; 517 void *data; 518 unsigned prim; 519 const unsigned index_size = nv50->idxbuf.index_size; 520 521 prim = nv50_prim_gl(mode); 522 523 if (index_bias != nv50->state.index_bias) { 524 BEGIN_RING(chan, RING_3D(VB_ELEMENT_BASE), 1); 525 OUT_RING (chan, index_bias); 526 nv50->state.index_bias = index_bias; 527 } 528 529 if (nouveau_resource_mapped_by_gpu(nv50->idxbuf.buffer)) { 530 struct nv04_resource *res = nv04_resource(nv50->idxbuf.buffer); 531 532 start += nv50->idxbuf.offset >> (index_size >> 1); 533 534 nouveau_buffer_adjust_score(&nv50->base, res, 1); 535 536 while (instance_count--) { 537 BEGIN_RING(chan, RING_3D(VERTEX_BEGIN_GL), 1); 538 OUT_RING (chan, mode); 539 540 switch (index_size) { 541 case 4: 542 { 543 WAIT_RING (chan, 2); 544 BEGIN_RING(chan, RING_3D(VB_ELEMENT_U32) | 0x30000, 0); 545 OUT_RING (chan, count); 546 nouveau_pushbuf_submit(chan, res->bo, res->offset + start * 4, 547 count * 4); 548 } 549 break; 550 case 2: 551 { 552 unsigned pb_start = (start & ~1); 553 unsigned pb_words = (((start + count + 1) & ~1) - pb_start) >> 1; 554 555 BEGIN_RING(chan, RING_3D(VB_ELEMENT_U16_SETUP), 1); 556 OUT_RING (chan, (start << 31) | count); 557 WAIT_RING (chan, 2); 558 BEGIN_RING(chan, RING_3D(VB_ELEMENT_U16) | 0x30000, 0); 559 OUT_RING (chan, pb_words); 560 nouveau_pushbuf_submit(chan, res->bo, res->offset + pb_start * 2, 561 pb_words * 4); 562 BEGIN_RING(chan, RING_3D(VB_ELEMENT_U16_SETUP), 1); 563 OUT_RING (chan, 0); 564 break; 565 } 566 case 1: 567 { 568 unsigned pb_start = (start & ~3); 569 unsigned pb_words = (((start + count + 3) & ~3) - pb_start) >> 1; 570 571 BEGIN_RING(chan, RING_3D(VB_ELEMENT_U8_SETUP), 1); 572 OUT_RING (chan, (start << 30) | count); 573 WAIT_RING (chan, 2); 574 BEGIN_RING(chan, RING_3D(VB_ELEMENT_U8) | 0x30000, 0); 575 OUT_RING (chan, pb_words); 576 nouveau_pushbuf_submit(chan, res->bo, res->offset + pb_start, 577 pb_words * 4); 578 BEGIN_RING(chan, RING_3D(VB_ELEMENT_U8_SETUP), 1); 579 OUT_RING (chan, 0); 580 break; 581 } 582 default: 583 assert(0); 584 return; 585 } 586 BEGIN_RING(chan, RING_3D(VERTEX_END_GL), 1); 587 OUT_RING (chan, 0); 588 589 nv50_resource_fence(res, NOUVEAU_BO_RD); 590 591 mode |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT; 592 } 593 } else { 594 data = nouveau_resource_map_offset(&nv50->base, 595 nv04_resource(nv50->idxbuf.buffer), 596 nv50->idxbuf.offset, NOUVEAU_BO_RD); 597 if (!data) 598 return; 599 600 while (instance_count--) { 601 BEGIN_RING(chan, RING_3D(VERTEX_BEGIN_GL), 1); 602 OUT_RING (chan, prim); 603 switch (index_size) { 604 case 1: 605 nv50_draw_elements_inline_u08(chan, data, start, count); 606 break; 607 case 2: 608 nv50_draw_elements_inline_u16(chan, data, start, count); 609 break; 610 case 4: 611 if (shorten) 612 nv50_draw_elements_inline_u32_short(chan, data, start, count); 613 else 614 nv50_draw_elements_inline_u32(chan, data, start, count); 615 break; 616 default: 617 assert(0); 618 return; 619 } 620 BEGIN_RING(chan, RING_3D(VERTEX_END_GL), 1); 621 OUT_RING (chan, 0); 622 623 prim |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT; 624 } 625 } 626} 627 628void 629nv50_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info) 630{ 631 struct nv50_context *nv50 = nv50_context(pipe); 632 struct nouveau_channel *chan = nv50->screen->base.channel; 633 634 /* For picking only a few vertices from a large user buffer, push is better, 635 * if index count is larger and we expect repeated vertices, suggest upload. 636 */ 637 nv50->vbo_push_hint = /* the 64 is heuristic */ 638 !(info->indexed && 639 ((info->max_index - info->min_index + 64) < info->count)); 640 641 nv50->vbo_min_index = info->min_index; 642 nv50->vbo_max_index = info->max_index; 643 644 if (nv50->vbo_push_hint != !!nv50->vbo_fifo) 645 nv50->dirty |= NV50_NEW_ARRAYS; 646 647 if (nv50->vbo_user && !(nv50->dirty & (NV50_NEW_VERTEX | NV50_NEW_ARRAYS))) 648 nv50_update_user_vbufs(nv50); 649 650 nv50_state_validate(nv50, ~0, 8); /* 8 as minimum, we use flush_notify */ 651 652 chan->flush_notify = nv50_draw_vbo_flush_notify; 653 654 if (nv50->vbo_fifo) { 655 nv50_push_vbo(nv50, info); 656 chan->flush_notify = nv50_default_flush_notify; 657 return; 658 } 659 660 if (nv50->state.instance_base != info->start_instance) { 661 nv50->state.instance_base = info->start_instance; 662 /* NOTE: this does not affect the shader input, should it ? */ 663 BEGIN_RING(chan, RING_3D(VB_INSTANCE_BASE), 1); 664 OUT_RING (chan, info->start_instance); 665 } 666 667 if (nv50->base.vbo_dirty) { 668 BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_FLUSH), 1); 669 OUT_RING (chan, 0); 670 nv50->base.vbo_dirty = FALSE; 671 } 672 673 if (!info->indexed) { 674 nv50_draw_arrays(nv50, 675 info->mode, info->start, info->count, 676 info->instance_count); 677 } else { 678 boolean shorten = info->max_index <= 65535; 679 680 assert(nv50->idxbuf.buffer); 681 682 if (info->primitive_restart != nv50->state.prim_restart) { 683 if (info->primitive_restart) { 684 BEGIN_RING(chan, RING_3D(PRIM_RESTART_ENABLE), 2); 685 OUT_RING (chan, 1); 686 OUT_RING (chan, info->restart_index); 687 688 if (info->restart_index > 65535) 689 shorten = FALSE; 690 } else { 691 BEGIN_RING(chan, RING_3D(PRIM_RESTART_ENABLE), 1); 692 OUT_RING (chan, 0); 693 } 694 nv50->state.prim_restart = info->primitive_restart; 695 } else 696 if (info->primitive_restart) { 697 BEGIN_RING(chan, RING_3D(PRIM_RESTART_INDEX), 1); 698 OUT_RING (chan, info->restart_index); 699 700 if (info->restart_index > 65535) 701 shorten = FALSE; 702 } 703 704 nv50_draw_elements(nv50, shorten, 705 info->mode, info->start, info->count, 706 info->instance_count, info->index_bias); 707 } 708 chan->flush_notify = nv50_default_flush_notify; 709 710 nv50_release_user_vbufs(nv50); 711} 712