r300_state.c revision 0a9510814e2dfff57f7d73cc68aece0554ad794d
1/* 2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com> 3 * Copyright 2009 Marek Olšák <maraeo@gmail.com> 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * on the rights to use, copy, modify, merge, publish, distribute, sub 9 * license, and/or sell copies of the Software, and to permit persons to whom 10 * the Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */ 23 24#include "draw/draw_context.h" 25 26#include "util/u_math.h" 27#include "util/u_memory.h" 28#include "util/u_pack_color.h" 29 30#include "tgsi/tgsi_parse.h" 31 32#include "pipe/p_config.h" 33 34#include "r300_cb.h" 35#include "r300_context.h" 36#include "r300_emit.h" 37#include "r300_reg.h" 38#include "r300_screen.h" 39#include "r300_screen_buffer.h" 40#include "r300_state_inlines.h" 41#include "r300_fs.h" 42#include "r300_texture.h" 43#include "r300_vs.h" 44#include "r300_winsys.h" 45 46/* r300_state: Functions used to intialize state context by translating 47 * Gallium state objects into semi-native r300 state objects. */ 48 49#define UPDATE_STATE(cso, atom) \ 50 if (cso != atom.state) { \ 51 atom.state = cso; \ 52 atom.dirty = TRUE; \ 53 } 54 55static boolean blend_discard_if_src_alpha_0(unsigned srcRGB, unsigned srcA, 56 unsigned dstRGB, unsigned dstA) 57{ 58 /* If the blend equation is ADD or REVERSE_SUBTRACT, 59 * SRC_ALPHA == 0, and the following state is set, the colorbuffer 60 * will not be changed. 61 * Notice that the dst factors are the src factors inverted. */ 62 return (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA || 63 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE || 64 srcRGB == PIPE_BLENDFACTOR_ZERO) && 65 (srcA == PIPE_BLENDFACTOR_SRC_COLOR || 66 srcA == PIPE_BLENDFACTOR_SRC_ALPHA || 67 srcA == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE || 68 srcA == PIPE_BLENDFACTOR_ZERO) && 69 (dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 70 dstRGB == PIPE_BLENDFACTOR_ONE) && 71 (dstA == PIPE_BLENDFACTOR_INV_SRC_COLOR || 72 dstA == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 73 dstA == PIPE_BLENDFACTOR_ONE); 74} 75 76static boolean blend_discard_if_src_alpha_1(unsigned srcRGB, unsigned srcA, 77 unsigned dstRGB, unsigned dstA) 78{ 79 /* If the blend equation is ADD or REVERSE_SUBTRACT, 80 * SRC_ALPHA == 1, and the following state is set, the colorbuffer 81 * will not be changed. 82 * Notice that the dst factors are the src factors inverted. */ 83 return (srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 84 srcRGB == PIPE_BLENDFACTOR_ZERO) && 85 (srcA == PIPE_BLENDFACTOR_INV_SRC_COLOR || 86 srcA == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 87 srcA == PIPE_BLENDFACTOR_ZERO) && 88 (dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA || 89 dstRGB == PIPE_BLENDFACTOR_ONE) && 90 (dstA == PIPE_BLENDFACTOR_SRC_COLOR || 91 dstA == PIPE_BLENDFACTOR_SRC_ALPHA || 92 dstA == PIPE_BLENDFACTOR_ONE); 93} 94 95static boolean blend_discard_if_src_color_0(unsigned srcRGB, unsigned srcA, 96 unsigned dstRGB, unsigned dstA) 97{ 98 /* If the blend equation is ADD or REVERSE_SUBTRACT, 99 * SRC_COLOR == (0,0,0), and the following state is set, the colorbuffer 100 * will not be changed. 101 * Notice that the dst factors are the src factors inverted. */ 102 return (srcRGB == PIPE_BLENDFACTOR_SRC_COLOR || 103 srcRGB == PIPE_BLENDFACTOR_ZERO) && 104 (srcA == PIPE_BLENDFACTOR_ZERO) && 105 (dstRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR || 106 dstRGB == PIPE_BLENDFACTOR_ONE) && 107 (dstA == PIPE_BLENDFACTOR_ONE); 108} 109 110static boolean blend_discard_if_src_color_1(unsigned srcRGB, unsigned srcA, 111 unsigned dstRGB, unsigned dstA) 112{ 113 /* If the blend equation is ADD or REVERSE_SUBTRACT, 114 * SRC_COLOR == (1,1,1), and the following state is set, the colorbuffer 115 * will not be changed. 116 * Notice that the dst factors are the src factors inverted. */ 117 return (srcRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR || 118 srcRGB == PIPE_BLENDFACTOR_ZERO) && 119 (srcA == PIPE_BLENDFACTOR_ZERO) && 120 (dstRGB == PIPE_BLENDFACTOR_SRC_COLOR || 121 dstRGB == PIPE_BLENDFACTOR_ONE) && 122 (dstA == PIPE_BLENDFACTOR_ONE); 123} 124 125static boolean blend_discard_if_src_alpha_color_0(unsigned srcRGB, unsigned srcA, 126 unsigned dstRGB, unsigned dstA) 127{ 128 /* If the blend equation is ADD or REVERSE_SUBTRACT, 129 * SRC_ALPHA_COLOR == (0,0,0,0), and the following state is set, 130 * the colorbuffer will not be changed. 131 * Notice that the dst factors are the src factors inverted. */ 132 return (srcRGB == PIPE_BLENDFACTOR_SRC_COLOR || 133 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA || 134 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE || 135 srcRGB == PIPE_BLENDFACTOR_ZERO) && 136 (srcA == PIPE_BLENDFACTOR_SRC_COLOR || 137 srcA == PIPE_BLENDFACTOR_SRC_ALPHA || 138 srcA == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE || 139 srcA == PIPE_BLENDFACTOR_ZERO) && 140 (dstRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR || 141 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 142 dstRGB == PIPE_BLENDFACTOR_ONE) && 143 (dstA == PIPE_BLENDFACTOR_INV_SRC_COLOR || 144 dstA == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 145 dstA == PIPE_BLENDFACTOR_ONE); 146} 147 148static boolean blend_discard_if_src_alpha_color_1(unsigned srcRGB, unsigned srcA, 149 unsigned dstRGB, unsigned dstA) 150{ 151 /* If the blend equation is ADD or REVERSE_SUBTRACT, 152 * SRC_ALPHA_COLOR == (1,1,1,1), and the following state is set, 153 * the colorbuffer will not be changed. 154 * Notice that the dst factors are the src factors inverted. */ 155 return (srcRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR || 156 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 157 srcRGB == PIPE_BLENDFACTOR_ZERO) && 158 (srcA == PIPE_BLENDFACTOR_INV_SRC_COLOR || 159 srcA == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 160 srcA == PIPE_BLENDFACTOR_ZERO) && 161 (dstRGB == PIPE_BLENDFACTOR_SRC_COLOR || 162 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA || 163 dstRGB == PIPE_BLENDFACTOR_ONE) && 164 (dstA == PIPE_BLENDFACTOR_SRC_COLOR || 165 dstA == PIPE_BLENDFACTOR_SRC_ALPHA || 166 dstA == PIPE_BLENDFACTOR_ONE); 167} 168 169static unsigned bgra_cmask(unsigned mask) 170{ 171 /* Gallium uses RGBA color ordering while R300 expects BGRA. */ 172 173 return ((mask & PIPE_MASK_R) << 2) | 174 ((mask & PIPE_MASK_B) >> 2) | 175 (mask & (PIPE_MASK_G | PIPE_MASK_A)); 176} 177 178/* Create a new blend state based on the CSO blend state. 179 * 180 * This encompasses alpha blending, logic/raster ops, and blend dithering. */ 181static void* r300_create_blend_state(struct pipe_context* pipe, 182 const struct pipe_blend_state* state) 183{ 184 struct r300_screen* r300screen = r300_screen(pipe->screen); 185 struct r300_blend_state* blend = CALLOC_STRUCT(r300_blend_state); 186 uint32_t blend_control = 0; /* R300_RB3D_CBLEND: 0x4e04 */ 187 uint32_t alpha_blend_control = 0; /* R300_RB3D_ABLEND: 0x4e08 */ 188 uint32_t color_channel_mask = 0; /* R300_RB3D_COLOR_CHANNEL_MASK: 0x4e0c */ 189 uint32_t rop = 0; /* R300_RB3D_ROPCNTL: 0x4e18 */ 190 uint32_t dither = 0; /* R300_RB3D_DITHER_CTL: 0x4e50 */ 191 CB_LOCALS; 192 193 if (state->rt[0].blend_enable) 194 { 195 unsigned eqRGB = state->rt[0].rgb_func; 196 unsigned srcRGB = state->rt[0].rgb_src_factor; 197 unsigned dstRGB = state->rt[0].rgb_dst_factor; 198 199 unsigned eqA = state->rt[0].alpha_func; 200 unsigned srcA = state->rt[0].alpha_src_factor; 201 unsigned dstA = state->rt[0].alpha_dst_factor; 202 203 /* despite the name, ALPHA_BLEND_ENABLE has nothing to do with alpha, 204 * this is just the crappy D3D naming */ 205 blend_control = R300_ALPHA_BLEND_ENABLE | 206 r300_translate_blend_function(eqRGB) | 207 ( r300_translate_blend_factor(srcRGB) << R300_SRC_BLEND_SHIFT) | 208 ( r300_translate_blend_factor(dstRGB) << R300_DST_BLEND_SHIFT); 209 210 /* Optimization: some operations do not require the destination color. 211 * 212 * When SRC_ALPHA_SATURATE is used, colorbuffer reads must be enabled, 213 * otherwise blending gives incorrect results. It seems to be 214 * a hardware bug. */ 215 if (eqRGB == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MIN || 216 eqRGB == PIPE_BLEND_MAX || eqA == PIPE_BLEND_MAX || 217 dstRGB != PIPE_BLENDFACTOR_ZERO || 218 dstA != PIPE_BLENDFACTOR_ZERO || 219 srcRGB == PIPE_BLENDFACTOR_DST_COLOR || 220 srcRGB == PIPE_BLENDFACTOR_DST_ALPHA || 221 srcRGB == PIPE_BLENDFACTOR_INV_DST_COLOR || 222 srcRGB == PIPE_BLENDFACTOR_INV_DST_ALPHA || 223 srcA == PIPE_BLENDFACTOR_DST_COLOR || 224 srcA == PIPE_BLENDFACTOR_DST_ALPHA || 225 srcA == PIPE_BLENDFACTOR_INV_DST_COLOR || 226 srcA == PIPE_BLENDFACTOR_INV_DST_ALPHA || 227 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE) { 228 /* Enable reading from the colorbuffer. */ 229 blend_control |= R300_READ_ENABLE; 230 231 if (r300screen->caps.is_r500) { 232 /* Optimization: Depending on incoming pixels, we can 233 * conditionally disable the reading in hardware... */ 234 if (eqRGB != PIPE_BLEND_MIN && eqA != PIPE_BLEND_MIN && 235 eqRGB != PIPE_BLEND_MAX && eqA != PIPE_BLEND_MAX) { 236 /* Disable reading if SRC_ALPHA == 0. */ 237 if ((dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA || 238 dstRGB == PIPE_BLENDFACTOR_ZERO) && 239 (dstA == PIPE_BLENDFACTOR_SRC_COLOR || 240 dstA == PIPE_BLENDFACTOR_SRC_ALPHA || 241 dstA == PIPE_BLENDFACTOR_ZERO)) { 242 blend_control |= R500_SRC_ALPHA_0_NO_READ; 243 } 244 245 /* Disable reading if SRC_ALPHA == 1. */ 246 if ((dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 247 dstRGB == PIPE_BLENDFACTOR_ZERO) && 248 (dstA == PIPE_BLENDFACTOR_INV_SRC_COLOR || 249 dstA == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 250 dstA == PIPE_BLENDFACTOR_ZERO)) { 251 blend_control |= R500_SRC_ALPHA_1_NO_READ; 252 } 253 } 254 } 255 } 256 257 /* Optimization: discard pixels which don't change the colorbuffer. 258 * 259 * The code below is non-trivial and some math is involved. 260 * 261 * Discarding pixels must be disabled when FP16 AA is enabled. 262 * This is a hardware bug. Also, this implementation wouldn't work 263 * with FP blending enabled and equation clamping disabled. 264 * 265 * Equations other than ADD are rarely used and therefore won't be 266 * optimized. */ 267 if ((eqRGB == PIPE_BLEND_ADD || eqRGB == PIPE_BLEND_REVERSE_SUBTRACT) && 268 (eqA == PIPE_BLEND_ADD || eqA == PIPE_BLEND_REVERSE_SUBTRACT)) { 269 /* ADD: X+Y 270 * REVERSE_SUBTRACT: Y-X 271 * 272 * The idea is: 273 * If X = src*srcFactor = 0 and Y = dst*dstFactor = 1, 274 * then CB will not be changed. 275 * 276 * Given the srcFactor and dstFactor variables, we can derive 277 * what src and dst should be equal to and discard appropriate 278 * pixels. 279 */ 280 if (blend_discard_if_src_alpha_0(srcRGB, srcA, dstRGB, dstA)) { 281 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_ALPHA_0; 282 } else if (blend_discard_if_src_alpha_1(srcRGB, srcA, 283 dstRGB, dstA)) { 284 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_ALPHA_1; 285 } else if (blend_discard_if_src_color_0(srcRGB, srcA, 286 dstRGB, dstA)) { 287 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_COLOR_0; 288 } else if (blend_discard_if_src_color_1(srcRGB, srcA, 289 dstRGB, dstA)) { 290 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_COLOR_1; 291 } else if (blend_discard_if_src_alpha_color_0(srcRGB, srcA, 292 dstRGB, dstA)) { 293 blend_control |= 294 R300_DISCARD_SRC_PIXELS_SRC_ALPHA_COLOR_0; 295 } else if (blend_discard_if_src_alpha_color_1(srcRGB, srcA, 296 dstRGB, dstA)) { 297 blend_control |= 298 R300_DISCARD_SRC_PIXELS_SRC_ALPHA_COLOR_1; 299 } 300 } 301 302 /* separate alpha */ 303 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) { 304 blend_control |= R300_SEPARATE_ALPHA_ENABLE; 305 alpha_blend_control = 306 r300_translate_blend_function(eqA) | 307 (r300_translate_blend_factor(srcA) << R300_SRC_BLEND_SHIFT) | 308 (r300_translate_blend_factor(dstA) << R300_DST_BLEND_SHIFT); 309 } 310 } 311 312 /* PIPE_LOGICOP_* don't need to be translated, fortunately. */ 313 if (state->logicop_enable) { 314 rop = R300_RB3D_ROPCNTL_ROP_ENABLE | 315 (state->logicop_func) << R300_RB3D_ROPCNTL_ROP_SHIFT; 316 } 317 318 /* Color channel masks for all MRTs. */ 319 color_channel_mask = bgra_cmask(state->rt[0].colormask); 320 if (r300screen->caps.is_r500 && state->independent_blend_enable) { 321 if (state->rt[1].blend_enable) { 322 color_channel_mask |= bgra_cmask(state->rt[1].colormask) << 4; 323 } 324 if (state->rt[2].blend_enable) { 325 color_channel_mask |= bgra_cmask(state->rt[2].colormask) << 8; 326 } 327 if (state->rt[3].blend_enable) { 328 color_channel_mask |= bgra_cmask(state->rt[3].colormask) << 12; 329 } 330 } 331 332 /* Neither fglrx nor classic r300 ever set this, regardless of dithering 333 * state. Since it's an optional implementation detail, we can leave it 334 * out and never dither. 335 * 336 * This could be revisited if we ever get quality or conformance hints. 337 * 338 if (state->dither) { 339 dither = R300_RB3D_DITHER_CTL_DITHER_MODE_LUT | 340 R300_RB3D_DITHER_CTL_ALPHA_DITHER_MODE_LUT; 341 } 342 */ 343 344 /* Build a command buffer. */ 345 BEGIN_CB(blend->cb, 8); 346 OUT_CB_REG(R300_RB3D_ROPCNTL, rop); 347 OUT_CB_REG_SEQ(R300_RB3D_CBLEND, 3); 348 OUT_CB(blend_control); 349 OUT_CB(alpha_blend_control); 350 OUT_CB(color_channel_mask); 351 OUT_CB_REG(R300_RB3D_DITHER_CTL, dither); 352 END_CB; 353 354 /* The same as above, but with no colorbuffer reads and writes. */ 355 BEGIN_CB(blend->cb_no_readwrite, 8); 356 OUT_CB_REG(R300_RB3D_ROPCNTL, rop); 357 OUT_CB_REG_SEQ(R300_RB3D_CBLEND, 3); 358 OUT_CB(0); 359 OUT_CB(0); 360 OUT_CB(0); 361 OUT_CB_REG(R300_RB3D_DITHER_CTL, dither); 362 END_CB; 363 364 return (void*)blend; 365} 366 367/* Bind blend state. */ 368static void r300_bind_blend_state(struct pipe_context* pipe, 369 void* state) 370{ 371 struct r300_context* r300 = r300_context(pipe); 372 373 UPDATE_STATE(state, r300->blend_state); 374} 375 376/* Free blend state. */ 377static void r300_delete_blend_state(struct pipe_context* pipe, 378 void* state) 379{ 380 FREE(state); 381} 382 383/* Convert float to 10bit integer */ 384static unsigned float_to_fixed10(float f) 385{ 386 return CLAMP((unsigned)(f * 1023.9f), 0, 1023); 387} 388 389/* Set blend color. 390 * Setup both R300 and R500 registers, figure out later which one to write. */ 391static void r300_set_blend_color(struct pipe_context* pipe, 392 const struct pipe_blend_color* color) 393{ 394 struct r300_context* r300 = r300_context(pipe); 395 struct r300_blend_color_state* state = 396 (struct r300_blend_color_state*)r300->blend_color_state.state; 397 CB_LOCALS; 398 399 if (r300->screen->caps.is_r500) { 400 /* XXX if FP16 blending is enabled, we should use the FP16 format */ 401 BEGIN_CB(state->cb, 3); 402 OUT_CB_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR, 2); 403 OUT_CB(float_to_fixed10(color->color[0]) | 404 (float_to_fixed10(color->color[3]) << 16)); 405 OUT_CB(float_to_fixed10(color->color[2]) | 406 (float_to_fixed10(color->color[1]) << 16)); 407 END_CB; 408 } else { 409 union util_color uc; 410 util_pack_color(color->color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc); 411 412 BEGIN_CB(state->cb, 2); 413 OUT_CB_REG(R300_RB3D_BLEND_COLOR, uc.ui); 414 END_CB; 415 } 416 417 r300->blend_color_state.dirty = TRUE; 418} 419 420static void r300_set_clip_state(struct pipe_context* pipe, 421 const struct pipe_clip_state* state) 422{ 423 struct r300_context* r300 = r300_context(pipe); 424 struct r300_clip_state *clip = 425 (struct r300_clip_state*)r300->clip_state.state; 426 CB_LOCALS; 427 428 clip->clip = *state; 429 430 if (r300->screen->caps.has_tcl) { 431 BEGIN_CB(clip->cb, 29); 432 OUT_CB_REG(R300_VAP_PVS_VECTOR_INDX_REG, 433 (r300->screen->caps.is_r500 ? 434 R500_PVS_UCP_START : R300_PVS_UCP_START)); 435 OUT_CB_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, 6 * 4); 436 OUT_CB_TABLE(state->ucp, 6 * 4); 437 OUT_CB_REG(R300_VAP_CLIP_CNTL, ((1 << state->nr) - 1) | 438 R300_PS_UCP_MODE_CLIP_AS_TRIFAN); 439 END_CB; 440 441 r300->clip_state.dirty = TRUE; 442 } else { 443 draw_flush(r300->draw); 444 draw_set_clip_state(r300->draw, state); 445 } 446} 447 448static void 449r300_set_sample_mask(struct pipe_context *pipe, 450 unsigned sample_mask) 451{ 452} 453 454 455/* Create a new depth, stencil, and alpha state based on the CSO dsa state. 456 * 457 * This contains the depth buffer, stencil buffer, alpha test, and such. 458 * On the Radeon, depth and stencil buffer setup are intertwined, which is 459 * the reason for some of the strange-looking assignments across registers. */ 460static void* 461 r300_create_dsa_state(struct pipe_context* pipe, 462 const struct pipe_depth_stencil_alpha_state* state) 463{ 464 struct r300_capabilities *caps = &r300_screen(pipe->screen)->caps; 465 struct r300_dsa_state* dsa = CALLOC_STRUCT(r300_dsa_state); 466 CB_LOCALS; 467 468 dsa->dsa = *state; 469 470 /* Depth test setup. */ 471 if (state->depth.enabled) { 472 dsa->z_buffer_control |= R300_Z_ENABLE; 473 474 if (state->depth.writemask) { 475 dsa->z_buffer_control |= R300_Z_WRITE_ENABLE; 476 } 477 478 dsa->z_stencil_control |= 479 (r300_translate_depth_stencil_function(state->depth.func) << 480 R300_Z_FUNC_SHIFT); 481 } 482 483 /* Stencil buffer setup. */ 484 if (state->stencil[0].enabled) { 485 dsa->z_buffer_control |= R300_STENCIL_ENABLE; 486 dsa->z_stencil_control |= 487 (r300_translate_depth_stencil_function(state->stencil[0].func) << 488 R300_S_FRONT_FUNC_SHIFT) | 489 (r300_translate_stencil_op(state->stencil[0].fail_op) << 490 R300_S_FRONT_SFAIL_OP_SHIFT) | 491 (r300_translate_stencil_op(state->stencil[0].zpass_op) << 492 R300_S_FRONT_ZPASS_OP_SHIFT) | 493 (r300_translate_stencil_op(state->stencil[0].zfail_op) << 494 R300_S_FRONT_ZFAIL_OP_SHIFT); 495 496 dsa->stencil_ref_mask = 497 (state->stencil[0].valuemask << R300_STENCILMASK_SHIFT) | 498 (state->stencil[0].writemask << R300_STENCILWRITEMASK_SHIFT); 499 500 if (state->stencil[1].enabled) { 501 dsa->two_sided = TRUE; 502 503 dsa->z_buffer_control |= R300_STENCIL_FRONT_BACK; 504 dsa->z_stencil_control |= 505 (r300_translate_depth_stencil_function(state->stencil[1].func) << 506 R300_S_BACK_FUNC_SHIFT) | 507 (r300_translate_stencil_op(state->stencil[1].fail_op) << 508 R300_S_BACK_SFAIL_OP_SHIFT) | 509 (r300_translate_stencil_op(state->stencil[1].zpass_op) << 510 R300_S_BACK_ZPASS_OP_SHIFT) | 511 (r300_translate_stencil_op(state->stencil[1].zfail_op) << 512 R300_S_BACK_ZFAIL_OP_SHIFT); 513 514 dsa->stencil_ref_bf = 515 (state->stencil[1].valuemask << R300_STENCILMASK_SHIFT) | 516 (state->stencil[1].writemask << R300_STENCILWRITEMASK_SHIFT); 517 518 if (caps->is_r500) { 519 dsa->z_buffer_control |= R500_STENCIL_REFMASK_FRONT_BACK; 520 } else { 521 dsa->two_sided_stencil_ref = 522 (state->stencil[0].valuemask != state->stencil[1].valuemask || 523 state->stencil[0].writemask != state->stencil[1].writemask); 524 } 525 } 526 } 527 528 /* Alpha test setup. */ 529 if (state->alpha.enabled) { 530 dsa->alpha_function = 531 r300_translate_alpha_function(state->alpha.func) | 532 R300_FG_ALPHA_FUNC_ENABLE; 533 534 /* We could use 10bit alpha ref but who needs that? */ 535 dsa->alpha_function |= float_to_ubyte(state->alpha.ref_value); 536 537 if (caps->is_r500) 538 dsa->alpha_function |= R500_FG_ALPHA_FUNC_8BIT; 539 } 540 541 BEGIN_CB(&dsa->cb_begin, 8); 542 OUT_CB_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function); 543 OUT_CB_REG_SEQ(R300_ZB_CNTL, 3); 544 OUT_CB(dsa->z_buffer_control); 545 OUT_CB(dsa->z_stencil_control); 546 OUT_CB(dsa->stencil_ref_mask); 547 OUT_CB_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf); 548 END_CB; 549 550 BEGIN_CB(dsa->cb_no_readwrite, 8); 551 OUT_CB_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function); 552 OUT_CB_REG_SEQ(R300_ZB_CNTL, 3); 553 OUT_CB(0); 554 OUT_CB(0); 555 OUT_CB(0); 556 OUT_CB_REG(R500_ZB_STENCILREFMASK_BF, 0); 557 END_CB; 558 559 return (void*)dsa; 560} 561 562static void r300_dsa_inject_stencilref(struct r300_context *r300) 563{ 564 struct r300_dsa_state *dsa = 565 (struct r300_dsa_state*)r300->dsa_state.state; 566 567 if (!dsa) 568 return; 569 570 dsa->stencil_ref_mask = 571 (dsa->stencil_ref_mask & ~R300_STENCILREF_MASK) | 572 r300->stencil_ref.ref_value[0]; 573 dsa->stencil_ref_bf = 574 (dsa->stencil_ref_bf & ~R300_STENCILREF_MASK) | 575 r300->stencil_ref.ref_value[1]; 576} 577 578/* Bind DSA state. */ 579static void r300_bind_dsa_state(struct pipe_context* pipe, 580 void* state) 581{ 582 struct r300_context* r300 = r300_context(pipe); 583 584 if (!state) { 585 return; 586 } 587 588 UPDATE_STATE(state, r300->dsa_state); 589 590 r300_dsa_inject_stencilref(r300); 591} 592 593/* Free DSA state. */ 594static void r300_delete_dsa_state(struct pipe_context* pipe, 595 void* state) 596{ 597 FREE(state); 598} 599 600static void r300_set_stencil_ref(struct pipe_context* pipe, 601 const struct pipe_stencil_ref* sr) 602{ 603 struct r300_context* r300 = r300_context(pipe); 604 605 r300->stencil_ref = *sr; 606 607 r300_dsa_inject_stencilref(r300); 608 r300->dsa_state.dirty = TRUE; 609} 610 611/* This switcheroo is needed just because of goddamned MACRO_SWITCH. */ 612static void r300_fb_set_tiling_flags(struct r300_context *r300, 613 const struct pipe_framebuffer_state *old_state, 614 const struct pipe_framebuffer_state *new_state) 615{ 616 struct r300_texture *tex; 617 unsigned i, level; 618 619 /* Set tiling flags for new surfaces. */ 620 for (i = 0; i < new_state->nr_cbufs; i++) { 621 tex = r300_texture(new_state->cbufs[i]->texture); 622 level = new_state->cbufs[i]->level; 623 624 r300->rws->buffer_set_tiling(r300->rws, tex->buffer, 625 tex->pitch[0] * util_format_get_blocksize(tex->b.b.format), 626 tex->microtile, 627 tex->mip_macrotile[level]); 628 } 629 if (new_state->zsbuf) { 630 tex = r300_texture(new_state->zsbuf->texture); 631 level = new_state->zsbuf->level; 632 633 r300->rws->buffer_set_tiling(r300->rws, tex->buffer, 634 tex->pitch[0] * util_format_get_blocksize(tex->b.b.format), 635 tex->microtile, 636 tex->mip_macrotile[level]); 637 } 638} 639 640static void r300_print_fb_surf_info(struct pipe_surface *surf, unsigned index, 641 const char *binding) 642{ 643 struct pipe_resource *tex = surf->texture; 644 struct r300_texture *rtex = r300_texture(tex); 645 646 fprintf(stderr, 647 "r300: %s[%i] Dim: %ix%i, Offset: %i, ZSlice: %i, " 648 "Face: %i, Level: %i, Format: %s\n" 649 650 "r300: TEX: Macro: %s, Micro: %s, Pitch: %i, " 651 "Dim: %ix%ix%i, LastLevel: %i, Format: %s\n", 652 653 binding, index, surf->width, surf->height, surf->offset, 654 surf->zslice, surf->face, surf->level, 655 util_format_short_name(surf->format), 656 657 rtex->macrotile ? "YES" : " NO", rtex->microtile ? "YES" : " NO", 658 rtex->hwpitch[0], tex->width0, tex->height0, tex->depth0, 659 tex->last_level, util_format_short_name(tex->format)); 660} 661 662static void 663 r300_set_framebuffer_state(struct pipe_context* pipe, 664 const struct pipe_framebuffer_state* state) 665{ 666 struct r300_context* r300 = r300_context(pipe); 667 struct r300_aa_state *aa = (struct r300_aa_state*)r300->aa_state.state; 668 struct pipe_framebuffer_state *old_state = r300->fb_state.state; 669 unsigned max_width, max_height, i; 670 uint32_t zbuffer_bpp = 0; 671 672 if (r300->screen->caps.is_r500) { 673 max_width = max_height = 4096; 674 } else if (r300->screen->caps.is_r400) { 675 max_width = max_height = 4021; 676 } else { 677 max_width = max_height = 2560; 678 } 679 680 if (state->width > max_width || state->height > max_height) { 681 fprintf(stderr, "r300: Implementation error: Render targets are too " 682 "big in %s, refusing to bind framebuffer state!\n", __FUNCTION__); 683 return; 684 } 685 686 if (r300->draw) { 687 draw_flush(r300->draw); 688 } 689 690 r300->gpu_flush.dirty = TRUE; 691 r300->aa_state.dirty = TRUE; 692 r300->fb_state.dirty = TRUE; 693 694 /* If nr_cbufs is changed from zero to non-zero or vice versa... */ 695 if (!!old_state->nr_cbufs != !!state->nr_cbufs) { 696 r300->blend_state.dirty = TRUE; 697 } 698 /* If zsbuf is set from NULL to non-NULL or vice versa.. */ 699 if (!!old_state->zsbuf != !!state->zsbuf) { 700 r300->dsa_state.dirty = TRUE; 701 } 702 703 /* The tiling flags are dependent on the surface miplevel, unfortunately. */ 704 r300_fb_set_tiling_flags(r300, r300->fb_state.state, state); 705 706 memcpy(r300->fb_state.state, state, sizeof(struct pipe_framebuffer_state)); 707 708 r300->fb_state.size = 709 7 + 710 (8 * state->nr_cbufs) + 711 (state->zsbuf ? (r300->screen->caps.has_hiz ? 22 : 18) : 0) + 712 (r300->rws->get_value(r300->rws, R300_VID_DRM_2_3_0) ? 3 : 0); 713 714 /* Polygon offset depends on the zbuffer bit depth. */ 715 if (state->zsbuf && r300->polygon_offset_enabled) { 716 switch (util_format_get_blocksize(state->zsbuf->texture->format)) { 717 case 2: 718 zbuffer_bpp = 16; 719 break; 720 case 4: 721 zbuffer_bpp = 24; 722 break; 723 } 724 725 if (r300->zbuffer_bpp != zbuffer_bpp) { 726 r300->zbuffer_bpp = zbuffer_bpp; 727 r300->rs_state.dirty = TRUE; 728 } 729 } 730 731 /* Set up AA config. */ 732 if (r300->rws->get_value(r300->rws, R300_VID_DRM_2_3_0)) { 733 if (state->nr_cbufs && state->cbufs[0]->texture->nr_samples > 1) { 734 aa->aa_config = R300_GB_AA_CONFIG_AA_ENABLE; 735 736 switch (state->cbufs[0]->texture->nr_samples) { 737 case 2: 738 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_2; 739 break; 740 case 3: 741 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_3; 742 break; 743 case 4: 744 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_4; 745 break; 746 case 6: 747 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_6; 748 break; 749 } 750 } else { 751 aa->aa_config = 0; 752 } 753 } 754 755 if (DBG_ON(r300, DBG_FB)) { 756 fprintf(stderr, "r300: set_framebuffer_state:\n"); 757 for (i = 0; i < state->nr_cbufs; i++) { 758 r300_print_fb_surf_info(state->cbufs[i], i, "CB"); 759 } 760 if (state->zsbuf) { 761 r300_print_fb_surf_info(state->zsbuf, 0, "ZB"); 762 } 763 } 764} 765 766/* Create fragment shader state. */ 767static void* r300_create_fs_state(struct pipe_context* pipe, 768 const struct pipe_shader_state* shader) 769{ 770 struct r300_fragment_shader* fs = NULL; 771 772 fs = (struct r300_fragment_shader*)CALLOC_STRUCT(r300_fragment_shader); 773 774 /* Copy state directly into shader. */ 775 fs->state = *shader; 776 fs->state.tokens = tgsi_dup_tokens(shader->tokens); 777 778 return (void*)fs; 779} 780 781void r300_mark_fs_code_dirty(struct r300_context *r300) 782{ 783 struct r300_fragment_shader* fs = r300_fs(r300); 784 785 r300->fs.dirty = TRUE; 786 r300->fs_rc_constant_state.dirty = TRUE; 787 r300->fs_constants.dirty = TRUE; 788 r300->fs.size = fs->shader->cb_code_size; 789 790 if (r300->screen->caps.is_r500) { 791 r300->fs_rc_constant_state.size = fs->shader->rc_state_count * 7; 792 r300->fs_constants.size = fs->shader->externals_count * 4 + 3; 793 } else { 794 r300->fs_rc_constant_state.size = fs->shader->rc_state_count * 5; 795 r300->fs_constants.size = fs->shader->externals_count * 4 + 1; 796 } 797} 798 799/* Bind fragment shader state. */ 800static void r300_bind_fs_state(struct pipe_context* pipe, void* shader) 801{ 802 struct r300_context* r300 = r300_context(pipe); 803 struct r300_fragment_shader* fs = (struct r300_fragment_shader*)shader; 804 805 if (fs == NULL) { 806 r300->fs.state = NULL; 807 return; 808 } 809 810 r300->fs.state = fs; 811 r300_pick_fragment_shader(r300); 812 r300_mark_fs_code_dirty(r300); 813 814 r300->rs_block_state.dirty = TRUE; /* Will be updated before the emission. */ 815} 816 817/* Delete fragment shader state. */ 818static void r300_delete_fs_state(struct pipe_context* pipe, void* shader) 819{ 820 struct r300_fragment_shader* fs = (struct r300_fragment_shader*)shader; 821 struct r300_fragment_shader_code *tmp, *ptr = fs->first; 822 823 while (ptr) { 824 tmp = ptr; 825 ptr = ptr->next; 826 rc_constants_destroy(&tmp->code.constants); 827 FREE(tmp->cb_code); 828 FREE(tmp); 829 } 830 FREE((void*)fs->state.tokens); 831 FREE(shader); 832} 833 834static void r300_set_polygon_stipple(struct pipe_context* pipe, 835 const struct pipe_poly_stipple* state) 836{ 837 /* XXX no idea how to set this up, but not terribly important */ 838} 839 840/* Create a new rasterizer state based on the CSO rasterizer state. 841 * 842 * This is a very large chunk of state, and covers most of the graphics 843 * backend (GB), geometry assembly (GA), and setup unit (SU) blocks. 844 * 845 * In a not entirely unironic sidenote, this state has nearly nothing to do 846 * with the actual block on the Radeon called the rasterizer (RS). */ 847static void* r300_create_rs_state(struct pipe_context* pipe, 848 const struct pipe_rasterizer_state* state) 849{ 850 struct r300_rs_state* rs = CALLOC_STRUCT(r300_rs_state); 851 int i; 852 float psiz; 853 uint32_t vap_control_status; /* R300_VAP_CNTL_STATUS: 0x2140 */ 854 uint32_t point_size; /* R300_GA_POINT_SIZE: 0x421c */ 855 uint32_t point_minmax; /* R300_GA_POINT_MINMAX: 0x4230 */ 856 uint32_t line_control; /* R300_GA_LINE_CNTL: 0x4234 */ 857 uint32_t polygon_offset_enable; /* R300_SU_POLY_OFFSET_ENABLE: 0x42b4 */ 858 uint32_t cull_mode; /* R300_SU_CULL_MODE: 0x42b8 */ 859 uint32_t line_stipple_config; /* R300_GA_LINE_STIPPLE_CONFIG: 0x4328 */ 860 uint32_t line_stipple_value; /* R300_GA_LINE_STIPPLE_VALUE: 0x4260 */ 861 uint32_t polygon_mode; /* R300_GA_POLY_MODE: 0x4288 */ 862 uint32_t clip_rule; /* R300_SC_CLIP_RULE: 0x43D0 */ 863 864 /* Specifies top of Raster pipe specific enable controls, 865 * i.e. texture coordinates stuffing for points, lines, triangles */ 866 uint32_t stuffing_enable; /* R300_GB_ENABLE: 0x4008 */ 867 868 /* Point sprites texture coordinates, 0: lower left, 1: upper right */ 869 float point_texcoord_left; /* R300_GA_POINT_S0: 0x4200 */ 870 float point_texcoord_bottom; /* R300_GA_POINT_T0: 0x4204 */ 871 float point_texcoord_right; /* R300_GA_POINT_S1: 0x4208 */ 872 float point_texcoord_top; /* R300_GA_POINT_T1: 0x420c */ 873 CB_LOCALS; 874 875 /* Copy rasterizer state. */ 876 rs->rs = *state; 877 rs->rs_draw = *state; 878 879 /* Override some states for Draw. */ 880 rs->rs_draw.sprite_coord_enable = 0; /* We can do this in HW. */ 881 882#ifdef PIPE_ARCH_LITTLE_ENDIAN 883 vap_control_status = R300_VC_NO_SWAP; 884#else 885 vap_control_status = R300_VC_32BIT_SWAP; 886#endif 887 888 /* If no TCL engine is present, turn off the HW TCL. */ 889 if (!r300_screen(pipe->screen)->caps.has_tcl) { 890 vap_control_status |= R300_VAP_TCL_BYPASS; 891 } 892 893 /* Point size width and height. */ 894 point_size = 895 pack_float_16_6x(state->point_size) | 896 (pack_float_16_6x(state->point_size) << R300_POINTSIZE_X_SHIFT); 897 898 /* Point size clamping. */ 899 if (state->point_size_per_vertex) { 900 /* Per-vertex point size. 901 * Clamp to [0, max FB size] */ 902 psiz = pipe->screen->get_paramf(pipe->screen, 903 PIPE_CAP_MAX_POINT_WIDTH); 904 point_minmax = 905 pack_float_16_6x(psiz) << R300_GA_POINT_MINMAX_MAX_SHIFT; 906 } else { 907 /* We cannot disable the point-size vertex output, 908 * so clamp it. */ 909 psiz = state->point_size; 910 point_minmax = 911 (pack_float_16_6x(psiz) << R300_GA_POINT_MINMAX_MIN_SHIFT) | 912 (pack_float_16_6x(psiz) << R300_GA_POINT_MINMAX_MAX_SHIFT); 913 } 914 915 /* Line control. */ 916 line_control = pack_float_16_6x(state->line_width) | 917 R300_GA_LINE_CNTL_END_TYPE_COMP; 918 919 /* Enable polygon mode */ 920 polygon_mode = 0; 921 if (state->fill_front != PIPE_POLYGON_MODE_FILL || 922 state->fill_back != PIPE_POLYGON_MODE_FILL) { 923 polygon_mode = R300_GA_POLY_MODE_DUAL; 924 } 925 926 /* Front face */ 927 if (state->front_ccw) 928 cull_mode = R300_FRONT_FACE_CCW; 929 else 930 cull_mode = R300_FRONT_FACE_CW; 931 932 /* Polygon offset */ 933 polygon_offset_enable = 0; 934 if (util_get_offset(state, state->fill_front)) { 935 polygon_offset_enable |= R300_FRONT_ENABLE; 936 } 937 if (util_get_offset(state, state->fill_back)) { 938 polygon_offset_enable |= R300_BACK_ENABLE; 939 } 940 941 rs->polygon_offset_enable = polygon_offset_enable != 0; 942 943 /* Polygon mode */ 944 if (polygon_mode) { 945 polygon_mode |= 946 r300_translate_polygon_mode_front(state->fill_front); 947 polygon_mode |= 948 r300_translate_polygon_mode_back(state->fill_back); 949 } 950 951 if (state->cull_face & PIPE_FACE_FRONT) { 952 cull_mode |= R300_CULL_FRONT; 953 } 954 if (state->cull_face & PIPE_FACE_BACK) { 955 cull_mode |= R300_CULL_BACK; 956 } 957 958 if (state->line_stipple_enable) { 959 line_stipple_config = 960 R300_GA_LINE_STIPPLE_CONFIG_LINE_RESET_LINE | 961 (fui((float)state->line_stipple_factor) & 962 R300_GA_LINE_STIPPLE_CONFIG_STIPPLE_SCALE_MASK); 963 /* XXX this might need to be scaled up */ 964 line_stipple_value = state->line_stipple_pattern; 965 } 966 967 if (state->flatshade) { 968 rs->color_control = R300_SHADE_MODEL_FLAT; 969 } else { 970 rs->color_control = R300_SHADE_MODEL_SMOOTH; 971 } 972 973 clip_rule = state->scissor ? 0xAAAA : 0xFFFF; 974 975 /* Point sprites */ 976 stuffing_enable = 0; 977 if (state->sprite_coord_enable) { 978 stuffing_enable = R300_GB_POINT_STUFF_ENABLE; 979 for (i = 0; i < 8; i++) { 980 if (state->sprite_coord_enable & (1 << i)) 981 stuffing_enable |= 982 R300_GB_TEX_STR << (R300_GB_TEX0_SOURCE_SHIFT + (i*2)); 983 } 984 985 point_texcoord_left = 0.0f; 986 point_texcoord_right = 1.0f; 987 988 switch (state->sprite_coord_mode) { 989 case PIPE_SPRITE_COORD_UPPER_LEFT: 990 point_texcoord_top = 0.0f; 991 point_texcoord_bottom = 1.0f; 992 break; 993 case PIPE_SPRITE_COORD_LOWER_LEFT: 994 point_texcoord_top = 1.0f; 995 point_texcoord_bottom = 0.0f; 996 break; 997 } 998 } 999 1000 /* Build the main command buffer. */ 1001 BEGIN_CB(rs->cb_main, 25); 1002 OUT_CB_REG(R300_VAP_CNTL_STATUS, vap_control_status); 1003 OUT_CB_REG(R300_GA_POINT_SIZE, point_size); 1004 OUT_CB_REG_SEQ(R300_GA_POINT_MINMAX, 2); 1005 OUT_CB(point_minmax); 1006 OUT_CB(line_control); 1007 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_ENABLE, 2); 1008 OUT_CB(polygon_offset_enable); 1009 rs->cull_mode_index = 25 - cs_count; 1010 OUT_CB(cull_mode); 1011 OUT_CB_REG(R300_GA_LINE_STIPPLE_CONFIG, line_stipple_config); 1012 OUT_CB_REG(R300_GA_LINE_STIPPLE_VALUE, line_stipple_value); 1013 OUT_CB_REG(R300_GA_POLY_MODE, polygon_mode); 1014 OUT_CB_REG(R300_SC_CLIP_RULE, clip_rule); 1015 OUT_CB_REG(R300_GB_ENABLE, stuffing_enable); 1016 OUT_CB_REG_SEQ(R300_GA_POINT_S0, 4); 1017 OUT_CB_32F(point_texcoord_left); 1018 OUT_CB_32F(point_texcoord_bottom); 1019 OUT_CB_32F(point_texcoord_right); 1020 OUT_CB_32F(point_texcoord_top); 1021 END_CB; 1022 1023 /* Build the two command buffers for polygon offset setup. */ 1024 if (polygon_offset_enable) { 1025 float scale = state->offset_scale * 12; 1026 float offset = state->offset_units * 4; 1027 1028 BEGIN_CB(rs->cb_poly_offset_zb16, 5); 1029 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4); 1030 OUT_CB_32F(scale); 1031 OUT_CB_32F(offset); 1032 OUT_CB_32F(scale); 1033 OUT_CB_32F(offset); 1034 END_CB; 1035 1036 offset = state->offset_units * 2; 1037 1038 BEGIN_CB(rs->cb_poly_offset_zb24, 5); 1039 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4); 1040 OUT_CB_32F(scale); 1041 OUT_CB_32F(offset); 1042 OUT_CB_32F(scale); 1043 OUT_CB_32F(offset); 1044 END_CB; 1045 } 1046 1047 return (void*)rs; 1048} 1049 1050/* Bind rasterizer state. */ 1051static void r300_bind_rs_state(struct pipe_context* pipe, void* state) 1052{ 1053 struct r300_context* r300 = r300_context(pipe); 1054 struct r300_rs_state* rs = (struct r300_rs_state*)state; 1055 int last_sprite_coord_enable = r300->sprite_coord_enable; 1056 boolean last_two_sided_color = r300->two_sided_color; 1057 1058 if (r300->draw && rs) { 1059 draw_flush(r300->draw); 1060 draw_set_rasterizer_state(r300->draw, &rs->rs_draw, state); 1061 } 1062 1063 if (rs) { 1064 r300->polygon_offset_enabled = (rs->rs.offset_point || 1065 rs->rs.offset_line || 1066 rs->rs.offset_tri); 1067 r300->sprite_coord_enable = rs->rs.sprite_coord_enable; 1068 r300->two_sided_color = rs->rs.light_twoside; 1069 } else { 1070 r300->polygon_offset_enabled = FALSE; 1071 r300->sprite_coord_enable = 0; 1072 r300->two_sided_color = FALSE; 1073 } 1074 1075 UPDATE_STATE(state, r300->rs_state); 1076 r300->rs_state.size = 25 + (r300->polygon_offset_enabled ? 5 : 0); 1077 1078 if (last_sprite_coord_enable != r300->sprite_coord_enable || 1079 last_two_sided_color != r300->two_sided_color) { 1080 r300->rs_block_state.dirty = TRUE; 1081 } 1082} 1083 1084/* Free rasterizer state. */ 1085static void r300_delete_rs_state(struct pipe_context* pipe, void* state) 1086{ 1087 FREE(state); 1088} 1089 1090static void* 1091 r300_create_sampler_state(struct pipe_context* pipe, 1092 const struct pipe_sampler_state* state) 1093{ 1094 struct r300_context* r300 = r300_context(pipe); 1095 struct r300_sampler_state* sampler = CALLOC_STRUCT(r300_sampler_state); 1096 boolean is_r500 = r300->screen->caps.is_r500; 1097 int lod_bias; 1098 union util_color uc; 1099 1100 sampler->state = *state; 1101 1102 /* r300 doesn't handle CLAMP and MIRROR_CLAMP correctly when either MAG 1103 * or MIN filter is NEAREST. Since texwrap produces same results 1104 * for CLAMP and CLAMP_TO_EDGE, we use them instead. */ 1105 if (sampler->state.min_img_filter == PIPE_TEX_FILTER_NEAREST || 1106 sampler->state.mag_img_filter == PIPE_TEX_FILTER_NEAREST) { 1107 /* Wrap S. */ 1108 if (sampler->state.wrap_s == PIPE_TEX_WRAP_CLAMP) 1109 sampler->state.wrap_s = PIPE_TEX_WRAP_CLAMP_TO_EDGE; 1110 else if (sampler->state.wrap_s == PIPE_TEX_WRAP_MIRROR_CLAMP) 1111 sampler->state.wrap_s = PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE; 1112 1113 /* Wrap T. */ 1114 if (sampler->state.wrap_t == PIPE_TEX_WRAP_CLAMP) 1115 sampler->state.wrap_t = PIPE_TEX_WRAP_CLAMP_TO_EDGE; 1116 else if (sampler->state.wrap_t == PIPE_TEX_WRAP_MIRROR_CLAMP) 1117 sampler->state.wrap_t = PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE; 1118 1119 /* Wrap R. */ 1120 if (sampler->state.wrap_r == PIPE_TEX_WRAP_CLAMP) 1121 sampler->state.wrap_r = PIPE_TEX_WRAP_CLAMP_TO_EDGE; 1122 else if (sampler->state.wrap_r == PIPE_TEX_WRAP_MIRROR_CLAMP) 1123 sampler->state.wrap_r = PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE; 1124 } 1125 1126 sampler->filter0 |= 1127 (r300_translate_wrap(sampler->state.wrap_s) << R300_TX_WRAP_S_SHIFT) | 1128 (r300_translate_wrap(sampler->state.wrap_t) << R300_TX_WRAP_T_SHIFT) | 1129 (r300_translate_wrap(sampler->state.wrap_r) << R300_TX_WRAP_R_SHIFT); 1130 1131 sampler->filter0 |= r300_translate_tex_filters(state->min_img_filter, 1132 state->mag_img_filter, 1133 state->min_mip_filter, 1134 state->max_anisotropy > 0); 1135 1136 sampler->filter0 |= r300_anisotropy(state->max_anisotropy); 1137 1138 /* Unfortunately, r300-r500 don't support floating-point mipmap lods. */ 1139 /* We must pass these to the merge function to clamp them properly. */ 1140 sampler->min_lod = MAX2((unsigned)state->min_lod, 0); 1141 sampler->max_lod = MAX2((unsigned)ceilf(state->max_lod), 0); 1142 1143 lod_bias = CLAMP((int)(state->lod_bias * 32 + 1), -(1 << 9), (1 << 9) - 1); 1144 1145 sampler->filter1 |= lod_bias << R300_LOD_BIAS_SHIFT; 1146 1147 /* This is very high quality anisotropic filtering for R5xx. 1148 * It's good for benchmarking the performance of texturing but 1149 * in practice we don't want to slow down the driver because it's 1150 * a pretty good performance killer. Feel free to play with it. */ 1151 if (DBG_ON(r300, DBG_ANISOHQ) && is_r500) { 1152 sampler->filter1 |= r500_anisotropy(state->max_anisotropy); 1153 } 1154 1155 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc); 1156 sampler->border_color = uc.ui; 1157 1158 /* R500-specific fixups and optimizations */ 1159 if (r300->screen->caps.is_r500) { 1160 sampler->filter1 |= R500_BORDER_FIX; 1161 } 1162 1163 return (void*)sampler; 1164} 1165 1166static void r300_bind_sampler_states(struct pipe_context* pipe, 1167 unsigned count, 1168 void** states) 1169{ 1170 struct r300_context* r300 = r300_context(pipe); 1171 struct r300_textures_state* state = 1172 (struct r300_textures_state*)r300->textures_state.state; 1173 unsigned tex_units = r300->screen->caps.num_tex_units; 1174 1175 if (count > tex_units) { 1176 return; 1177 } 1178 1179 memcpy(state->sampler_states, states, sizeof(void*) * count); 1180 state->sampler_state_count = count; 1181 1182 r300->textures_state.dirty = TRUE; 1183} 1184 1185static void r300_lacks_vertex_textures(struct pipe_context* pipe, 1186 unsigned count, 1187 void** states) 1188{ 1189} 1190 1191static void r300_delete_sampler_state(struct pipe_context* pipe, void* state) 1192{ 1193 FREE(state); 1194} 1195 1196static uint32_t r300_assign_texture_cache_region(unsigned index, unsigned num) 1197{ 1198 /* This looks like a hack, but I believe it's suppose to work like 1199 * that. To illustrate how this works, let's assume you have 5 textures. 1200 * From docs, 5 and the successive numbers are: 1201 * 1202 * FOURTH_1 = 5 1203 * FOURTH_2 = 6 1204 * FOURTH_3 = 7 1205 * EIGHTH_0 = 8 1206 * EIGHTH_1 = 9 1207 * 1208 * First 3 textures will get 3/4 of size of the cache, divived evenly 1209 * between them. The last 1/4 of the cache must be divided between 1210 * the last 2 textures, each will therefore get 1/8 of the cache. 1211 * Why not just to use "5 + texture_index" ? 1212 * 1213 * This simple trick works for all "num" <= 16. 1214 */ 1215 if (num <= 1) 1216 return R300_TX_CACHE(R300_TX_CACHE_WHOLE); 1217 else 1218 return R300_TX_CACHE(num + index); 1219} 1220 1221static void r300_set_fragment_sampler_views(struct pipe_context* pipe, 1222 unsigned count, 1223 struct pipe_sampler_view** views) 1224{ 1225 struct r300_context* r300 = r300_context(pipe); 1226 struct r300_textures_state* state = 1227 (struct r300_textures_state*)r300->textures_state.state; 1228 struct r300_texture *texture; 1229 unsigned i, real_num_views = 0, view_index = 0; 1230 unsigned tex_units = r300->screen->caps.num_tex_units; 1231 boolean dirty_tex = FALSE; 1232 1233 if (count > tex_units) { 1234 return; 1235 } 1236 1237 /* Calculate the real number of views. */ 1238 for (i = 0; i < count; i++) { 1239 if (views[i]) 1240 real_num_views++; 1241 } 1242 1243 for (i = 0; i < count; i++) { 1244 if (&state->sampler_views[i]->base != views[i]) { 1245 pipe_sampler_view_reference( 1246 (struct pipe_sampler_view**)&state->sampler_views[i], 1247 views[i]); 1248 1249 if (!views[i]) { 1250 continue; 1251 } 1252 1253 /* A new sampler view (= texture)... */ 1254 dirty_tex = TRUE; 1255 1256 /* Set the texrect factor in the fragment shader. 1257 * Needed for RECT and NPOT fallback. */ 1258 texture = r300_texture(views[i]->texture); 1259 if (texture->uses_pitch) { 1260 r300->fs_rc_constant_state.dirty = TRUE; 1261 } 1262 1263 state->sampler_views[i]->texcache_region = 1264 r300_assign_texture_cache_region(view_index, real_num_views); 1265 view_index++; 1266 } 1267 } 1268 1269 for (i = count; i < tex_units; i++) { 1270 if (state->sampler_views[i]) { 1271 pipe_sampler_view_reference( 1272 (struct pipe_sampler_view**)&state->sampler_views[i], 1273 NULL); 1274 } 1275 } 1276 1277 state->sampler_view_count = count; 1278 1279 r300->textures_state.dirty = TRUE; 1280 1281 if (dirty_tex) { 1282 r300->texture_cache_inval.dirty = TRUE; 1283 } 1284} 1285 1286static struct pipe_sampler_view * 1287r300_create_sampler_view(struct pipe_context *pipe, 1288 struct pipe_resource *texture, 1289 const struct pipe_sampler_view *templ) 1290{ 1291 struct r300_sampler_view *view = CALLOC_STRUCT(r300_sampler_view); 1292 struct r300_texture *tex = r300_texture(texture); 1293 1294 if (view) { 1295 view->base = *templ; 1296 view->base.reference.count = 1; 1297 view->base.context = pipe; 1298 view->base.texture = NULL; 1299 pipe_resource_reference(&view->base.texture, texture); 1300 1301 view->swizzle[0] = templ->swizzle_r; 1302 view->swizzle[1] = templ->swizzle_g; 1303 view->swizzle[2] = templ->swizzle_b; 1304 view->swizzle[3] = templ->swizzle_a; 1305 1306 view->format = tex->tx_format; 1307 view->format.format1 |= r300_translate_texformat(templ->format, 1308 view->swizzle); 1309 if (r300_screen(pipe->screen)->caps.is_r500) { 1310 view->format.format2 |= r500_tx_format_msb_bit(templ->format); 1311 } 1312 } 1313 1314 return (struct pipe_sampler_view*)view; 1315} 1316 1317static void 1318r300_sampler_view_destroy(struct pipe_context *pipe, 1319 struct pipe_sampler_view *view) 1320{ 1321 pipe_resource_reference(&view->texture, NULL); 1322 FREE(view); 1323} 1324 1325static void r300_set_scissor_state(struct pipe_context* pipe, 1326 const struct pipe_scissor_state* state) 1327{ 1328 struct r300_context* r300 = r300_context(pipe); 1329 1330 memcpy(r300->scissor_state.state, state, 1331 sizeof(struct pipe_scissor_state)); 1332 1333 r300->scissor_state.dirty = TRUE; 1334} 1335 1336static void r300_set_viewport_state(struct pipe_context* pipe, 1337 const struct pipe_viewport_state* state) 1338{ 1339 struct r300_context* r300 = r300_context(pipe); 1340 struct r300_viewport_state* viewport = 1341 (struct r300_viewport_state*)r300->viewport_state.state; 1342 1343 r300->viewport = *state; 1344 1345 if (r300->draw) { 1346 draw_flush(r300->draw); 1347 draw_set_viewport_state(r300->draw, state); 1348 viewport->vte_control = R300_VTX_XY_FMT | R300_VTX_Z_FMT; 1349 return; 1350 } 1351 1352 /* Do the transform in HW. */ 1353 viewport->vte_control = R300_VTX_W0_FMT; 1354 1355 if (state->scale[0] != 1.0f) { 1356 viewport->xscale = state->scale[0]; 1357 viewport->vte_control |= R300_VPORT_X_SCALE_ENA; 1358 } 1359 if (state->scale[1] != 1.0f) { 1360 viewport->yscale = state->scale[1]; 1361 viewport->vte_control |= R300_VPORT_Y_SCALE_ENA; 1362 } 1363 if (state->scale[2] != 1.0f) { 1364 viewport->zscale = state->scale[2]; 1365 viewport->vte_control |= R300_VPORT_Z_SCALE_ENA; 1366 } 1367 if (state->translate[0] != 0.0f) { 1368 viewport->xoffset = state->translate[0]; 1369 viewport->vte_control |= R300_VPORT_X_OFFSET_ENA; 1370 } 1371 if (state->translate[1] != 0.0f) { 1372 viewport->yoffset = state->translate[1]; 1373 viewport->vte_control |= R300_VPORT_Y_OFFSET_ENA; 1374 } 1375 if (state->translate[2] != 0.0f) { 1376 viewport->zoffset = state->translate[2]; 1377 viewport->vte_control |= R300_VPORT_Z_OFFSET_ENA; 1378 } 1379 1380 r300->viewport_state.dirty = TRUE; 1381 if (r300->fs.state && r300_fs(r300)->shader->inputs.wpos != ATTR_UNUSED) { 1382 r300->fs_rc_constant_state.dirty = TRUE; 1383 } 1384} 1385 1386static void r300_set_vertex_buffers(struct pipe_context* pipe, 1387 unsigned count, 1388 const struct pipe_vertex_buffer* buffers) 1389{ 1390 struct r300_context* r300 = r300_context(pipe); 1391 struct pipe_vertex_buffer *vbo; 1392 unsigned i, max_index = (1 << 24) - 1; 1393 boolean any_user_buffer = FALSE; 1394 1395 if (count == r300->vertex_buffer_count && 1396 memcmp(r300->vertex_buffer, buffers, 1397 sizeof(struct pipe_vertex_buffer) * count) == 0) { 1398 return; 1399 } 1400 1401 if (r300->screen->caps.has_tcl) { 1402 /* HW TCL. */ 1403 r300->incompatible_vb_layout = FALSE; 1404 1405 /* Check if the strides and offsets are aligned to the size of DWORD. */ 1406 for (i = 0; i < count; i++) { 1407 if (buffers[i].buffer) { 1408 if (buffers[i].stride % 4 != 0 || 1409 buffers[i].buffer_offset % 4 != 0) { 1410 r300->incompatible_vb_layout = TRUE; 1411 break; 1412 } 1413 } 1414 } 1415 1416 for (i = 0; i < count; i++) { 1417 /* Why, yes, I AM casting away constness. How did you know? */ 1418 vbo = (struct pipe_vertex_buffer*)&buffers[i]; 1419 1420 /* Skip NULL buffers */ 1421 if (!buffers[i].buffer) { 1422 continue; 1423 } 1424 1425 if (r300_buffer_is_user_buffer(vbo->buffer)) { 1426 any_user_buffer = TRUE; 1427 } 1428 1429 if (vbo->max_index == ~0) { 1430 /* if no VBO stride then only one vertex value so max index is 1 */ 1431 /* should think about converting to VS constants like svga does */ 1432 if (!vbo->stride) 1433 vbo->max_index = 1; 1434 else 1435 vbo->max_index = 1436 (vbo->buffer->width0 - vbo->buffer_offset) / vbo->stride; 1437 } 1438 1439 max_index = MIN2(vbo->max_index, max_index); 1440 } 1441 1442 r300->any_user_vbs = any_user_buffer; 1443 r300->vertex_buffer_max_index = max_index; 1444 1445 } else { 1446 /* SW TCL. */ 1447 draw_flush(r300->draw); 1448 draw_set_vertex_buffers(r300->draw, count, buffers); 1449 } 1450 1451 /* Common code. */ 1452 for (i = 0; i < count; i++) { 1453 /* Reference our buffer. */ 1454 pipe_resource_reference(&r300->vertex_buffer[i].buffer, buffers[i].buffer); 1455 } 1456 for (; i < r300->vertex_buffer_count; i++) { 1457 /* Dereference any old buffers. */ 1458 pipe_resource_reference(&r300->vertex_buffer[i].buffer, NULL); 1459 } 1460 1461 memcpy(r300->vertex_buffer, buffers, 1462 sizeof(struct pipe_vertex_buffer) * count); 1463 r300->vertex_buffer_count = count; 1464} 1465 1466/* Initialize the PSC tables. */ 1467static void r300_vertex_psc(struct r300_vertex_element_state *velems) 1468{ 1469 struct r300_vertex_stream_state *vstream = &velems->vertex_stream; 1470 uint16_t type, swizzle; 1471 enum pipe_format format; 1472 unsigned i; 1473 1474 if (velems->count > 16) { 1475 fprintf(stderr, "r300: More than 16 vertex elements are not supported," 1476 " requested %i, using 16.\n", velems->count); 1477 velems->count = 16; 1478 } 1479 1480 /* Vertex shaders have no semantics on their inputs, 1481 * so PSC should just route stuff based on the vertex elements, 1482 * and not on attrib information. */ 1483 for (i = 0; i < velems->count; i++) { 1484 format = velems->hw_format[i]; 1485 1486 type = r300_translate_vertex_data_type(format); 1487 if (type == R300_INVALID_FORMAT) { 1488 fprintf(stderr, "r300: Bad vertex format %s.\n", 1489 util_format_short_name(format)); 1490 assert(0); 1491 abort(); 1492 } 1493 1494 type |= i << R300_DST_VEC_LOC_SHIFT; 1495 swizzle = r300_translate_vertex_data_swizzle(format); 1496 1497 if (i & 1) { 1498 vstream->vap_prog_stream_cntl[i >> 1] |= type << 16; 1499 vstream->vap_prog_stream_cntl_ext[i >> 1] |= swizzle << 16; 1500 } else { 1501 vstream->vap_prog_stream_cntl[i >> 1] |= type; 1502 vstream->vap_prog_stream_cntl_ext[i >> 1] |= swizzle; 1503 } 1504 } 1505 1506 /* Set the last vector in the PSC. */ 1507 if (i) { 1508 i -= 1; 1509 } 1510 vstream->vap_prog_stream_cntl[i >> 1] |= 1511 (R300_LAST_VEC << (i & 1 ? 16 : 0)); 1512 1513 vstream->count = (i >> 1) + 1; 1514} 1515 1516#define FORMAT_REPLACE(what, withwhat) \ 1517 case PIPE_FORMAT_##what: *format = PIPE_FORMAT_##withwhat; break 1518 1519static void* r300_create_vertex_elements_state(struct pipe_context* pipe, 1520 unsigned count, 1521 const struct pipe_vertex_element* attribs) 1522{ 1523 struct r300_vertex_element_state *velems; 1524 unsigned i; 1525 enum pipe_format *format; 1526 1527 assert(count <= PIPE_MAX_ATTRIBS); 1528 velems = CALLOC_STRUCT(r300_vertex_element_state); 1529 if (velems != NULL) { 1530 velems->count = count; 1531 memcpy(velems->velem, attribs, sizeof(struct pipe_vertex_element) * count); 1532 1533 if (r300_screen(pipe->screen)->caps.has_tcl) { 1534 /* Set the best hw format in case the original format is not 1535 * supported by hw. */ 1536 for (i = 0; i < count; i++) { 1537 velems->hw_format[i] = velems->velem[i].src_format; 1538 format = &velems->hw_format[i]; 1539 1540 /* This is basically the list of unsupported formats. 1541 * For now we don't care about the alignment, that's going to 1542 * be sorted out after the PSC setup. */ 1543 switch (*format) { 1544 FORMAT_REPLACE(R64_FLOAT, R32_FLOAT); 1545 FORMAT_REPLACE(R64G64_FLOAT, R32G32_FLOAT); 1546 FORMAT_REPLACE(R64G64B64_FLOAT, R32G32B32_FLOAT); 1547 FORMAT_REPLACE(R64G64B64A64_FLOAT, R32G32B32A32_FLOAT); 1548 1549 FORMAT_REPLACE(R32_UNORM, R32_FLOAT); 1550 FORMAT_REPLACE(R32G32_UNORM, R32G32_FLOAT); 1551 FORMAT_REPLACE(R32G32B32_UNORM, R32G32B32_FLOAT); 1552 FORMAT_REPLACE(R32G32B32A32_UNORM, R32G32B32A32_FLOAT); 1553 1554 FORMAT_REPLACE(R32_USCALED, R32_FLOAT); 1555 FORMAT_REPLACE(R32G32_USCALED, R32G32_FLOAT); 1556 FORMAT_REPLACE(R32G32B32_USCALED, R32G32B32_FLOAT); 1557 FORMAT_REPLACE(R32G32B32A32_USCALED,R32G32B32A32_FLOAT); 1558 1559 FORMAT_REPLACE(R32_SNORM, R32_FLOAT); 1560 FORMAT_REPLACE(R32G32_SNORM, R32G32_FLOAT); 1561 FORMAT_REPLACE(R32G32B32_SNORM, R32G32B32_FLOAT); 1562 FORMAT_REPLACE(R32G32B32A32_SNORM, R32G32B32A32_FLOAT); 1563 1564 FORMAT_REPLACE(R32_SSCALED, R32_FLOAT); 1565 FORMAT_REPLACE(R32G32_SSCALED, R32G32_FLOAT); 1566 FORMAT_REPLACE(R32G32B32_SSCALED, R32G32B32_FLOAT); 1567 FORMAT_REPLACE(R32G32B32A32_SSCALED,R32G32B32A32_FLOAT); 1568 1569 FORMAT_REPLACE(R32_FIXED, R32_FLOAT); 1570 FORMAT_REPLACE(R32G32_FIXED, R32G32_FLOAT); 1571 FORMAT_REPLACE(R32G32B32_FIXED, R32G32B32_FLOAT); 1572 FORMAT_REPLACE(R32G32B32A32_FIXED, R32G32B32A32_FLOAT); 1573 1574 default:; 1575 } 1576 1577 velems->incompatible_layout = 1578 velems->incompatible_layout || 1579 velems->velem[i].src_format != velems->hw_format[i] || 1580 velems->velem[i].src_offset % 4 != 0; 1581 } 1582 1583 /* Now setup PSC. 1584 * The unused components will be replaced by (..., 0, 1). */ 1585 r300_vertex_psc(velems); 1586 1587 /* Align the formats to the size of DWORD. 1588 * We only care about the blocksizes of the formats since 1589 * swizzles are already set up. 1590 * Also compute the vertex size. */ 1591 for (i = 0; i < count; i++) { 1592 /* This is OK because we check for aligned strides too. */ 1593 velems->hw_format_size[i] = 1594 align(util_format_get_blocksize(velems->hw_format[i]), 4); 1595 velems->vertex_size_dwords += velems->hw_format_size[i] / 4; 1596 } 1597 } 1598 } 1599 return velems; 1600} 1601 1602static void r300_bind_vertex_elements_state(struct pipe_context *pipe, 1603 void *state) 1604{ 1605 struct r300_context *r300 = r300_context(pipe); 1606 struct r300_vertex_element_state *velems = state; 1607 1608 if (velems == NULL) { 1609 return; 1610 } 1611 1612 r300->velems = velems; 1613 1614 if (r300->draw) { 1615 draw_flush(r300->draw); 1616 draw_set_vertex_elements(r300->draw, velems->count, velems->velem); 1617 return; 1618 } 1619 1620 UPDATE_STATE(&velems->vertex_stream, r300->vertex_stream_state); 1621 r300->vertex_stream_state.size = (1 + velems->vertex_stream.count) * 2; 1622} 1623 1624static void r300_delete_vertex_elements_state(struct pipe_context *pipe, void *state) 1625{ 1626 FREE(state); 1627} 1628 1629static void* r300_create_vs_state(struct pipe_context* pipe, 1630 const struct pipe_shader_state* shader) 1631{ 1632 struct r300_context* r300 = r300_context(pipe); 1633 struct r300_vertex_shader* vs = CALLOC_STRUCT(r300_vertex_shader); 1634 1635 /* Copy state directly into shader. */ 1636 vs->state = *shader; 1637 vs->state.tokens = tgsi_dup_tokens(shader->tokens); 1638 1639 if (r300->screen->caps.has_tcl) { 1640 r300_init_vs_outputs(vs); 1641 r300_translate_vertex_shader(r300, vs); 1642 } else { 1643 r300_draw_init_vertex_shader(r300->draw, vs); 1644 } 1645 1646 return vs; 1647} 1648 1649static void r300_bind_vs_state(struct pipe_context* pipe, void* shader) 1650{ 1651 struct r300_context* r300 = r300_context(pipe); 1652 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)shader; 1653 1654 if (vs == NULL) { 1655 r300->vs_state.state = NULL; 1656 return; 1657 } 1658 if (vs == r300->vs_state.state) { 1659 return; 1660 } 1661 r300->vs_state.state = vs; 1662 1663 /* The majority of the RS block bits is dependent on the vertex shader. */ 1664 r300->rs_block_state.dirty = TRUE; /* Will be updated before the emission. */ 1665 1666 if (r300->screen->caps.has_tcl) { 1667 r300->vs_state.dirty = TRUE; 1668 r300->vs_state.size = 1669 vs->code.length + 9 + 1670 (vs->immediates_count ? vs->immediates_count * 4 + 3 : 0); 1671 1672 if (vs->externals_count) { 1673 r300->vs_constants.dirty = TRUE; 1674 r300->vs_constants.size = vs->externals_count * 4 + 3; 1675 } else { 1676 r300->vs_constants.size = 0; 1677 } 1678 1679 r300->pvs_flush.dirty = TRUE; 1680 } else { 1681 draw_flush(r300->draw); 1682 draw_bind_vertex_shader(r300->draw, 1683 (struct draw_vertex_shader*)vs->draw_vs); 1684 } 1685} 1686 1687static void r300_delete_vs_state(struct pipe_context* pipe, void* shader) 1688{ 1689 struct r300_context* r300 = r300_context(pipe); 1690 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)shader; 1691 1692 if (r300->screen->caps.has_tcl) { 1693 rc_constants_destroy(&vs->code.constants); 1694 } else { 1695 draw_delete_vertex_shader(r300->draw, 1696 (struct draw_vertex_shader*)vs->draw_vs); 1697 } 1698 1699 FREE((void*)vs->state.tokens); 1700 FREE(shader); 1701} 1702 1703static void r300_set_constant_buffer(struct pipe_context *pipe, 1704 uint shader, uint index, 1705 struct pipe_resource *buf) 1706{ 1707 struct r300_context* r300 = r300_context(pipe); 1708 struct r300_constant_buffer *cbuf; 1709 struct pipe_transfer *tr; 1710 float *mapped; 1711 int max_size = 0, max_size_bytes = 0, clamped_size = 0; 1712 1713 switch (shader) { 1714 case PIPE_SHADER_VERTEX: 1715 cbuf = (struct r300_constant_buffer*)r300->vs_constants.state; 1716 max_size = 256; 1717 break; 1718 case PIPE_SHADER_FRAGMENT: 1719 cbuf = (struct r300_constant_buffer*)r300->fs_constants.state; 1720 if (r300->screen->caps.is_r500) { 1721 max_size = 256; 1722 } else { 1723 max_size = 32; 1724 } 1725 break; 1726 default: 1727 assert(0); 1728 return; 1729 } 1730 max_size_bytes = max_size * 4 * sizeof(float); 1731 1732 if (buf == NULL || buf->width0 == 0 || 1733 (mapped = pipe_buffer_map(pipe, buf, PIPE_TRANSFER_READ, &tr)) == NULL) 1734 { 1735 cbuf->count = 0; 1736 return; 1737 } 1738 1739 if (shader == PIPE_SHADER_FRAGMENT || 1740 (shader == PIPE_SHADER_VERTEX && r300->screen->caps.has_tcl)) { 1741 assert((buf->width0 % (4 * sizeof(float))) == 0); 1742 1743 /* Check the size of the constant buffer. */ 1744 /* XXX Subtract immediates and RC_STATE_* variables. */ 1745 if (buf->width0 > max_size_bytes) { 1746 fprintf(stderr, "r300: Max size of the constant buffer is " 1747 "%i*4 floats.\n", max_size); 1748 } 1749 1750 clamped_size = MIN2(buf->width0, max_size_bytes); 1751 cbuf->count = clamped_size / (4 * sizeof(float)); 1752 1753 if (shader == PIPE_SHADER_FRAGMENT && !r300->screen->caps.is_r500) { 1754 unsigned i,j; 1755 1756 /* Convert constants to float24. */ 1757 for (i = 0; i < cbuf->count; i++) 1758 for (j = 0; j < 4; j++) 1759 cbuf->constants[i][j] = pack_float24(mapped[i*4+j]); 1760 } else { 1761 memcpy(cbuf->constants, mapped, clamped_size); 1762 } 1763 } 1764 1765 if (shader == PIPE_SHADER_VERTEX) { 1766 if (r300->screen->caps.has_tcl) { 1767 if (r300->vs_constants.size) { 1768 r300->vs_constants.dirty = TRUE; 1769 } 1770 r300->pvs_flush.dirty = TRUE; 1771 } else if (r300->draw) { 1772 draw_set_mapped_constant_buffer(r300->draw, PIPE_SHADER_VERTEX, 1773 0, mapped, buf->width0); 1774 } 1775 } else if (shader == PIPE_SHADER_FRAGMENT) { 1776 r300->fs_constants.dirty = TRUE; 1777 } 1778 1779 pipe_buffer_unmap(pipe, buf, tr); 1780} 1781 1782void r300_init_state_functions(struct r300_context* r300) 1783{ 1784 r300->context.create_blend_state = r300_create_blend_state; 1785 r300->context.bind_blend_state = r300_bind_blend_state; 1786 r300->context.delete_blend_state = r300_delete_blend_state; 1787 1788 r300->context.set_blend_color = r300_set_blend_color; 1789 1790 r300->context.set_clip_state = r300_set_clip_state; 1791 r300->context.set_sample_mask = r300_set_sample_mask; 1792 1793 r300->context.set_constant_buffer = r300_set_constant_buffer; 1794 1795 r300->context.create_depth_stencil_alpha_state = r300_create_dsa_state; 1796 r300->context.bind_depth_stencil_alpha_state = r300_bind_dsa_state; 1797 r300->context.delete_depth_stencil_alpha_state = r300_delete_dsa_state; 1798 1799 r300->context.set_stencil_ref = r300_set_stencil_ref; 1800 1801 r300->context.set_framebuffer_state = r300_set_framebuffer_state; 1802 1803 r300->context.create_fs_state = r300_create_fs_state; 1804 r300->context.bind_fs_state = r300_bind_fs_state; 1805 r300->context.delete_fs_state = r300_delete_fs_state; 1806 1807 r300->context.set_polygon_stipple = r300_set_polygon_stipple; 1808 1809 r300->context.create_rasterizer_state = r300_create_rs_state; 1810 r300->context.bind_rasterizer_state = r300_bind_rs_state; 1811 r300->context.delete_rasterizer_state = r300_delete_rs_state; 1812 1813 r300->context.create_sampler_state = r300_create_sampler_state; 1814 r300->context.bind_fragment_sampler_states = r300_bind_sampler_states; 1815 r300->context.bind_vertex_sampler_states = r300_lacks_vertex_textures; 1816 r300->context.delete_sampler_state = r300_delete_sampler_state; 1817 1818 r300->context.set_fragment_sampler_views = r300_set_fragment_sampler_views; 1819 r300->context.create_sampler_view = r300_create_sampler_view; 1820 r300->context.sampler_view_destroy = r300_sampler_view_destroy; 1821 1822 r300->context.set_scissor_state = r300_set_scissor_state; 1823 1824 r300->context.set_viewport_state = r300_set_viewport_state; 1825 1826 r300->context.set_vertex_buffers = r300_set_vertex_buffers; 1827 1828 r300->context.create_vertex_elements_state = r300_create_vertex_elements_state; 1829 r300->context.bind_vertex_elements_state = r300_bind_vertex_elements_state; 1830 r300->context.delete_vertex_elements_state = r300_delete_vertex_elements_state; 1831 1832 r300->context.create_vs_state = r300_create_vs_state; 1833 r300->context.bind_vs_state = r300_bind_vs_state; 1834 r300->context.delete_vs_state = r300_delete_vs_state; 1835} 1836