r300_state.c revision 185ed2105829d6f5eb19edb9abbf0d7977e157c3
1/* 2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com> 3 * Copyright 2009 Marek Olšák <maraeo@gmail.com> 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * on the rights to use, copy, modify, merge, publish, distribute, sub 9 * license, and/or sell copies of the Software, and to permit persons to whom 10 * the Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */ 23 24#include "draw/draw_context.h" 25 26#include "util/u_framebuffer.h" 27#include "util/u_half.h" 28#include "util/u_math.h" 29#include "util/u_mm.h" 30#include "util/u_memory.h" 31#include "util/u_pack_color.h" 32#include "util/u_transfer.h" 33 34#include "tgsi/tgsi_parse.h" 35 36#include "pipe/p_config.h" 37 38#include "r300_cb.h" 39#include "r300_context.h" 40#include "r300_emit.h" 41#include "r300_reg.h" 42#include "r300_screen.h" 43#include "r300_screen_buffer.h" 44#include "r300_state_inlines.h" 45#include "r300_fs.h" 46#include "r300_texture.h" 47#include "r300_vs.h" 48 49/* r300_state: Functions used to intialize state context by translating 50 * Gallium state objects into semi-native r300 state objects. */ 51 52#define UPDATE_STATE(cso, atom) \ 53 if (cso != atom.state) { \ 54 atom.state = cso; \ 55 r300_mark_atom_dirty(r300, &(atom)); \ 56 } 57 58static boolean blend_discard_if_src_alpha_0(unsigned srcRGB, unsigned srcA, 59 unsigned dstRGB, unsigned dstA) 60{ 61 /* If the blend equation is ADD or REVERSE_SUBTRACT, 62 * SRC_ALPHA == 0, and the following state is set, the colorbuffer 63 * will not be changed. 64 * Notice that the dst factors are the src factors inverted. */ 65 return (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA || 66 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE || 67 srcRGB == PIPE_BLENDFACTOR_ZERO) && 68 (srcA == PIPE_BLENDFACTOR_SRC_COLOR || 69 srcA == PIPE_BLENDFACTOR_SRC_ALPHA || 70 srcA == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE || 71 srcA == PIPE_BLENDFACTOR_ZERO) && 72 (dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 73 dstRGB == PIPE_BLENDFACTOR_ONE) && 74 (dstA == PIPE_BLENDFACTOR_INV_SRC_COLOR || 75 dstA == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 76 dstA == PIPE_BLENDFACTOR_ONE); 77} 78 79static boolean blend_discard_if_src_alpha_1(unsigned srcRGB, unsigned srcA, 80 unsigned dstRGB, unsigned dstA) 81{ 82 /* If the blend equation is ADD or REVERSE_SUBTRACT, 83 * SRC_ALPHA == 1, and the following state is set, the colorbuffer 84 * will not be changed. 85 * Notice that the dst factors are the src factors inverted. */ 86 return (srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 87 srcRGB == PIPE_BLENDFACTOR_ZERO) && 88 (srcA == PIPE_BLENDFACTOR_INV_SRC_COLOR || 89 srcA == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 90 srcA == PIPE_BLENDFACTOR_ZERO) && 91 (dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA || 92 dstRGB == PIPE_BLENDFACTOR_ONE) && 93 (dstA == PIPE_BLENDFACTOR_SRC_COLOR || 94 dstA == PIPE_BLENDFACTOR_SRC_ALPHA || 95 dstA == PIPE_BLENDFACTOR_ONE); 96} 97 98static boolean blend_discard_if_src_color_0(unsigned srcRGB, unsigned srcA, 99 unsigned dstRGB, unsigned dstA) 100{ 101 /* If the blend equation is ADD or REVERSE_SUBTRACT, 102 * SRC_COLOR == (0,0,0), and the following state is set, the colorbuffer 103 * will not be changed. 104 * Notice that the dst factors are the src factors inverted. */ 105 return (srcRGB == PIPE_BLENDFACTOR_SRC_COLOR || 106 srcRGB == PIPE_BLENDFACTOR_ZERO) && 107 (srcA == PIPE_BLENDFACTOR_ZERO) && 108 (dstRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR || 109 dstRGB == PIPE_BLENDFACTOR_ONE) && 110 (dstA == PIPE_BLENDFACTOR_ONE); 111} 112 113static boolean blend_discard_if_src_color_1(unsigned srcRGB, unsigned srcA, 114 unsigned dstRGB, unsigned dstA) 115{ 116 /* If the blend equation is ADD or REVERSE_SUBTRACT, 117 * SRC_COLOR == (1,1,1), and the following state is set, the colorbuffer 118 * will not be changed. 119 * Notice that the dst factors are the src factors inverted. */ 120 return (srcRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR || 121 srcRGB == PIPE_BLENDFACTOR_ZERO) && 122 (srcA == PIPE_BLENDFACTOR_ZERO) && 123 (dstRGB == PIPE_BLENDFACTOR_SRC_COLOR || 124 dstRGB == PIPE_BLENDFACTOR_ONE) && 125 (dstA == PIPE_BLENDFACTOR_ONE); 126} 127 128static boolean blend_discard_if_src_alpha_color_0(unsigned srcRGB, unsigned srcA, 129 unsigned dstRGB, unsigned dstA) 130{ 131 /* If the blend equation is ADD or REVERSE_SUBTRACT, 132 * SRC_ALPHA_COLOR == (0,0,0,0), and the following state is set, 133 * the colorbuffer will not be changed. 134 * Notice that the dst factors are the src factors inverted. */ 135 return (srcRGB == PIPE_BLENDFACTOR_SRC_COLOR || 136 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA || 137 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE || 138 srcRGB == PIPE_BLENDFACTOR_ZERO) && 139 (srcA == PIPE_BLENDFACTOR_SRC_COLOR || 140 srcA == PIPE_BLENDFACTOR_SRC_ALPHA || 141 srcA == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE || 142 srcA == PIPE_BLENDFACTOR_ZERO) && 143 (dstRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR || 144 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 145 dstRGB == PIPE_BLENDFACTOR_ONE) && 146 (dstA == PIPE_BLENDFACTOR_INV_SRC_COLOR || 147 dstA == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 148 dstA == PIPE_BLENDFACTOR_ONE); 149} 150 151static boolean blend_discard_if_src_alpha_color_1(unsigned srcRGB, unsigned srcA, 152 unsigned dstRGB, unsigned dstA) 153{ 154 /* If the blend equation is ADD or REVERSE_SUBTRACT, 155 * SRC_ALPHA_COLOR == (1,1,1,1), and the following state is set, 156 * the colorbuffer will not be changed. 157 * Notice that the dst factors are the src factors inverted. */ 158 return (srcRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR || 159 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 160 srcRGB == PIPE_BLENDFACTOR_ZERO) && 161 (srcA == PIPE_BLENDFACTOR_INV_SRC_COLOR || 162 srcA == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 163 srcA == PIPE_BLENDFACTOR_ZERO) && 164 (dstRGB == PIPE_BLENDFACTOR_SRC_COLOR || 165 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA || 166 dstRGB == PIPE_BLENDFACTOR_ONE) && 167 (dstA == PIPE_BLENDFACTOR_SRC_COLOR || 168 dstA == PIPE_BLENDFACTOR_SRC_ALPHA || 169 dstA == PIPE_BLENDFACTOR_ONE); 170} 171 172static unsigned bgra_cmask(unsigned mask) 173{ 174 /* Gallium uses RGBA color ordering while R300 expects BGRA. */ 175 176 return ((mask & PIPE_MASK_R) << 2) | 177 ((mask & PIPE_MASK_B) >> 2) | 178 (mask & (PIPE_MASK_G | PIPE_MASK_A)); 179} 180 181/* Create a new blend state based on the CSO blend state. 182 * 183 * This encompasses alpha blending, logic/raster ops, and blend dithering. */ 184static void* r300_create_blend_state(struct pipe_context* pipe, 185 const struct pipe_blend_state* state) 186{ 187 struct r300_screen* r300screen = r300_screen(pipe->screen); 188 struct r300_blend_state* blend = CALLOC_STRUCT(r300_blend_state); 189 uint32_t blend_control = 0; /* R300_RB3D_CBLEND: 0x4e04 */ 190 uint32_t blend_control_noclamp = 0; /* R300_RB3D_CBLEND: 0x4e04 */ 191 uint32_t alpha_blend_control = 0; /* R300_RB3D_ABLEND: 0x4e08 */ 192 uint32_t alpha_blend_control_noclamp = 0; /* R300_RB3D_ABLEND: 0x4e08 */ 193 uint32_t color_channel_mask = 0; /* R300_RB3D_COLOR_CHANNEL_MASK: 0x4e0c */ 194 uint32_t rop = 0; /* R300_RB3D_ROPCNTL: 0x4e18 */ 195 uint32_t dither = 0; /* R300_RB3D_DITHER_CTL: 0x4e50 */ 196 CB_LOCALS; 197 198 blend->state = *state; 199 200 if (state->rt[0].blend_enable) 201 { 202 unsigned eqRGB = state->rt[0].rgb_func; 203 unsigned srcRGB = state->rt[0].rgb_src_factor; 204 unsigned dstRGB = state->rt[0].rgb_dst_factor; 205 206 unsigned eqA = state->rt[0].alpha_func; 207 unsigned srcA = state->rt[0].alpha_src_factor; 208 unsigned dstA = state->rt[0].alpha_dst_factor; 209 210 /* despite the name, ALPHA_BLEND_ENABLE has nothing to do with alpha, 211 * this is just the crappy D3D naming */ 212 blend_control = blend_control_noclamp = 213 R300_ALPHA_BLEND_ENABLE | 214 ( r300_translate_blend_factor(srcRGB) << R300_SRC_BLEND_SHIFT) | 215 ( r300_translate_blend_factor(dstRGB) << R300_DST_BLEND_SHIFT); 216 blend_control |= 217 r300_translate_blend_function(eqRGB, TRUE); 218 blend_control_noclamp |= 219 r300_translate_blend_function(eqRGB, FALSE); 220 221 /* Optimization: some operations do not require the destination color. 222 * 223 * When SRC_ALPHA_SATURATE is used, colorbuffer reads must be enabled, 224 * otherwise blending gives incorrect results. It seems to be 225 * a hardware bug. */ 226 if (eqRGB == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MIN || 227 eqRGB == PIPE_BLEND_MAX || eqA == PIPE_BLEND_MAX || 228 dstRGB != PIPE_BLENDFACTOR_ZERO || 229 dstA != PIPE_BLENDFACTOR_ZERO || 230 srcRGB == PIPE_BLENDFACTOR_DST_COLOR || 231 srcRGB == PIPE_BLENDFACTOR_DST_ALPHA || 232 srcRGB == PIPE_BLENDFACTOR_INV_DST_COLOR || 233 srcRGB == PIPE_BLENDFACTOR_INV_DST_ALPHA || 234 srcA == PIPE_BLENDFACTOR_DST_COLOR || 235 srcA == PIPE_BLENDFACTOR_DST_ALPHA || 236 srcA == PIPE_BLENDFACTOR_INV_DST_COLOR || 237 srcA == PIPE_BLENDFACTOR_INV_DST_ALPHA || 238 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE) { 239 /* Enable reading from the colorbuffer. */ 240 blend_control |= R300_READ_ENABLE; 241 blend_control_noclamp |= R300_READ_ENABLE; 242 243 if (r300screen->caps.is_r500) { 244 /* Optimization: Depending on incoming pixels, we can 245 * conditionally disable the reading in hardware... */ 246 if (eqRGB != PIPE_BLEND_MIN && eqA != PIPE_BLEND_MIN && 247 eqRGB != PIPE_BLEND_MAX && eqA != PIPE_BLEND_MAX) { 248 /* Disable reading if SRC_ALPHA == 0. */ 249 if ((dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA || 250 dstRGB == PIPE_BLENDFACTOR_ZERO) && 251 (dstA == PIPE_BLENDFACTOR_SRC_COLOR || 252 dstA == PIPE_BLENDFACTOR_SRC_ALPHA || 253 dstA == PIPE_BLENDFACTOR_ZERO)) { 254 blend_control |= R500_SRC_ALPHA_0_NO_READ; 255 } 256 257 /* Disable reading if SRC_ALPHA == 1. */ 258 if ((dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 259 dstRGB == PIPE_BLENDFACTOR_ZERO) && 260 (dstA == PIPE_BLENDFACTOR_INV_SRC_COLOR || 261 dstA == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 262 dstA == PIPE_BLENDFACTOR_ZERO)) { 263 blend_control |= R500_SRC_ALPHA_1_NO_READ; 264 } 265 } 266 } 267 } 268 269 /* Optimization: discard pixels which don't change the colorbuffer. 270 * 271 * The code below is non-trivial and some math is involved. 272 * 273 * Discarding pixels must be disabled when FP16 AA is enabled. 274 * This is a hardware bug. Also, this implementation wouldn't work 275 * with FP blending enabled and equation clamping disabled. 276 * 277 * Equations other than ADD are rarely used and therefore won't be 278 * optimized. */ 279 if ((eqRGB == PIPE_BLEND_ADD || eqRGB == PIPE_BLEND_REVERSE_SUBTRACT) && 280 (eqA == PIPE_BLEND_ADD || eqA == PIPE_BLEND_REVERSE_SUBTRACT)) { 281 /* ADD: X+Y 282 * REVERSE_SUBTRACT: Y-X 283 * 284 * The idea is: 285 * If X = src*srcFactor = 0 and Y = dst*dstFactor = 1, 286 * then CB will not be changed. 287 * 288 * Given the srcFactor and dstFactor variables, we can derive 289 * what src and dst should be equal to and discard appropriate 290 * pixels. 291 */ 292 if (blend_discard_if_src_alpha_0(srcRGB, srcA, dstRGB, dstA)) { 293 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_ALPHA_0; 294 } else if (blend_discard_if_src_alpha_1(srcRGB, srcA, 295 dstRGB, dstA)) { 296 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_ALPHA_1; 297 } else if (blend_discard_if_src_color_0(srcRGB, srcA, 298 dstRGB, dstA)) { 299 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_COLOR_0; 300 } else if (blend_discard_if_src_color_1(srcRGB, srcA, 301 dstRGB, dstA)) { 302 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_COLOR_1; 303 } else if (blend_discard_if_src_alpha_color_0(srcRGB, srcA, 304 dstRGB, dstA)) { 305 blend_control |= 306 R300_DISCARD_SRC_PIXELS_SRC_ALPHA_COLOR_0; 307 } else if (blend_discard_if_src_alpha_color_1(srcRGB, srcA, 308 dstRGB, dstA)) { 309 blend_control |= 310 R300_DISCARD_SRC_PIXELS_SRC_ALPHA_COLOR_1; 311 } 312 } 313 314 /* separate alpha */ 315 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) { 316 blend_control |= R300_SEPARATE_ALPHA_ENABLE; 317 blend_control_noclamp |= R300_SEPARATE_ALPHA_ENABLE; 318 alpha_blend_control = alpha_blend_control_noclamp = 319 (r300_translate_blend_factor(srcA) << R300_SRC_BLEND_SHIFT) | 320 (r300_translate_blend_factor(dstA) << R300_DST_BLEND_SHIFT); 321 alpha_blend_control |= 322 r300_translate_blend_function(eqA, TRUE); 323 alpha_blend_control_noclamp |= 324 r300_translate_blend_function(eqA, FALSE); 325 } 326 } 327 328 /* PIPE_LOGICOP_* don't need to be translated, fortunately. */ 329 if (state->logicop_enable) { 330 rop = R300_RB3D_ROPCNTL_ROP_ENABLE | 331 (state->logicop_func) << R300_RB3D_ROPCNTL_ROP_SHIFT; 332 } 333 334 /* Color channel masks for all MRTs. */ 335 color_channel_mask = bgra_cmask(state->rt[0].colormask); 336 if (r300screen->caps.is_r500 && state->independent_blend_enable) { 337 if (state->rt[1].blend_enable) { 338 color_channel_mask |= bgra_cmask(state->rt[1].colormask) << 4; 339 } 340 if (state->rt[2].blend_enable) { 341 color_channel_mask |= bgra_cmask(state->rt[2].colormask) << 8; 342 } 343 if (state->rt[3].blend_enable) { 344 color_channel_mask |= bgra_cmask(state->rt[3].colormask) << 12; 345 } 346 } 347 348 /* Neither fglrx nor classic r300 ever set this, regardless of dithering 349 * state. Since it's an optional implementation detail, we can leave it 350 * out and never dither. 351 * 352 * This could be revisited if we ever get quality or conformance hints. 353 * 354 if (state->dither) { 355 dither = R300_RB3D_DITHER_CTL_DITHER_MODE_LUT | 356 R300_RB3D_DITHER_CTL_ALPHA_DITHER_MODE_LUT; 357 } 358 */ 359 360 /* Build a command buffer. */ 361 BEGIN_CB(blend->cb_clamp, 8); 362 OUT_CB_REG(R300_RB3D_ROPCNTL, rop); 363 OUT_CB_REG_SEQ(R300_RB3D_CBLEND, 3); 364 OUT_CB(blend_control); 365 OUT_CB(alpha_blend_control); 366 OUT_CB(color_channel_mask); 367 OUT_CB_REG(R300_RB3D_DITHER_CTL, dither); 368 END_CB; 369 370 /* Build a command buffer. */ 371 BEGIN_CB(blend->cb_noclamp, 8); 372 OUT_CB_REG(R300_RB3D_ROPCNTL, rop); 373 OUT_CB_REG_SEQ(R300_RB3D_CBLEND, 3); 374 OUT_CB(blend_control_noclamp); 375 OUT_CB(alpha_blend_control_noclamp); 376 OUT_CB(color_channel_mask); 377 OUT_CB_REG(R300_RB3D_DITHER_CTL, dither); 378 END_CB; 379 380 /* The same as above, but with no colorbuffer reads and writes. */ 381 BEGIN_CB(blend->cb_no_readwrite, 8); 382 OUT_CB_REG(R300_RB3D_ROPCNTL, rop); 383 OUT_CB_REG_SEQ(R300_RB3D_CBLEND, 3); 384 OUT_CB(0); 385 OUT_CB(0); 386 OUT_CB(0); 387 OUT_CB_REG(R300_RB3D_DITHER_CTL, dither); 388 END_CB; 389 390 return (void*)blend; 391} 392 393/* Bind blend state. */ 394static void r300_bind_blend_state(struct pipe_context* pipe, 395 void* state) 396{ 397 struct r300_context* r300 = r300_context(pipe); 398 399 UPDATE_STATE(state, r300->blend_state); 400} 401 402/* Free blend state. */ 403static void r300_delete_blend_state(struct pipe_context* pipe, 404 void* state) 405{ 406 FREE(state); 407} 408 409/* Convert float to 10bit integer */ 410static unsigned float_to_fixed10(float f) 411{ 412 return CLAMP((unsigned)(f * 1023.9f), 0, 1023); 413} 414 415/* Set blend color. 416 * Setup both R300 and R500 registers, figure out later which one to write. */ 417static void r300_set_blend_color(struct pipe_context* pipe, 418 const struct pipe_blend_color* color) 419{ 420 struct r300_context* r300 = r300_context(pipe); 421 struct pipe_framebuffer_state *fb = r300->fb_state.state; 422 struct r300_blend_color_state *state = 423 (struct r300_blend_color_state*)r300->blend_color_state.state; 424 struct pipe_blend_color c; 425 enum pipe_format format = fb->nr_cbufs ? fb->cbufs[0]->format : 0; 426 CB_LOCALS; 427 428 state->state = *color; /* Save it, so that we can reuse it in set_fb_state */ 429 c = *color; 430 431 /* The blend color is dependent on the colorbuffer format. */ 432 if (fb->nr_cbufs) { 433 switch (format) { 434 case PIPE_FORMAT_R8_UNORM: 435 case PIPE_FORMAT_L8_UNORM: 436 case PIPE_FORMAT_I8_UNORM: 437 c.color[1] = c.color[0]; 438 break; 439 440 case PIPE_FORMAT_A8_UNORM: 441 c.color[1] = c.color[3]; 442 break; 443 444 case PIPE_FORMAT_R8G8_UNORM: 445 c.color[2] = c.color[1]; 446 break; 447 448 case PIPE_FORMAT_L8A8_UNORM: 449 c.color[2] = c.color[3]; 450 break; 451 452 default:; 453 } 454 } 455 456 if (r300->screen->caps.is_r500) { 457 BEGIN_CB(state->cb, 3); 458 OUT_CB_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR, 2); 459 460 switch (format) { 461 case PIPE_FORMAT_R16G16B16A16_FLOAT: 462 OUT_CB(util_float_to_half(c.color[2]) | 463 (util_float_to_half(c.color[3]) << 16)); 464 OUT_CB(util_float_to_half(c.color[0]) | 465 (util_float_to_half(c.color[1]) << 16)); 466 break; 467 468 default: 469 OUT_CB(float_to_fixed10(c.color[0]) | 470 (float_to_fixed10(c.color[3]) << 16)); 471 OUT_CB(float_to_fixed10(c.color[2]) | 472 (float_to_fixed10(c.color[1]) << 16)); 473 } 474 475 END_CB; 476 } else { 477 union util_color uc; 478 util_pack_color(c.color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc); 479 480 BEGIN_CB(state->cb, 2); 481 OUT_CB_REG(R300_RB3D_BLEND_COLOR, uc.ui); 482 END_CB; 483 } 484 485 r300_mark_atom_dirty(r300, &r300->blend_color_state); 486} 487 488static void r300_set_clip_state(struct pipe_context* pipe, 489 const struct pipe_clip_state* state) 490{ 491 struct r300_context* r300 = r300_context(pipe); 492 struct r300_clip_state *clip = 493 (struct r300_clip_state*)r300->clip_state.state; 494 CB_LOCALS; 495 496 if (r300->screen->caps.has_tcl) { 497 BEGIN_CB(clip->cb, r300->clip_state.size); 498 OUT_CB_REG(R300_VAP_PVS_VECTOR_INDX_REG, 499 (r300->screen->caps.is_r500 ? 500 R500_PVS_UCP_START : R300_PVS_UCP_START)); 501 OUT_CB_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, 6 * 4); 502 OUT_CB_TABLE(state->ucp, 6 * 4); 503 END_CB; 504 505 r300_mark_atom_dirty(r300, &r300->clip_state); 506 } else { 507 draw_set_clip_state(r300->draw, state); 508 } 509} 510 511static void 512r300_set_sample_mask(struct pipe_context *pipe, 513 unsigned sample_mask) 514{ 515} 516 517 518/* Create a new depth, stencil, and alpha state based on the CSO dsa state. 519 * 520 * This contains the depth buffer, stencil buffer, alpha test, and such. 521 * On the Radeon, depth and stencil buffer setup are intertwined, which is 522 * the reason for some of the strange-looking assignments across registers. */ 523static void* 524 r300_create_dsa_state(struct pipe_context* pipe, 525 const struct pipe_depth_stencil_alpha_state* state) 526{ 527 struct r300_capabilities *caps = &r300_screen(pipe->screen)->caps; 528 struct r300_dsa_state* dsa = CALLOC_STRUCT(r300_dsa_state); 529 CB_LOCALS; 530 531 dsa->dsa = *state; 532 533 /* Depth test setup. - separate write mask depth for decomp flush */ 534 if (state->depth.writemask) { 535 dsa->z_buffer_control |= R300_Z_WRITE_ENABLE; 536 } 537 538 if (state->depth.enabled) { 539 dsa->z_buffer_control |= R300_Z_ENABLE; 540 541 dsa->z_stencil_control |= 542 (r300_translate_depth_stencil_function(state->depth.func) << 543 R300_Z_FUNC_SHIFT); 544 } else { 545 /* We must enable depth test, otherwise occlusion queries won't work. */ 546 dsa->z_buffer_control |= R300_Z_ENABLE; 547 dsa->z_stencil_control |= R300_ZS_ALWAYS; 548 } 549 550 /* Stencil buffer setup. */ 551 if (state->stencil[0].enabled) { 552 dsa->z_buffer_control |= R300_STENCIL_ENABLE; 553 dsa->z_stencil_control |= 554 (r300_translate_depth_stencil_function(state->stencil[0].func) << 555 R300_S_FRONT_FUNC_SHIFT) | 556 (r300_translate_stencil_op(state->stencil[0].fail_op) << 557 R300_S_FRONT_SFAIL_OP_SHIFT) | 558 (r300_translate_stencil_op(state->stencil[0].zpass_op) << 559 R300_S_FRONT_ZPASS_OP_SHIFT) | 560 (r300_translate_stencil_op(state->stencil[0].zfail_op) << 561 R300_S_FRONT_ZFAIL_OP_SHIFT); 562 563 dsa->stencil_ref_mask = 564 (state->stencil[0].valuemask << R300_STENCILMASK_SHIFT) | 565 (state->stencil[0].writemask << R300_STENCILWRITEMASK_SHIFT); 566 567 if (state->stencil[1].enabled) { 568 dsa->two_sided = TRUE; 569 570 dsa->z_buffer_control |= R300_STENCIL_FRONT_BACK; 571 dsa->z_stencil_control |= 572 (r300_translate_depth_stencil_function(state->stencil[1].func) << 573 R300_S_BACK_FUNC_SHIFT) | 574 (r300_translate_stencil_op(state->stencil[1].fail_op) << 575 R300_S_BACK_SFAIL_OP_SHIFT) | 576 (r300_translate_stencil_op(state->stencil[1].zpass_op) << 577 R300_S_BACK_ZPASS_OP_SHIFT) | 578 (r300_translate_stencil_op(state->stencil[1].zfail_op) << 579 R300_S_BACK_ZFAIL_OP_SHIFT); 580 581 dsa->stencil_ref_bf = 582 (state->stencil[1].valuemask << R300_STENCILMASK_SHIFT) | 583 (state->stencil[1].writemask << R300_STENCILWRITEMASK_SHIFT); 584 585 if (caps->is_r500) { 586 dsa->z_buffer_control |= R500_STENCIL_REFMASK_FRONT_BACK; 587 } else { 588 dsa->two_sided_stencil_ref = 589 (state->stencil[0].valuemask != state->stencil[1].valuemask || 590 state->stencil[0].writemask != state->stencil[1].writemask); 591 } 592 } 593 } 594 595 /* Alpha test setup. */ 596 if (state->alpha.enabled) { 597 dsa->alpha_function = 598 r300_translate_alpha_function(state->alpha.func) | 599 R300_FG_ALPHA_FUNC_ENABLE; 600 601 dsa->alpha_function |= float_to_ubyte(state->alpha.ref_value); 602 dsa->alpha_value = util_float_to_half(state->alpha.ref_value); 603 604 if (caps->is_r500) { 605 dsa->alpha_function_fp16 = dsa->alpha_function | 606 R500_FG_ALPHA_FUNC_FP16_ENABLE; 607 dsa->alpha_function |= R500_FG_ALPHA_FUNC_8BIT; 608 } 609 } 610 611 BEGIN_CB(&dsa->cb_begin, 10); 612 OUT_CB_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function); 613 OUT_CB_REG_SEQ(R300_ZB_CNTL, 3); 614 OUT_CB(dsa->z_buffer_control); 615 OUT_CB(dsa->z_stencil_control); 616 OUT_CB(dsa->stencil_ref_mask); 617 OUT_CB_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf); 618 OUT_CB_REG(R500_FG_ALPHA_VALUE, dsa->alpha_value); 619 END_CB; 620 621 BEGIN_CB(&dsa->cb_begin_fp16, 10); 622 OUT_CB_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function_fp16); 623 OUT_CB_REG_SEQ(R300_ZB_CNTL, 3); 624 OUT_CB(dsa->z_buffer_control); 625 OUT_CB(dsa->z_stencil_control); 626 OUT_CB(dsa->stencil_ref_mask); 627 OUT_CB_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf); 628 OUT_CB_REG(R500_FG_ALPHA_VALUE, dsa->alpha_value); 629 END_CB; 630 631 /* We must enable depth test, otherwise occlusion queries won't work. 632 * We setup a dummy zbuffer to silent the CS checker, see emit_fb_state. */ 633 BEGIN_CB(dsa->cb_zb_no_readwrite, 10); 634 OUT_CB_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function); 635 OUT_CB_REG_SEQ(R300_ZB_CNTL, 3); 636 OUT_CB(R300_Z_ENABLE); 637 OUT_CB(R300_ZS_ALWAYS); 638 OUT_CB(0); 639 OUT_CB_REG(R500_ZB_STENCILREFMASK_BF, 0); 640 OUT_CB_REG(R500_FG_ALPHA_VALUE, dsa->alpha_value); 641 END_CB; 642 643 BEGIN_CB(dsa->cb_fp16_zb_no_readwrite, 10); 644 OUT_CB_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function_fp16); 645 OUT_CB_REG_SEQ(R300_ZB_CNTL, 3); 646 OUT_CB(R300_Z_ENABLE); 647 OUT_CB(R300_ZS_ALWAYS); 648 OUT_CB(0); 649 OUT_CB_REG(R500_ZB_STENCILREFMASK_BF, 0); 650 OUT_CB_REG(R500_FG_ALPHA_VALUE, dsa->alpha_value); 651 END_CB; 652 653 return (void*)dsa; 654} 655 656static void r300_dsa_inject_stencilref(struct r300_context *r300) 657{ 658 struct r300_dsa_state *dsa = 659 (struct r300_dsa_state*)r300->dsa_state.state; 660 661 if (!dsa) 662 return; 663 664 dsa->stencil_ref_mask = 665 (dsa->stencil_ref_mask & ~R300_STENCILREF_MASK) | 666 r300->stencil_ref.ref_value[0]; 667 dsa->stencil_ref_bf = 668 (dsa->stencil_ref_bf & ~R300_STENCILREF_MASK) | 669 r300->stencil_ref.ref_value[1]; 670} 671 672/* Bind DSA state. */ 673static void r300_bind_dsa_state(struct pipe_context* pipe, 674 void* state) 675{ 676 struct r300_context* r300 = r300_context(pipe); 677 678 if (!state) { 679 return; 680 } 681 682 UPDATE_STATE(state, r300->dsa_state); 683 684 r300_mark_atom_dirty(r300, &r300->hyperz_state); /* Will be updated before the emission. */ 685 r300_dsa_inject_stencilref(r300); 686} 687 688/* Free DSA state. */ 689static void r300_delete_dsa_state(struct pipe_context* pipe, 690 void* state) 691{ 692 FREE(state); 693} 694 695static void r300_set_stencil_ref(struct pipe_context* pipe, 696 const struct pipe_stencil_ref* sr) 697{ 698 struct r300_context* r300 = r300_context(pipe); 699 700 r300->stencil_ref = *sr; 701 702 r300_dsa_inject_stencilref(r300); 703 r300_mark_atom_dirty(r300, &r300->dsa_state); 704} 705 706static void r300_tex_set_tiling_flags(struct r300_context *r300, 707 struct r300_resource *tex, 708 unsigned level) 709{ 710 /* Check if the macrotile flag needs to be changed. 711 * Skip changing the flags otherwise. */ 712 if (tex->tex.macrotile[tex->surface_level] != 713 tex->tex.macrotile[level]) { 714 r300->rws->buffer_set_tiling(tex->buf, r300->cs, 715 tex->tex.microtile, tex->tex.macrotile[level], 716 0, 0, 0, 0, 0, 717 tex->tex.stride_in_bytes[0]); 718 719 tex->surface_level = level; 720 } 721} 722 723/* This switcheroo is needed just because of goddamned MACRO_SWITCH. */ 724static void r300_fb_set_tiling_flags(struct r300_context *r300, 725 const struct pipe_framebuffer_state *state) 726{ 727 unsigned i; 728 729 /* Set tiling flags for new surfaces. */ 730 for (i = 0; i < state->nr_cbufs; i++) { 731 r300_tex_set_tiling_flags(r300, 732 r300_resource(state->cbufs[i]->texture), 733 state->cbufs[i]->u.tex.level); 734 } 735 if (state->zsbuf) { 736 r300_tex_set_tiling_flags(r300, 737 r300_resource(state->zsbuf->texture), 738 state->zsbuf->u.tex.level); 739 } 740} 741 742static void r300_print_fb_surf_info(struct pipe_surface *surf, unsigned index, 743 const char *binding) 744{ 745 struct pipe_resource *tex = surf->texture; 746 struct r300_resource *rtex = r300_resource(tex); 747 748 fprintf(stderr, 749 "r300: %s[%i] Dim: %ix%i, Firstlayer: %i, " 750 "Lastlayer: %i, Level: %i, Format: %s\n" 751 752 "r300: TEX: Macro: %s, Micro: %s, " 753 "Dim: %ix%ix%i, LastLevel: %i, Format: %s\n", 754 755 binding, index, surf->width, surf->height, 756 surf->u.tex.first_layer, surf->u.tex.last_layer, surf->u.tex.level, 757 util_format_short_name(surf->format), 758 759 rtex->tex.macrotile[0] ? "YES" : " NO", 760 rtex->tex.microtile ? "YES" : " NO", 761 tex->width0, tex->height0, tex->depth0, 762 tex->last_level, util_format_short_name(surf->format)); 763} 764 765void r300_mark_fb_state_dirty(struct r300_context *r300, 766 enum r300_fb_state_change change) 767{ 768 struct pipe_framebuffer_state *state = r300->fb_state.state; 769 770 r300_mark_atom_dirty(r300, &r300->gpu_flush); 771 r300_mark_atom_dirty(r300, &r300->fb_state); 772 773 /* What is marked as dirty depends on the enum r300_fb_state_change. */ 774 if (change == R300_CHANGED_FB_STATE) { 775 r300_mark_atom_dirty(r300, &r300->aa_state); 776 r300_mark_atom_dirty(r300, &r300->dsa_state); /* for AlphaRef */ 777 r300_set_blend_color(&r300->context, r300->blend_color_state.state); 778 } 779 780 if (change == R300_CHANGED_FB_STATE || 781 change == R300_CHANGED_HYPERZ_FLAG) { 782 r300_mark_atom_dirty(r300, &r300->hyperz_state); 783 } 784 785 if (change == R300_CHANGED_FB_STATE || 786 change == R300_CHANGED_MULTIWRITE) { 787 r300_mark_atom_dirty(r300, &r300->fb_state_pipelined); 788 } 789 790 /* Now compute the fb_state atom size. */ 791 r300->fb_state.size = 2 + (8 * state->nr_cbufs); 792 793 if (r300->cbzb_clear) { 794 r300->fb_state.size += 10; 795 } else if (state->zsbuf) { 796 r300->fb_state.size += 10; 797 if (r300->hyperz_enabled) 798 r300->fb_state.size += 8; 799 } else if (state->nr_cbufs) { 800 r300->fb_state.size += 10; 801 } 802 803 /* The size of the rest of atoms stays the same. */ 804} 805 806static void 807r300_set_framebuffer_state(struct pipe_context* pipe, 808 const struct pipe_framebuffer_state* state) 809{ 810 struct r300_context* r300 = r300_context(pipe); 811 struct r300_aa_state *aa = (struct r300_aa_state*)r300->aa_state.state; 812 struct pipe_framebuffer_state *old_state = r300->fb_state.state; 813 unsigned max_width, max_height, i; 814 uint32_t zbuffer_bpp = 0; 815 boolean unlock_zbuffer = FALSE; 816 817 if (r300->screen->caps.is_r500) { 818 max_width = max_height = 4096; 819 } else if (r300->screen->caps.is_r400) { 820 max_width = max_height = 4021; 821 } else { 822 max_width = max_height = 2560; 823 } 824 825 if (state->width > max_width || state->height > max_height) { 826 fprintf(stderr, "r300: Implementation error: Render targets are too " 827 "big in %s, refusing to bind framebuffer state!\n", __FUNCTION__); 828 return; 829 } 830 831 if (old_state->zsbuf && r300->zmask_in_use && !r300->locked_zbuffer) { 832 /* There is a zmask in use, what are we gonna do? */ 833 if (state->zsbuf) { 834 if (!pipe_surface_equal(old_state->zsbuf, state->zsbuf)) { 835 /* Decompress the currently bound zbuffer before we bind another one. */ 836 r300_decompress_zmask(r300); 837 r300->hiz_in_use = FALSE; 838 } 839 } else { 840 /* We don't bind another zbuffer, so lock the current one. */ 841 pipe_surface_reference(&r300->locked_zbuffer, old_state->zsbuf); 842 } 843 } else if (r300->locked_zbuffer) { 844 /* We have a locked zbuffer now, what are we gonna do? */ 845 if (state->zsbuf) { 846 if (!pipe_surface_equal(r300->locked_zbuffer, state->zsbuf)) { 847 /* We are binding some other zbuffer, so decompress the locked one, 848 * it gets unlocked automatically. */ 849 r300_decompress_zmask_locked_unsafe(r300); 850 r300->hiz_in_use = FALSE; 851 } else { 852 /* We are binding the locked zbuffer again, so unlock it. */ 853 unlock_zbuffer = TRUE; 854 } 855 } 856 } 857 assert(state->zsbuf || (r300->locked_zbuffer && !unlock_zbuffer) || !r300->zmask_in_use); 858 859 /* Need to reset clamping or colormask. */ 860 r300_mark_atom_dirty(r300, &r300->blend_state); 861 862 /* If zsbuf is set from NULL to non-NULL or vice versa.. */ 863 if (!!old_state->zsbuf != !!state->zsbuf) { 864 r300_mark_atom_dirty(r300, &r300->dsa_state); 865 } 866 867 if (r300->screen->info.drm_minor < 12) { 868 /* The tiling flags are dependent on the surface miplevel, unfortunately. 869 * This workarounds a bad design decision in old kernels which were 870 * rewriting tile fields in registers. */ 871 r300_fb_set_tiling_flags(r300, state); 872 } 873 874 util_copy_framebuffer_state(r300->fb_state.state, state); 875 876 if (unlock_zbuffer) { 877 pipe_surface_reference(&r300->locked_zbuffer, NULL); 878 } 879 880 r300_mark_fb_state_dirty(r300, R300_CHANGED_FB_STATE); 881 882 if (state->zsbuf) { 883 switch (util_format_get_blocksize(state->zsbuf->format)) { 884 case 2: 885 zbuffer_bpp = 16; 886 break; 887 case 4: 888 zbuffer_bpp = 24; 889 break; 890 } 891 892 /* Polygon offset depends on the zbuffer bit depth. */ 893 if (r300->zbuffer_bpp != zbuffer_bpp) { 894 r300->zbuffer_bpp = zbuffer_bpp; 895 896 if (r300->polygon_offset_enabled) 897 r300_mark_atom_dirty(r300, &r300->rs_state); 898 } 899 } 900 901 /* Set up AA config. */ 902 if (state->nr_cbufs && state->cbufs[0]->texture->nr_samples > 1) { 903 aa->aa_config = R300_GB_AA_CONFIG_AA_ENABLE; 904 905 switch (state->cbufs[0]->texture->nr_samples) { 906 case 2: 907 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_2; 908 break; 909 case 3: 910 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_3; 911 break; 912 case 4: 913 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_4; 914 break; 915 case 6: 916 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_6; 917 break; 918 } 919 } else { 920 aa->aa_config = 0; 921 } 922 923 if (DBG_ON(r300, DBG_FB)) { 924 fprintf(stderr, "r300: set_framebuffer_state:\n"); 925 for (i = 0; i < state->nr_cbufs; i++) { 926 r300_print_fb_surf_info(state->cbufs[i], i, "CB"); 927 } 928 if (state->zsbuf) { 929 r300_print_fb_surf_info(state->zsbuf, 0, "ZB"); 930 } 931 } 932} 933 934/* Create fragment shader state. */ 935static void* r300_create_fs_state(struct pipe_context* pipe, 936 const struct pipe_shader_state* shader) 937{ 938 struct r300_fragment_shader* fs = NULL; 939 940 fs = (struct r300_fragment_shader*)CALLOC_STRUCT(r300_fragment_shader); 941 942 /* Copy state directly into shader. */ 943 fs->state = *shader; 944 fs->state.tokens = tgsi_dup_tokens(shader->tokens); 945 946 return (void*)fs; 947} 948 949void r300_mark_fs_code_dirty(struct r300_context *r300) 950{ 951 struct r300_fragment_shader* fs = r300_fs(r300); 952 953 r300_mark_atom_dirty(r300, &r300->fs); 954 r300_mark_atom_dirty(r300, &r300->fs_rc_constant_state); 955 r300_mark_atom_dirty(r300, &r300->fs_constants); 956 r300->fs.size = fs->shader->cb_code_size; 957 958 if (r300->screen->caps.is_r500) { 959 r300->fs_rc_constant_state.size = fs->shader->rc_state_count * 7; 960 r300->fs_constants.size = fs->shader->externals_count * 4 + 3; 961 } else { 962 r300->fs_rc_constant_state.size = fs->shader->rc_state_count * 5; 963 r300->fs_constants.size = fs->shader->externals_count * 4 + 1; 964 } 965 966 ((struct r300_constant_buffer*)r300->fs_constants.state)->remap_table = 967 fs->shader->code.constants_remap_table; 968} 969 970/* Bind fragment shader state. */ 971static void r300_bind_fs_state(struct pipe_context* pipe, void* shader) 972{ 973 struct r300_context* r300 = r300_context(pipe); 974 struct r300_fragment_shader* fs = (struct r300_fragment_shader*)shader; 975 976 if (fs == NULL) { 977 r300->fs.state = NULL; 978 return; 979 } 980 981 r300->fs.state = fs; 982 r300->fs_status = FRAGMENT_SHADER_DIRTY; 983 984 r300_mark_atom_dirty(r300, &r300->rs_block_state); /* Will be updated before the emission. */ 985} 986 987/* Delete fragment shader state. */ 988static void r300_delete_fs_state(struct pipe_context* pipe, void* shader) 989{ 990 struct r300_fragment_shader* fs = (struct r300_fragment_shader*)shader; 991 struct r300_fragment_shader_code *tmp, *ptr = fs->first; 992 993 while (ptr) { 994 tmp = ptr; 995 ptr = ptr->next; 996 rc_constants_destroy(&tmp->code.constants); 997 FREE(tmp->cb_code); 998 FREE(tmp); 999 } 1000 FREE((void*)fs->state.tokens); 1001 FREE(shader); 1002} 1003 1004static void r300_set_polygon_stipple(struct pipe_context* pipe, 1005 const struct pipe_poly_stipple* state) 1006{ 1007 /* XXX no idea how to set this up, but not terribly important */ 1008} 1009 1010/* Create a new rasterizer state based on the CSO rasterizer state. 1011 * 1012 * This is a very large chunk of state, and covers most of the graphics 1013 * backend (GB), geometry assembly (GA), and setup unit (SU) blocks. 1014 * 1015 * In a not entirely unironic sidenote, this state has nearly nothing to do 1016 * with the actual block on the Radeon called the rasterizer (RS). */ 1017static void* r300_create_rs_state(struct pipe_context* pipe, 1018 const struct pipe_rasterizer_state* state) 1019{ 1020 struct r300_rs_state* rs = CALLOC_STRUCT(r300_rs_state); 1021 uint32_t vap_control_status; /* R300_VAP_CNTL_STATUS: 0x2140 */ 1022 uint32_t vap_clip_cntl; /* R300_VAP_CLIP_CNTL: 0x221C */ 1023 uint32_t point_size; /* R300_GA_POINT_SIZE: 0x421c */ 1024 uint32_t point_minmax; /* R300_GA_POINT_MINMAX: 0x4230 */ 1025 uint32_t line_control; /* R300_GA_LINE_CNTL: 0x4234 */ 1026 uint32_t polygon_offset_enable; /* R300_SU_POLY_OFFSET_ENABLE: 0x42b4 */ 1027 uint32_t cull_mode; /* R300_SU_CULL_MODE: 0x42b8 */ 1028 uint32_t line_stipple_config; /* R300_GA_LINE_STIPPLE_CONFIG: 0x4328 */ 1029 uint32_t line_stipple_value; /* R300_GA_LINE_STIPPLE_VALUE: 0x4260 */ 1030 uint32_t polygon_mode; /* R300_GA_POLY_MODE: 0x4288 */ 1031 uint32_t clip_rule; /* R300_SC_CLIP_RULE: 0x43D0 */ 1032 uint32_t round_mode; /* R300_GA_ROUND_MODE: 0x428c */ 1033 1034 /* Point sprites texture coordinates, 0: lower left, 1: upper right */ 1035 float point_texcoord_left = 0; /* R300_GA_POINT_S0: 0x4200 */ 1036 float point_texcoord_bottom = 0;/* R300_GA_POINT_T0: 0x4204 */ 1037 float point_texcoord_right = 1; /* R300_GA_POINT_S1: 0x4208 */ 1038 float point_texcoord_top = 0; /* R300_GA_POINT_T1: 0x420c */ 1039 boolean vclamp = state->clamp_vertex_color || 1040 !r300_context(pipe)->screen->caps.is_r500; 1041 CB_LOCALS; 1042 1043 /* Copy rasterizer state. */ 1044 rs->rs = *state; 1045 rs->rs_draw = *state; 1046 1047 rs->rs.sprite_coord_enable = state->point_quad_rasterization * 1048 state->sprite_coord_enable; 1049 1050 /* Override some states for Draw. */ 1051 rs->rs_draw.sprite_coord_enable = 0; /* We can do this in HW. */ 1052 rs->rs_draw.offset_point = 0; 1053 rs->rs_draw.offset_line = 0; 1054 rs->rs_draw.offset_tri = 0; 1055 rs->rs_draw.offset_clamp = 0; 1056 1057#ifdef PIPE_ARCH_LITTLE_ENDIAN 1058 vap_control_status = R300_VC_NO_SWAP; 1059#else 1060 vap_control_status = R300_VC_32BIT_SWAP; 1061#endif 1062 1063 /* If no TCL engine is present, turn off the HW TCL. */ 1064 if (!r300_screen(pipe->screen)->caps.has_tcl) { 1065 vap_control_status |= R300_VAP_TCL_BYPASS; 1066 } 1067 1068 /* Point size width and height. */ 1069 point_size = 1070 pack_float_16_6x(state->point_size) | 1071 (pack_float_16_6x(state->point_size) << R300_POINTSIZE_X_SHIFT); 1072 1073 /* Point size clamping. */ 1074 if (state->point_size_per_vertex) { 1075 /* Per-vertex point size. 1076 * Clamp to [0, max FB size] */ 1077 float min_psiz = util_get_min_point_size(state); 1078 float max_psiz = pipe->screen->get_paramf(pipe->screen, 1079 PIPE_CAPF_MAX_POINT_WIDTH); 1080 point_minmax = 1081 (pack_float_16_6x(min_psiz) << R300_GA_POINT_MINMAX_MIN_SHIFT) | 1082 (pack_float_16_6x(max_psiz) << R300_GA_POINT_MINMAX_MAX_SHIFT); 1083 } else { 1084 /* We cannot disable the point-size vertex output, 1085 * so clamp it. */ 1086 float psiz = state->point_size; 1087 point_minmax = 1088 (pack_float_16_6x(psiz) << R300_GA_POINT_MINMAX_MIN_SHIFT) | 1089 (pack_float_16_6x(psiz) << R300_GA_POINT_MINMAX_MAX_SHIFT); 1090 } 1091 1092 /* Line control. */ 1093 line_control = pack_float_16_6x(state->line_width) | 1094 R300_GA_LINE_CNTL_END_TYPE_COMP; 1095 1096 /* Enable polygon mode */ 1097 polygon_mode = 0; 1098 if (state->fill_front != PIPE_POLYGON_MODE_FILL || 1099 state->fill_back != PIPE_POLYGON_MODE_FILL) { 1100 polygon_mode = R300_GA_POLY_MODE_DUAL; 1101 } 1102 1103 /* Front face */ 1104 if (state->front_ccw) 1105 cull_mode = R300_FRONT_FACE_CCW; 1106 else 1107 cull_mode = R300_FRONT_FACE_CW; 1108 1109 /* Polygon offset */ 1110 polygon_offset_enable = 0; 1111 if (util_get_offset(state, state->fill_front)) { 1112 polygon_offset_enable |= R300_FRONT_ENABLE; 1113 } 1114 if (util_get_offset(state, state->fill_back)) { 1115 polygon_offset_enable |= R300_BACK_ENABLE; 1116 } 1117 1118 rs->polygon_offset_enable = polygon_offset_enable != 0; 1119 1120 /* Polygon mode */ 1121 if (polygon_mode) { 1122 polygon_mode |= 1123 r300_translate_polygon_mode_front(state->fill_front); 1124 polygon_mode |= 1125 r300_translate_polygon_mode_back(state->fill_back); 1126 } 1127 1128 if (state->cull_face & PIPE_FACE_FRONT) { 1129 cull_mode |= R300_CULL_FRONT; 1130 } 1131 if (state->cull_face & PIPE_FACE_BACK) { 1132 cull_mode |= R300_CULL_BACK; 1133 } 1134 1135 if (state->line_stipple_enable) { 1136 line_stipple_config = 1137 R300_GA_LINE_STIPPLE_CONFIG_LINE_RESET_LINE | 1138 (fui((float)state->line_stipple_factor) & 1139 R300_GA_LINE_STIPPLE_CONFIG_STIPPLE_SCALE_MASK); 1140 /* XXX this might need to be scaled up */ 1141 line_stipple_value = state->line_stipple_pattern; 1142 } else { 1143 line_stipple_config = 0; 1144 line_stipple_value = 0; 1145 } 1146 1147 if (state->flatshade) { 1148 rs->color_control = R300_SHADE_MODEL_FLAT; 1149 } else { 1150 rs->color_control = R300_SHADE_MODEL_SMOOTH; 1151 } 1152 1153 clip_rule = state->scissor ? 0xAAAA : 0xFFFF; 1154 1155 /* Point sprites coord mode */ 1156 if (rs->rs.sprite_coord_enable) { 1157 switch (state->sprite_coord_mode) { 1158 case PIPE_SPRITE_COORD_UPPER_LEFT: 1159 point_texcoord_top = 0.0f; 1160 point_texcoord_bottom = 1.0f; 1161 break; 1162 case PIPE_SPRITE_COORD_LOWER_LEFT: 1163 point_texcoord_top = 1.0f; 1164 point_texcoord_bottom = 0.0f; 1165 break; 1166 } 1167 } 1168 1169 if (r300_screen(pipe->screen)->caps.has_tcl) { 1170 vap_clip_cntl = (state->clip_plane_enable & 63) | 1171 R300_PS_UCP_MODE_CLIP_AS_TRIFAN; 1172 } else { 1173 vap_clip_cntl = R300_CLIP_DISABLE; 1174 } 1175 1176 /* Vertex color clamping. FP20 means no clamping. */ 1177 round_mode = 1178 R300_GA_ROUND_MODE_GEOMETRY_ROUND_NEAREST | 1179 (!vclamp ? (R300_GA_ROUND_MODE_RGB_CLAMP_FP20 | 1180 R300_GA_ROUND_MODE_ALPHA_CLAMP_FP20) : 0); 1181 1182 /* Build the main command buffer. */ 1183 BEGIN_CB(rs->cb_main, RS_STATE_MAIN_SIZE); 1184 OUT_CB_REG(R300_VAP_CNTL_STATUS, vap_control_status); 1185 OUT_CB_REG(R300_VAP_CLIP_CNTL, vap_clip_cntl); 1186 OUT_CB_REG(R300_GA_POINT_SIZE, point_size); 1187 OUT_CB_REG_SEQ(R300_GA_POINT_MINMAX, 2); 1188 OUT_CB(point_minmax); 1189 OUT_CB(line_control); 1190 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_ENABLE, 2); 1191 OUT_CB(polygon_offset_enable); 1192 rs->cull_mode_index = 11; 1193 OUT_CB(cull_mode); 1194 OUT_CB_REG(R300_GA_LINE_STIPPLE_CONFIG, line_stipple_config); 1195 OUT_CB_REG(R300_GA_LINE_STIPPLE_VALUE, line_stipple_value); 1196 OUT_CB_REG(R300_GA_POLY_MODE, polygon_mode); 1197 OUT_CB_REG(R300_GA_ROUND_MODE, round_mode); 1198 OUT_CB_REG(R300_SC_CLIP_RULE, clip_rule); 1199 OUT_CB_REG_SEQ(R300_GA_POINT_S0, 4); 1200 OUT_CB_32F(point_texcoord_left); 1201 OUT_CB_32F(point_texcoord_bottom); 1202 OUT_CB_32F(point_texcoord_right); 1203 OUT_CB_32F(point_texcoord_top); 1204 END_CB; 1205 1206 /* Build the two command buffers for polygon offset setup. */ 1207 if (polygon_offset_enable) { 1208 float scale = state->offset_scale * 12; 1209 float offset = state->offset_units * 4; 1210 1211 BEGIN_CB(rs->cb_poly_offset_zb16, 5); 1212 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4); 1213 OUT_CB_32F(scale); 1214 OUT_CB_32F(offset); 1215 OUT_CB_32F(scale); 1216 OUT_CB_32F(offset); 1217 END_CB; 1218 1219 offset = state->offset_units * 2; 1220 1221 BEGIN_CB(rs->cb_poly_offset_zb24, 5); 1222 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4); 1223 OUT_CB_32F(scale); 1224 OUT_CB_32F(offset); 1225 OUT_CB_32F(scale); 1226 OUT_CB_32F(offset); 1227 END_CB; 1228 } 1229 1230 return (void*)rs; 1231} 1232 1233/* Bind rasterizer state. */ 1234static void r300_bind_rs_state(struct pipe_context* pipe, void* state) 1235{ 1236 struct r300_context* r300 = r300_context(pipe); 1237 struct r300_rs_state* rs = (struct r300_rs_state*)state; 1238 int last_sprite_coord_enable = r300->sprite_coord_enable; 1239 boolean last_two_sided_color = r300->two_sided_color; 1240 1241 if (r300->draw && rs) { 1242 draw_set_rasterizer_state(r300->draw, &rs->rs_draw, state); 1243 } 1244 1245 if (rs) { 1246 r300->polygon_offset_enabled = rs->polygon_offset_enable; 1247 r300->sprite_coord_enable = rs->rs.sprite_coord_enable; 1248 r300->two_sided_color = rs->rs.light_twoside; 1249 } else { 1250 r300->polygon_offset_enabled = FALSE; 1251 r300->sprite_coord_enable = 0; 1252 r300->two_sided_color = FALSE; 1253 } 1254 1255 UPDATE_STATE(state, r300->rs_state); 1256 r300->rs_state.size = RS_STATE_MAIN_SIZE + (r300->polygon_offset_enabled ? 5 : 0); 1257 1258 if (last_sprite_coord_enable != r300->sprite_coord_enable || 1259 last_two_sided_color != r300->two_sided_color) { 1260 r300_mark_atom_dirty(r300, &r300->rs_block_state); 1261 } 1262} 1263 1264/* Free rasterizer state. */ 1265static void r300_delete_rs_state(struct pipe_context* pipe, void* state) 1266{ 1267 FREE(state); 1268} 1269 1270static void* 1271 r300_create_sampler_state(struct pipe_context* pipe, 1272 const struct pipe_sampler_state* state) 1273{ 1274 struct r300_context* r300 = r300_context(pipe); 1275 struct r300_sampler_state* sampler = CALLOC_STRUCT(r300_sampler_state); 1276 boolean is_r500 = r300->screen->caps.is_r500; 1277 int lod_bias; 1278 1279 sampler->state = *state; 1280 1281 /* r300 doesn't handle CLAMP and MIRROR_CLAMP correctly when either MAG 1282 * or MIN filter is NEAREST. Since texwrap produces same results 1283 * for CLAMP and CLAMP_TO_EDGE, we use them instead. */ 1284 if (sampler->state.min_img_filter == PIPE_TEX_FILTER_NEAREST || 1285 sampler->state.mag_img_filter == PIPE_TEX_FILTER_NEAREST) { 1286 /* Wrap S. */ 1287 if (sampler->state.wrap_s == PIPE_TEX_WRAP_CLAMP) 1288 sampler->state.wrap_s = PIPE_TEX_WRAP_CLAMP_TO_EDGE; 1289 else if (sampler->state.wrap_s == PIPE_TEX_WRAP_MIRROR_CLAMP) 1290 sampler->state.wrap_s = PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE; 1291 1292 /* Wrap T. */ 1293 if (sampler->state.wrap_t == PIPE_TEX_WRAP_CLAMP) 1294 sampler->state.wrap_t = PIPE_TEX_WRAP_CLAMP_TO_EDGE; 1295 else if (sampler->state.wrap_t == PIPE_TEX_WRAP_MIRROR_CLAMP) 1296 sampler->state.wrap_t = PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE; 1297 1298 /* Wrap R. */ 1299 if (sampler->state.wrap_r == PIPE_TEX_WRAP_CLAMP) 1300 sampler->state.wrap_r = PIPE_TEX_WRAP_CLAMP_TO_EDGE; 1301 else if (sampler->state.wrap_r == PIPE_TEX_WRAP_MIRROR_CLAMP) 1302 sampler->state.wrap_r = PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE; 1303 } 1304 1305 sampler->filter0 |= 1306 (r300_translate_wrap(sampler->state.wrap_s) << R300_TX_WRAP_S_SHIFT) | 1307 (r300_translate_wrap(sampler->state.wrap_t) << R300_TX_WRAP_T_SHIFT) | 1308 (r300_translate_wrap(sampler->state.wrap_r) << R300_TX_WRAP_R_SHIFT); 1309 1310 sampler->filter0 |= r300_translate_tex_filters(state->min_img_filter, 1311 state->mag_img_filter, 1312 state->min_mip_filter, 1313 state->max_anisotropy > 1); 1314 1315 sampler->filter0 |= r300_anisotropy(state->max_anisotropy); 1316 1317 /* Unfortunately, r300-r500 don't support floating-point mipmap lods. */ 1318 /* We must pass these to the merge function to clamp them properly. */ 1319 sampler->min_lod = (unsigned)MAX2(state->min_lod, 0); 1320 sampler->max_lod = (unsigned)MAX2(ceilf(state->max_lod), 0); 1321 1322 lod_bias = CLAMP((int)(state->lod_bias * 32 + 1), -(1 << 9), (1 << 9) - 1); 1323 1324 sampler->filter1 |= (lod_bias << R300_LOD_BIAS_SHIFT) & R300_LOD_BIAS_MASK; 1325 1326 /* This is very high quality anisotropic filtering for R5xx. 1327 * It's good for benchmarking the performance of texturing but 1328 * in practice we don't want to slow down the driver because it's 1329 * a pretty good performance killer. Feel free to play with it. */ 1330 if (DBG_ON(r300, DBG_ANISOHQ) && is_r500) { 1331 sampler->filter1 |= r500_anisotropy(state->max_anisotropy); 1332 } 1333 1334 /* R500-specific fixups and optimizations */ 1335 if (r300->screen->caps.is_r500) { 1336 sampler->filter1 |= R500_BORDER_FIX; 1337 } 1338 1339 return (void*)sampler; 1340} 1341 1342static void r300_bind_sampler_states(struct pipe_context* pipe, 1343 unsigned count, 1344 void** states) 1345{ 1346 struct r300_context* r300 = r300_context(pipe); 1347 struct r300_textures_state* state = 1348 (struct r300_textures_state*)r300->textures_state.state; 1349 unsigned tex_units = r300->screen->caps.num_tex_units; 1350 1351 if (count > tex_units) { 1352 return; 1353 } 1354 1355 memcpy(state->sampler_states, states, sizeof(void*) * count); 1356 state->sampler_state_count = count; 1357 1358 r300_mark_atom_dirty(r300, &r300->textures_state); 1359} 1360 1361static void r300_lacks_vertex_textures(struct pipe_context* pipe, 1362 unsigned count, 1363 void** states) 1364{ 1365} 1366 1367static void r300_delete_sampler_state(struct pipe_context* pipe, void* state) 1368{ 1369 FREE(state); 1370} 1371 1372static uint32_t r300_assign_texture_cache_region(unsigned index, unsigned num) 1373{ 1374 /* This looks like a hack, but I believe it's suppose to work like 1375 * that. To illustrate how this works, let's assume you have 5 textures. 1376 * From docs, 5 and the successive numbers are: 1377 * 1378 * FOURTH_1 = 5 1379 * FOURTH_2 = 6 1380 * FOURTH_3 = 7 1381 * EIGHTH_0 = 8 1382 * EIGHTH_1 = 9 1383 * 1384 * First 3 textures will get 3/4 of size of the cache, divived evenly 1385 * between them. The last 1/4 of the cache must be divided between 1386 * the last 2 textures, each will therefore get 1/8 of the cache. 1387 * Why not just to use "5 + texture_index" ? 1388 * 1389 * This simple trick works for all "num" <= 16. 1390 */ 1391 if (num <= 1) 1392 return R300_TX_CACHE(R300_TX_CACHE_WHOLE); 1393 else 1394 return R300_TX_CACHE(num + index); 1395} 1396 1397static void r300_set_fragment_sampler_views(struct pipe_context* pipe, 1398 unsigned count, 1399 struct pipe_sampler_view** views) 1400{ 1401 struct r300_context* r300 = r300_context(pipe); 1402 struct r300_textures_state* state = 1403 (struct r300_textures_state*)r300->textures_state.state; 1404 struct r300_resource *texture; 1405 unsigned i, real_num_views = 0, view_index = 0; 1406 unsigned tex_units = r300->screen->caps.num_tex_units; 1407 boolean dirty_tex = FALSE; 1408 1409 if (count > tex_units) { 1410 return; 1411 } 1412 1413 /* Calculate the real number of views. */ 1414 for (i = 0; i < count; i++) { 1415 if (views[i]) 1416 real_num_views++; 1417 } 1418 1419 for (i = 0; i < count; i++) { 1420 pipe_sampler_view_reference( 1421 (struct pipe_sampler_view**)&state->sampler_views[i], 1422 views[i]); 1423 1424 if (!views[i]) { 1425 continue; 1426 } 1427 1428 /* A new sampler view (= texture)... */ 1429 dirty_tex = TRUE; 1430 1431 /* Set the texrect factor in the fragment shader. 1432 * Needed for RECT and NPOT fallback. */ 1433 texture = r300_resource(views[i]->texture); 1434 if (texture->tex.is_npot) { 1435 r300_mark_atom_dirty(r300, &r300->fs_rc_constant_state); 1436 } 1437 1438 state->sampler_views[i]->texcache_region = 1439 r300_assign_texture_cache_region(view_index, real_num_views); 1440 view_index++; 1441 } 1442 1443 for (i = count; i < tex_units; i++) { 1444 if (state->sampler_views[i]) { 1445 pipe_sampler_view_reference( 1446 (struct pipe_sampler_view**)&state->sampler_views[i], 1447 NULL); 1448 } 1449 } 1450 1451 state->sampler_view_count = count; 1452 1453 r300_mark_atom_dirty(r300, &r300->textures_state); 1454 1455 if (dirty_tex) { 1456 r300_mark_atom_dirty(r300, &r300->texture_cache_inval); 1457 } 1458} 1459 1460struct pipe_sampler_view * 1461r300_create_sampler_view_custom(struct pipe_context *pipe, 1462 struct pipe_resource *texture, 1463 const struct pipe_sampler_view *templ, 1464 unsigned width0_override, 1465 unsigned height0_override) 1466{ 1467 struct r300_sampler_view *view = CALLOC_STRUCT(r300_sampler_view); 1468 struct r300_resource *tex = r300_resource(texture); 1469 boolean is_r500 = r300_screen(pipe->screen)->caps.is_r500; 1470 boolean dxtc_swizzle = r300_screen(pipe->screen)->caps.dxtc_swizzle; 1471 1472 if (view) { 1473 unsigned hwformat; 1474 1475 view->base = *templ; 1476 view->base.reference.count = 1; 1477 view->base.context = pipe; 1478 view->base.texture = NULL; 1479 pipe_resource_reference(&view->base.texture, texture); 1480 1481 view->width0_override = width0_override; 1482 view->height0_override = height0_override; 1483 view->swizzle[0] = templ->swizzle_r; 1484 view->swizzle[1] = templ->swizzle_g; 1485 view->swizzle[2] = templ->swizzle_b; 1486 view->swizzle[3] = templ->swizzle_a; 1487 1488 hwformat = r300_translate_texformat(templ->format, 1489 view->swizzle, 1490 is_r500, 1491 dxtc_swizzle); 1492 1493 if (hwformat == ~0) { 1494 fprintf(stderr, "r300: Ooops. Got unsupported format %s in %s.\n", 1495 util_format_short_name(templ->format), __func__); 1496 } 1497 assert(hwformat != ~0); 1498 1499 r300_texture_setup_format_state(r300_screen(pipe->screen), tex, 1500 templ->format, 0, 1501 width0_override, height0_override, 1502 &view->format); 1503 view->format.format1 |= hwformat; 1504 if (is_r500) { 1505 view->format.format2 |= r500_tx_format_msb_bit(templ->format); 1506 } 1507 } 1508 1509 return (struct pipe_sampler_view*)view; 1510} 1511 1512static struct pipe_sampler_view * 1513r300_create_sampler_view(struct pipe_context *pipe, 1514 struct pipe_resource *texture, 1515 const struct pipe_sampler_view *templ) 1516{ 1517 return r300_create_sampler_view_custom(pipe, texture, templ, 1518 r300_resource(texture)->tex.width0, 1519 r300_resource(texture)->tex.height0); 1520} 1521 1522 1523static void 1524r300_sampler_view_destroy(struct pipe_context *pipe, 1525 struct pipe_sampler_view *view) 1526{ 1527 pipe_resource_reference(&view->texture, NULL); 1528 FREE(view); 1529} 1530 1531static void r300_set_scissor_state(struct pipe_context* pipe, 1532 const struct pipe_scissor_state* state) 1533{ 1534 struct r300_context* r300 = r300_context(pipe); 1535 1536 memcpy(r300->scissor_state.state, state, 1537 sizeof(struct pipe_scissor_state)); 1538 1539 r300_mark_atom_dirty(r300, &r300->scissor_state); 1540} 1541 1542static void r300_set_viewport_state(struct pipe_context* pipe, 1543 const struct pipe_viewport_state* state) 1544{ 1545 struct r300_context* r300 = r300_context(pipe); 1546 struct r300_viewport_state* viewport = 1547 (struct r300_viewport_state*)r300->viewport_state.state; 1548 1549 r300->viewport = *state; 1550 1551 if (r300->draw) { 1552 draw_set_viewport_state(r300->draw, state); 1553 viewport->vte_control = R300_VTX_XY_FMT | R300_VTX_Z_FMT; 1554 return; 1555 } 1556 1557 /* Do the transform in HW. */ 1558 viewport->vte_control = R300_VTX_W0_FMT; 1559 1560 if (state->scale[0] != 1.0f) { 1561 viewport->xscale = state->scale[0]; 1562 viewport->vte_control |= R300_VPORT_X_SCALE_ENA; 1563 } 1564 if (state->scale[1] != 1.0f) { 1565 viewport->yscale = state->scale[1]; 1566 viewport->vte_control |= R300_VPORT_Y_SCALE_ENA; 1567 } 1568 if (state->scale[2] != 1.0f) { 1569 viewport->zscale = state->scale[2]; 1570 viewport->vte_control |= R300_VPORT_Z_SCALE_ENA; 1571 } 1572 if (state->translate[0] != 0.0f) { 1573 viewport->xoffset = state->translate[0]; 1574 viewport->vte_control |= R300_VPORT_X_OFFSET_ENA; 1575 } 1576 if (state->translate[1] != 0.0f) { 1577 viewport->yoffset = state->translate[1]; 1578 viewport->vte_control |= R300_VPORT_Y_OFFSET_ENA; 1579 } 1580 if (state->translate[2] != 0.0f) { 1581 viewport->zoffset = state->translate[2]; 1582 viewport->vte_control |= R300_VPORT_Z_OFFSET_ENA; 1583 } 1584 1585 r300_mark_atom_dirty(r300, &r300->viewport_state); 1586 if (r300->fs.state && r300_fs(r300)->shader && 1587 r300_fs(r300)->shader->inputs.wpos != ATTR_UNUSED) { 1588 r300_mark_atom_dirty(r300, &r300->fs_rc_constant_state); 1589 } 1590} 1591 1592static void r300_set_vertex_buffers_hwtcl(struct pipe_context* pipe, 1593 unsigned count, 1594 const struct pipe_vertex_buffer* buffers) 1595{ 1596 struct r300_context* r300 = r300_context(pipe); 1597 1598 /* There must be at least one vertex buffer set, otherwise it locks up. */ 1599 if (!count) { 1600 buffers = &r300->dummy_vb; 1601 count = 1; 1602 } 1603 1604 util_copy_vertex_buffers(r300->vertex_buffer, 1605 &r300->nr_vertex_buffers, 1606 buffers, count); 1607 1608 r300->vertex_arrays_dirty = TRUE; 1609} 1610 1611static void r300_set_vertex_buffers_swtcl(struct pipe_context* pipe, 1612 unsigned count, 1613 const struct pipe_vertex_buffer* buffers) 1614{ 1615 struct r300_context* r300 = r300_context(pipe); 1616 unsigned i; 1617 1618 util_copy_vertex_buffers(r300->vertex_buffer, 1619 &r300->nr_vertex_buffers, 1620 buffers, count); 1621 draw_set_vertex_buffers(r300->draw, count, buffers); 1622 1623 for (i = 0; i < count; i++) { 1624 if (buffers[i].user_buffer) { 1625 draw_set_mapped_vertex_buffer(r300->draw, i, 1626 buffers[i].user_buffer); 1627 } else if (buffers[i].buffer) { 1628 draw_set_mapped_vertex_buffer(r300->draw, i, 1629 r300_resource(buffers[i].buffer)->malloced_buffer); 1630 } 1631 } 1632} 1633 1634static void r300_set_index_buffer_hwtcl(struct pipe_context* pipe, 1635 const struct pipe_index_buffer *ib) 1636{ 1637 struct r300_context* r300 = r300_context(pipe); 1638 1639 if (ib) { 1640 pipe_resource_reference(&r300->index_buffer.buffer, ib->buffer); 1641 memcpy(&r300->index_buffer, ib, sizeof(*ib)); 1642 } else { 1643 pipe_resource_reference(&r300->index_buffer.buffer, NULL); 1644 } 1645} 1646 1647static void r300_set_index_buffer_swtcl(struct pipe_context* pipe, 1648 const struct pipe_index_buffer *ib) 1649{ 1650 struct r300_context* r300 = r300_context(pipe); 1651 1652 if (ib) { 1653 const void *buf = NULL; 1654 if (ib->user_buffer) { 1655 buf = ib->user_buffer; 1656 } else if (ib->buffer) { 1657 buf = r300_resource(ib->buffer)->malloced_buffer; 1658 } 1659 draw_set_indexes(r300->draw, 1660 (const ubyte *) buf + ib->offset, 1661 ib->index_size); 1662 } 1663} 1664 1665/* Initialize the PSC tables. */ 1666static void r300_vertex_psc(struct r300_vertex_element_state *velems) 1667{ 1668 struct r300_vertex_stream_state *vstream = &velems->vertex_stream; 1669 uint16_t type, swizzle; 1670 enum pipe_format format; 1671 unsigned i; 1672 1673 /* Vertex shaders have no semantics on their inputs, 1674 * so PSC should just route stuff based on the vertex elements, 1675 * and not on attrib information. */ 1676 for (i = 0; i < velems->count; i++) { 1677 format = velems->velem[i].src_format; 1678 1679 type = r300_translate_vertex_data_type(format); 1680 if (type == R300_INVALID_FORMAT) { 1681 fprintf(stderr, "r300: Bad vertex format %s.\n", 1682 util_format_short_name(format)); 1683 assert(0); 1684 abort(); 1685 } 1686 1687 type |= i << R300_DST_VEC_LOC_SHIFT; 1688 swizzle = r300_translate_vertex_data_swizzle(format); 1689 1690 if (i & 1) { 1691 vstream->vap_prog_stream_cntl[i >> 1] |= type << 16; 1692 vstream->vap_prog_stream_cntl_ext[i >> 1] |= swizzle << 16; 1693 } else { 1694 vstream->vap_prog_stream_cntl[i >> 1] |= type; 1695 vstream->vap_prog_stream_cntl_ext[i >> 1] |= swizzle; 1696 } 1697 } 1698 1699 /* Set the last vector in the PSC. */ 1700 if (i) { 1701 i -= 1; 1702 } 1703 vstream->vap_prog_stream_cntl[i >> 1] |= 1704 (R300_LAST_VEC << (i & 1 ? 16 : 0)); 1705 1706 vstream->count = (i >> 1) + 1; 1707} 1708 1709static void* r300_create_vertex_elements_state(struct pipe_context* pipe, 1710 unsigned count, 1711 const struct pipe_vertex_element* attribs) 1712{ 1713 struct r300_vertex_element_state *velems; 1714 unsigned i; 1715 struct pipe_vertex_element dummy_attrib = {0}; 1716 1717 /* R300 Programmable Stream Control (PSC) doesn't support 0 vertex elements. */ 1718 if (!count) { 1719 dummy_attrib.src_format = PIPE_FORMAT_R8G8B8A8_UNORM; 1720 attribs = &dummy_attrib; 1721 count = 1; 1722 } else if (count > 16) { 1723 fprintf(stderr, "r300: More than 16 vertex elements are not supported," 1724 " requested %i, using 16.\n", count); 1725 count = 16; 1726 } 1727 1728 velems = CALLOC_STRUCT(r300_vertex_element_state); 1729 if (!velems) 1730 return NULL; 1731 1732 velems->count = count; 1733 memcpy(velems->velem, attribs, sizeof(struct pipe_vertex_element) * count); 1734 1735 if (r300_screen(pipe->screen)->caps.has_tcl) { 1736 /* Setup PSC. 1737 * The unused components will be replaced by (..., 0, 1). */ 1738 r300_vertex_psc(velems); 1739 1740 for (i = 0; i < count; i++) { 1741 velems->format_size[i] = 1742 align(util_format_get_blocksize(velems->velem[i].src_format), 4); 1743 velems->vertex_size_dwords += velems->format_size[i] / 4; 1744 } 1745 } 1746 1747 return velems; 1748} 1749 1750static void r300_bind_vertex_elements_state(struct pipe_context *pipe, 1751 void *state) 1752{ 1753 struct r300_context *r300 = r300_context(pipe); 1754 struct r300_vertex_element_state *velems = state; 1755 1756 if (velems == NULL) { 1757 return; 1758 } 1759 1760 r300->velems = velems; 1761 1762 if (r300->draw) { 1763 draw_set_vertex_elements(r300->draw, velems->count, velems->velem); 1764 return; 1765 } 1766 1767 UPDATE_STATE(&velems->vertex_stream, r300->vertex_stream_state); 1768 r300->vertex_stream_state.size = (1 + velems->vertex_stream.count) * 2; 1769 r300->vertex_arrays_dirty = TRUE; 1770} 1771 1772static void r300_delete_vertex_elements_state(struct pipe_context *pipe, void *state) 1773{ 1774 FREE(state); 1775} 1776 1777static void* r300_create_vs_state(struct pipe_context* pipe, 1778 const struct pipe_shader_state* shader) 1779{ 1780 struct r300_context* r300 = r300_context(pipe); 1781 struct r300_vertex_shader* vs = CALLOC_STRUCT(r300_vertex_shader); 1782 1783 /* Copy state directly into shader. */ 1784 vs->state = *shader; 1785 vs->state.tokens = tgsi_dup_tokens(shader->tokens); 1786 1787 if (r300->screen->caps.has_tcl) { 1788 r300_init_vs_outputs(r300, vs); 1789 r300_translate_vertex_shader(r300, vs); 1790 } else { 1791 r300_draw_init_vertex_shader(r300, vs); 1792 } 1793 1794 return vs; 1795} 1796 1797static void r300_bind_vs_state(struct pipe_context* pipe, void* shader) 1798{ 1799 struct r300_context* r300 = r300_context(pipe); 1800 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)shader; 1801 1802 if (vs == NULL) { 1803 r300->vs_state.state = NULL; 1804 return; 1805 } 1806 if (vs == r300->vs_state.state) { 1807 return; 1808 } 1809 r300->vs_state.state = vs; 1810 1811 /* The majority of the RS block bits is dependent on the vertex shader. */ 1812 r300_mark_atom_dirty(r300, &r300->rs_block_state); /* Will be updated before the emission. */ 1813 1814 if (r300->screen->caps.has_tcl) { 1815 unsigned fc_op_dwords = r300->screen->caps.is_r500 ? 3 : 2; 1816 r300_mark_atom_dirty(r300, &r300->vs_state); 1817 r300->vs_state.size = vs->code.length + 9 + 1818 (R300_VS_MAX_FC_OPS * fc_op_dwords + 4); 1819 1820 r300_mark_atom_dirty(r300, &r300->vs_constants); 1821 r300->vs_constants.size = 1822 2 + 1823 (vs->externals_count ? vs->externals_count * 4 + 3 : 0) + 1824 (vs->immediates_count ? vs->immediates_count * 4 + 3 : 0); 1825 1826 ((struct r300_constant_buffer*)r300->vs_constants.state)->remap_table = 1827 vs->code.constants_remap_table; 1828 1829 r300_mark_atom_dirty(r300, &r300->pvs_flush); 1830 } else { 1831 draw_bind_vertex_shader(r300->draw, 1832 (struct draw_vertex_shader*)vs->draw_vs); 1833 } 1834} 1835 1836static void r300_delete_vs_state(struct pipe_context* pipe, void* shader) 1837{ 1838 struct r300_context* r300 = r300_context(pipe); 1839 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)shader; 1840 1841 if (r300->screen->caps.has_tcl) { 1842 rc_constants_destroy(&vs->code.constants); 1843 if (vs->code.constants_remap_table) 1844 FREE(vs->code.constants_remap_table); 1845 } else { 1846 draw_delete_vertex_shader(r300->draw, 1847 (struct draw_vertex_shader*)vs->draw_vs); 1848 } 1849 1850 FREE((void*)vs->state.tokens); 1851 FREE(shader); 1852} 1853 1854static void r300_set_constant_buffer(struct pipe_context *pipe, 1855 uint shader, uint index, 1856 struct pipe_constant_buffer *cb) 1857{ 1858 struct r300_context* r300 = r300_context(pipe); 1859 struct r300_constant_buffer *cbuf; 1860 uint32_t *mapped; 1861 1862 if (!cb) 1863 return; 1864 1865 switch (shader) { 1866 case PIPE_SHADER_VERTEX: 1867 cbuf = (struct r300_constant_buffer*)r300->vs_constants.state; 1868 break; 1869 case PIPE_SHADER_FRAGMENT: 1870 cbuf = (struct r300_constant_buffer*)r300->fs_constants.state; 1871 break; 1872 default: 1873 return; 1874 } 1875 1876 1877 if (cb->user_buffer) 1878 mapped = (uint32_t*)cb->user_buffer; 1879 else { 1880 struct r300_resource *rbuf = r300_resource(cb->buffer); 1881 1882 if (rbuf && rbuf->malloced_buffer) 1883 mapped = (uint32_t*)rbuf->malloced_buffer; 1884 else 1885 return; 1886 } 1887 1888 if (shader == PIPE_SHADER_FRAGMENT || 1889 (shader == PIPE_SHADER_VERTEX && r300->screen->caps.has_tcl)) { 1890 cbuf->ptr = mapped; 1891 } 1892 1893 if (shader == PIPE_SHADER_VERTEX) { 1894 if (r300->screen->caps.has_tcl) { 1895 struct r300_vertex_shader *vs = 1896 (struct r300_vertex_shader*)r300->vs_state.state; 1897 1898 if (!vs) { 1899 cbuf->buffer_base = 0; 1900 return; 1901 } 1902 1903 cbuf->buffer_base = r300->vs_const_base; 1904 r300->vs_const_base += vs->code.constants.Count; 1905 if (r300->vs_const_base > R500_MAX_PVS_CONST_VECS) { 1906 r300->vs_const_base = vs->code.constants.Count; 1907 cbuf->buffer_base = 0; 1908 r300_mark_atom_dirty(r300, &r300->pvs_flush); 1909 } 1910 r300_mark_atom_dirty(r300, &r300->vs_constants); 1911 } else if (r300->draw) { 1912 draw_set_mapped_constant_buffer(r300->draw, PIPE_SHADER_VERTEX, 1913 0, mapped, cb->buffer_size); 1914 } 1915 } else if (shader == PIPE_SHADER_FRAGMENT) { 1916 r300_mark_atom_dirty(r300, &r300->fs_constants); 1917 } 1918} 1919 1920static void r300_texture_barrier(struct pipe_context *pipe) 1921{ 1922 struct r300_context *r300 = r300_context(pipe); 1923 1924 r300_mark_atom_dirty(r300, &r300->gpu_flush); 1925 r300_mark_atom_dirty(r300, &r300->texture_cache_inval); 1926} 1927 1928void r300_init_state_functions(struct r300_context* r300) 1929{ 1930 r300->context.create_blend_state = r300_create_blend_state; 1931 r300->context.bind_blend_state = r300_bind_blend_state; 1932 r300->context.delete_blend_state = r300_delete_blend_state; 1933 1934 r300->context.set_blend_color = r300_set_blend_color; 1935 1936 r300->context.set_clip_state = r300_set_clip_state; 1937 r300->context.set_sample_mask = r300_set_sample_mask; 1938 1939 r300->context.set_constant_buffer = r300_set_constant_buffer; 1940 1941 r300->context.create_depth_stencil_alpha_state = r300_create_dsa_state; 1942 r300->context.bind_depth_stencil_alpha_state = r300_bind_dsa_state; 1943 r300->context.delete_depth_stencil_alpha_state = r300_delete_dsa_state; 1944 1945 r300->context.set_stencil_ref = r300_set_stencil_ref; 1946 1947 r300->context.set_framebuffer_state = r300_set_framebuffer_state; 1948 1949 r300->context.create_fs_state = r300_create_fs_state; 1950 r300->context.bind_fs_state = r300_bind_fs_state; 1951 r300->context.delete_fs_state = r300_delete_fs_state; 1952 1953 r300->context.set_polygon_stipple = r300_set_polygon_stipple; 1954 1955 r300->context.create_rasterizer_state = r300_create_rs_state; 1956 r300->context.bind_rasterizer_state = r300_bind_rs_state; 1957 r300->context.delete_rasterizer_state = r300_delete_rs_state; 1958 1959 r300->context.create_sampler_state = r300_create_sampler_state; 1960 r300->context.bind_fragment_sampler_states = r300_bind_sampler_states; 1961 r300->context.bind_vertex_sampler_states = r300_lacks_vertex_textures; 1962 r300->context.delete_sampler_state = r300_delete_sampler_state; 1963 1964 r300->context.set_fragment_sampler_views = r300_set_fragment_sampler_views; 1965 r300->context.create_sampler_view = r300_create_sampler_view; 1966 r300->context.sampler_view_destroy = r300_sampler_view_destroy; 1967 1968 r300->context.set_scissor_state = r300_set_scissor_state; 1969 1970 r300->context.set_viewport_state = r300_set_viewport_state; 1971 1972 if (r300->screen->caps.has_tcl) { 1973 r300->context.set_vertex_buffers = r300_set_vertex_buffers_hwtcl; 1974 r300->context.set_index_buffer = r300_set_index_buffer_hwtcl; 1975 } else { 1976 r300->context.set_vertex_buffers = r300_set_vertex_buffers_swtcl; 1977 r300->context.set_index_buffer = r300_set_index_buffer_swtcl; 1978 } 1979 1980 r300->context.create_vertex_elements_state = r300_create_vertex_elements_state; 1981 r300->context.bind_vertex_elements_state = r300_bind_vertex_elements_state; 1982 r300->context.delete_vertex_elements_state = r300_delete_vertex_elements_state; 1983 1984 r300->context.create_vs_state = r300_create_vs_state; 1985 r300->context.bind_vs_state = r300_bind_vs_state; 1986 r300->context.delete_vs_state = r300_delete_vs_state; 1987 1988 r300->context.texture_barrier = r300_texture_barrier; 1989} 1990