svga_screen.c revision 80efb524ee94efc7c6b8f849b82305144838eea1
1868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles)/**********************************************************
2868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles) * Copyright 2008-2009 VMware, Inc.  All rights reserved.
3868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles) *
4868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles) * Permission is hereby granted, free of charge, to any person
5868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles) * obtaining a copy of this software and associated documentation
6868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles) * files (the "Software"), to deal in the Software without
7868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles) * restriction, including without limitation the rights to use, copy,
8868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles) * modify, merge, publish, distribute, sublicense, and/or sell copies
9868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles) * of the Software, and to permit persons to whom the Software is
10868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles) * furnished to do so, subject to the following conditions:
11868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles) *
12868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles) * The above copyright notice and this permission notice shall be
13868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles) * included in all copies or substantial portions of the Software.
14868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles) *
15868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles) * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles) * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 **********************************************************/
25
26#include "util/u_memory.h"
27#include "util/u_inlines.h"
28#include "util/u_string.h"
29#include "util/u_math.h"
30
31#include "svga_winsys.h"
32#include "svga_public.h"
33#include "svga_context.h"
34#include "svga_format.h"
35#include "svga_screen.h"
36#include "svga_resource_texture.h"
37#include "svga_resource.h"
38#include "svga_debug.h"
39
40#include "svga3d_shaderdefs.h"
41
42
43#ifdef DEBUG
44int SVGA_DEBUG = 0;
45
46static const struct debug_named_value svga_debug_flags[] = {
47   { "dma",      DEBUG_DMA, NULL },
48   { "tgsi",     DEBUG_TGSI, NULL },
49   { "pipe",     DEBUG_PIPE, NULL },
50   { "state",    DEBUG_STATE, NULL },
51   { "screen",   DEBUG_SCREEN, NULL },
52   { "tex",      DEBUG_TEX, NULL },
53   { "swtnl",    DEBUG_SWTNL, NULL },
54   { "const",    DEBUG_CONSTS, NULL },
55   { "viewport", DEBUG_VIEWPORT, NULL },
56   { "views",    DEBUG_VIEWS, NULL },
57   { "perf",     DEBUG_PERF, NULL },
58   { "flush",    DEBUG_FLUSH, NULL },
59   { "sync",     DEBUG_SYNC, NULL },
60   { "cache",    DEBUG_CACHE, NULL },
61   DEBUG_NAMED_VALUE_END
62};
63#endif
64
65static const char *
66svga_get_vendor( struct pipe_screen *pscreen )
67{
68   return "VMware, Inc.";
69}
70
71
72static const char *
73svga_get_name( struct pipe_screen *pscreen )
74{
75   const char *build = "", *llvm = "", *mutex = "";
76   static char name[100];
77#ifdef DEBUG
78   /* Only return internal details in the DEBUG version:
79    */
80   build = "build: DEBUG;";
81   mutex = "mutex: " PIPE_ATOMIC ";";
82#ifdef HAVE_LLVM
83   llvm = "LLVM;";
84#endif
85#else
86   build = "build: RELEASE;";
87#endif
88
89   util_snprintf(name, sizeof(name), "SVGA3D; %s %s %s", build, mutex, llvm);
90   return name;
91}
92
93
94
95
96static float
97svga_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
98{
99   struct svga_screen *svgascreen = svga_screen(screen);
100   struct svga_winsys_screen *sws = svgascreen->sws;
101   SVGA3dDevCapResult result;
102
103   switch (param) {
104   case PIPE_CAPF_MAX_LINE_WIDTH:
105      /* fall-through */
106   case PIPE_CAPF_MAX_LINE_WIDTH_AA:
107      return 7.0;
108
109   case PIPE_CAPF_MAX_POINT_WIDTH:
110      /* fall-through */
111   case PIPE_CAPF_MAX_POINT_WIDTH_AA:
112      return svgascreen->maxPointSize;
113
114   case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
115      if(!sws->get_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY, &result))
116         return 4.0;
117      return result.u;
118
119   case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
120      return 15.0;
121
122   default:
123      debug_printf("Unexpected PIPE_CAPF_ query %u\n", param);
124      return 0;
125   }
126}
127
128
129static int
130svga_get_param(struct pipe_screen *screen, enum pipe_cap param)
131{
132   struct svga_screen *svgascreen = svga_screen(screen);
133   struct svga_winsys_screen *sws = svgascreen->sws;
134   SVGA3dDevCapResult result;
135
136   switch (param) {
137   case PIPE_CAP_MAX_COMBINED_SAMPLERS:
138      return 16;
139   case PIPE_CAP_NPOT_TEXTURES:
140      return 1;
141   case PIPE_CAP_TWO_SIDED_STENCIL:
142      return 1;
143   case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
144      return 0;
145   case PIPE_CAP_ANISOTROPIC_FILTER:
146      return 1;
147   case PIPE_CAP_POINT_SPRITE:
148      return 1;
149   case PIPE_CAP_MAX_RENDER_TARGETS:
150      if(!sws->get_cap(sws, SVGA3D_DEVCAP_MAX_RENDER_TARGETS, &result))
151         return 1;
152      if(!result.u)
153         return 1;
154      return MIN2(result.u, PIPE_MAX_COLOR_BUFS);
155   case PIPE_CAP_OCCLUSION_QUERY:
156      return 1;
157   case PIPE_CAP_TIMER_QUERY:
158      return 0;
159   case PIPE_CAP_TEXTURE_SHADOW_MAP:
160      return 1;
161   case PIPE_CAP_TEXTURE_SWIZZLE:
162      return 1;
163   case PIPE_CAP_USER_VERTEX_BUFFERS:
164   case PIPE_CAP_USER_INDEX_BUFFERS:
165      return 0;
166   case PIPE_CAP_USER_CONSTANT_BUFFERS:
167      return 1;
168   case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
169      return 16;
170
171   case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
172      {
173         unsigned levels = SVGA_MAX_TEXTURE_LEVELS;
174         if (sws->get_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH, &result))
175            levels = MIN2(util_logbase2(result.u) + 1, levels);
176         else
177            levels = 12 /* 2048x2048 */;
178         if (sws->get_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT, &result))
179            levels = MIN2(util_logbase2(result.u) + 1, levels);
180         else
181            levels = 12 /* 2048x2048 */;
182         return levels;
183      }
184
185   case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
186      if (!sws->get_cap(sws, SVGA3D_DEVCAP_MAX_VOLUME_EXTENT, &result))
187         return 8;  /* max 128x128x128 */
188      return MIN2(util_logbase2(result.u) + 1, SVGA_MAX_TEXTURE_LEVELS);
189
190   case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
191      /*
192       * No mechanism to query the host, and at least limited to 2048x2048 on
193       * certain hardware.
194       */
195      return MIN2(screen->get_param(screen, PIPE_CAP_MAX_TEXTURE_2D_LEVELS),
196                  12 /* 2048x2048 */);
197
198   case PIPE_CAP_BLEND_EQUATION_SEPARATE: /* req. for GL 1.5 */
199      return 1;
200
201   case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
202   case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
203      return 1;
204   case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
205   case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
206      return 0;
207
208   case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
209      return 1;
210
211   case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
212      return 1; /* The color outputs of vertex shaders are not clamped */
213   case PIPE_CAP_VERTEX_COLOR_CLAMPED:
214      return 0; /* The driver can't clamp vertex colors */
215   case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
216      return 0; /* The driver can't clamp fragment colors */
217
218   case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
219      return 1; /* expected for GL_ARB_framebuffer_object */
220
221   /* Unsupported features */
222   case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
223   case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
224   case PIPE_CAP_SM3:
225   case PIPE_CAP_SHADER_STENCIL_EXPORT:
226   case PIPE_CAP_DEPTH_CLIP_DISABLE:
227   case PIPE_CAP_SEAMLESS_CUBE_MAP:
228   case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
229   case PIPE_CAP_INDEP_BLEND_ENABLE:
230   case PIPE_CAP_INDEP_BLEND_FUNC:
231   case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
232   case PIPE_CAP_PRIMITIVE_RESTART:
233   case PIPE_CAP_TGSI_INSTANCEID:
234   case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
235   case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
236   case PIPE_CAP_MIN_TEXEL_OFFSET:
237   case PIPE_CAP_MAX_TEXEL_OFFSET:
238   case PIPE_CAP_CONDITIONAL_RENDER:
239   case PIPE_CAP_TEXTURE_BARRIER:
240   case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
241   case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
242   case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
243   case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS:
244   case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
245   case PIPE_CAP_GLSL_FEATURE_LEVEL:
246   case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
247   case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
248   case PIPE_CAP_START_INSTANCE:
249      return 0;
250   case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
251      return 1;
252
253   default:
254      debug_printf("Unexpected PIPE_CAP_ query %u\n", param);
255      return 0;
256   }
257}
258
259static int svga_get_shader_param(struct pipe_screen *screen, unsigned shader, enum pipe_shader_cap param)
260{
261   struct svga_screen *svgascreen = svga_screen(screen);
262   struct svga_winsys_screen *sws = svgascreen->sws;
263   SVGA3dDevCapResult result;
264
265   switch (shader)
266   {
267   case PIPE_SHADER_FRAGMENT:
268      switch (param)
269      {
270      case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
271      case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
272      case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
273      case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
274         return 512;
275      case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
276         return SVGA3D_MAX_NESTING_LEVEL;
277      case PIPE_SHADER_CAP_MAX_INPUTS:
278         return 10;
279      case PIPE_SHADER_CAP_MAX_CONSTS:
280         return 224;
281      case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
282         return 1;
283      case PIPE_SHADER_CAP_MAX_TEMPS:
284         if (!sws->get_cap(sws, SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS, &result))
285            return 32;
286         return MIN2(result.u, SVGA3D_TEMPREG_MAX);
287      case PIPE_SHADER_CAP_MAX_ADDRS:
288      case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
289	 /*
290	  * Although PS 3.0 has some addressing abilities it can only represent
291	  * loops that can be statically determined and unrolled. Given we can
292	  * only handle a subset of the cases that the state tracker already
293	  * does it is better to defer loop unrolling to the state tracker.
294	  */
295         return 0;
296      case PIPE_SHADER_CAP_MAX_PREDS:
297         return 1;
298      case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
299         return 1;
300      case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
301      case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
302      case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
303         return 0;
304      case PIPE_SHADER_CAP_SUBROUTINES:
305         return 0;
306      case PIPE_SHADER_CAP_INTEGERS:
307         return 0;
308      case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
309         return 16;
310      default:
311         debug_printf("Unexpected vertex shader query %u\n", param);
312         return 0;
313      }
314      break;
315   case PIPE_SHADER_VERTEX:
316      switch (param)
317      {
318      case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
319      case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
320         if (!sws->get_cap(sws, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS, &result))
321            return 512;
322         return result.u;
323      case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
324      case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
325         /* XXX: until we have vertex texture support */
326         return 0;
327      case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
328         return SVGA3D_MAX_NESTING_LEVEL;
329      case PIPE_SHADER_CAP_MAX_INPUTS:
330         return 16;
331      case PIPE_SHADER_CAP_MAX_CONSTS:
332         return 256;
333      case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
334         return 1;
335      case PIPE_SHADER_CAP_MAX_TEMPS:
336         if (!sws->get_cap(sws, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS, &result))
337            return 32;
338         return MIN2(result.u, SVGA3D_TEMPREG_MAX);
339      case PIPE_SHADER_CAP_MAX_ADDRS:
340         return 1;
341      case PIPE_SHADER_CAP_MAX_PREDS:
342         return 1;
343      case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
344         return 1;
345      case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
346      case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
347         return 1;
348      case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
349         return 0;
350      case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
351         return 1;
352      case PIPE_SHADER_CAP_SUBROUTINES:
353         return 0;
354      case PIPE_SHADER_CAP_INTEGERS:
355         return 0;
356      case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
357         return 0;
358      default:
359         debug_printf("Unexpected vertex shader query %u\n", param);
360         return 0;
361      }
362      break;
363   case PIPE_SHADER_GEOMETRY:
364      /* no support for geometry shaders at this time */
365      return 0;
366   default:
367      debug_printf("Unexpected vertex shader query %u\n", param);
368      return 0;
369   }
370   return 0;
371}
372
373
374static boolean
375svga_is_format_supported( struct pipe_screen *screen,
376                          enum pipe_format format,
377                          enum pipe_texture_target target,
378                          unsigned sample_count,
379                          unsigned tex_usage)
380{
381   struct svga_screen *ss = svga_screen(screen);
382   SVGA3dSurfaceFormat svga_format;
383   SVGA3dSurfaceFormatCaps caps;
384   SVGA3dSurfaceFormatCaps mask;
385
386   assert(tex_usage);
387
388   if (sample_count > 1) {
389      return FALSE;
390   }
391
392   svga_format = svga_translate_format(ss, format, tex_usage);
393   if (svga_format == SVGA3D_FORMAT_INVALID) {
394      return FALSE;
395   }
396
397   /*
398    * Override host capabilities, so that we end up with the same
399    * visuals for all virtual hardware implementations.
400    */
401
402   if (tex_usage & PIPE_BIND_DISPLAY_TARGET) {
403      switch (svga_format) {
404      case SVGA3D_A8R8G8B8:
405      case SVGA3D_X8R8G8B8:
406      case SVGA3D_R5G6B5:
407         break;
408
409      /* Often unsupported/problematic. This means we end up with the same
410       * visuals for all virtual hardware implementations.
411       */
412      case SVGA3D_A4R4G4B4:
413      case SVGA3D_A1R5G5B5:
414         return FALSE;
415
416      default:
417         return FALSE;
418      }
419   }
420
421   /*
422    * Query the host capabilities.
423    */
424
425   svga_get_format_cap(ss, svga_format, &caps);
426
427   mask.value = 0;
428   if (tex_usage & PIPE_BIND_RENDER_TARGET) {
429      mask.offscreenRenderTarget = 1;
430   }
431   if (tex_usage & PIPE_BIND_DEPTH_STENCIL) {
432      mask.zStencil = 1;
433   }
434   if (tex_usage & PIPE_BIND_SAMPLER_VIEW) {
435      mask.texture = 1;
436   }
437
438   return (caps.value & mask.value) == mask.value;
439}
440
441
442static void
443svga_fence_reference(struct pipe_screen *screen,
444                     struct pipe_fence_handle **ptr,
445                     struct pipe_fence_handle *fence)
446{
447   struct svga_winsys_screen *sws = svga_screen(screen)->sws;
448   sws->fence_reference(sws, ptr, fence);
449}
450
451
452static boolean
453svga_fence_signalled(struct pipe_screen *screen,
454                     struct pipe_fence_handle *fence)
455{
456   struct svga_winsys_screen *sws = svga_screen(screen)->sws;
457   return sws->fence_signalled(sws, fence, 0) == 0;
458}
459
460
461static boolean
462svga_fence_finish(struct pipe_screen *screen,
463                  struct pipe_fence_handle *fence,
464                  uint64_t timeout)
465{
466   struct svga_winsys_screen *sws = svga_screen(screen)->sws;
467
468   SVGA_DBG(DEBUG_DMA|DEBUG_PERF, "%s fence_ptr %p\n",
469            __FUNCTION__, fence);
470
471   return sws->fence_finish(sws, fence, 0) == 0;
472}
473
474
475static void
476svga_destroy_screen( struct pipe_screen *screen )
477{
478   struct svga_screen *svgascreen = svga_screen(screen);
479
480   svga_screen_cache_cleanup(svgascreen);
481
482   pipe_mutex_destroy(svgascreen->swc_mutex);
483   pipe_mutex_destroy(svgascreen->tex_mutex);
484
485   svgascreen->sws->destroy(svgascreen->sws);
486
487   FREE(svgascreen);
488}
489
490
491/**
492 * Create a new svga_screen object
493 */
494struct pipe_screen *
495svga_screen_create(struct svga_winsys_screen *sws)
496{
497   struct svga_screen *svgascreen;
498   struct pipe_screen *screen;
499   SVGA3dDevCapResult result;
500   boolean use_vs30, use_ps30;
501
502#ifdef DEBUG
503   SVGA_DEBUG = debug_get_flags_option("SVGA_DEBUG", svga_debug_flags, 0 );
504#endif
505
506   svgascreen = CALLOC_STRUCT(svga_screen);
507   if (!svgascreen)
508      goto error1;
509
510   svgascreen->debug.force_level_surface_view =
511      debug_get_bool_option("SVGA_FORCE_LEVEL_SURFACE_VIEW", FALSE);
512   svgascreen->debug.force_surface_view =
513      debug_get_bool_option("SVGA_FORCE_SURFACE_VIEW", FALSE);
514   svgascreen->debug.force_sampler_view =
515      debug_get_bool_option("SVGA_FORCE_SAMPLER_VIEW", FALSE);
516   svgascreen->debug.no_surface_view =
517      debug_get_bool_option("SVGA_NO_SURFACE_VIEW", FALSE);
518   svgascreen->debug.no_sampler_view =
519      debug_get_bool_option("SVGA_NO_SAMPLER_VIEW", FALSE);
520
521   screen = &svgascreen->screen;
522
523   screen->destroy = svga_destroy_screen;
524   screen->get_name = svga_get_name;
525   screen->get_vendor = svga_get_vendor;
526   screen->get_param = svga_get_param;
527   screen->get_shader_param = svga_get_shader_param;
528   screen->get_paramf = svga_get_paramf;
529   screen->is_format_supported = svga_is_format_supported;
530   screen->context_create = svga_context_create;
531   screen->fence_reference = svga_fence_reference;
532   screen->fence_signalled = svga_fence_signalled;
533   screen->fence_finish = svga_fence_finish;
534   svgascreen->sws = sws;
535
536   svga_init_screen_resource_functions(svgascreen);
537
538   if (sws->get_hw_version) {
539      svgascreen->hw_version = sws->get_hw_version(sws);
540   } else {
541      svgascreen->hw_version = SVGA3D_HWVERSION_WS65_B1;
542   }
543
544   use_ps30 =
545      sws->get_cap(sws, SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION, &result) &&
546      result.u >= SVGA3DPSVERSION_30 ? TRUE : FALSE;
547
548   use_vs30 =
549      sws->get_cap(sws, SVGA3D_DEVCAP_VERTEX_SHADER_VERSION, &result) &&
550      result.u >= SVGA3DVSVERSION_30 ? TRUE : FALSE;
551
552   /* we require Shader model 3.0 or later */
553   if (!use_ps30 || !use_vs30)
554      goto error2;
555
556   /*
557    * The D16, D24X8, and D24S8 formats always do an implicit shadow compare
558    * when sampled from, where as the DF16, DF24, and D24S8_INT do not.  So
559    * we prefer the later when available.
560    *
561    * This mimics hardware vendors extensions for D3D depth sampling. See also
562    * http://aras-p.info/texts/D3D9GPUHacks.html
563    */
564
565   {
566      boolean has_df16, has_df24, has_d24s8_int;
567      SVGA3dSurfaceFormatCaps caps;
568      SVGA3dSurfaceFormatCaps mask;
569      mask.value = 0;
570      mask.zStencil = 1;
571      mask.texture = 1;
572
573      svgascreen->depth.z16 = SVGA3D_Z_D16;
574      svgascreen->depth.x8z24 = SVGA3D_Z_D24X8;
575      svgascreen->depth.s8z24 = SVGA3D_Z_D24S8;
576
577      svga_get_format_cap(svgascreen, SVGA3D_Z_DF16, &caps);
578      has_df16 = (caps.value & mask.value) == mask.value;
579
580      svga_get_format_cap(svgascreen, SVGA3D_Z_DF24, &caps);
581      has_df24 = (caps.value & mask.value) == mask.value;
582
583      svga_get_format_cap(svgascreen, SVGA3D_Z_D24S8_INT, &caps);
584      has_d24s8_int = (caps.value & mask.value) == mask.value;
585
586      /* XXX: We might want some other logic here.
587       * Like if we only have d24s8_int we should
588       * emulate the other formats with that.
589       */
590      if (has_df16) {
591         svgascreen->depth.z16 = SVGA3D_Z_DF16;
592      }
593      if (has_df24) {
594         svgascreen->depth.x8z24 = SVGA3D_Z_DF24;
595      }
596      if (has_d24s8_int) {
597         svgascreen->depth.s8z24 = SVGA3D_Z_D24S8_INT;
598      }
599   }
600
601   if (!sws->get_cap(sws, SVGA3D_DEVCAP_MAX_POINT_SIZE, &result)) {
602      svgascreen->maxPointSize = 1.0F;
603   } else {
604      /* Keep this to a reasonable size to avoid failures in
605       * conform/pntaa.c:
606       */
607      svgascreen->maxPointSize = MIN2(result.f, 80.0f);
608   }
609
610   pipe_mutex_init(svgascreen->tex_mutex);
611   pipe_mutex_init(svgascreen->swc_mutex);
612
613   svga_screen_cache_init(svgascreen);
614
615   return screen;
616error2:
617   FREE(svgascreen);
618error1:
619   return NULL;
620}
621
622struct svga_winsys_screen *
623svga_winsys_screen(struct pipe_screen *screen)
624{
625   return svga_screen(screen)->sws;
626}
627
628#ifdef DEBUG
629struct svga_screen *
630svga_screen(struct pipe_screen *screen)
631{
632   assert(screen);
633   assert(screen->destroy == svga_destroy_screen);
634   return (struct svga_screen *)screen;
635}
636#endif
637