radeon_drm_bo.c revision 8decb0a96de0accfc8361890cbcf9db89f8fe8ba
1/* 2 * Copyright © 2011 Marek Olšák <maraeo@gmail.com> 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining 6 * a copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 15 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 16 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS 17 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 20 * USE OR OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * The above copyright notice and this permission notice (including the 23 * next paragraph) shall be included in all copies or substantial portions 24 * of the Software. 25 */ 26 27#define _FILE_OFFSET_BITS 64 28#include "radeon_drm_cs.h" 29 30#include "util/u_hash_table.h" 31#include "util/u_memory.h" 32#include "util/u_simple_list.h" 33#include "os/os_thread.h" 34 35#include "state_tracker/drm_driver.h" 36 37#include <sys/ioctl.h> 38#include <sys/mman.h> 39#include <xf86drm.h> 40#include <errno.h> 41 42#define RADEON_BO_FLAGS_MACRO_TILE 1 43#define RADEON_BO_FLAGS_MICRO_TILE 2 44#define RADEON_BO_FLAGS_MICRO_TILE_SQUARE 0x20 45 46extern const struct pb_vtbl radeon_bo_vtbl; 47 48 49static INLINE struct radeon_bo *radeon_bo(struct pb_buffer *bo) 50{ 51 assert(bo->vtbl == &radeon_bo_vtbl); 52 return (struct radeon_bo *)bo; 53} 54 55struct radeon_bomgr { 56 /* Base class. */ 57 struct pb_manager base; 58 59 /* Winsys. */ 60 struct radeon_drm_winsys *rws; 61 62 /* List of buffer handles and its mutex. */ 63 struct util_hash_table *bo_handles; 64 pipe_mutex bo_handles_mutex; 65}; 66 67static INLINE struct radeon_bomgr *radeon_bomgr(struct pb_manager *mgr) 68{ 69 return (struct radeon_bomgr *)mgr; 70} 71 72static struct radeon_bo *get_radeon_bo(struct pb_buffer *_buf) 73{ 74 struct radeon_bo *bo = NULL; 75 76 if (_buf->vtbl == &radeon_bo_vtbl) { 77 bo = radeon_bo(_buf); 78 } else { 79 struct pb_buffer *base_buf; 80 pb_size offset; 81 pb_get_base_buffer(_buf, &base_buf, &offset); 82 83 if (base_buf->vtbl == &radeon_bo_vtbl) 84 bo = radeon_bo(base_buf); 85 } 86 87 return bo; 88} 89 90void radeon_bo_unref(struct radeon_bo *bo) 91{ 92 struct drm_gem_close args = {}; 93 94 if (!p_atomic_dec_zero(&bo->ref_count)) 95 return; 96 97 if (bo->name) { 98 pipe_mutex_lock(bo->mgr->bo_handles_mutex); 99 util_hash_table_remove(bo->mgr->bo_handles, 100 (void*)(uintptr_t)bo->name); 101 pipe_mutex_unlock(bo->mgr->bo_handles_mutex); 102 } 103 104 if (bo->ptr) 105 munmap(bo->ptr, bo->size); 106 107 /* Close object. */ 108 args.handle = bo->handle; 109 drmIoctl(bo->rws->fd, DRM_IOCTL_GEM_CLOSE, &args); 110 pipe_mutex_destroy(bo->map_mutex); 111 FREE(bo); 112} 113 114static void radeon_bo_wait(struct r300_winsys_bo *_buf) 115{ 116 struct radeon_bo *bo = get_radeon_bo(pb_buffer(_buf)); 117 struct drm_radeon_gem_wait_idle args = {}; 118 119 args.handle = bo->handle; 120 while (drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_WAIT_IDLE, 121 &args, sizeof(args)) == -EBUSY); 122} 123 124static boolean radeon_bo_is_busy(struct r300_winsys_bo *_buf) 125{ 126 struct radeon_bo *bo = get_radeon_bo(pb_buffer(_buf)); 127 struct drm_radeon_gem_busy args = {}; 128 129 args.handle = bo->handle; 130 return drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_BUSY, 131 &args, sizeof(args)) != 0; 132} 133 134static void radeon_bo_destroy(struct pb_buffer *_buf) 135{ 136 struct radeon_bo *bo = radeon_bo(_buf); 137 138 radeon_bo_unref(bo); 139} 140 141static unsigned get_pb_usage_from_transfer_flags(enum pipe_transfer_usage usage) 142{ 143 unsigned res = 0; 144 145 if (usage & PIPE_TRANSFER_DONTBLOCK) 146 res |= PB_USAGE_DONTBLOCK; 147 148 if (usage & PIPE_TRANSFER_UNSYNCHRONIZED) 149 res |= PB_USAGE_UNSYNCHRONIZED; 150 151 return res; 152} 153 154static void *radeon_bo_map_internal(struct pb_buffer *_buf, 155 unsigned flags, void *flush_ctx) 156{ 157 struct radeon_bo *bo = radeon_bo(_buf); 158 struct radeon_drm_cs *cs = flush_ctx; 159 struct drm_radeon_gem_mmap args = {}; 160 void *ptr; 161 /* prevents a call to radeon_bo_wait if (usage & DONTBLOCK) and 162 * radeon_is_busy returns FALSE. */ 163 boolean may_be_busy = TRUE; 164 165 if (flags & PB_USAGE_DONTBLOCK) { 166 if (radeon_bo_is_referenced_by_cs(cs, bo)) { 167 cs->flush_cs(cs->flush_data); 168 return NULL; 169 } 170 171 if (radeon_bo_is_busy((struct r300_winsys_bo*)bo)) { 172 return NULL; 173 } 174 175 may_be_busy = FALSE; 176 } 177 178 /* If it's not unsynchronized bo_map, flush CS if needed and then wait. */ 179 if (may_be_busy && !(flags & PB_USAGE_UNSYNCHRONIZED)) { 180 if (radeon_bo_is_referenced_by_cs(cs, bo)) { 181 cs->flush_cs(cs->flush_data); 182 } 183 184 radeon_bo_wait((struct r300_winsys_bo*)bo); 185 } 186 187 /* Return the pointer if it's already mapped. */ 188 if (bo->ptr) 189 return bo->ptr; 190 191 /* Map the buffer. */ 192 pipe_mutex_lock(bo->map_mutex); 193 args.handle = bo->handle; 194 args.offset = 0; 195 args.size = (uint64_t)bo->size; 196 if (drmCommandWriteRead(bo->rws->fd, 197 DRM_RADEON_GEM_MMAP, 198 &args, 199 sizeof(args))) { 200 pipe_mutex_unlock(bo->map_mutex); 201 fprintf(stderr, "radeon: gem_mmap failed: %p 0x%08X\n", 202 bo, bo->handle); 203 return NULL; 204 } 205 206 ptr = mmap(0, args.size, PROT_READ|PROT_WRITE, MAP_SHARED, 207 bo->rws->fd, args.addr_ptr); 208 if (ptr == MAP_FAILED) { 209 pipe_mutex_unlock(bo->map_mutex); 210 fprintf(stderr, "radeon: mmap failed, errno: %i\n", errno); 211 return NULL; 212 } 213 bo->ptr = ptr; 214 pipe_mutex_unlock(bo->map_mutex); 215 216 return bo->ptr; 217} 218 219static void radeon_bo_unmap_internal(struct pb_buffer *_buf) 220{ 221 /* NOP */ 222} 223 224static void radeon_bo_get_base_buffer(struct pb_buffer *buf, 225 struct pb_buffer **base_buf, 226 unsigned *offset) 227{ 228 *base_buf = buf; 229 *offset = 0; 230} 231 232static enum pipe_error radeon_bo_validate(struct pb_buffer *_buf, 233 struct pb_validate *vl, 234 unsigned flags) 235{ 236 /* Always pinned */ 237 return PIPE_OK; 238} 239 240static void radeon_bo_fence(struct pb_buffer *buf, 241 struct pipe_fence_handle *fence) 242{ 243} 244 245const struct pb_vtbl radeon_bo_vtbl = { 246 radeon_bo_destroy, 247 radeon_bo_map_internal, 248 radeon_bo_unmap_internal, 249 radeon_bo_validate, 250 radeon_bo_fence, 251 radeon_bo_get_base_buffer, 252}; 253 254static struct pb_buffer *radeon_bomgr_create_bo(struct pb_manager *_mgr, 255 pb_size size, 256 const struct pb_desc *desc) 257{ 258 struct radeon_bomgr *mgr = radeon_bomgr(_mgr); 259 struct radeon_drm_winsys *rws = mgr->rws; 260 struct radeon_bo *bo; 261 struct drm_radeon_gem_create args = {}; 262 263 args.size = size; 264 args.alignment = desc->alignment; 265 args.initial_domain = 266 (desc->usage & RADEON_PB_USAGE_DOMAIN_GTT ? 267 RADEON_GEM_DOMAIN_GTT : 0) | 268 (desc->usage & RADEON_PB_USAGE_DOMAIN_VRAM ? 269 RADEON_GEM_DOMAIN_VRAM : 0); 270 271 if (drmCommandWriteRead(rws->fd, DRM_RADEON_GEM_CREATE, 272 &args, sizeof(args))) { 273 fprintf(stderr, "Failed to allocate :\n"); 274 fprintf(stderr, " size : %d bytes\n", size); 275 fprintf(stderr, " alignment : %d bytes\n", desc->alignment); 276 fprintf(stderr, " domains : %d\n", args.initial_domain); 277 return NULL; 278 } 279 280 bo = CALLOC_STRUCT(radeon_bo); 281 if (!bo) 282 return NULL; 283 284 pipe_reference_init(&bo->base.base.reference, 1); 285 bo->base.base.alignment = desc->alignment; 286 bo->base.base.usage = desc->usage; 287 bo->base.base.size = size; 288 bo->base.vtbl = &radeon_bo_vtbl; 289 bo->mgr = mgr; 290 bo->rws = mgr->rws; 291 bo->handle = args.handle; 292 bo->size = size; 293 pipe_mutex_init(bo->map_mutex); 294 295 radeon_bo_ref(bo); 296 return &bo->base; 297} 298 299static void radeon_bomgr_flush(struct pb_manager *mgr) 300{ 301 /* NOP */ 302} 303 304/* This is for the cache bufmgr. */ 305static boolean radeon_bomgr_is_buffer_busy(struct pb_manager *_mgr, 306 struct pb_buffer *_buf) 307{ 308 struct radeon_bo *bo = radeon_bo(_buf); 309 310 if (radeon_bo_is_referenced_by_any_cs(bo)) { 311 return FALSE; 312 } 313 314 if (radeon_bo_is_busy((struct r300_winsys_bo*)bo)) { 315 return FALSE; 316 } 317 318 return TRUE; 319} 320 321static void radeon_bomgr_destroy(struct pb_manager *_mgr) 322{ 323 struct radeon_bomgr *mgr = radeon_bomgr(_mgr); 324 util_hash_table_destroy(mgr->bo_handles); 325 pipe_mutex_destroy(mgr->bo_handles_mutex); 326 FREE(mgr); 327} 328 329#define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x))) 330 331static unsigned handle_hash(void *key) 332{ 333 return PTR_TO_UINT(key); 334} 335 336static int handle_compare(void *key1, void *key2) 337{ 338 return PTR_TO_UINT(key1) != PTR_TO_UINT(key2); 339} 340 341struct pb_manager *radeon_bomgr_create(struct radeon_drm_winsys *rws) 342{ 343 struct radeon_bomgr *mgr; 344 345 mgr = CALLOC_STRUCT(radeon_bomgr); 346 if (!mgr) 347 return NULL; 348 349 mgr->base.destroy = radeon_bomgr_destroy; 350 mgr->base.create_buffer = radeon_bomgr_create_bo; 351 mgr->base.flush = radeon_bomgr_flush; 352 mgr->base.is_buffer_busy = radeon_bomgr_is_buffer_busy; 353 354 mgr->rws = rws; 355 mgr->bo_handles = util_hash_table_create(handle_hash, handle_compare); 356 pipe_mutex_init(mgr->bo_handles_mutex); 357 return &mgr->base; 358} 359 360static void *radeon_bo_map(struct r300_winsys_bo *buf, 361 struct r300_winsys_cs *cs, 362 enum pipe_transfer_usage usage) 363{ 364 struct pb_buffer *_buf = pb_buffer(buf); 365 366 return pb_map(_buf, get_pb_usage_from_transfer_flags(usage), cs); 367} 368 369static void radeon_bo_get_tiling(struct r300_winsys_bo *_buf, 370 enum r300_buffer_tiling *microtiled, 371 enum r300_buffer_tiling *macrotiled) 372{ 373 struct radeon_bo *bo = get_radeon_bo(pb_buffer(_buf)); 374 struct drm_radeon_gem_set_tiling args = {}; 375 376 args.handle = bo->handle; 377 378 drmCommandWriteRead(bo->rws->fd, 379 DRM_RADEON_GEM_GET_TILING, 380 &args, 381 sizeof(args)); 382 383 *microtiled = R300_BUFFER_LINEAR; 384 *macrotiled = R300_BUFFER_LINEAR; 385 if (args.tiling_flags & RADEON_BO_FLAGS_MICRO_TILE) 386 *microtiled = R300_BUFFER_TILED; 387 388 if (args.tiling_flags & RADEON_BO_FLAGS_MACRO_TILE) 389 *macrotiled = R300_BUFFER_TILED; 390} 391 392static void radeon_bo_set_tiling(struct r300_winsys_bo *_buf, 393 enum r300_buffer_tiling microtiled, 394 enum r300_buffer_tiling macrotiled, 395 uint32_t pitch) 396{ 397 struct radeon_bo *bo = get_radeon_bo(pb_buffer(_buf)); 398 struct drm_radeon_gem_set_tiling args = {}; 399 400 if (microtiled == R300_BUFFER_TILED) 401 args.tiling_flags |= RADEON_BO_FLAGS_MICRO_TILE; 402 else if (microtiled == R300_BUFFER_SQUARETILED) 403 args.tiling_flags |= RADEON_BO_FLAGS_MICRO_TILE_SQUARE; 404 405 if (macrotiled == R300_BUFFER_TILED) 406 args.tiling_flags |= RADEON_BO_FLAGS_MACRO_TILE; 407 408 args.handle = bo->handle; 409 args.pitch = pitch; 410 411 drmCommandWriteRead(bo->rws->fd, 412 DRM_RADEON_GEM_SET_TILING, 413 &args, 414 sizeof(args)); 415} 416 417static struct r300_winsys_cs_handle *radeon_drm_get_cs_handle( 418 struct r300_winsys_bo *_buf) 419{ 420 /* return radeon_bo. */ 421 return (struct r300_winsys_cs_handle*) 422 get_radeon_bo(pb_buffer(_buf)); 423} 424 425static unsigned get_pb_usage_from_create_flags(unsigned bind, unsigned usage, 426 enum r300_buffer_domain domain) 427{ 428 unsigned res = 0; 429 430 if (bind & (PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER)) 431 res |= RADEON_PB_USAGE_CACHE; 432 433 if (domain & R300_DOMAIN_GTT) 434 res |= RADEON_PB_USAGE_DOMAIN_GTT; 435 436 if (domain & R300_DOMAIN_VRAM) 437 res |= RADEON_PB_USAGE_DOMAIN_VRAM; 438 439 return res; 440} 441 442static struct r300_winsys_bo * 443radeon_winsys_bo_create(struct r300_winsys_screen *rws, 444 unsigned size, 445 unsigned alignment, 446 unsigned bind, 447 unsigned usage, 448 enum r300_buffer_domain domain) 449{ 450 struct radeon_drm_winsys *ws = radeon_drm_winsys(rws); 451 struct pb_desc desc; 452 struct pb_manager *provider; 453 struct pb_buffer *buffer; 454 455 memset(&desc, 0, sizeof(desc)); 456 desc.alignment = alignment; 457 desc.usage = get_pb_usage_from_create_flags(bind, usage, domain); 458 459 /* Assign a buffer manager. */ 460 if (bind & (PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER)) 461 provider = ws->cman; 462 else 463 provider = ws->kman; 464 465 buffer = provider->create_buffer(provider, size, &desc); 466 if (!buffer) 467 return NULL; 468 469 return (struct r300_winsys_bo*)buffer; 470} 471 472static struct r300_winsys_bo *radeon_winsys_bo_from_handle(struct r300_winsys_screen *rws, 473 struct winsys_handle *whandle, 474 unsigned *stride, 475 unsigned *size) 476{ 477 struct radeon_drm_winsys *ws = radeon_drm_winsys(rws); 478 struct radeon_bo *bo; 479 struct radeon_bomgr *mgr = radeon_bomgr(ws->kman); 480 struct drm_gem_open open_arg = {}; 481 482 /* We must maintain a list of pairs <handle, bo>, so that we always return 483 * the same BO for one particular handle. If we didn't do that and created 484 * more than one BO for the same handle and then relocated them in a CS, 485 * we would hit a deadlock in the kernel. 486 * 487 * The list of pairs is guarded by a mutex, of course. */ 488 pipe_mutex_lock(mgr->bo_handles_mutex); 489 490 /* First check if there already is an existing bo for the handle. */ 491 bo = util_hash_table_get(mgr->bo_handles, (void*)(uintptr_t)whandle->handle); 492 if (bo) { 493 /* Increase the refcount. */ 494 struct pb_buffer *b = NULL; 495 pb_reference(&b, &bo->base); 496 goto done; 497 } 498 499 /* There isn't, create a new one. */ 500 bo = CALLOC_STRUCT(radeon_bo); 501 if (!bo) { 502 goto fail; 503 } 504 505 /* Open the BO. */ 506 open_arg.name = whandle->handle; 507 if (drmIoctl(ws->fd, DRM_IOCTL_GEM_OPEN, &open_arg)) { 508 FREE(bo); 509 goto fail; 510 } 511 bo->handle = open_arg.handle; 512 bo->size = open_arg.size; 513 bo->name = whandle->handle; 514 radeon_bo_ref(bo); 515 516 /* Initialize it. */ 517 pipe_reference_init(&bo->base.base.reference, 1); 518 bo->base.base.alignment = 0; 519 bo->base.base.usage = PB_USAGE_GPU_WRITE | PB_USAGE_GPU_READ; 520 bo->base.base.size = bo->size; 521 bo->base.vtbl = &radeon_bo_vtbl; 522 bo->mgr = mgr; 523 bo->rws = mgr->rws; 524 pipe_mutex_init(bo->map_mutex); 525 526 util_hash_table_set(mgr->bo_handles, (void*)(uintptr_t)whandle->handle, bo); 527 528done: 529 pipe_mutex_unlock(mgr->bo_handles_mutex); 530 531 if (stride) 532 *stride = whandle->stride; 533 if (size) 534 *size = bo->base.base.size; 535 536 return (struct r300_winsys_bo*)bo; 537 538fail: 539 pipe_mutex_unlock(mgr->bo_handles_mutex); 540 return NULL; 541} 542 543static boolean radeon_winsys_bo_get_handle(struct r300_winsys_bo *buffer, 544 unsigned stride, 545 struct winsys_handle *whandle) 546{ 547 struct drm_gem_flink flink = {}; 548 struct radeon_bo *bo = get_radeon_bo(pb_buffer(buffer)); 549 550 if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) { 551 if (!bo->flinked) { 552 flink.handle = bo->handle; 553 554 if (ioctl(bo->rws->fd, DRM_IOCTL_GEM_FLINK, &flink)) { 555 return FALSE; 556 } 557 558 bo->flinked = TRUE; 559 bo->flink = flink.name; 560 } 561 whandle->handle = bo->flink; 562 } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) { 563 whandle->handle = bo->handle; 564 } 565 566 whandle->stride = stride; 567 return TRUE; 568} 569 570void radeon_bomgr_init_functions(struct radeon_drm_winsys *ws) 571{ 572 ws->base.buffer_get_cs_handle = radeon_drm_get_cs_handle; 573 ws->base.buffer_set_tiling = radeon_bo_set_tiling; 574 ws->base.buffer_get_tiling = radeon_bo_get_tiling; 575 ws->base.buffer_map = radeon_bo_map; 576 ws->base.buffer_unmap = pb_unmap; 577 ws->base.buffer_wait = radeon_bo_wait; 578 ws->base.buffer_is_busy = radeon_bo_is_busy; 579 ws->base.buffer_create = radeon_winsys_bo_create; 580 ws->base.buffer_from_handle = radeon_winsys_bo_from_handle; 581 ws->base.buffer_get_handle = radeon_winsys_bo_get_handle; 582} 583