radeon_drm_bo.c revision bfa51dfeac67a7e3383614374c86bdfb5751997a
1/* 2 * Copyright © 2011 Marek Olšák <maraeo@gmail.com> 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining 6 * a copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 15 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 16 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS 17 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 20 * USE OR OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * The above copyright notice and this permission notice (including the 23 * next paragraph) shall be included in all copies or substantial portions 24 * of the Software. 25 */ 26 27#define _FILE_OFFSET_BITS 64 28#include "radeon_drm_cs.h" 29 30#include "util/u_hash_table.h" 31#include "util/u_memory.h" 32#include "util/u_simple_list.h" 33#include "os/os_thread.h" 34#include "os/os_mman.h" 35 36#include "state_tracker/drm_driver.h" 37 38#include <sys/ioctl.h> 39#include <xf86drm.h> 40#include <errno.h> 41 42#define RADEON_BO_FLAGS_MACRO_TILE 1 43#define RADEON_BO_FLAGS_MICRO_TILE 2 44#define RADEON_BO_FLAGS_MICRO_TILE_SQUARE 0x20 45 46#ifndef DRM_RADEON_GEM_WAIT 47#define DRM_RADEON_GEM_WAIT 0x2b 48 49#define RADEON_GEM_NO_WAIT 0x1 50#define RADEON_GEM_USAGE_READ 0x2 51#define RADEON_GEM_USAGE_WRITE 0x4 52 53struct drm_radeon_gem_wait { 54 uint32_t handle; 55 uint32_t flags; /* one of RADEON_GEM_* */ 56}; 57 58#endif 59 60 61extern const struct pb_vtbl radeon_bo_vtbl; 62 63 64static INLINE struct radeon_bo *radeon_bo(struct pb_buffer *bo) 65{ 66 assert(bo->vtbl == &radeon_bo_vtbl); 67 return (struct radeon_bo *)bo; 68} 69 70struct radeon_bomgr { 71 /* Base class. */ 72 struct pb_manager base; 73 74 /* Winsys. */ 75 struct radeon_drm_winsys *rws; 76 77 /* List of buffer handles and its mutex. */ 78 struct util_hash_table *bo_handles; 79 pipe_mutex bo_handles_mutex; 80}; 81 82static INLINE struct radeon_bomgr *radeon_bomgr(struct pb_manager *mgr) 83{ 84 return (struct radeon_bomgr *)mgr; 85} 86 87static struct radeon_bo *get_radeon_bo(struct pb_buffer *_buf) 88{ 89 struct radeon_bo *bo = NULL; 90 91 if (_buf->vtbl == &radeon_bo_vtbl) { 92 bo = radeon_bo(_buf); 93 } else { 94 struct pb_buffer *base_buf; 95 pb_size offset; 96 pb_get_base_buffer(_buf, &base_buf, &offset); 97 98 if (base_buf->vtbl == &radeon_bo_vtbl) 99 bo = radeon_bo(base_buf); 100 } 101 102 return bo; 103} 104 105static void radeon_bo_wait(struct pb_buffer *_buf, enum radeon_bo_usage usage) 106{ 107 struct radeon_bo *bo = get_radeon_bo(_buf); 108 109 while (p_atomic_read(&bo->num_active_ioctls)) { 110 sched_yield(); 111 } 112 113 if (bo->rws->info.drm_minor >= 12) { 114 struct drm_radeon_gem_wait args = {}; 115 args.handle = bo->handle; 116 args.flags = usage; 117 while (drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_WAIT, 118 &args, sizeof(args)) == -EBUSY); 119 } else { 120 struct drm_radeon_gem_wait_idle args = {}; 121 args.handle = bo->handle; 122 while (drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_WAIT_IDLE, 123 &args, sizeof(args)) == -EBUSY); 124 } 125} 126 127static boolean radeon_bo_is_busy(struct pb_buffer *_buf, 128 enum radeon_bo_usage usage) 129{ 130 struct radeon_bo *bo = get_radeon_bo(_buf); 131 132 if (p_atomic_read(&bo->num_active_ioctls)) { 133 return TRUE; 134 } 135 136 if (bo->rws->info.drm_minor >= 12) { 137 struct drm_radeon_gem_wait args = {}; 138 args.handle = bo->handle; 139 args.flags = usage | RADEON_GEM_NO_WAIT; 140 return drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_WAIT, 141 &args, sizeof(args)) != 0; 142 } else { 143 struct drm_radeon_gem_busy args = {}; 144 args.handle = bo->handle; 145 return drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_BUSY, 146 &args, sizeof(args)) != 0; 147 } 148} 149 150static void radeon_bo_destroy(struct pb_buffer *_buf) 151{ 152 struct radeon_bo *bo = radeon_bo(_buf); 153 struct drm_gem_close args = {}; 154 155 if (bo->name) { 156 pipe_mutex_lock(bo->mgr->bo_handles_mutex); 157 util_hash_table_remove(bo->mgr->bo_handles, 158 (void*)(uintptr_t)bo->name); 159 pipe_mutex_unlock(bo->mgr->bo_handles_mutex); 160 } 161 162 if (bo->ptr) 163 os_munmap(bo->ptr, bo->size); 164 165 /* Close object. */ 166 args.handle = bo->handle; 167 drmIoctl(bo->rws->fd, DRM_IOCTL_GEM_CLOSE, &args); 168 pipe_mutex_destroy(bo->map_mutex); 169 FREE(bo); 170} 171 172static unsigned get_pb_usage_from_transfer_flags(enum pipe_transfer_usage usage) 173{ 174 unsigned res = 0; 175 176 if (usage & PIPE_TRANSFER_WRITE) 177 res |= PB_USAGE_CPU_WRITE; 178 179 if (usage & PIPE_TRANSFER_DONTBLOCK) 180 res |= PB_USAGE_DONTBLOCK; 181 182 if (usage & PIPE_TRANSFER_UNSYNCHRONIZED) 183 res |= PB_USAGE_UNSYNCHRONIZED; 184 185 return res; 186} 187 188static void *radeon_bo_map_internal(struct pb_buffer *_buf, 189 unsigned flags, void *flush_ctx) 190{ 191 struct radeon_bo *bo = radeon_bo(_buf); 192 struct radeon_drm_cs *cs = flush_ctx; 193 struct drm_radeon_gem_mmap args = {}; 194 void *ptr; 195 196 /* If it's not unsynchronized bo_map, flush CS if needed and then wait. */ 197 if (!(flags & PB_USAGE_UNSYNCHRONIZED)) { 198 /* DONTBLOCK doesn't make sense with UNSYNCHRONIZED. */ 199 if (flags & PB_USAGE_DONTBLOCK) { 200 if (!(flags & PB_USAGE_CPU_WRITE)) { 201 /* Mapping for read. 202 * 203 * Since we are mapping for read, we don't need to wait 204 * if the GPU is using the buffer for read too 205 * (neither one is changing it). 206 * 207 * Only check whether the buffer is being used for write. */ 208 if (radeon_bo_is_referenced_by_cs_for_write(cs, bo)) { 209 cs->flush_cs(cs->flush_data, RADEON_FLUSH_ASYNC); 210 return NULL; 211 } 212 213 if (radeon_bo_is_busy((struct pb_buffer*)bo, 214 RADEON_USAGE_WRITE)) { 215 return NULL; 216 } 217 } else { 218 if (radeon_bo_is_referenced_by_cs(cs, bo)) { 219 cs->flush_cs(cs->flush_data, RADEON_FLUSH_ASYNC); 220 return NULL; 221 } 222 223 if (radeon_bo_is_busy((struct pb_buffer*)bo, 224 RADEON_USAGE_READWRITE)) { 225 return NULL; 226 } 227 } 228 } else { 229 if (!(flags & PB_USAGE_CPU_WRITE)) { 230 /* Mapping for read. 231 * 232 * Since we are mapping for read, we don't need to wait 233 * if the GPU is using the buffer for read too 234 * (neither one is changing it). 235 * 236 * Only check whether the buffer is being used for write. */ 237 if (radeon_bo_is_referenced_by_cs_for_write(cs, bo)) { 238 cs->flush_cs(cs->flush_data, 0); 239 } 240 radeon_bo_wait((struct pb_buffer*)bo, 241 RADEON_USAGE_WRITE); 242 } else { 243 /* Mapping for write. */ 244 if (radeon_bo_is_referenced_by_cs(cs, bo)) { 245 cs->flush_cs(cs->flush_data, 0); 246 } else { 247 /* Try to avoid busy-waiting in radeon_bo_wait. */ 248 if (p_atomic_read(&bo->num_active_ioctls)) 249 radeon_drm_cs_sync_flush(cs); 250 } 251 252 radeon_bo_wait((struct pb_buffer*)bo, RADEON_USAGE_READWRITE); 253 } 254 } 255 } 256 257 /* Return the pointer if it's already mapped. */ 258 if (bo->ptr) 259 return bo->ptr; 260 261 /* Map the buffer. */ 262 pipe_mutex_lock(bo->map_mutex); 263 /* Return the pointer if it's already mapped (in case of a race). */ 264 if (bo->ptr) { 265 pipe_mutex_unlock(bo->map_mutex); 266 return bo->ptr; 267 } 268 args.handle = bo->handle; 269 args.offset = 0; 270 args.size = (uint64_t)bo->size; 271 if (drmCommandWriteRead(bo->rws->fd, 272 DRM_RADEON_GEM_MMAP, 273 &args, 274 sizeof(args))) { 275 pipe_mutex_unlock(bo->map_mutex); 276 fprintf(stderr, "radeon: gem_mmap failed: %p 0x%08X\n", 277 bo, bo->handle); 278 return NULL; 279 } 280 281 ptr = os_mmap(0, args.size, PROT_READ|PROT_WRITE, MAP_SHARED, 282 bo->rws->fd, args.addr_ptr); 283 if (ptr == MAP_FAILED) { 284 pipe_mutex_unlock(bo->map_mutex); 285 fprintf(stderr, "radeon: mmap failed, errno: %i\n", errno); 286 return NULL; 287 } 288 bo->ptr = ptr; 289 pipe_mutex_unlock(bo->map_mutex); 290 291 return bo->ptr; 292} 293 294static void radeon_bo_unmap_internal(struct pb_buffer *_buf) 295{ 296 /* NOP */ 297} 298 299static void radeon_bo_get_base_buffer(struct pb_buffer *buf, 300 struct pb_buffer **base_buf, 301 unsigned *offset) 302{ 303 *base_buf = buf; 304 *offset = 0; 305} 306 307static enum pipe_error radeon_bo_validate(struct pb_buffer *_buf, 308 struct pb_validate *vl, 309 unsigned flags) 310{ 311 /* Always pinned */ 312 return PIPE_OK; 313} 314 315static void radeon_bo_fence(struct pb_buffer *buf, 316 struct pipe_fence_handle *fence) 317{ 318} 319 320const struct pb_vtbl radeon_bo_vtbl = { 321 radeon_bo_destroy, 322 radeon_bo_map_internal, 323 radeon_bo_unmap_internal, 324 radeon_bo_validate, 325 radeon_bo_fence, 326 radeon_bo_get_base_buffer, 327}; 328 329static struct pb_buffer *radeon_bomgr_create_bo(struct pb_manager *_mgr, 330 pb_size size, 331 const struct pb_desc *desc) 332{ 333 struct radeon_bomgr *mgr = radeon_bomgr(_mgr); 334 struct radeon_drm_winsys *rws = mgr->rws; 335 struct radeon_bo *bo; 336 struct drm_radeon_gem_create args = {}; 337 struct radeon_bo_desc *rdesc = (struct radeon_bo_desc*)desc; 338 339 args.size = size; 340 args.alignment = desc->alignment; 341 args.initial_domain = rdesc->initial_domains; 342 343 if (drmCommandWriteRead(rws->fd, DRM_RADEON_GEM_CREATE, 344 &args, sizeof(args))) { 345 fprintf(stderr, "radeon: Failed to allocate a buffer:\n"); 346 fprintf(stderr, "radeon: size : %d bytes\n", size); 347 fprintf(stderr, "radeon: alignment : %d bytes\n", desc->alignment); 348 fprintf(stderr, "radeon: domains : %d\n", args.initial_domain); 349 return NULL; 350 } 351 352 bo = CALLOC_STRUCT(radeon_bo); 353 if (!bo) 354 return NULL; 355 356 pipe_reference_init(&bo->base.reference, 1); 357 bo->base.alignment = desc->alignment; 358 bo->base.usage = desc->usage; 359 bo->base.size = size; 360 bo->base.vtbl = &radeon_bo_vtbl; 361 bo->mgr = mgr; 362 bo->rws = mgr->rws; 363 bo->handle = args.handle; 364 bo->size = size; 365 pipe_mutex_init(bo->map_mutex); 366 367 return &bo->base; 368} 369 370static void radeon_bomgr_flush(struct pb_manager *mgr) 371{ 372 /* NOP */ 373} 374 375/* This is for the cache bufmgr. */ 376static boolean radeon_bomgr_is_buffer_busy(struct pb_manager *_mgr, 377 struct pb_buffer *_buf) 378{ 379 struct radeon_bo *bo = radeon_bo(_buf); 380 381 if (radeon_bo_is_referenced_by_any_cs(bo)) { 382 return TRUE; 383 } 384 385 if (radeon_bo_is_busy((struct pb_buffer*)bo, RADEON_USAGE_READWRITE)) { 386 return TRUE; 387 } 388 389 return FALSE; 390} 391 392static void radeon_bomgr_destroy(struct pb_manager *_mgr) 393{ 394 struct radeon_bomgr *mgr = radeon_bomgr(_mgr); 395 util_hash_table_destroy(mgr->bo_handles); 396 pipe_mutex_destroy(mgr->bo_handles_mutex); 397 FREE(mgr); 398} 399 400#define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x))) 401 402static unsigned handle_hash(void *key) 403{ 404 return PTR_TO_UINT(key); 405} 406 407static int handle_compare(void *key1, void *key2) 408{ 409 return PTR_TO_UINT(key1) != PTR_TO_UINT(key2); 410} 411 412struct pb_manager *radeon_bomgr_create(struct radeon_drm_winsys *rws) 413{ 414 struct radeon_bomgr *mgr; 415 416 mgr = CALLOC_STRUCT(radeon_bomgr); 417 if (!mgr) 418 return NULL; 419 420 mgr->base.destroy = radeon_bomgr_destroy; 421 mgr->base.create_buffer = radeon_bomgr_create_bo; 422 mgr->base.flush = radeon_bomgr_flush; 423 mgr->base.is_buffer_busy = radeon_bomgr_is_buffer_busy; 424 425 mgr->rws = rws; 426 mgr->bo_handles = util_hash_table_create(handle_hash, handle_compare); 427 pipe_mutex_init(mgr->bo_handles_mutex); 428 return &mgr->base; 429} 430 431static void *radeon_bo_map(struct pb_buffer *buf, 432 struct radeon_winsys_cs *cs, 433 enum pipe_transfer_usage usage) 434{ 435 return pb_map(buf, get_pb_usage_from_transfer_flags(usage), cs); 436} 437 438static void radeon_bo_get_tiling(struct pb_buffer *_buf, 439 enum radeon_bo_layout *microtiled, 440 enum radeon_bo_layout *macrotiled) 441{ 442 struct radeon_bo *bo = get_radeon_bo(_buf); 443 struct drm_radeon_gem_set_tiling args = {}; 444 445 args.handle = bo->handle; 446 447 drmCommandWriteRead(bo->rws->fd, 448 DRM_RADEON_GEM_GET_TILING, 449 &args, 450 sizeof(args)); 451 452 *microtiled = RADEON_LAYOUT_LINEAR; 453 *macrotiled = RADEON_LAYOUT_LINEAR; 454 if (args.tiling_flags & RADEON_BO_FLAGS_MICRO_TILE) 455 *microtiled = RADEON_LAYOUT_TILED; 456 457 if (args.tiling_flags & RADEON_BO_FLAGS_MACRO_TILE) 458 *macrotiled = RADEON_LAYOUT_TILED; 459} 460 461static void radeon_bo_set_tiling(struct pb_buffer *_buf, 462 struct radeon_winsys_cs *rcs, 463 enum radeon_bo_layout microtiled, 464 enum radeon_bo_layout macrotiled, 465 uint32_t pitch) 466{ 467 struct radeon_bo *bo = get_radeon_bo(_buf); 468 struct radeon_drm_cs *cs = radeon_drm_cs(rcs); 469 struct drm_radeon_gem_set_tiling args = {}; 470 471 /* Tiling determines how DRM treats the buffer data. 472 * We must flush CS when changing it if the buffer is referenced. */ 473 if (cs && radeon_bo_is_referenced_by_cs(cs, bo)) { 474 cs->flush_cs(cs->flush_data, 0); 475 } 476 477 while (p_atomic_read(&bo->num_active_ioctls)) { 478 sched_yield(); 479 } 480 481 if (microtiled == RADEON_LAYOUT_TILED) 482 args.tiling_flags |= RADEON_BO_FLAGS_MICRO_TILE; 483 else if (microtiled == RADEON_LAYOUT_SQUARETILED) 484 args.tiling_flags |= RADEON_BO_FLAGS_MICRO_TILE_SQUARE; 485 486 if (macrotiled == RADEON_LAYOUT_TILED) 487 args.tiling_flags |= RADEON_BO_FLAGS_MACRO_TILE; 488 489 args.handle = bo->handle; 490 args.pitch = pitch; 491 492 drmCommandWriteRead(bo->rws->fd, 493 DRM_RADEON_GEM_SET_TILING, 494 &args, 495 sizeof(args)); 496} 497 498static struct radeon_winsys_cs_handle *radeon_drm_get_cs_handle( 499 struct pb_buffer *_buf) 500{ 501 /* return radeon_bo. */ 502 return (struct radeon_winsys_cs_handle*)get_radeon_bo(_buf); 503} 504 505static struct pb_buffer * 506radeon_winsys_bo_create(struct radeon_winsys *rws, 507 unsigned size, 508 unsigned alignment, 509 unsigned bind, 510 enum radeon_bo_domain domain) 511{ 512 struct radeon_drm_winsys *ws = radeon_drm_winsys(rws); 513 struct radeon_bo_desc desc; 514 struct pb_manager *provider; 515 struct pb_buffer *buffer; 516 517 memset(&desc, 0, sizeof(desc)); 518 desc.base.alignment = alignment; 519 desc.base.usage = domain; 520 desc.initial_domains = domain; 521 522 /* Assign a buffer manager. */ 523 if (bind & (PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER | 524 PIPE_BIND_CONSTANT_BUFFER | PIPE_BIND_CUSTOM)) 525 provider = ws->cman; 526 else 527 provider = ws->kman; 528 529 buffer = provider->create_buffer(provider, size, &desc.base); 530 if (!buffer) 531 return NULL; 532 533 return (struct pb_buffer*)buffer; 534} 535 536static struct pb_buffer *radeon_winsys_bo_from_handle(struct radeon_winsys *rws, 537 struct winsys_handle *whandle, 538 unsigned *stride, 539 unsigned *size) 540{ 541 struct radeon_drm_winsys *ws = radeon_drm_winsys(rws); 542 struct radeon_bo *bo; 543 struct radeon_bomgr *mgr = radeon_bomgr(ws->kman); 544 struct drm_gem_open open_arg = {}; 545 546 /* We must maintain a list of pairs <handle, bo>, so that we always return 547 * the same BO for one particular handle. If we didn't do that and created 548 * more than one BO for the same handle and then relocated them in a CS, 549 * we would hit a deadlock in the kernel. 550 * 551 * The list of pairs is guarded by a mutex, of course. */ 552 pipe_mutex_lock(mgr->bo_handles_mutex); 553 554 /* First check if there already is an existing bo for the handle. */ 555 bo = util_hash_table_get(mgr->bo_handles, (void*)(uintptr_t)whandle->handle); 556 if (bo) { 557 /* Increase the refcount. */ 558 struct pb_buffer *b = NULL; 559 pb_reference(&b, &bo->base); 560 goto done; 561 } 562 563 /* There isn't, create a new one. */ 564 bo = CALLOC_STRUCT(radeon_bo); 565 if (!bo) { 566 goto fail; 567 } 568 569 /* Open the BO. */ 570 open_arg.name = whandle->handle; 571 if (drmIoctl(ws->fd, DRM_IOCTL_GEM_OPEN, &open_arg)) { 572 FREE(bo); 573 goto fail; 574 } 575 bo->handle = open_arg.handle; 576 bo->size = open_arg.size; 577 bo->name = whandle->handle; 578 579 /* Initialize it. */ 580 pipe_reference_init(&bo->base.reference, 1); 581 bo->base.alignment = 0; 582 bo->base.usage = PB_USAGE_GPU_WRITE | PB_USAGE_GPU_READ; 583 bo->base.size = bo->size; 584 bo->base.vtbl = &radeon_bo_vtbl; 585 bo->mgr = mgr; 586 bo->rws = mgr->rws; 587 pipe_mutex_init(bo->map_mutex); 588 589 util_hash_table_set(mgr->bo_handles, (void*)(uintptr_t)whandle->handle, bo); 590 591done: 592 pipe_mutex_unlock(mgr->bo_handles_mutex); 593 594 if (stride) 595 *stride = whandle->stride; 596 if (size) 597 *size = bo->base.size; 598 599 return (struct pb_buffer*)bo; 600 601fail: 602 pipe_mutex_unlock(mgr->bo_handles_mutex); 603 return NULL; 604} 605 606static boolean radeon_winsys_bo_get_handle(struct pb_buffer *buffer, 607 unsigned stride, 608 struct winsys_handle *whandle) 609{ 610 struct drm_gem_flink flink = {}; 611 struct radeon_bo *bo = get_radeon_bo(buffer); 612 613 if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) { 614 if (!bo->flinked) { 615 flink.handle = bo->handle; 616 617 if (ioctl(bo->rws->fd, DRM_IOCTL_GEM_FLINK, &flink)) { 618 return FALSE; 619 } 620 621 bo->flinked = TRUE; 622 bo->flink = flink.name; 623 } 624 whandle->handle = bo->flink; 625 } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) { 626 whandle->handle = bo->handle; 627 } 628 629 whandle->stride = stride; 630 return TRUE; 631} 632 633void radeon_bomgr_init_functions(struct radeon_drm_winsys *ws) 634{ 635 ws->base.buffer_get_cs_handle = radeon_drm_get_cs_handle; 636 ws->base.buffer_set_tiling = radeon_bo_set_tiling; 637 ws->base.buffer_get_tiling = radeon_bo_get_tiling; 638 ws->base.buffer_map = radeon_bo_map; 639 ws->base.buffer_unmap = pb_unmap; 640 ws->base.buffer_wait = radeon_bo_wait; 641 ws->base.buffer_is_busy = radeon_bo_is_busy; 642 ws->base.buffer_create = radeon_winsys_bo_create; 643 ws->base.buffer_from_handle = radeon_winsys_bo_from_handle; 644 ws->base.buffer_get_handle = radeon_winsys_bo_get_handle; 645} 646