cpu.h revision beefcee15f800fa4875ea5470f10f0ce5e18e67c
1/* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19#ifndef CPU_ARM_H 20#define CPU_ARM_H 21 22#include "config.h" 23 24#include "kvm-consts.h" 25 26#if defined(TARGET_AARCH64) 27 /* AArch64 definitions */ 28# define TARGET_LONG_BITS 64 29# define ELF_MACHINE EM_AARCH64 30#else 31# define TARGET_LONG_BITS 32 32# define ELF_MACHINE EM_ARM 33#endif 34 35// TODO(digit): Remove this line. 36#define CPUOldState struct CPUARMState 37 38#define CPUArchState struct CPUARMState 39 40#include "qemu-common.h" 41#include "exec/cpu-defs.h" 42 43#include "fpu/softfloat.h" 44 45#define TARGET_HAS_ICE 1 46 47#define EXCP_UDEF 1 /* undefined instruction */ 48#define EXCP_SWI 2 /* software interrupt */ 49#define EXCP_PREFETCH_ABORT 3 50#define EXCP_DATA_ABORT 4 51#define EXCP_IRQ 5 52#define EXCP_FIQ 6 53#define EXCP_BKPT 7 54#define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 55#define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 56#define EXCP_STREX 10 57#define EXCP_SMC 11 /* secure monitor call */ 58 59#define ARMV7M_EXCP_RESET 1 60#define ARMV7M_EXCP_NMI 2 61#define ARMV7M_EXCP_HARD 3 62#define ARMV7M_EXCP_MEM 4 63#define ARMV7M_EXCP_BUS 5 64#define ARMV7M_EXCP_USAGE 6 65#define ARMV7M_EXCP_SVC 11 66#define ARMV7M_EXCP_DEBUG 12 67#define ARMV7M_EXCP_PENDSV 14 68#define ARMV7M_EXCP_SYSTICK 15 69 70/* ARM-specific interrupt pending bits. */ 71#define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 72 73/* Meanings of the ARMCPU object's two inbound GPIO lines */ 74#define ARM_CPU_IRQ 0 75#define ARM_CPU_FIQ 1 76 77typedef void ARMWriteCPFunc(void *opaque, int cp_info, 78 int srcreg, int operand, uint32_t value, 79 void *retaddr); 80typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info, 81 int dstreg, int operand, 82 void *retaddr); 83 84struct arm_boot_info; 85 86#define NB_MMU_MODES 2 87 88/* We currently assume float and double are IEEE single and double 89 precision respectively. 90 Doing runtime conversions is tricky because VFP registers may contain 91 integer values (eg. as the result of a FTOSI instruction). 92 s<2n> maps to the least significant half of d<n> 93 s<2n+1> maps to the most significant half of d<n> 94 */ 95 96/* CPU state for each instance of a generic timer (in cp15 c14) */ 97typedef struct ARMGenericTimer { 98 uint64_t cval; /* Timer CompareValue register */ 99 uint32_t ctl; /* Timer Control register */ 100} ARMGenericTimer; 101 102#define GTIMER_PHYS 0 103#define GTIMER_VIRT 1 104#define NUM_GTIMERS 2 105 106/* Scale factor for generic timers, ie number of ns per tick. 107 * This gives a 62.5MHz timer. 108 */ 109#define GTIMER_SCALE 16 110 111typedef struct CPUARMState { 112 /* Regs for current mode. */ 113 uint32_t regs[16]; 114 /* Frequently accessed CPSR bits are stored separately for efficiently. 115 This contains all the other bits. Use cpsr_{read,write} to access 116 the whole CPSR. */ 117 uint32_t uncached_cpsr; 118 uint32_t spsr; 119 120 /* Banked registers. */ 121 uint32_t banked_spsr[7]; 122 uint32_t banked_r13[7]; 123 uint32_t banked_r14[7]; 124 125 /* These hold r8-r12. */ 126 uint32_t usr_regs[5]; 127 uint32_t fiq_regs[5]; 128 129 /* cpsr flag cache for faster execution */ 130 uint32_t CF; /* 0 or 1 */ 131 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 132 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 133 uint32_t ZF; /* Z set if zero. */ 134 uint32_t QF; /* 0 or 1 */ 135 uint32_t GE; /* cpsr[19:16] */ 136 uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */ 137 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 138 139 /* System control coprocessor (cp15) */ 140 struct { 141 uint32_t c0_cpuid; 142 uint32_t c0_cachetype; 143 uint32_t c0_ccsid[16]; /* Cache size. */ 144 uint32_t c0_clid; /* Cache level. */ 145 uint32_t c0_cssel; /* Cache size selection. */ 146 uint32_t c0_c1[8]; /* Feature registers. */ 147 uint32_t c0_c2[8]; /* Instruction set registers. */ 148 uint32_t c1_sys; /* System control register. */ 149 uint32_t c1_coproc; /* Coprocessor access register. */ 150 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 151 uint32_t c1_secfg; /* Secure configuration register. */ 152 uint32_t c1_sedbg; /* Secure debug enable register. */ 153 uint32_t c1_nseac; /* Non-secure access control register. */ 154 uint32_t c2_base0; /* MMU translation table base 0. */ 155 uint32_t c2_base1; /* MMU translation table base 1. */ 156 uint32_t c2_control; /* MMU translation table base control. */ 157 uint32_t c2_mask; /* MMU translation table base selection mask. */ 158 uint32_t c2_base_mask; /* MMU translation table base 0 mask. */ 159 uint32_t c2_data; /* MPU data cachable bits. */ 160 uint32_t c2_insn; /* MPU instruction cachable bits. */ 161 uint32_t c3; /* MMU domain access control register 162 MPU write buffer control. */ 163 uint32_t c5_insn; /* Fault status registers. */ 164 uint32_t c5_data; 165 uint32_t c6_region[8]; /* MPU base/size registers. */ 166 uint32_t c6_insn; /* Fault address registers. */ 167 uint32_t c6_data; 168 uint32_t c7_par; /* Translation result. */ 169 uint32_t c9_insn; /* Cache lockdown registers. */ 170 uint32_t c9_data; 171 uint32_t c9_pmcr; /* performance monitor control register */ 172 uint32_t c9_pmcnten; /* perf monitor counter enables */ 173 uint32_t c9_pmovsr; /* perf monitor overflow status */ 174 uint32_t c9_pmxevtyper; /* perf monitor event type */ 175 uint32_t c9_pmuserenr; /* perf monitor user enable */ 176 uint32_t c9_pminten; /* perf monitor interrupt enables */ 177 uint32_t c12_vbar; /* secure/nonsecure vector base address register. */ 178 uint32_t c12_mvbar; /* monitor vector base address register. */ 179 uint32_t c13_fcse; /* FCSE PID. */ 180 uint32_t c13_context; /* Context ID. */ 181 uint32_t c13_tls1; /* User RW Thread register. */ 182 uint32_t c13_tls2; /* User RO Thread register. */ 183 uint32_t c13_tls3; /* Privileged Thread register. */ 184 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 185 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 186 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 187 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 188 uint32_t c15_threadid; /* TI debugger thread-ID. */ 189 } cp15; 190 191 struct { 192 uint32_t other_sp; 193 uint32_t vecbase; 194 uint32_t basepri; 195 uint32_t control; 196 int current_sp; 197 int exception; 198 int pending_exception; 199 } v7m; 200 201 /* Minimal set of debug coprocessor state (cp14) */ 202 uint32_t cp14_dbgdidr; 203 204 /* Thumb-2 EE state. */ 205 uint32_t teecr; 206 uint32_t teehbr; 207 208 /* Internal CPU feature flags. */ 209 uint32_t features; 210 211 /* VFP coprocessor state. */ 212 struct { 213 float64 regs[32]; 214 215 uint32_t xregs[16]; 216 /* We store these fpcsr fields separately for convenience. */ 217 int vec_len; 218 int vec_stride; 219 220 /* scratch space when Tn are not sufficient. */ 221 uint32_t scratch[8]; 222 223 /* fp_status is the "normal" fp status. standard_fp_status retains 224 * values corresponding to the ARM "Standard FPSCR Value", ie 225 * default-NaN, flush-to-zero, round-to-nearest and is used by 226 * any operations (generally Neon) which the architecture defines 227 * as controlled by the standard FPSCR value rather than the FPSCR. 228 * 229 * To avoid having to transfer exception bits around, we simply 230 * say that the FPSCR cumulative exception flags are the logical 231 * OR of the flags in the two fp statuses. This relies on the 232 * only thing which needs to read the exception flags being 233 * an explicit FPSCR read. 234 */ 235 float_status fp_status; 236 float_status standard_fp_status; 237 } vfp; 238 uint32_t exclusive_addr; 239 uint32_t exclusive_val; 240 uint32_t exclusive_high; 241#if defined(CONFIG_USER_ONLY) 242 uint32_t exclusive_test; 243 uint32_t exclusive_info; 244#endif 245 246 /* iwMMXt coprocessor state. */ 247 struct { 248 uint64_t regs[16]; 249 uint64_t val; 250 251 uint32_t cregs[16]; 252 } iwmmxt; 253 254#if defined(CONFIG_USER_ONLY) 255 /* For usermode syscall translation. */ 256 int eabi; 257#endif 258 259 CPU_COMMON 260 261 /* These fields after the common ones so they are preserved on reset. */ 262 263 /* Coprocessor IO used by peripherals */ 264 struct { 265 ARMReadCPFunc *cp_read; 266 ARMWriteCPFunc *cp_write; 267 void *opaque; 268 } cp[15]; 269 void *nvic; 270 const struct arm_boot_info *boot_info; 271} CPUARMState; 272 273CPUARMState *cpu_arm_init(const char *cpu_model); 274void arm_translate_init(void); 275int cpu_arm_exec(CPUARMState *s); 276void cpu_arm_close(CPUARMState *s); 277void do_interrupt(CPUARMState *); 278void switch_mode(CPUARMState *, int); 279uint32_t do_arm_semihosting(CPUARMState *env); 280 281static inline bool is_a64(CPUARMState *env) 282{ 283#ifdef CONFIG_ANDROID // TODO(digit) 284 return 0; 285#else 286 return env->aarch64; 287#endif 288} 289 290#define PSTATE_N_SHIFT 3 291#define PSTATE_N (1 << PSTATE_N_SHIFT) 292#define PSTATE_Z_SHIFT 2 293#define PSTATE_Z (1 << PSTATE_Z_SHIFT) 294#define PSTATE_C_SHIFT 1 295#define PSTATE_C (1 << PSTATE_C_SHIFT) 296#define PSTATE_V_SHIFT 0 297#define PSTATE_V (1 << PSTATE_V_SHIFT) 298 299/* you can call this signal handler from your SIGBUS and SIGSEGV 300 signal handlers to inform the virtual CPU of exceptions. non zero 301 is returned if the signal was handled by the virtual CPU. */ 302int cpu_arm_signal_handler(int host_signum, void *pinfo, 303 void *puc); 304int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw, 305 int mmu_idx); 306#define cpu_handle_mmu_fault cpu_arm_handle_mmu_fault 307 308static inline void cpu_set_tls(CPUARMState *env, target_ulong newtls) 309{ 310 env->cp15.c13_tls2 = newtls; 311} 312 313#define CPSR_M (0x1fU) 314#define CPSR_T (1U << 5) 315#define CPSR_F (1U << 6) 316#define CPSR_I (1U << 7) 317#define CPSR_A (1U << 8) 318#define CPSR_E (1U << 9) 319#define CPSR_IT_2_7 (0xfc00U) 320#define CPSR_GE (0xfU << 16) 321#define CPSR_RESERVED (0xfU << 20) 322#define CPSR_J (1U << 24) 323#define CPSR_IT_0_1 (3U << 25) 324#define CPSR_Q (1U << 27) 325#define CPSR_V (1U << 28) 326#define CPSR_C (1U << 29) 327#define CPSR_Z (1U << 30) 328#define CPSR_N (1U << 31) 329#define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 330 331#define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 332#define CACHED_CPSR_BITS (CPSR_T | CPSR_GE | CPSR_IT | CPSR_Q | CPSR_NZCV) 333/* Bits writable in user mode. */ 334#define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE) 335/* Execution state bits. MRS read as zero, MSR writes ignored. */ 336#define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J) 337 338/* Return the current CPSR value. */ 339uint32_t cpsr_read(CPUARMState *env); 340/* Set the CPSR. Note that some bits of mask must be all-set or all-clear. */ 341void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask); 342 343/* Return the current xPSR value. */ 344static inline uint32_t xpsr_read(CPUARMState *env) 345{ 346 int ZF; 347 ZF = (env->ZF == 0); 348 return (env->NF & 0x80000000) | (ZF << 30) 349 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 350 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 351 | ((env->condexec_bits & 0xfc) << 8) 352 | env->v7m.exception; 353} 354 355/* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 356static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 357{ 358 if (mask & CPSR_NZCV) { 359 env->ZF = (~val) & CPSR_Z; 360 env->NF = val; 361 env->CF = (val >> 29) & 1; 362 env->VF = (val << 3) & 0x80000000; 363 } 364 if (mask & CPSR_Q) 365 env->QF = ((val & CPSR_Q) != 0); 366 if (mask & (1 << 24)) 367 env->thumb = ((val & (1 << 24)) != 0); 368 if (mask & CPSR_IT_0_1) { 369 env->condexec_bits &= ~3; 370 env->condexec_bits |= (val >> 25) & 3; 371 } 372 if (mask & CPSR_IT_2_7) { 373 env->condexec_bits &= 3; 374 env->condexec_bits |= (val >> 8) & 0xfc; 375 } 376 if (mask & 0x1ff) { 377 env->v7m.exception = val & 0x1ff; 378 } 379} 380 381/* Return the current FPSCR value. */ 382uint32_t vfp_get_fpscr(CPUARMState *env); 383void vfp_set_fpscr(CPUARMState *env, uint32_t val); 384 385enum arm_cpu_mode { 386 ARM_CPU_MODE_USR = 0x10, 387 ARM_CPU_MODE_FIQ = 0x11, 388 ARM_CPU_MODE_IRQ = 0x12, 389 ARM_CPU_MODE_SVC = 0x13, 390 ARM_CPU_MODE_SMC = 0x16, 391 ARM_CPU_MODE_ABT = 0x17, 392 ARM_CPU_MODE_UND = 0x1b, 393 ARM_CPU_MODE_SYS = 0x1f 394}; 395 396/* VFP system registers. */ 397#define ARM_VFP_FPSID 0 398#define ARM_VFP_FPSCR 1 399#define ARM_VFP_MVFR1 6 400#define ARM_VFP_MVFR0 7 401#define ARM_VFP_FPEXC 8 402#define ARM_VFP_FPINST 9 403#define ARM_VFP_FPINST2 10 404 405/* iwMMXt coprocessor control registers. */ 406#define ARM_IWMMXT_wCID 0 407#define ARM_IWMMXT_wCon 1 408#define ARM_IWMMXT_wCSSF 2 409#define ARM_IWMMXT_wCASF 3 410#define ARM_IWMMXT_wCGR0 8 411#define ARM_IWMMXT_wCGR1 9 412#define ARM_IWMMXT_wCGR2 10 413#define ARM_IWMMXT_wCGR3 11 414 415/* If adding a feature bit which corresponds to a Linux ELF 416 * HWCAP bit, remember to update the feature-bit-to-hwcap 417 * mapping in linux-user/elfload.c:get_elf_hwcap(). 418 */ 419enum arm_features { 420 ARM_FEATURE_VFP, 421 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 422 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 423 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 424 ARM_FEATURE_V6, 425 ARM_FEATURE_V6K, 426 ARM_FEATURE_V7, 427 ARM_FEATURE_THUMB2, 428 ARM_FEATURE_MPU, /* Only has Memory Protection Unit, not full MMU. */ 429 ARM_FEATURE_VFP3, 430 ARM_FEATURE_VFP_FP16, 431 ARM_FEATURE_NEON, 432 ARM_FEATURE_DIV, 433 ARM_FEATURE_M, /* Microcontroller profile. */ 434 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 435 ARM_FEATURE_THUMB2EE, 436 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 437 ARM_FEATURE_V4T, 438 ARM_FEATURE_V5, 439 ARM_FEATURE_STRONGARM, 440 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 441 ARM_FEATURE_TRUSTZONE, /* TrustZone Security Extensions. */ 442}; 443 444static inline int arm_feature(CPUARMState *env, int feature) 445{ 446 return (env->features & (1ULL << feature)) != 0; 447} 448 449void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf); 450 451/* Interface between CPU and Interrupt controller. */ 452void armv7m_nvic_set_pending(void *opaque, int irq); 453int armv7m_nvic_acknowledge_irq(void *opaque); 454void armv7m_nvic_complete_irq(void *opaque, int irq); 455 456/* Interface for defining coprocessor registers. 457 * Registers are defined in tables of arm_cp_reginfo structs 458 * which are passed to define_arm_cp_regs(). 459 */ 460 461/* When looking up a coprocessor register we look for it 462 * via an integer which encodes all of: 463 * coprocessor number 464 * Crn, Crm, opc1, opc2 fields 465 * 32 or 64 bit register (ie is it accessed via MRC/MCR 466 * or via MRRC/MCRR?) 467 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. 468 * (In this case crn and opc2 should be zero.) 469 */ 470#define ENCODE_CP_REG(cp, is64, crn, crm, opc1, opc2) \ 471 (((cp) << 16) | ((is64) << 15) | ((crn) << 11) | \ 472 ((crm) << 7) | ((opc1) << 3) | (opc2)) 473 474/* Convert a full 64 bit KVM register ID to the truncated 32 bit 475 * version used as a key for the coprocessor register hashtable 476 */ 477static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) 478{ 479 uint32_t cpregid = kvmid; 480 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { 481 cpregid |= (1 << 15); 482 } 483 return cpregid; 484} 485 486/* Convert a truncated 32 bit hashtable key into the full 487 * 64 bit KVM register ID. 488 */ 489static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) 490{ 491 uint64_t kvmid = cpregid & ~(1 << 15); 492 if (cpregid & (1 << 15)) { 493 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; 494 } else { 495 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; 496 } 497 return kvmid; 498} 499 500/* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a 501 * special-behaviour cp reg and bits [15..8] indicate what behaviour 502 * it has. Otherwise it is a simple cp reg, where CONST indicates that 503 * TCG can assume the value to be constant (ie load at translate time) 504 * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END 505 * indicates that the TB should not be ended after a write to this register 506 * (the default is that the TB ends after cp writes). OVERRIDE permits 507 * a register definition to override a previous definition for the 508 * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the 509 * old must have the OVERRIDE bit set. 510 * NO_MIGRATE indicates that this register should be ignored for migration; 511 * (eg because any state is accessed via some other coprocessor register). 512 * IO indicates that this register does I/O and therefore its accesses 513 * need to be surrounded by gen_io_start()/gen_io_end(). In particular, 514 * registers which implement clocks or timers require this. 515 */ 516#define ARM_CP_SPECIAL 1 517#define ARM_CP_CONST 2 518#define ARM_CP_64BIT 4 519#define ARM_CP_SUPPRESS_TB_END 8 520#define ARM_CP_OVERRIDE 16 521#define ARM_CP_NO_MIGRATE 32 522#define ARM_CP_IO 64 523#define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8)) 524#define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8)) 525#define ARM_LAST_SPECIAL ARM_CP_WFI 526/* Used only as a terminator for ARMCPRegInfo lists */ 527#define ARM_CP_SENTINEL 0xffff 528/* Mask of only the flag bits in a type field */ 529#define ARM_CP_FLAG_MASK 0x7f 530 531/* Return true if cptype is a valid type field. This is used to try to 532 * catch errors where the sentinel has been accidentally left off the end 533 * of a list of registers. 534 */ 535static inline bool cptype_valid(int cptype) 536{ 537 return ((cptype & ~ARM_CP_FLAG_MASK) == 0) 538 || ((cptype & ARM_CP_SPECIAL) && 539 ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL)); 540} 541 542/* Access rights: 543 * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM 544 * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and 545 * PL2 (hyp). The other level which has Read and Write bits is Secure PL1 546 * (ie any of the privileged modes in Secure state, or Monitor mode). 547 * If a register is accessible in one privilege level it's always accessible 548 * in higher privilege levels too. Since "Secure PL1" also follows this rule 549 * (ie anything visible in PL2 is visible in S-PL1, some things are only 550 * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the 551 * terminology a little and call this PL3. 552 * 553 * If access permissions for a register are more complex than can be 554 * described with these bits, then use a laxer set of restrictions, and 555 * do the more restrictive/complex check inside a helper function. 556 */ 557#define PL3_R 0x80 558#define PL3_W 0x40 559#define PL2_R (0x20 | PL3_R) 560#define PL2_W (0x10 | PL3_W) 561#define PL1_R (0x08 | PL2_R) 562#define PL1_W (0x04 | PL2_W) 563#define PL0_R (0x02 | PL1_R) 564#define PL0_W (0x01 | PL1_W) 565 566#define PL3_RW (PL3_R | PL3_W) 567#define PL2_RW (PL2_R | PL2_W) 568#define PL1_RW (PL1_R | PL1_W) 569#define PL0_RW (PL0_R | PL0_W) 570 571static inline int arm_current_pl(CPUARMState *env) 572{ 573 if ((env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_USR) { 574 return 0; 575 } 576 /* We don't currently implement the Virtualization or TrustZone 577 * extensions, so PL2 and PL3 don't exist for us. 578 */ 579 return 1; 580} 581 582typedef struct ARMCPRegInfo ARMCPRegInfo; 583 584/* Access functions for coprocessor registers. These should return 585 * 0 on success, or one of the EXCP_* constants if access should cause 586 * an exception (in which case *value is not written). 587 */ 588typedef int CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque, 589 uint64_t *value); 590typedef int CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, 591 uint64_t value); 592/* Hook function for register reset */ 593typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); 594 595#define CP_ANY 0xff 596 597/* Definition of an ARM coprocessor register */ 598struct ARMCPRegInfo { 599 /* Name of register (useful mainly for debugging, need not be unique) */ 600 const char *name; 601 /* Location of register: coprocessor number and (crn,crm,opc1,opc2) 602 * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a 603 * 'wildcard' field -- any value of that field in the MRC/MCR insn 604 * will be decoded to this register. The register read and write 605 * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2 606 * used by the program, so it is possible to register a wildcard and 607 * then behave differently on read/write if necessary. 608 * For 64 bit registers, only crm and opc1 are relevant; crn and opc2 609 * must both be zero. 610 */ 611 uint8_t cp; 612 uint8_t crn; 613 uint8_t crm; 614 uint8_t opc1; 615 uint8_t opc2; 616 /* Register type: ARM_CP_* bits/values */ 617 int type; 618 /* Access rights: PL*_[RW] */ 619 int access; 620 /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when 621 * this register was defined: can be used to hand data through to the 622 * register read/write functions, since they are passed the ARMCPRegInfo*. 623 */ 624 void *opaque; 625 /* Value of this register, if it is ARM_CP_CONST. Otherwise, if 626 * fieldoffset is non-zero, the reset value of the register. 627 */ 628 uint64_t resetvalue; 629 /* Offset of the field in CPUARMState for this register. This is not 630 * needed if either: 631 * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs 632 * 2. both readfn and writefn are specified 633 */ 634 ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ 635 /* Function for handling reads of this register. If NULL, then reads 636 * will be done by loading from the offset into CPUARMState specified 637 * by fieldoffset. 638 */ 639 CPReadFn *readfn; 640 /* Function for handling writes of this register. If NULL, then writes 641 * will be done by writing to the offset into CPUARMState specified 642 * by fieldoffset. 643 */ 644 CPWriteFn *writefn; 645 /* Function for doing a "raw" read; used when we need to copy 646 * coprocessor state to the kernel for KVM or out for 647 * migration. This only needs to be provided if there is also a 648 * readfn and it makes an access permission check. 649 */ 650 CPReadFn *raw_readfn; 651 /* Function for doing a "raw" write; used when we need to copy KVM 652 * kernel coprocessor state into userspace, or for inbound 653 * migration. This only needs to be provided if there is also a 654 * writefn and it makes an access permission check or masks out 655 * "unwritable" bits or has write-one-to-clear or similar behaviour. 656 */ 657 CPWriteFn *raw_writefn; 658 /* Function for resetting the register. If NULL, then reset will be done 659 * by writing resetvalue to the field specified in fieldoffset. If 660 * fieldoffset is 0 then no reset will be done. 661 */ 662 CPResetFn *resetfn; 663}; 664 665/* Macros which are lvalues for the field in CPUARMState for the 666 * ARMCPRegInfo *ri. 667 */ 668#define CPREG_FIELD32(env, ri) \ 669 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) 670#define CPREG_FIELD64(env, ri) \ 671 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) 672 673#define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL } 674 675#ifndef CONFIG_ANDROID // TODO(digit): Implement ARMCPU 676void define_arm_cp_regs_with_opaque(ARMCPU *cpu, 677 const ARMCPRegInfo *regs, void *opaque); 678void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, 679 const ARMCPRegInfo *regs, void *opaque); 680static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs) 681{ 682 define_arm_cp_regs_with_opaque(cpu, regs, 0); 683} 684static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs) 685{ 686 define_one_arm_cp_reg_with_opaque(cpu, regs, 0); 687} 688const ARMCPRegInfo *get_arm_cp_reginfo(ARMCPU *cpu, uint32_t encoded_cp); 689#endif // !CONFIG_ANDROID 690 691/* CPWriteFn that can be used to implement writes-ignored behaviour */ 692int arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, 693 uint64_t value); 694/* CPReadFn that can be used for read-as-zero behaviour */ 695int arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value); 696 697static inline bool cp_access_ok(CPUARMState *env, 698 const ARMCPRegInfo *ri, int isread) 699{ 700 return (ri->access >> ((arm_current_pl(env) * 2) + isread)) & 1; 701} 702 703#ifndef CONFIG_ANDROID // TODO(digit): Implement ARMCPU 704/** 705 * write_list_to_cpustate 706 * @cpu: ARMCPU 707 * 708 * For each register listed in the ARMCPU cpreg_indexes list, write 709 * its value from the cpreg_values list into the ARMCPUARMState structure. 710 * This updates TCG's working data structures from KVM data or 711 * from incoming migration state. 712 * 713 * Returns: true if all register values were updated correctly, 714 * false if some register was unknown or could not be written. 715 * Note that we do not stop early on failure -- we will attempt 716 * writing all registers in the list. 717 */ 718bool write_list_to_cpustate(ARMCPU *cpu); 719 720/** 721 * write_cpustate_to_list: 722 * @cpu: ARMCPU 723 * 724 * For each register listed in the ARMCPU cpreg_indexes list, write 725 * its value from the ARMCPUARMState structure into the cpreg_values list. 726 * This is used to copy info from TCG's working data structures into 727 * KVM or for outbound migration. 728 * 729 * Returns: true if all register values were read correctly, 730 * false if some register was unknown or could not be read. 731 * Note that we do not stop early on failure -- we will attempt 732 * reading all registers in the list. 733 */ 734bool write_cpustate_to_list(ARMCPU *cpu); 735#endif // !CONFIG_ANDROID 736 737void cpu_arm_set_cp_io(CPUARMState *env, int cpnum, 738 ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write, 739 void *opaque); 740 741/* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3. 742 Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are 743 conventional cores (ie. Application or Realtime profile). */ 744 745#define IS_M(env) arm_feature(env, ARM_FEATURE_M) 746#define ARM_CPUID(env) (env->cp15.c0_cpuid) 747 748#define ARM_CPUID_ARM1026 0x4106a262 749#define ARM_CPUID_ARM926 0x41069265 750#define ARM_CPUID_ARM946 0x41059461 751#define ARM_CPUID_TI915T 0x54029152 752#define ARM_CPUID_TI925T 0x54029252 753#define ARM_CPUID_SA1100 0x4401A11B 754#define ARM_CPUID_SA1110 0x6901B119 755#define ARM_CPUID_PXA250 0x69052100 756#define ARM_CPUID_PXA255 0x69052d00 757#define ARM_CPUID_PXA260 0x69052903 758#define ARM_CPUID_PXA261 0x69052d05 759#define ARM_CPUID_PXA262 0x69052d06 760#define ARM_CPUID_PXA270 0x69054110 761#define ARM_CPUID_PXA270_A0 0x69054110 762#define ARM_CPUID_PXA270_A1 0x69054111 763#define ARM_CPUID_PXA270_B0 0x69054112 764#define ARM_CPUID_PXA270_B1 0x69054113 765#define ARM_CPUID_PXA270_C0 0x69054114 766#define ARM_CPUID_PXA270_C5 0x69054117 767#define ARM_CPUID_ARM1136 0x4117b363 768#define ARM_CPUID_ARM1136_R2 0x4107b362 769#define ARM_CPUID_ARM1176 0x410fb767 770#define ARM_CPUID_ARM11MPCORE 0x410fb022 771#define ARM_CPUID_CORTEXA8 0x410fc080 772#define ARM_CPUID_CORTEXA8_R2 0x412fc083 773#define ARM_CPUID_CORTEXA9 0x410fc090 774#define ARM_CPUID_CORTEXM3 0x410fc231 775#define ARM_CPUID_ANY 0xffffffff 776 777#if defined(CONFIG_USER_ONLY) 778#define TARGET_PAGE_BITS 12 779#else 780/* The ARM MMU allows 1k pages. */ 781/* ??? Linux doesn't actually use these, and they're deprecated in recent 782 architecture revisions. Maybe a configure option to disable them. */ 783#define TARGET_PAGE_BITS 10 784#endif 785 786#if defined(TARGET_AARCH64) 787# define TARGET_PHYS_ADDR_SPACE_BITS 48 788# define TARGET_VIRT_ADDR_SPACE_BITS 64 789#else 790# define TARGET_PHYS_ADDR_SPACE_BITS 40 791# define TARGET_VIRT_ADDR_SPACE_BITS 32 792#endif 793 794#define cpu_init cpu_arm_init 795#define cpu_exec cpu_arm_exec 796#define cpu_gen_code cpu_arm_gen_code 797#define cpu_signal_handler cpu_arm_signal_handler 798#define cpu_list arm_cpu_list 799 800#define CPU_SAVE_VERSION 4 801 802/* MMU modes definitions */ 803#define MMU_MODE0_SUFFIX _kernel 804#define MMU_MODE1_SUFFIX _user 805#define MMU_USER_IDX 1 806static inline int cpu_mmu_index (CPUARMState *env) 807{ 808 return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0; 809} 810 811static inline int is_cpu_user (CPUARMState *env) 812{ 813#ifdef CONFIG_USER_ONLY 814 return 1; 815#else 816 return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR; 817#endif // CONFIG_USER_ONLY 818} 819 820#if defined(CONFIG_USER_ONLY) 821static inline void cpu_clone_regs(CPUARMState *env, target_ulong newsp) 822{ 823 if (newsp) 824 env->regs[13] = newsp; 825 env->regs[0] = 0; 826} 827#endif 828 829#include "exec/cpu-all.h" 830 831/* Bit usage in the TB flags field: bit 31 indicates whether we are 832 * in 32 or 64 bit mode. The meaning of the other bits depends on that. 833 */ 834#define ARM_TBFLAG_AARCH64_STATE_SHIFT 31 835#define ARM_TBFLAG_AARCH64_STATE_MASK (1U << ARM_TBFLAG_AARCH64_STATE_SHIFT) 836 837/* Bit usage when in AArch32 state: */ 838#define ARM_TBFLAG_THUMB_SHIFT 0 839#define ARM_TBFLAG_THUMB_MASK (1 << ARM_TBFLAG_THUMB_SHIFT) 840#define ARM_TBFLAG_VECLEN_SHIFT 1 841#define ARM_TBFLAG_VECLEN_MASK (0x7 << ARM_TBFLAG_VECLEN_SHIFT) 842#define ARM_TBFLAG_VECSTRIDE_SHIFT 4 843#define ARM_TBFLAG_VECSTRIDE_MASK (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT) 844#define ARM_TBFLAG_PRIV_SHIFT 6 845#define ARM_TBFLAG_PRIV_MASK (1 << ARM_TBFLAG_PRIV_SHIFT) 846#define ARM_TBFLAG_VFPEN_SHIFT 7 847#define ARM_TBFLAG_VFPEN_MASK (1 << ARM_TBFLAG_VFPEN_SHIFT) 848#define ARM_TBFLAG_CONDEXEC_SHIFT 8 849#define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT) 850#define ARM_TBFLAG_BSWAP_CODE_SHIFT 16 851#define ARM_TBFLAG_BSWAP_CODE_MASK (1 << ARM_TBFLAG_BSWAP_CODE_SHIFT) 852 853/* Bit usage when in AArch64 state: currently no bits defined */ 854 855/* some convenience accessor macros */ 856#define ARM_TBFLAG_AARCH64_STATE(F) \ 857 (((F) & ARM_TBFLAG_AARCH64_STATE_MASK) >> ARM_TBFLAG_AARCH64_STATE_SHIFT) 858#define ARM_TBFLAG_THUMB(F) \ 859 (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT) 860#define ARM_TBFLAG_VECLEN(F) \ 861 (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT) 862#define ARM_TBFLAG_VECSTRIDE(F) \ 863 (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT) 864#define ARM_TBFLAG_PRIV(F) \ 865 (((F) & ARM_TBFLAG_PRIV_MASK) >> ARM_TBFLAG_PRIV_SHIFT) 866#define ARM_TBFLAG_VFPEN(F) \ 867 (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT) 868#define ARM_TBFLAG_CONDEXEC(F) \ 869 (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT) 870#define ARM_TBFLAG_BSWAP_CODE(F) \ 871 (((F) & ARM_TBFLAG_BSWAP_CODE_MASK) >> ARM_TBFLAG_BSWAP_CODE_SHIFT) 872 873static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, 874 target_ulong *cs_base, int *flags) 875{ 876 if (is_a64(env)) { 877 *pc = env->regs[15]; 878 *flags = ARM_TBFLAG_AARCH64_STATE_MASK; 879 } else { 880 int privmode; 881 *pc = env->regs[15]; 882 *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT) 883 | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT) 884 | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT) 885 | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT); 886 // | (env->bswap_code << ARM_TBFLAG_BSWAP_CODE_SHIFT); 887 if (arm_feature(env, ARM_FEATURE_M)) { 888 privmode = !((env->v7m.exception == 0) && (env->v7m.control & 1)); 889 } else { 890 privmode = (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR; 891 } 892 if (privmode) { 893 *flags |= ARM_TBFLAG_PRIV_MASK; 894 } 895 if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) { 896 *flags |= ARM_TBFLAG_VFPEN_MASK; 897 } 898 } 899 900 *cs_base = 0; 901} 902 903static inline bool cpu_has_work(CPUARMState *env) 904{ 905 return (env->interrupt_request & 906 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB)); 907} 908 909#include "exec/exec-all.h" 910 911static inline void cpu_pc_from_tb(CPUARMState *env, TranslationBlock *tb) 912{ 913 env->regs[15] = tb->pc; 914} 915 916#endif 917