cpu.h revision e2678e116c8cdb0f36b247a5bd9cfacc849362fc
1/* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19#ifndef CPU_ARM_H 20#define CPU_ARM_H 21 22#include "config.h" 23 24#include "kvm-consts.h" 25 26#if defined(TARGET_AARCH64) 27 /* AArch64 definitions */ 28# define TARGET_LONG_BITS 64 29# define ELF_MACHINE EM_AARCH64 30#else 31# define TARGET_LONG_BITS 32 32# define ELF_MACHINE EM_ARM 33#endif 34 35// TODO(digit): Remove this line. 36#define CPUOldState struct CPUARMState 37 38#define CPUArchState struct CPUARMState 39 40#include "qemu-common.h" 41#include "exec/cpu-defs.h" 42 43#include "fpu/softfloat.h" 44 45#define TARGET_HAS_ICE 1 46 47#define EXCP_UDEF 1 /* undefined instruction */ 48#define EXCP_SWI 2 /* software interrupt */ 49#define EXCP_PREFETCH_ABORT 3 50#define EXCP_DATA_ABORT 4 51#define EXCP_IRQ 5 52#define EXCP_FIQ 6 53#define EXCP_BKPT 7 54#define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 55#define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 56#define EXCP_STREX 10 57#define EXCP_SMC 11 /* secure monitor call */ 58 59#define ARMV7M_EXCP_RESET 1 60#define ARMV7M_EXCP_NMI 2 61#define ARMV7M_EXCP_HARD 3 62#define ARMV7M_EXCP_MEM 4 63#define ARMV7M_EXCP_BUS 5 64#define ARMV7M_EXCP_USAGE 6 65#define ARMV7M_EXCP_SVC 11 66#define ARMV7M_EXCP_DEBUG 12 67#define ARMV7M_EXCP_PENDSV 14 68#define ARMV7M_EXCP_SYSTICK 15 69 70/* ARM-specific interrupt pending bits. */ 71#define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 72 73/* Meanings of the ARMCPU object's two inbound GPIO lines */ 74#define ARM_CPU_IRQ 0 75#define ARM_CPU_FIQ 1 76 77typedef void ARMWriteCPFunc(void *opaque, int cp_info, 78 int srcreg, int operand, uint32_t value, 79 void *retaddr); 80typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info, 81 int dstreg, int operand, 82 void *retaddr); 83 84struct arm_boot_info; 85 86#define NB_MMU_MODES 2 87 88/* We currently assume float and double are IEEE single and double 89 precision respectively. 90 Doing runtime conversions is tricky because VFP registers may contain 91 integer values (eg. as the result of a FTOSI instruction). 92 s<2n> maps to the least significant half of d<n> 93 s<2n+1> maps to the most significant half of d<n> 94 */ 95 96/* CPU state for each instance of a generic timer (in cp15 c14) */ 97typedef struct ARMGenericTimer { 98 uint64_t cval; /* Timer CompareValue register */ 99 uint32_t ctl; /* Timer Control register */ 100} ARMGenericTimer; 101 102#define GTIMER_PHYS 0 103#define GTIMER_VIRT 1 104#define NUM_GTIMERS 2 105 106/* Scale factor for generic timers, ie number of ns per tick. 107 * This gives a 62.5MHz timer. 108 */ 109#define GTIMER_SCALE 16 110 111typedef struct CPUARMState { 112 /* Regs for current mode. */ 113 uint32_t regs[16]; 114 /* Frequently accessed CPSR bits are stored separately for efficiently. 115 This contains all the other bits. Use cpsr_{read,write} to access 116 the whole CPSR. */ 117 uint32_t uncached_cpsr; 118 uint32_t spsr; 119 120 /* Banked registers. */ 121 uint32_t banked_spsr[7]; 122 uint32_t banked_r13[7]; 123 uint32_t banked_r14[7]; 124 125 /* These hold r8-r12. */ 126 uint32_t usr_regs[5]; 127 uint32_t fiq_regs[5]; 128 129 /* cpsr flag cache for faster execution */ 130 uint32_t CF; /* 0 or 1 */ 131 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 132 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 133 uint32_t ZF; /* Z set if zero. */ 134 uint32_t QF; /* 0 or 1 */ 135 uint32_t GE; /* cpsr[19:16] */ 136 uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */ 137 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 138 139 /* System control coprocessor (cp15) */ 140 struct { 141 uint32_t c0_cpuid; 142 uint32_t c0_cachetype; 143 uint32_t c0_ccsid[16]; /* Cache size. */ 144 uint32_t c0_clid; /* Cache level. */ 145 uint32_t c0_cssel; /* Cache size selection. */ 146 uint32_t c0_c1[8]; /* Feature registers. */ 147 uint32_t c0_c2[8]; /* Instruction set registers. */ 148 uint32_t c1_sys; /* System control register. */ 149 uint32_t c1_coproc; /* Coprocessor access register. */ 150 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 151 uint32_t c1_secfg; /* Secure configuration register. */ 152 uint32_t c1_sedbg; /* Secure debug enable register. */ 153 uint32_t c1_nseac; /* Non-secure access control register. */ 154 uint32_t c2_base0; /* MMU translation table base 0. */ 155 uint32_t c2_base1; /* MMU translation table base 1. */ 156 uint32_t c2_control; /* MMU translation table base control. */ 157 uint32_t c2_mask; /* MMU translation table base selection mask. */ 158 uint32_t c2_base_mask; /* MMU translation table base 0 mask. */ 159 uint32_t c2_data; /* MPU data cachable bits. */ 160 uint32_t c2_insn; /* MPU instruction cachable bits. */ 161 uint32_t c3; /* MMU domain access control register 162 MPU write buffer control. */ 163 uint32_t c5_insn; /* Fault status registers. */ 164 uint32_t c5_data; 165 uint32_t c6_region[8]; /* MPU base/size registers. */ 166 uint32_t c6_insn; /* Fault address registers. */ 167 uint32_t c6_data; 168 uint32_t c7_par; /* Translation result. */ 169 uint32_t c9_insn; /* Cache lockdown registers. */ 170 uint32_t c9_data; 171 uint32_t c9_pmcr_data; /* Performance Monitor Control Register */ 172 uint32_t c9_useren; /* user enable register */ 173 uint32_t c9_inten; /* interrupt enable set/clear register */ 174 uint32_t c12_vbar; /* secure/nonsecure vector base address register. */ 175 uint32_t c12_mvbar; /* monitor vector base address register. */ 176 uint32_t c13_fcse; /* FCSE PID. */ 177 uint32_t c13_context; /* Context ID. */ 178 uint32_t c13_tls1; /* User RW Thread register. */ 179 uint32_t c13_tls2; /* User RO Thread register. */ 180 uint32_t c13_tls3; /* Privileged Thread register. */ 181 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 182 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 183 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 184 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 185 uint32_t c15_threadid; /* TI debugger thread-ID. */ 186 } cp15; 187 188 struct { 189 uint32_t other_sp; 190 uint32_t vecbase; 191 uint32_t basepri; 192 uint32_t control; 193 int current_sp; 194 int exception; 195 int pending_exception; 196 } v7m; 197 198 /* Minimal set of debug coprocessor state (cp14) */ 199 uint32_t cp14_dbgdidr; 200 201 /* Thumb-2 EE state. */ 202 uint32_t teecr; 203 uint32_t teehbr; 204 205 /* Internal CPU feature flags. */ 206 uint32_t features; 207 208 /* VFP coprocessor state. */ 209 struct { 210 float64 regs[32]; 211 212 uint32_t xregs[16]; 213 /* We store these fpcsr fields separately for convenience. */ 214 int vec_len; 215 int vec_stride; 216 217 /* scratch space when Tn are not sufficient. */ 218 uint32_t scratch[8]; 219 220 /* fp_status is the "normal" fp status. standard_fp_status retains 221 * values corresponding to the ARM "Standard FPSCR Value", ie 222 * default-NaN, flush-to-zero, round-to-nearest and is used by 223 * any operations (generally Neon) which the architecture defines 224 * as controlled by the standard FPSCR value rather than the FPSCR. 225 * 226 * To avoid having to transfer exception bits around, we simply 227 * say that the FPSCR cumulative exception flags are the logical 228 * OR of the flags in the two fp statuses. This relies on the 229 * only thing which needs to read the exception flags being 230 * an explicit FPSCR read. 231 */ 232 float_status fp_status; 233 float_status standard_fp_status; 234 } vfp; 235 uint32_t exclusive_addr; 236 uint32_t exclusive_val; 237 uint32_t exclusive_high; 238#if defined(CONFIG_USER_ONLY) 239 uint32_t exclusive_test; 240 uint32_t exclusive_info; 241#endif 242 243 /* iwMMXt coprocessor state. */ 244 struct { 245 uint64_t regs[16]; 246 uint64_t val; 247 248 uint32_t cregs[16]; 249 } iwmmxt; 250 251#if defined(CONFIG_USER_ONLY) 252 /* For usermode syscall translation. */ 253 int eabi; 254#endif 255 256 CPU_COMMON 257 258 /* These fields after the common ones so they are preserved on reset. */ 259 260 /* Coprocessor IO used by peripherals */ 261 struct { 262 ARMReadCPFunc *cp_read; 263 ARMWriteCPFunc *cp_write; 264 void *opaque; 265 } cp[15]; 266 void *nvic; 267 struct arm_boot_info *boot_info; 268} CPUARMState; 269 270CPUARMState *cpu_arm_init(const char *cpu_model); 271void arm_translate_init(void); 272int cpu_arm_exec(CPUARMState *s); 273void cpu_arm_close(CPUARMState *s); 274void do_interrupt(CPUARMState *); 275void switch_mode(CPUARMState *, int); 276uint32_t do_arm_semihosting(CPUARMState *env); 277 278static inline bool is_a64(CPUARMState *env) 279{ 280#ifdef CONFIG_ANDROID // TODO(digit) 281 return 0; 282#else 283 return env->aarch64; 284#endif 285} 286 287#define PSTATE_N_SHIFT 3 288#define PSTATE_N (1 << PSTATE_N_SHIFT) 289#define PSTATE_Z_SHIFT 2 290#define PSTATE_Z (1 << PSTATE_Z_SHIFT) 291#define PSTATE_C_SHIFT 1 292#define PSTATE_C (1 << PSTATE_C_SHIFT) 293#define PSTATE_V_SHIFT 0 294#define PSTATE_V (1 << PSTATE_V_SHIFT) 295 296/* you can call this signal handler from your SIGBUS and SIGSEGV 297 signal handlers to inform the virtual CPU of exceptions. non zero 298 is returned if the signal was handled by the virtual CPU. */ 299int cpu_arm_signal_handler(int host_signum, void *pinfo, 300 void *puc); 301int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw, 302 int mmu_idx, int is_softmuu); 303#define cpu_handle_mmu_fault cpu_arm_handle_mmu_fault 304 305static inline void cpu_set_tls(CPUARMState *env, target_ulong newtls) 306{ 307 env->cp15.c13_tls2 = newtls; 308} 309 310#define CPSR_M (0x1fU) 311#define CPSR_T (1U << 5) 312#define CPSR_F (1U << 6) 313#define CPSR_I (1U << 7) 314#define CPSR_A (1U << 8) 315#define CPSR_E (1U << 9) 316#define CPSR_IT_2_7 (0xfc00U) 317#define CPSR_GE (0xfU << 16) 318#define CPSR_RESERVED (0xfU << 20) 319#define CPSR_J (1U << 24) 320#define CPSR_IT_0_1 (3U << 25) 321#define CPSR_Q (1U << 27) 322#define CPSR_V (1U << 28) 323#define CPSR_C (1U << 29) 324#define CPSR_Z (1U << 30) 325#define CPSR_N (1U << 31) 326#define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 327 328#define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 329#define CACHED_CPSR_BITS (CPSR_T | CPSR_GE | CPSR_IT | CPSR_Q | CPSR_NZCV) 330/* Bits writable in user mode. */ 331#define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE) 332/* Execution state bits. MRS read as zero, MSR writes ignored. */ 333#define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J) 334 335/* Return the current CPSR value. */ 336uint32_t cpsr_read(CPUARMState *env); 337/* Set the CPSR. Note that some bits of mask must be all-set or all-clear. */ 338void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask); 339 340/* Return the current xPSR value. */ 341static inline uint32_t xpsr_read(CPUARMState *env) 342{ 343 int ZF; 344 ZF = (env->ZF == 0); 345 return (env->NF & 0x80000000) | (ZF << 30) 346 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 347 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 348 | ((env->condexec_bits & 0xfc) << 8) 349 | env->v7m.exception; 350} 351 352/* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 353static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 354{ 355 if (mask & CPSR_NZCV) { 356 env->ZF = (~val) & CPSR_Z; 357 env->NF = val; 358 env->CF = (val >> 29) & 1; 359 env->VF = (val << 3) & 0x80000000; 360 } 361 if (mask & CPSR_Q) 362 env->QF = ((val & CPSR_Q) != 0); 363 if (mask & (1 << 24)) 364 env->thumb = ((val & (1 << 24)) != 0); 365 if (mask & CPSR_IT_0_1) { 366 env->condexec_bits &= ~3; 367 env->condexec_bits |= (val >> 25) & 3; 368 } 369 if (mask & CPSR_IT_2_7) { 370 env->condexec_bits &= 3; 371 env->condexec_bits |= (val >> 8) & 0xfc; 372 } 373 if (mask & 0x1ff) { 374 env->v7m.exception = val & 0x1ff; 375 } 376} 377 378/* Return the current FPSCR value. */ 379uint32_t vfp_get_fpscr(CPUARMState *env); 380void vfp_set_fpscr(CPUARMState *env, uint32_t val); 381 382enum arm_cpu_mode { 383 ARM_CPU_MODE_USR = 0x10, 384 ARM_CPU_MODE_FIQ = 0x11, 385 ARM_CPU_MODE_IRQ = 0x12, 386 ARM_CPU_MODE_SVC = 0x13, 387 ARM_CPU_MODE_SMC = 0x16, 388 ARM_CPU_MODE_ABT = 0x17, 389 ARM_CPU_MODE_UND = 0x1b, 390 ARM_CPU_MODE_SYS = 0x1f 391}; 392 393/* VFP system registers. */ 394#define ARM_VFP_FPSID 0 395#define ARM_VFP_FPSCR 1 396#define ARM_VFP_MVFR1 6 397#define ARM_VFP_MVFR0 7 398#define ARM_VFP_FPEXC 8 399#define ARM_VFP_FPINST 9 400#define ARM_VFP_FPINST2 10 401 402/* iwMMXt coprocessor control registers. */ 403#define ARM_IWMMXT_wCID 0 404#define ARM_IWMMXT_wCon 1 405#define ARM_IWMMXT_wCSSF 2 406#define ARM_IWMMXT_wCASF 3 407#define ARM_IWMMXT_wCGR0 8 408#define ARM_IWMMXT_wCGR1 9 409#define ARM_IWMMXT_wCGR2 10 410#define ARM_IWMMXT_wCGR3 11 411 412/* If adding a feature bit which corresponds to a Linux ELF 413 * HWCAP bit, remember to update the feature-bit-to-hwcap 414 * mapping in linux-user/elfload.c:get_elf_hwcap(). 415 */ 416enum arm_features { 417 ARM_FEATURE_VFP, 418 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 419 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 420 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 421 ARM_FEATURE_V6, 422 ARM_FEATURE_V6K, 423 ARM_FEATURE_V7, 424 ARM_FEATURE_THUMB2, 425 ARM_FEATURE_MPU, /* Only has Memory Protection Unit, not full MMU. */ 426 ARM_FEATURE_VFP3, 427 ARM_FEATURE_VFP_FP16, 428 ARM_FEATURE_NEON, 429 ARM_FEATURE_DIV, 430 ARM_FEATURE_M, /* Microcontroller profile. */ 431 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 432 ARM_FEATURE_THUMB2EE, 433 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 434 ARM_FEATURE_V4T, 435 ARM_FEATURE_V5, 436 ARM_FEATURE_STRONGARM, 437 ARM_FEATURE_TRUSTZONE, /* TrustZone Security Extensions. */ 438}; 439 440static inline int arm_feature(CPUARMState *env, int feature) 441{ 442 return (env->features & (1ULL << feature)) != 0; 443} 444 445void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf); 446 447/* Interface between CPU and Interrupt controller. */ 448void armv7m_nvic_set_pending(void *opaque, int irq); 449int armv7m_nvic_acknowledge_irq(void *opaque); 450void armv7m_nvic_complete_irq(void *opaque, int irq); 451 452/* Interface for defining coprocessor registers. 453 * Registers are defined in tables of arm_cp_reginfo structs 454 * which are passed to define_arm_cp_regs(). 455 */ 456 457/* When looking up a coprocessor register we look for it 458 * via an integer which encodes all of: 459 * coprocessor number 460 * Crn, Crm, opc1, opc2 fields 461 * 32 or 64 bit register (ie is it accessed via MRC/MCR 462 * or via MRRC/MCRR?) 463 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. 464 * (In this case crn and opc2 should be zero.) 465 */ 466#define ENCODE_CP_REG(cp, is64, crn, crm, opc1, opc2) \ 467 (((cp) << 16) | ((is64) << 15) | ((crn) << 11) | \ 468 ((crm) << 7) | ((opc1) << 3) | (opc2)) 469 470/* Convert a full 64 bit KVM register ID to the truncated 32 bit 471 * version used as a key for the coprocessor register hashtable 472 */ 473static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) 474{ 475 uint32_t cpregid = kvmid; 476 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { 477 cpregid |= (1 << 15); 478 } 479 return cpregid; 480} 481 482/* Convert a truncated 32 bit hashtable key into the full 483 * 64 bit KVM register ID. 484 */ 485static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) 486{ 487 uint64_t kvmid = cpregid & ~(1 << 15); 488 if (cpregid & (1 << 15)) { 489 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; 490 } else { 491 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; 492 } 493 return kvmid; 494} 495 496/* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a 497 * special-behaviour cp reg and bits [15..8] indicate what behaviour 498 * it has. Otherwise it is a simple cp reg, where CONST indicates that 499 * TCG can assume the value to be constant (ie load at translate time) 500 * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END 501 * indicates that the TB should not be ended after a write to this register 502 * (the default is that the TB ends after cp writes). OVERRIDE permits 503 * a register definition to override a previous definition for the 504 * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the 505 * old must have the OVERRIDE bit set. 506 * NO_MIGRATE indicates that this register should be ignored for migration; 507 * (eg because any state is accessed via some other coprocessor register). 508 * IO indicates that this register does I/O and therefore its accesses 509 * need to be surrounded by gen_io_start()/gen_io_end(). In particular, 510 * registers which implement clocks or timers require this. 511 */ 512#define ARM_CP_SPECIAL 1 513#define ARM_CP_CONST 2 514#define ARM_CP_64BIT 4 515#define ARM_CP_SUPPRESS_TB_END 8 516#define ARM_CP_OVERRIDE 16 517#define ARM_CP_NO_MIGRATE 32 518#define ARM_CP_IO 64 519#define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8)) 520#define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8)) 521#define ARM_LAST_SPECIAL ARM_CP_WFI 522/* Used only as a terminator for ARMCPRegInfo lists */ 523#define ARM_CP_SENTINEL 0xffff 524/* Mask of only the flag bits in a type field */ 525#define ARM_CP_FLAG_MASK 0x7f 526 527/* Return true if cptype is a valid type field. This is used to try to 528 * catch errors where the sentinel has been accidentally left off the end 529 * of a list of registers. 530 */ 531static inline bool cptype_valid(int cptype) 532{ 533 return ((cptype & ~ARM_CP_FLAG_MASK) == 0) 534 || ((cptype & ARM_CP_SPECIAL) && 535 ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL)); 536} 537 538/* Access rights: 539 * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM 540 * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and 541 * PL2 (hyp). The other level which has Read and Write bits is Secure PL1 542 * (ie any of the privileged modes in Secure state, or Monitor mode). 543 * If a register is accessible in one privilege level it's always accessible 544 * in higher privilege levels too. Since "Secure PL1" also follows this rule 545 * (ie anything visible in PL2 is visible in S-PL1, some things are only 546 * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the 547 * terminology a little and call this PL3. 548 * 549 * If access permissions for a register are more complex than can be 550 * described with these bits, then use a laxer set of restrictions, and 551 * do the more restrictive/complex check inside a helper function. 552 */ 553#define PL3_R 0x80 554#define PL3_W 0x40 555#define PL2_R (0x20 | PL3_R) 556#define PL2_W (0x10 | PL3_W) 557#define PL1_R (0x08 | PL2_R) 558#define PL1_W (0x04 | PL2_W) 559#define PL0_R (0x02 | PL1_R) 560#define PL0_W (0x01 | PL1_W) 561 562#define PL3_RW (PL3_R | PL3_W) 563#define PL2_RW (PL2_R | PL2_W) 564#define PL1_RW (PL1_R | PL1_W) 565#define PL0_RW (PL0_R | PL0_W) 566 567static inline int arm_current_pl(CPUARMState *env) 568{ 569 if ((env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_USR) { 570 return 0; 571 } 572 /* We don't currently implement the Virtualization or TrustZone 573 * extensions, so PL2 and PL3 don't exist for us. 574 */ 575 return 1; 576} 577 578typedef struct ARMCPRegInfo ARMCPRegInfo; 579 580/* Access functions for coprocessor registers. These should return 581 * 0 on success, or one of the EXCP_* constants if access should cause 582 * an exception (in which case *value is not written). 583 */ 584typedef int CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque, 585 uint64_t *value); 586typedef int CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, 587 uint64_t value); 588/* Hook function for register reset */ 589typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); 590 591#define CP_ANY 0xff 592 593/* Definition of an ARM coprocessor register */ 594struct ARMCPRegInfo { 595 /* Name of register (useful mainly for debugging, need not be unique) */ 596 const char *name; 597 /* Location of register: coprocessor number and (crn,crm,opc1,opc2) 598 * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a 599 * 'wildcard' field -- any value of that field in the MRC/MCR insn 600 * will be decoded to this register. The register read and write 601 * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2 602 * used by the program, so it is possible to register a wildcard and 603 * then behave differently on read/write if necessary. 604 * For 64 bit registers, only crm and opc1 are relevant; crn and opc2 605 * must both be zero. 606 */ 607 uint8_t cp; 608 uint8_t crn; 609 uint8_t crm; 610 uint8_t opc1; 611 uint8_t opc2; 612 /* Register type: ARM_CP_* bits/values */ 613 int type; 614 /* Access rights: PL*_[RW] */ 615 int access; 616 /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when 617 * this register was defined: can be used to hand data through to the 618 * register read/write functions, since they are passed the ARMCPRegInfo*. 619 */ 620 void *opaque; 621 /* Value of this register, if it is ARM_CP_CONST. Otherwise, if 622 * fieldoffset is non-zero, the reset value of the register. 623 */ 624 uint64_t resetvalue; 625 /* Offset of the field in CPUARMState for this register. This is not 626 * needed if either: 627 * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs 628 * 2. both readfn and writefn are specified 629 */ 630 ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ 631 /* Function for handling reads of this register. If NULL, then reads 632 * will be done by loading from the offset into CPUARMState specified 633 * by fieldoffset. 634 */ 635 CPReadFn *readfn; 636 /* Function for handling writes of this register. If NULL, then writes 637 * will be done by writing to the offset into CPUARMState specified 638 * by fieldoffset. 639 */ 640 CPWriteFn *writefn; 641 /* Function for doing a "raw" read; used when we need to copy 642 * coprocessor state to the kernel for KVM or out for 643 * migration. This only needs to be provided if there is also a 644 * readfn and it makes an access permission check. 645 */ 646 CPReadFn *raw_readfn; 647 /* Function for doing a "raw" write; used when we need to copy KVM 648 * kernel coprocessor state into userspace, or for inbound 649 * migration. This only needs to be provided if there is also a 650 * writefn and it makes an access permission check or masks out 651 * "unwritable" bits or has write-one-to-clear or similar behaviour. 652 */ 653 CPWriteFn *raw_writefn; 654 /* Function for resetting the register. If NULL, then reset will be done 655 * by writing resetvalue to the field specified in fieldoffset. If 656 * fieldoffset is 0 then no reset will be done. 657 */ 658 CPResetFn *resetfn; 659}; 660 661/* Macros which are lvalues for the field in CPUARMState for the 662 * ARMCPRegInfo *ri. 663 */ 664#define CPREG_FIELD32(env, ri) \ 665 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) 666#define CPREG_FIELD64(env, ri) \ 667 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) 668 669#define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL } 670 671#ifndef CONFIG_ANDROID // TODO(digit): Implement ARMCPU 672void define_arm_cp_regs_with_opaque(ARMCPU *cpu, 673 const ARMCPRegInfo *regs, void *opaque); 674void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, 675 const ARMCPRegInfo *regs, void *opaque); 676static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs) 677{ 678 define_arm_cp_regs_with_opaque(cpu, regs, 0); 679} 680static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs) 681{ 682 define_one_arm_cp_reg_with_opaque(cpu, regs, 0); 683} 684const ARMCPRegInfo *get_arm_cp_reginfo(ARMCPU *cpu, uint32_t encoded_cp); 685#endif // !CONFIG_ANDROID 686 687/* CPWriteFn that can be used to implement writes-ignored behaviour */ 688int arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, 689 uint64_t value); 690/* CPReadFn that can be used for read-as-zero behaviour */ 691int arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value); 692 693static inline bool cp_access_ok(CPUARMState *env, 694 const ARMCPRegInfo *ri, int isread) 695{ 696 return (ri->access >> ((arm_current_pl(env) * 2) + isread)) & 1; 697} 698 699#ifndef CONFIG_ANDROID // TODO(digit): Implement ARMCPU 700/** 701 * write_list_to_cpustate 702 * @cpu: ARMCPU 703 * 704 * For each register listed in the ARMCPU cpreg_indexes list, write 705 * its value from the cpreg_values list into the ARMCPUARMState structure. 706 * This updates TCG's working data structures from KVM data or 707 * from incoming migration state. 708 * 709 * Returns: true if all register values were updated correctly, 710 * false if some register was unknown or could not be written. 711 * Note that we do not stop early on failure -- we will attempt 712 * writing all registers in the list. 713 */ 714bool write_list_to_cpustate(ARMCPU *cpu); 715 716/** 717 * write_cpustate_to_list: 718 * @cpu: ARMCPU 719 * 720 * For each register listed in the ARMCPU cpreg_indexes list, write 721 * its value from the ARMCPUARMState structure into the cpreg_values list. 722 * This is used to copy info from TCG's working data structures into 723 * KVM or for outbound migration. 724 * 725 * Returns: true if all register values were read correctly, 726 * false if some register was unknown or could not be read. 727 * Note that we do not stop early on failure -- we will attempt 728 * reading all registers in the list. 729 */ 730bool write_cpustate_to_list(ARMCPU *cpu); 731#endif // !CONFIG_ANDROID 732 733void cpu_arm_set_cp_io(CPUARMState *env, int cpnum, 734 ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write, 735 void *opaque); 736 737/* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3. 738 Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are 739 conventional cores (ie. Application or Realtime profile). */ 740 741#define IS_M(env) arm_feature(env, ARM_FEATURE_M) 742#define ARM_CPUID(env) (env->cp15.c0_cpuid) 743 744#define ARM_CPUID_ARM1026 0x4106a262 745#define ARM_CPUID_ARM926 0x41069265 746#define ARM_CPUID_ARM946 0x41059461 747#define ARM_CPUID_TI915T 0x54029152 748#define ARM_CPUID_TI925T 0x54029252 749#define ARM_CPUID_SA1100 0x4401A11B 750#define ARM_CPUID_SA1110 0x6901B119 751#define ARM_CPUID_PXA250 0x69052100 752#define ARM_CPUID_PXA255 0x69052d00 753#define ARM_CPUID_PXA260 0x69052903 754#define ARM_CPUID_PXA261 0x69052d05 755#define ARM_CPUID_PXA262 0x69052d06 756#define ARM_CPUID_PXA270 0x69054110 757#define ARM_CPUID_PXA270_A0 0x69054110 758#define ARM_CPUID_PXA270_A1 0x69054111 759#define ARM_CPUID_PXA270_B0 0x69054112 760#define ARM_CPUID_PXA270_B1 0x69054113 761#define ARM_CPUID_PXA270_C0 0x69054114 762#define ARM_CPUID_PXA270_C5 0x69054117 763#define ARM_CPUID_ARM1136 0x4117b363 764#define ARM_CPUID_ARM1136_R2 0x4107b362 765#define ARM_CPUID_ARM11MPCORE 0x410fb022 766#define ARM_CPUID_CORTEXA8 0x410fc080 767#define ARM_CPUID_CORTEXA8_R2 0x412fc083 768#define ARM_CPUID_CORTEXA9 0x410fc090 769#define ARM_CPUID_CORTEXM3 0x410fc231 770#define ARM_CPUID_ANY 0xffffffff 771 772#if defined(CONFIG_USER_ONLY) 773#define TARGET_PAGE_BITS 12 774#else 775/* The ARM MMU allows 1k pages. */ 776/* ??? Linux doesn't actually use these, and they're deprecated in recent 777 architecture revisions. Maybe a configure option to disable them. */ 778#define TARGET_PAGE_BITS 10 779#endif 780 781#if defined(TARGET_AARCH64) 782# define TARGET_PHYS_ADDR_SPACE_BITS 48 783# define TARGET_VIRT_ADDR_SPACE_BITS 64 784#else 785# define TARGET_PHYS_ADDR_SPACE_BITS 40 786# define TARGET_VIRT_ADDR_SPACE_BITS 32 787#endif 788 789#define cpu_init cpu_arm_init 790#define cpu_exec cpu_arm_exec 791#define cpu_gen_code cpu_arm_gen_code 792#define cpu_signal_handler cpu_arm_signal_handler 793#define cpu_list arm_cpu_list 794 795#define CPU_SAVE_VERSION 3 796 797/* MMU modes definitions */ 798#define MMU_MODE0_SUFFIX _kernel 799#define MMU_MODE1_SUFFIX _user 800#define MMU_USER_IDX 1 801static inline int cpu_mmu_index (CPUARMState *env) 802{ 803 return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0; 804} 805 806static inline int is_cpu_user (CPUARMState *env) 807{ 808#ifdef CONFIG_USER_ONLY 809 return 1; 810#else 811 return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR; 812#endif // CONFIG_USER_ONLY 813} 814 815#if defined(CONFIG_USER_ONLY) 816static inline void cpu_clone_regs(CPUARMState *env, target_ulong newsp) 817{ 818 if (newsp) 819 env->regs[13] = newsp; 820 env->regs[0] = 0; 821} 822#endif 823 824#include "exec/cpu-all.h" 825 826/* Bit usage in the TB flags field: bit 31 indicates whether we are 827 * in 32 or 64 bit mode. The meaning of the other bits depends on that. 828 */ 829#define ARM_TBFLAG_AARCH64_STATE_SHIFT 31 830#define ARM_TBFLAG_AARCH64_STATE_MASK (1U << ARM_TBFLAG_AARCH64_STATE_SHIFT) 831 832/* Bit usage when in AArch32 state: */ 833#define ARM_TBFLAG_THUMB_SHIFT 0 834#define ARM_TBFLAG_THUMB_MASK (1 << ARM_TBFLAG_THUMB_SHIFT) 835#define ARM_TBFLAG_VECLEN_SHIFT 1 836#define ARM_TBFLAG_VECLEN_MASK (0x7 << ARM_TBFLAG_VECLEN_SHIFT) 837#define ARM_TBFLAG_VECSTRIDE_SHIFT 4 838#define ARM_TBFLAG_VECSTRIDE_MASK (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT) 839#define ARM_TBFLAG_PRIV_SHIFT 6 840#define ARM_TBFLAG_PRIV_MASK (1 << ARM_TBFLAG_PRIV_SHIFT) 841#define ARM_TBFLAG_VFPEN_SHIFT 7 842#define ARM_TBFLAG_VFPEN_MASK (1 << ARM_TBFLAG_VFPEN_SHIFT) 843#define ARM_TBFLAG_CONDEXEC_SHIFT 8 844#define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT) 845#define ARM_TBFLAG_BSWAP_CODE_SHIFT 16 846#define ARM_TBFLAG_BSWAP_CODE_MASK (1 << ARM_TBFLAG_BSWAP_CODE_SHIFT) 847 848/* Bit usage when in AArch64 state: currently no bits defined */ 849 850/* some convenience accessor macros */ 851#define ARM_TBFLAG_AARCH64_STATE(F) \ 852 (((F) & ARM_TBFLAG_AARCH64_STATE_MASK) >> ARM_TBFLAG_AARCH64_STATE_SHIFT) 853#define ARM_TBFLAG_THUMB(F) \ 854 (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT) 855#define ARM_TBFLAG_VECLEN(F) \ 856 (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT) 857#define ARM_TBFLAG_VECSTRIDE(F) \ 858 (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT) 859#define ARM_TBFLAG_PRIV(F) \ 860 (((F) & ARM_TBFLAG_PRIV_MASK) >> ARM_TBFLAG_PRIV_SHIFT) 861#define ARM_TBFLAG_VFPEN(F) \ 862 (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT) 863#define ARM_TBFLAG_CONDEXEC(F) \ 864 (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT) 865#define ARM_TBFLAG_BSWAP_CODE(F) \ 866 (((F) & ARM_TBFLAG_BSWAP_CODE_MASK) >> ARM_TBFLAG_BSWAP_CODE_SHIFT) 867 868static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, 869 target_ulong *cs_base, int *flags) 870{ 871 if (is_a64(env)) { 872 *pc = env->regs[15]; 873 *flags = ARM_TBFLAG_AARCH64_STATE_MASK; 874 } else { 875 int privmode; 876 *pc = env->regs[15]; 877 *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT) 878 | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT) 879 | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT) 880 | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT); 881 // | (env->bswap_code << ARM_TBFLAG_BSWAP_CODE_SHIFT); 882 if (arm_feature(env, ARM_FEATURE_M)) { 883 privmode = !((env->v7m.exception == 0) && (env->v7m.control & 1)); 884 } else { 885 privmode = (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR; 886 } 887 if (privmode) { 888 *flags |= ARM_TBFLAG_PRIV_MASK; 889 } 890 if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) { 891 *flags |= ARM_TBFLAG_VFPEN_MASK; 892 } 893 } 894 895 *cs_base = 0; 896} 897 898#endif 899