1409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#if !defined (__MIPS_CPU_H__) 2409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define __MIPS_CPU_H__ 3409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 426a8fb6421ab91cfdecdbee299e5e28918c4f0d4David 'Digit' Turner//#define DEBUG_OP 526a8fb6421ab91cfdecdbee299e5e28918c4f0d4David 'Digit' Turner 6409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define TARGET_HAS_ICE 1 7409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 8409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define ELF_MACHINE EM_MIPS 9409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 1026a8fb6421ab91cfdecdbee299e5e28918c4f0d4David 'Digit' Turner// TODO(digit): Remove this define. 11e2678e116c8cdb0f36b247a5bd9cfacc849362fcDavid 'Digit' Turner#define CPUOldState struct CPUMIPSState 12409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 1326a8fb6421ab91cfdecdbee299e5e28918c4f0d4David 'Digit' Turner#define CPUArchState struct CPUMIPSState 1426a8fb6421ab91cfdecdbee299e5e28918c4f0d4David 'Digit' Turner 15409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#include "config.h" 1626a8fb6421ab91cfdecdbee299e5e28918c4f0d4David 'Digit' Turner#include "qemu-common.h" 17409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#include "mips-defs.h" 18852088c7e08182c2de563872d558309815cbfa0dDavid 'Digit' Turner#include "exec/cpu-defs.h" 195425d40d2955e859097ded7a04913c3e7ee1a7b6David 'Digit' Turner#include "fpu/softfloat.h" 20409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 21409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli// uint_fast8_t and uint_fast16_t not in <sys/int_types.h> 22409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli// XXX: move that elsewhere 23409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#if defined(CONFIG_SOLARIS) && CONFIG_SOLARIS_VERSION < 10 24409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallitypedef unsigned char uint_fast8_t; 25409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallitypedef unsigned int uint_fast16_t; 26409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#endif 27409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 28409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallistruct CPUMIPSState; 29409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 30409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallitypedef struct r4k_tlb_t r4k_tlb_t; 31409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallistruct r4k_tlb_t { 32409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong VPN; 33409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli uint32_t PageMask; 34409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli uint_fast8_t ASID; 35409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli uint_fast16_t G:1; 36409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli uint_fast16_t C0:3; 37409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli uint_fast16_t C1:3; 38409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli uint_fast16_t V0:1; 39409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli uint_fast16_t V1:1; 40409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli uint_fast16_t D0:1; 41409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli uint_fast16_t D1:1; 42409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong PFN[2]; 43409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli}; 44409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 4526a8fb6421ab91cfdecdbee299e5e28918c4f0d4David 'Digit' Turner#if !defined(CONFIG_USER_ONLY) 46409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallitypedef struct CPUMIPSTLBContext CPUMIPSTLBContext; 47409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallistruct CPUMIPSTLBContext { 48409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli uint32_t nb_tlb; 49bcde1092aca184dbd7860078af020de7d1e4e22fDavid 'Digit' Turner int (*map_address) (struct CPUMIPSState *env, hwaddr *physical, int *prot, target_ulong address, int rw, int access_type); 50758fa08712c9b1075c49adf86fd0a24c8fdb30ecDavid 'Digit' Turner void (*helper_tlbwi)(struct CPUMIPSState *env); 51758fa08712c9b1075c49adf86fd0a24c8fdb30ecDavid 'Digit' Turner void (*helper_tlbwr)(struct CPUMIPSState *env); 52758fa08712c9b1075c49adf86fd0a24c8fdb30ecDavid 'Digit' Turner void (*helper_tlbp)(struct CPUMIPSState *env); 53758fa08712c9b1075c49adf86fd0a24c8fdb30ecDavid 'Digit' Turner void (*helper_tlbr)(struct CPUMIPSState *env); 54409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli union { 55409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli struct { 56409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli r4k_tlb_t tlb[MIPS_TLB_MAX]; 57409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli } r4k; 58409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli } mmu; 59409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli}; 6026a8fb6421ab91cfdecdbee299e5e28918c4f0d4David 'Digit' Turner#endif 61409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 62409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallitypedef union fpr_t fpr_t; 63409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalliunion fpr_t { 64409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli float64 fd; /* ieee double precision */ 65409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli float32 fs[2];/* ieee single precision */ 66409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli uint64_t d; /* binary double fixed-point */ 67409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli uint32_t w[2]; /* binary single fixed-point */ 68409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli}; 69409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli/* define FP_ENDIAN_IDX to access the same location 7026a8fb6421ab91cfdecdbee299e5e28918c4f0d4David 'Digit' Turner * in the fpr_t union regardless of the host endianness 71409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli */ 72409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#if defined(HOST_WORDS_BIGENDIAN) 73409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli# define FP_ENDIAN_IDX 1 74409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#else 75409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli# define FP_ENDIAN_IDX 0 76409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#endif 77409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 78409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallitypedef struct CPUMIPSFPUContext CPUMIPSFPUContext; 79409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallistruct CPUMIPSFPUContext { 80409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli /* Floating point registers */ 81409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli fpr_t fpr[32]; 82409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli float_status fp_status; 83409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli /* fpu implementation/revision register (fir) */ 84409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli uint32_t fcr0; 85409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define FCR0_F64 22 86409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define FCR0_L 21 87409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define FCR0_W 20 88409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define FCR0_3D 19 89409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define FCR0_PS 18 90409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define FCR0_D 17 91409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define FCR0_S 16 92409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define FCR0_PRID 8 93409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define FCR0_REV 0 94409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli /* fcsr */ 95409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli uint32_t fcr31; 96409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define SET_FP_COND(num,env) do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0) 97409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CLEAR_FP_COND(num,env) do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0) 98409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | (((env).fcr31 >> 23) & 0x1)) 99409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f) 100409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f) 101409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f) 102409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define SET_FP_CAUSE(reg,v) do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0) 103409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define SET_FP_ENABLE(reg,v) do { (reg) = ((reg) & ~(0x1f << 7)) | ((v & 0x1f) << 7); } while(0) 104409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define SET_FP_FLAGS(reg,v) do { (reg) = ((reg) & ~(0x1f << 2)) | ((v & 0x1f) << 2); } while(0) 105409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define UPDATE_FP_FLAGS(reg,v) do { (reg) |= ((v & 0x1f) << 2); } while(0) 106409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define FP_INEXACT 1 107409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define FP_UNDERFLOW 2 108409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define FP_OVERFLOW 4 109409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define FP_DIV0 8 110409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define FP_INVALID 16 111409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define FP_UNIMPLEMENTED 32 112409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli}; 113409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 114409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define NB_MMU_MODES 3 115409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 116409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallitypedef struct CPUMIPSMVPContext CPUMIPSMVPContext; 117409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallistruct CPUMIPSMVPContext { 118409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_MVPControl; 119409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0MVPCo_CPA 3 120409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0MVPCo_STLB 2 121409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0MVPCo_VPC 1 122409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0MVPCo_EVP 0 123409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_MVPConf0; 124409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0MVPC0_M 31 125409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0MVPC0_TLBS 29 126409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0MVPC0_GS 28 127409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0MVPC0_PCP 27 128409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0MVPC0_PTLBE 16 129409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0MVPC0_TCA 15 130409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0MVPC0_PVPE 10 131409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0MVPC0_PTC 0 132409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_MVPConf1; 133409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0MVPC1_CIM 31 134409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0MVPC1_CIF 30 135409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0MVPC1_PCX 20 136409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0MVPC1_PCP2 10 137409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0MVPC1_PCP1 0 138409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli}; 139409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 140409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallitypedef struct mips_def_t mips_def_t; 141409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 142409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define MIPS_SHADOW_SET_MAX 16 143409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define MIPS_TC_MAX 5 144409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define MIPS_FPU_MAX 1 145409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define MIPS_DSP_ACC 4 146409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 147409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallitypedef struct TCState TCState; 148409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallistruct TCState { 149409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong gpr[32]; 150409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong PC; 151409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong HI[MIPS_DSP_ACC]; 152409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong LO[MIPS_DSP_ACC]; 153409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong ACX[MIPS_DSP_ACC]; 154409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong DSPControl; 155409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_TCStatus; 156409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0TCSt_TCU3 31 157409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0TCSt_TCU2 30 158409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0TCSt_TCU1 29 159409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0TCSt_TCU0 28 160409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0TCSt_TMX 27 161409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0TCSt_RNST 23 162409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0TCSt_TDS 21 163409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0TCSt_DT 20 164409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0TCSt_DA 15 165409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0TCSt_A 13 166409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0TCSt_TKSU 11 167409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0TCSt_IXMT 10 168409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0TCSt_TASID 0 169409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_TCBind; 170409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0TCBd_CurTC 21 171409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0TCBd_TBE 17 172409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0TCBd_CurVPE 0 173409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong CP0_TCHalt; 174409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong CP0_TCContext; 175409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong CP0_TCSchedule; 176409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong CP0_TCScheFBack; 177409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_Debug_tcstatus; 178409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli}; 179409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 180409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallitypedef struct CPUMIPSState CPUMIPSState; 181409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallistruct CPUMIPSState { 182409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli TCState active_tc; 183409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli CPUMIPSFPUContext active_fpu; 184409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 185409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli uint32_t current_tc; 186409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli uint32_t current_fpu; 187409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 188409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli uint32_t SEGBITS; 189409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli uint32_t PABITS; 190409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong SEGMask; 191409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong PAMask; 192409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 193409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_Index; 194409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli /* CP0_MVP* are per MVP registers. */ 195409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_Random; 196409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_VPEControl; 197409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPECo_YSI 21 198409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPECo_GSI 20 199409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPECo_EXCPT 16 200409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPECo_TE 15 201409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPECo_TargTC 0 202409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_VPEConf0; 203409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPEC0_M 31 204409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPEC0_XTC 21 205409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPEC0_TCS 19 206409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPEC0_SCS 18 207409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPEC0_DSC 17 208409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPEC0_ICS 16 209409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPEC0_MVP 1 210409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPEC0_VPA 0 211409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_VPEConf1; 212409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPEC1_NCX 20 213409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPEC1_NCP2 10 214409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPEC1_NCP1 0 215409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong CP0_YQMask; 216409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong CP0_VPESchedule; 217409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong CP0_VPEScheFBack; 218409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_VPEOpt; 219409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPEOpt_IWX7 15 220409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPEOpt_IWX6 14 221409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPEOpt_IWX5 13 222409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPEOpt_IWX4 12 223409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPEOpt_IWX3 11 224409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPEOpt_IWX2 10 225409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPEOpt_IWX1 9 226409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPEOpt_IWX0 8 227409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPEOpt_DWX7 7 228409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPEOpt_DWX6 6 229409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPEOpt_DWX5 5 230409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPEOpt_DWX4 4 231409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPEOpt_DWX3 3 232409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPEOpt_DWX2 2 233409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPEOpt_DWX1 1 234409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0VPEOpt_DWX0 0 235409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong CP0_EntryLo0; 236409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong CP0_EntryLo1; 237409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong CP0_Context; 238409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_PageMask; 239409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_PageGrain; 240409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_Wired; 241409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_SRSConf0_rw_bitmask; 242409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_SRSConf0; 243409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSC0_M 31 244409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSC0_SRS3 20 245409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSC0_SRS2 10 246409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSC0_SRS1 0 247409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_SRSConf1_rw_bitmask; 248409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_SRSConf1; 249409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSC1_M 31 250409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSC1_SRS6 20 251409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSC1_SRS5 10 252409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSC1_SRS4 0 253409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_SRSConf2_rw_bitmask; 254409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_SRSConf2; 255409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSC2_M 31 256409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSC2_SRS9 20 257409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSC2_SRS8 10 258409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSC2_SRS7 0 259409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_SRSConf3_rw_bitmask; 260409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_SRSConf3; 261409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSC3_M 31 262409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSC3_SRS12 20 263409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSC3_SRS11 10 264409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSC3_SRS10 0 265409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_SRSConf4_rw_bitmask; 266409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_SRSConf4; 267409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSC4_SRS15 20 268409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSC4_SRS14 10 269409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSC4_SRS13 0 270409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_HWREna; 271409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong CP0_BadVAddr; 272409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_Count; 273409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong CP0_EntryHi; 274409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_Compare; 275409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_Status; 276409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0St_CU3 31 277409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0St_CU2 30 278409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0St_CU1 29 279409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0St_CU0 28 280409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0St_RP 27 281409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0St_FR 26 282409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0St_RE 25 283409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0St_MX 24 284409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0St_PX 23 285409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0St_BEV 22 286409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0St_TS 21 287409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0St_SR 20 288409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0St_NMI 19 289409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0St_IM 8 290409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0St_KX 7 291409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0St_SX 6 292409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0St_UX 5 293409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0St_KSU 3 294409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0St_ERL 2 295409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0St_EXL 1 296409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0St_IE 0 297409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_IntCtl; 298409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0IntCtl_IPTI 29 299409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0IntCtl_IPPC1 26 300409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0IntCtl_VS 5 301409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_SRSCtl; 302409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSCtl_HSS 26 303409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSCtl_EICSS 18 304409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSCtl_ESS 12 305409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSCtl_PSS 6 306409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSCtl_CSS 0 307409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_SRSMap; 308409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSMap_SSV7 28 309409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSMap_SSV6 24 310409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSMap_SSV5 20 311409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSMap_SSV4 16 312409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSMap_SSV3 12 313409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSMap_SSV2 8 314409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSMap_SSV1 4 315409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0SRSMap_SSV0 0 316409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_Cause; 317409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0Ca_BD 31 318409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0Ca_TI 30 319409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0Ca_CE 28 320409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0Ca_DC 27 321409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0Ca_PCI 26 322409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0Ca_IV 23 323409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0Ca_WP 22 324409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0Ca_IP 8 325409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0Ca_IP_mask 0x0000FF00 326409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0Ca_EC 2 327409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong CP0_EPC; 328409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_PRid; 329409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_EBase; 330409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_Config0; 331409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C0_M 31 332409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C0_K23 28 333409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C0_KU 25 334409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C0_MDU 20 335409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C0_MM 17 336409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C0_BM 16 337409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C0_BE 15 338409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C0_AT 13 339409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C0_AR 10 340409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C0_MT 7 341409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C0_VI 3 342409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C0_K0 0 343409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_Config1; 344409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C1_M 31 345409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C1_MMU 25 346409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C1_IS 22 347409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C1_IL 19 348409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C1_IA 16 349409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C1_DS 13 350409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C1_DL 10 351409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C1_DA 7 352409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C1_C2 6 353409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C1_MD 5 354409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C1_PC 4 355409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C1_WR 3 356409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C1_CA 2 357409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C1_EP 1 358409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C1_FP 0 359409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_Config2; 360409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C2_M 31 361409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C2_TU 28 362409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C2_TS 24 363409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C2_TL 20 364409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C2_TA 16 365409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C2_SU 12 366409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C2_SS 8 367409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C2_SL 4 368409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C2_SA 0 369409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_Config3; 370409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C3_M 31 37126a8fb6421ab91cfdecdbee299e5e28918c4f0d4David 'Digit' Turner#define CP0C3_ISA_ON_EXC 16 372409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C3_DSPP 10 373409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C3_LPA 7 374409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C3_VEIC 6 375409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C3_VInt 5 376409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C3_SP 4 377409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C3_MT 2 378409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C3_SM 1 379409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0C3_TL 0 380409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_Config6; 381409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_Config7; 382409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli /* XXX: Maybe make LLAddr per-TC? */ 383409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong lladdr; 384409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong llval; 385409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong llnewval; 386409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong llreg; 387409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong CP0_LLAddr_rw_bitmask; 388409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int CP0_LLAddr_shift; 389409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong CP0_WatchLo[8]; 390409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_WatchHi[8]; 391409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong CP0_XContext; 392409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_Framemask; 393409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_Debug; 394409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0DB_DBD 31 395409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0DB_DM 30 396409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0DB_LSNM 28 397409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0DB_Doze 27 398409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0DB_Halt 26 399409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0DB_CNT 25 400409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0DB_IBEP 24 401409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0DB_DBEP 21 402409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0DB_IEXI 20 403409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0DB_VER 15 404409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0DB_DEC 10 405409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0DB_SSt 8 406409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0DB_DINT 5 407409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0DB_DIB 4 408409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0DB_DDBS 3 409409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0DB_DDBL 2 410409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0DB_DBp 1 411409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CP0DB_DSS 0 412409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong CP0_DEPC; 413409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_Performance0; 414409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_TagLo; 415409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_DataLo; 416409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_TagHi; 417409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_DataHi; 418409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong CP0_ErrorEPC; 419409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_DESAVE; 420409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli /* We waste some space so we can handle shadow registers like TCs. */ 421409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli TCState tcs[MIPS_SHADOW_SET_MAX]; 422409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli CPUMIPSFPUContext fpus[MIPS_FPU_MAX]; 42326a8fb6421ab91cfdecdbee299e5e28918c4f0d4David 'Digit' Turner /* QEMU */ 424409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int error_code; 425409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli uint32_t hflags; /* CPU State */ 426409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli /* TMASK defines different execution modes */ 427409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define MIPS_HFLAG_TMASK 0x03FF 428409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define MIPS_HFLAG_MODE 0x0007 /* execution modes */ 429409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli /* The KSU flags must be the lowest bits in hflags. The flag order 430409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli must be the same as defined for CP0 Status. This allows to use 431409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli the bits as the value of mmu_idx. */ 432409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define MIPS_HFLAG_KSU 0x0003 /* kernel/supervisor/user mode mask */ 433409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define MIPS_HFLAG_UM 0x0002 /* user mode flag */ 434409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define MIPS_HFLAG_SM 0x0001 /* supervisor mode flag */ 435409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define MIPS_HFLAG_KM 0x0000 /* kernel mode flag */ 436409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define MIPS_HFLAG_DM 0x0004 /* Debug mode */ 437409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define MIPS_HFLAG_64 0x0008 /* 64-bit instructions enabled */ 438409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define MIPS_HFLAG_CP0 0x0010 /* CP0 enabled */ 439409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define MIPS_HFLAG_FPU 0x0020 /* FPU enabled */ 440409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define MIPS_HFLAG_F64 0x0040 /* 64-bit FPU enabled */ 441409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli /* True if the MIPS IV COP1X instructions can be used. This also 442409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S 443409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli and RSQRT.D. */ 444409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define MIPS_HFLAG_COP1X 0x0080 /* COP1X instructions enabled */ 445409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define MIPS_HFLAG_RE 0x0100 /* Reversed endianness */ 446409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define MIPS_HFLAG_UX 0x0200 /* 64-bit user mode */ 447409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli /* If translation is interrupted between the branch instruction and 448409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli * the delay slot, record what type of branch it is so that we can 449409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli * resume translation properly. It might be possible to reduce 450409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli * this from three bits to two. */ 451409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define MIPS_HFLAG_BMASK 0x1C00 452409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define MIPS_HFLAG_B 0x0400 /* Unconditional branch */ 453409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define MIPS_HFLAG_BC 0x0800 /* Conditional branch */ 454409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define MIPS_HFLAG_BL 0x0C00 /* Likely branch */ 455409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define MIPS_HFLAG_BR 0x1000 /* branch to register (can't link TB) */ 456409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong btarget; /* Jump / branch target */ 457409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong bcond; /* Branch condition (if needed) */ 458409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 459409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int SYNCI_Step; /* Address step size for SYNCI */ 460409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int CCRes; /* Cycle count resolution/divisor */ 461409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */ 462409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */ 463409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int insn_flags; /* Supported instruction set */ 464409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 465409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong tls_value; /* For usermode emulation */ 466409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 467409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli CPU_COMMON 468409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 469409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli CPUMIPSMVPContext *mvp; 47026a8fb6421ab91cfdecdbee299e5e28918c4f0d4David 'Digit' Turner#if !defined(CONFIG_USER_ONLY) 471409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli CPUMIPSTLBContext *tlb; 47226a8fb6421ab91cfdecdbee299e5e28918c4f0d4David 'Digit' Turner#endif 473409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 474409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli const mips_def_t *cpu_model; 475409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli void *irq[8]; 476409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli struct QEMUTimer *timer; /* Internal timer */ 477409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli}; 478409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 4796657678c3d86395084f6a699e73614195f06c445David 'Digit' Turner#include "cpu-qom.h" 4806657678c3d86395084f6a699e73614195f06c445David 'Digit' Turner 481bcde1092aca184dbd7860078af020de7d1e4e22fDavid 'Digit' Turnerint no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, 482409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong address, int rw, int access_type); 483bcde1092aca184dbd7860078af020de7d1e4e22fDavid 'Digit' Turnerint fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, 484409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong address, int rw, int access_type); 485bcde1092aca184dbd7860078af020de7d1e4e22fDavid 'Digit' Turnerint r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, 486409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong address, int rw, int access_type); 487758fa08712c9b1075c49adf86fd0a24c8fdb30ecDavid 'Digit' Turnervoid r4k_helper_tlbwi(CPUMIPSState *env); 488758fa08712c9b1075c49adf86fd0a24c8fdb30ecDavid 'Digit' Turnervoid r4k_helper_tlbwr(CPUMIPSState *env); 489758fa08712c9b1075c49adf86fd0a24c8fdb30ecDavid 'Digit' Turnervoid r4k_helper_tlbp(CPUMIPSState *env); 490758fa08712c9b1075c49adf86fd0a24c8fdb30ecDavid 'Digit' Turnervoid r4k_helper_tlbr(CPUMIPSState *env); 491409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallivoid mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)); 492409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 4936cf763a179bb432ef845025bb3639fcaf1251bd0David 'Digit' Turnervoid cpu_unassigned_access(CPUArchState* env, hwaddr addr, 4946cf763a179bb432ef845025bb3639fcaf1251bd0David 'Digit' Turner int is_write, int is_exec, int unused, int size); 495409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 496409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define cpu_init cpu_mips_init 497409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define cpu_exec cpu_mips_exec 498409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define cpu_gen_code cpu_mips_gen_code 499409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define cpu_signal_handler cpu_mips_signal_handler 500409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define cpu_list mips_cpu_list 501409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 502409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CPU_SAVE_VERSION 3 503409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 50426a8fb6421ab91cfdecdbee299e5e28918c4f0d4David 'Digit' Turner// NOTE(digit): Came from cpu-all.h, to be removed later. 50526a8fb6421ab91cfdecdbee299e5e28918c4f0d4David 'Digit' Turner#define CPU_INTERRUPT_TIMER 0x08 /* internal timer exception pending */ 50626a8fb6421ab91cfdecdbee299e5e28918c4f0d4David 'Digit' Turner 507409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli/* MMU modes definitions. We carefully match the indices with our 508409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli hflags layout. */ 509409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define MMU_MODE0_SUFFIX _kernel 510409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define MMU_MODE1_SUFFIX _super 511409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define MMU_MODE2_SUFFIX _user 512409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define MMU_USER_IDX 2 51326a8fb6421ab91cfdecdbee299e5e28918c4f0d4David 'Digit' Turnerstatic inline int cpu_mmu_index (CPUMIPSState *env) 514409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli{ 515409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli return env->hflags & MIPS_HFLAG_KSU; 516409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli} 517409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 51826a8fb6421ab91cfdecdbee299e5e28918c4f0d4David 'Digit' Turnerstatic inline int is_cpu_user (CPUMIPSState *env) 519325e19d19ff9e1fc9c6acb12eeb754563fc2e251Bhanu Chetlapalli{ 520325e19d19ff9e1fc9c6acb12eeb754563fc2e251Bhanu Chetlapalli#ifdef CONFIG_USER_ONLY 521325e19d19ff9e1fc9c6acb12eeb754563fc2e251Bhanu Chetlapalli return 1; 522325e19d19ff9e1fc9c6acb12eeb754563fc2e251Bhanu Chetlapalli#else 523325e19d19ff9e1fc9c6acb12eeb754563fc2e251Bhanu Chetlapalli return ((env->CP0_Status & 524325e19d19ff9e1fc9c6acb12eeb754563fc2e251Bhanu Chetlapalli ((3 << CP0St_KSU) | (1 << CP0St_ERL) | (1 << CP0St_EXL))) == (3 << CP0St_KSU)); 525325e19d19ff9e1fc9c6acb12eeb754563fc2e251Bhanu Chetlapalli#endif // CONFIG_USER_ONLY 526325e19d19ff9e1fc9c6acb12eeb754563fc2e251Bhanu Chetlapalli} 527325e19d19ff9e1fc9c6acb12eeb754563fc2e251Bhanu Chetlapalli 528e2678e116c8cdb0f36b247a5bd9cfacc849362fcDavid 'Digit' Turnerstatic inline void cpu_clone_regs(CPUMIPSState *env, target_ulong newsp) 529409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli{ 530409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli if (newsp) 531409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli env->active_tc.gpr[29] = newsp; 532409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli env->active_tc.gpr[7] = 0; 533409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli env->active_tc.gpr[2] = 0; 534409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli} 535409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 536e2678e116c8cdb0f36b247a5bd9cfacc849362fcDavid 'Digit' Turnerstatic inline int cpu_mips_hw_interrupts_pending(CPUMIPSState *env) 537741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli{ 538741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli int32_t pending; 539741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli int32_t status; 540741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli int r; 541741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli 542741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli if (!(env->CP0_Status & (1 << CP0St_IE)) || 543741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli (env->CP0_Status & (1 << CP0St_EXL)) || 544741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli (env->CP0_Status & (1 << CP0St_ERL)) || 545741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli (env->hflags & MIPS_HFLAG_DM)) { 546741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli /* Interrupts are disabled */ 547741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli return 0; 548741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli } 549741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli 550741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli pending = env->CP0_Cause & CP0Ca_IP_mask; 551741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli status = env->CP0_Status & CP0Ca_IP_mask; 552741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli 553741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli if (env->CP0_Config3 & (1 << CP0C3_VEIC)) { 554741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli /* A MIPS configured with a vectorizing external interrupt controller 555741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli will feed a vector into the Cause pending lines. The core treats 556741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli the status lines as a vector level, not as indiviual masks. */ 557741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli r = pending > status; 558741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli } else { 559741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli /* A MIPS configured with compatibility or VInt (Vectored Interrupts) 560741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli treats the pending lines as individual interrupt lines, the status 561741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli lines are individual masks. */ 562741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli r = pending & status; 563741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli } 564741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli return r; 565741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli} 566741dc13597ac064e6a48bb2a6ec069cbc1cd0dbbBhanu Chetlapalli 567852088c7e08182c2de563872d558309815cbfa0dDavid 'Digit' Turner#include "exec/cpu-all.h" 568852088c7e08182c2de563872d558309815cbfa0dDavid 'Digit' Turner#include "exec/exec-all.h" 569409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 570409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli/* Memory access type : 571409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli * may be needed for precise access rights control and precise exceptions. 572409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli */ 573409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallienum { 574409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli /* 1 bit to define user level / supervisor access */ 575409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli ACCESS_USER = 0x00, 576409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli ACCESS_SUPER = 0x01, 577409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli /* 1 bit to indicate direction */ 578409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli ACCESS_STORE = 0x02, 579409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli /* Type of instruction that generated the access */ 580409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli ACCESS_CODE = 0x10, /* Code fetch access */ 581409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli ACCESS_INT = 0x20, /* Integer load/store access */ 582409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli ACCESS_FLOAT = 0x30, /* floating point load/store access */ 583409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli}; 584409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 585409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli/* Exceptions */ 586409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallienum { 587409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_NONE = -1, 588409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_RESET = 0, 589409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_SRESET, 590409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_DSS, 591409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_DINT, 592409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_DDBL, 593409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_DDBS, 594409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_NMI, 595409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_MCHECK, 596409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_EXT_INTERRUPT, /* 8 */ 597409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_DFWATCH, 598409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_DIB, 599409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_IWATCH, 600409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_AdEL, 601409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_AdES, 602409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_TLBF, 603409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_IBE, 604409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_DBp, /* 16 */ 605409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_SYSCALL, 606409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_BREAK, 607409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_CpU, 608409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_RI, 609409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_OVERFLOW, 610409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_TRAP, 611409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_FPE, 612409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_DWATCH, /* 24 */ 613409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_LTLBL, 614409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_TLBL, 615409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_TLBS, 616409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_DBE, 617409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_THREAD, 618409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_MDMX, 619409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_C2E, 620409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_CACHE, /* 32 */ 621409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 622409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli EXCP_LAST = EXCP_CACHE, 623409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli}; 624409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli/* Dummy exception for conditional stores. */ 625409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define EXCP_SC 0x100 626409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 62726a8fb6421ab91cfdecdbee299e5e28918c4f0d4David 'Digit' Turner/* 62826a8fb6421ab91cfdecdbee299e5e28918c4f0d4David 'Digit' Turner * This is an interrnally generated WAKE request line. 62926a8fb6421ab91cfdecdbee299e5e28918c4f0d4David 'Digit' Turner * It is driven by the CPU itself. Raised when the MT 63026a8fb6421ab91cfdecdbee299e5e28918c4f0d4David 'Digit' Turner * block wants to wake a VPE from an inactive state and 63126a8fb6421ab91cfdecdbee299e5e28918c4f0d4David 'Digit' Turner * cleared when VPE goes from active to inactive. 63226a8fb6421ab91cfdecdbee299e5e28918c4f0d4David 'Digit' Turner */ 63326a8fb6421ab91cfdecdbee299e5e28918c4f0d4David 'Digit' Turner#define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0 63426a8fb6421ab91cfdecdbee299e5e28918c4f0d4David 'Digit' Turner 635409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalliint cpu_mips_exec(CPUMIPSState *s); 636409c7b66435cf5947cab6bf0710f92507317f22eBhanu ChetlapalliCPUMIPSState *cpu_mips_init(const char *cpu_model); 637409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli//~ uint32_t cpu_mips_get_clock (void); 638409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalliint cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc); 639409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 640409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli/* mips_timer.c */ 641e2678e116c8cdb0f36b247a5bd9cfacc849362fcDavid 'Digit' Turneruint32_t cpu_mips_get_random (CPUMIPSState *env); 642e2678e116c8cdb0f36b247a5bd9cfacc849362fcDavid 'Digit' Turneruint32_t cpu_mips_get_count (CPUMIPSState *env); 643e2678e116c8cdb0f36b247a5bd9cfacc849362fcDavid 'Digit' Turnervoid cpu_mips_store_count (CPUMIPSState *env, uint32_t value); 644e2678e116c8cdb0f36b247a5bd9cfacc849362fcDavid 'Digit' Turnervoid cpu_mips_store_compare (CPUMIPSState *env, uint32_t value); 645e2678e116c8cdb0f36b247a5bd9cfacc849362fcDavid 'Digit' Turnervoid cpu_mips_start_count(CPUMIPSState *env); 646e2678e116c8cdb0f36b247a5bd9cfacc849362fcDavid 'Digit' Turnervoid cpu_mips_stop_count(CPUMIPSState *env); 647409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 648409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli/* mips_int.c */ 649e2678e116c8cdb0f36b247a5bd9cfacc849362fcDavid 'Digit' Turnervoid cpu_mips_update_irq (CPUMIPSState *env); 650409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 651409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli/* helper.c */ 652e2678e116c8cdb0f36b247a5bd9cfacc849362fcDavid 'Digit' Turnerint cpu_mips_handle_mmu_fault (CPUMIPSState *env, target_ulong address, int rw, 6530d8b235c0c6c02de86a4e7415d574175b4518ff0David 'Digit' Turner int mmu_idx); 654409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define cpu_handle_mmu_fault cpu_mips_handle_mmu_fault 655e2678e116c8cdb0f36b247a5bd9cfacc849362fcDavid 'Digit' Turnervoid do_interrupt (CPUMIPSState *env); 656e2678e116c8cdb0f36b247a5bd9cfacc849362fcDavid 'Digit' Turnerhwaddr cpu_mips_translate_address (CPUMIPSState *env, target_ulong address, 657409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int rw); 658409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 659e2678e116c8cdb0f36b247a5bd9cfacc849362fcDavid 'Digit' Turnerstatic inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc, 660409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong *cs_base, int *flags) 661409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli{ 662409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli *pc = env->active_tc.PC; 663409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli *cs_base = 0; 664409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK); 665409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli} 666409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 667e2678e116c8cdb0f36b247a5bd9cfacc849362fcDavid 'Digit' Turnerstatic inline void cpu_set_tls(CPUMIPSState *env, target_ulong newtls) 668409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli{ 669409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli env->tls_value = newtls; 670409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli} 671409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 6726657678c3d86395084f6a699e73614195f06c445David 'Digit' Turnerstatic inline bool cpu_has_work(CPUState *cpu) 67393949dc9a6f5a702db214d19080397a9e94b45f6David 'Digit' Turner{ 67493949dc9a6f5a702db214d19080397a9e94b45f6David 'Digit' Turner int has_work = 0; 67593949dc9a6f5a702db214d19080397a9e94b45f6David 'Digit' Turner 67693949dc9a6f5a702db214d19080397a9e94b45f6David 'Digit' Turner /* It is implementation dependent if non-enabled interrupts 67793949dc9a6f5a702db214d19080397a9e94b45f6David 'Digit' Turner wake-up the CPU, however most of the implementations only 67893949dc9a6f5a702db214d19080397a9e94b45f6David 'Digit' Turner check for interrupts that can be taken. */ 6796657678c3d86395084f6a699e73614195f06c445David 'Digit' Turner if ((cpu->interrupt_request & CPU_INTERRUPT_HARD) && 6806657678c3d86395084f6a699e73614195f06c445David 'Digit' Turner cpu_mips_hw_interrupts_pending(cpu->env_ptr)) { 68193949dc9a6f5a702db214d19080397a9e94b45f6David 'Digit' Turner has_work = 1; 68293949dc9a6f5a702db214d19080397a9e94b45f6David 'Digit' Turner } 68393949dc9a6f5a702db214d19080397a9e94b45f6David 'Digit' Turner 6846657678c3d86395084f6a699e73614195f06c445David 'Digit' Turner if (cpu->interrupt_request & CPU_INTERRUPT_TIMER) { 68593949dc9a6f5a702db214d19080397a9e94b45f6David 'Digit' Turner has_work = 1; 68693949dc9a6f5a702db214d19080397a9e94b45f6David 'Digit' Turner } 68793949dc9a6f5a702db214d19080397a9e94b45f6David 'Digit' Turner 68893949dc9a6f5a702db214d19080397a9e94b45f6David 'Digit' Turner return has_work; 68993949dc9a6f5a702db214d19080397a9e94b45f6David 'Digit' Turner} 69093949dc9a6f5a702db214d19080397a9e94b45f6David 'Digit' Turner 69193949dc9a6f5a702db214d19080397a9e94b45f6David 'Digit' Turnerstatic inline void cpu_pc_from_tb(CPUMIPSState *env, TranslationBlock *tb) 69293949dc9a6f5a702db214d19080397a9e94b45f6David 'Digit' Turner{ 69393949dc9a6f5a702db214d19080397a9e94b45f6David 'Digit' Turner env->active_tc.PC = tb->pc; 69493949dc9a6f5a702db214d19080397a9e94b45f6David 'Digit' Turner env->hflags &= ~MIPS_HFLAG_BMASK; 69593949dc9a6f5a702db214d19080397a9e94b45f6David 'Digit' Turner env->hflags |= tb->flags & MIPS_HFLAG_BMASK; 69693949dc9a6f5a702db214d19080397a9e94b45f6David 'Digit' Turner} 69793949dc9a6f5a702db214d19080397a9e94b45f6David 'Digit' Turner 698409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#endif /* !defined (__MIPS_CPU_H__) */ 699