1409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli/* 2409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli * MIPS emulation for qemu: CPU initialisation routines. 3409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli * 4409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli * Copyright (c) 2004-2005 Jocelyn Mayer 5409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli * Copyright (c) 2007 Herve Poussineau 6409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli * 7409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli * This library is free software; you can redistribute it and/or 8409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli * modify it under the terms of the GNU Lesser General Public 9409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli * License as published by the Free Software Foundation; either 10409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli * version 2 of the License, or (at your option) any later version. 11409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli * 12409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli * This library is distributed in the hope that it will be useful, 13409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli * but WITHOUT ANY WARRANTY; without even the implied warranty of 14409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli * Lesser General Public License for more details. 16409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli * 17409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli * You should have received a copy of the GNU Lesser General Public 18409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli */ 20409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 21409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli/* CPU / CPU family specific config register values. */ 22409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 23409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli/* Have config1, uncached coherency */ 24409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define MIPS_CONFIG0 \ 25409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli ((1 << CP0C0_M) | (0x2 << CP0C0_K0)) 26409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 27409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli/* Have config2, no coprocessor2 attached, no MDMX support attached, 28409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli no performance counters, watch registers present, 29409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli no code compression, EJTAG present, no FPU */ 30409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define MIPS_CONFIG1 \ 31409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli((1 << CP0C1_M) | \ 32409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \ 33409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \ 34409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (0 << CP0C1_FP)) 35409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 36409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli/* Have config3, no tertiary/secondary caches implemented */ 37409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define MIPS_CONFIG2 \ 38409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli((1 << CP0C2_M)) 39409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 40409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli/* No config4, no DSP ASE, no large physaddr (PABITS), 41409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli no external interrupt controller, no vectored interupts, 42409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli no 1kb pages, no SmartMIPS ASE, no trace logic */ 43409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define MIPS_CONFIG3 \ 44409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \ 45409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \ 46409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (0 << CP0C3_SM) | (0 << CP0C3_TL)) 47409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 48409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli/* Define a implementation number of 1. 49409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli Define a major version 1, minor version 0. */ 50409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define MIPS_FCR0 ((0 << FCR0_S) | (0x1 << FCR0_PRID) | (0x10 << FCR0_REV)) 51409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 52409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli/* MMU types, the first four entries have the same layout as the 53409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli CP0C0_MT field. */ 54409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallienum mips_mmu_types { 55409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli MMU_TYPE_NONE, 56409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli MMU_TYPE_R4000, 57409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli MMU_TYPE_RESERVED, 58409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli MMU_TYPE_FMT, 59409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli MMU_TYPE_R3000, 60409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli MMU_TYPE_R6000, 61409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli MMU_TYPE_R8000 62409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli}; 63409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 64409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallistruct mips_def_t { 65409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli const char *name; 66409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_PRid; 67409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_Config0; 68409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_Config1; 69409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_Config2; 70409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_Config3; 71409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_Config6; 72409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_Config7; 73409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli target_ulong CP0_LLAddr_rw_bitmask; 74409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int CP0_LLAddr_shift; 75409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t SYNCI_Step; 76409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CCRes; 77409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_Status_rw_bitmask; 78409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_TCStatus_rw_bitmask; 79409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_SRSCtl; 80409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP1_fcr0; 81409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t SEGBITS; 82409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t PABITS; 83409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_SRSConf0_rw_bitmask; 84409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_SRSConf0; 85409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_SRSConf1_rw_bitmask; 86409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_SRSConf1; 87409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_SRSConf2_rw_bitmask; 88409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_SRSConf2; 89409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_SRSConf3_rw_bitmask; 90409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_SRSConf3; 91409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_SRSConf4_rw_bitmask; 92409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int32_t CP0_SRSConf4; 93409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int insn_flags; 94409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli enum mips_mmu_types mmu_type; 95409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli}; 96409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 97409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli/*****************************************************************************/ 98409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli/* MIPS CPU definitions */ 99409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallistatic const mips_def_t mips_defs[] = 100409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli{ 101409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli { 102409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .name = "4Kc", 103409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_PRid = 0x00018000, 104409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT), 105409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | 106409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | 107409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), 108409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Config2 = MIPS_CONFIG2, 109409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Config3 = MIPS_CONFIG3, 110409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_LLAddr_rw_bitmask = 0, 111409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_LLAddr_shift = 4, 112409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .SYNCI_Step = 32, 113409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CCRes = 2, 114409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Status_rw_bitmask = 0x1278FF17, 115409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .SEGBITS = 32, 116409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .PABITS = 32, 117409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .insn_flags = CPU_MIPS32 | ASE_MIPS16, 118409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .mmu_type = MMU_TYPE_R4000, 119409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli }, 120409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli { 121409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .name = "4Km", 122409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_PRid = 0x00018300, 123409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli /* Config1 implemented, fixed mapping MMU, 124409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli no virtual icache, uncached coherency. */ 125409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT), 126409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Config1 = MIPS_CONFIG1 | 127409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | 128409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), 129409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Config2 = MIPS_CONFIG2, 130409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Config3 = MIPS_CONFIG3, 131409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_LLAddr_rw_bitmask = 0, 132409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_LLAddr_shift = 4, 133409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .SYNCI_Step = 32, 134409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CCRes = 2, 135409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Status_rw_bitmask = 0x1258FF17, 136409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .SEGBITS = 32, 137409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .PABITS = 32, 138409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .insn_flags = CPU_MIPS32 | ASE_MIPS16, 139409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .mmu_type = MMU_TYPE_FMT, 140409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli }, 141409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli { 142409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .name = "4KEcR1", 143409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_PRid = 0x00018400, 144409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT), 145409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | 146409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | 147409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), 148409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Config2 = MIPS_CONFIG2, 149409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Config3 = MIPS_CONFIG3, 150409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_LLAddr_rw_bitmask = 0, 151409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_LLAddr_shift = 4, 152409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .SYNCI_Step = 32, 153409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CCRes = 2, 154409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Status_rw_bitmask = 0x1278FF17, 155409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .SEGBITS = 32, 156409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .PABITS = 32, 157409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .insn_flags = CPU_MIPS32 | ASE_MIPS16, 158409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .mmu_type = MMU_TYPE_R4000, 159409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli }, 160409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli { 161409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .name = "4KEmR1", 162409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_PRid = 0x00018500, 163409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT), 164409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Config1 = MIPS_CONFIG1 | 165409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | 166409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), 167409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Config2 = MIPS_CONFIG2, 168409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Config3 = MIPS_CONFIG3, 169409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_LLAddr_rw_bitmask = 0, 170409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_LLAddr_shift = 4, 171409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .SYNCI_Step = 32, 172409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CCRes = 2, 173409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Status_rw_bitmask = 0x1258FF17, 174409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .SEGBITS = 32, 175409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .PABITS = 32, 176409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .insn_flags = CPU_MIPS32 | ASE_MIPS16, 177409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .mmu_type = MMU_TYPE_FMT, 178409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli }, 179409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli { 180409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .name = "4KEc", 181409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_PRid = 0x00019000, 182409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | 183409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (MMU_TYPE_R4000 << CP0C0_MT), 184409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | 185409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | 186409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), 187409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Config2 = MIPS_CONFIG2, 188409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt), 189409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_LLAddr_rw_bitmask = 0, 190409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_LLAddr_shift = 4, 191409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .SYNCI_Step = 32, 192409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CCRes = 2, 193409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Status_rw_bitmask = 0x1278FF17, 194409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .SEGBITS = 32, 195409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .PABITS = 32, 196409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .insn_flags = CPU_MIPS32R2 | ASE_MIPS16, 197409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .mmu_type = MMU_TYPE_R4000, 198409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli }, 199409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli { 200409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .name = "4KEm", 201409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_PRid = 0x00019100, 202409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | 203409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (MMU_TYPE_FMT << CP0C0_MT), 204409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Config1 = MIPS_CONFIG1 | 205409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | 206409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), 207409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Config2 = MIPS_CONFIG2, 208409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Config3 = MIPS_CONFIG3, 209409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_LLAddr_rw_bitmask = 0, 210409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_LLAddr_shift = 4, 211409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .SYNCI_Step = 32, 212409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CCRes = 2, 213409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Status_rw_bitmask = 0x1258FF17, 214409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .SEGBITS = 32, 215409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .PABITS = 32, 216409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .insn_flags = CPU_MIPS32R2 | ASE_MIPS16, 217409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .mmu_type = MMU_TYPE_FMT, 218409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli }, 219409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli { 220409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .name = "24Kc", 221409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_PRid = 0x00019300, 222409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | 223409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (MMU_TYPE_R4000 << CP0C0_MT), 224409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | 225409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | 226409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), 227409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Config2 = MIPS_CONFIG2, 228409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt), 229409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_LLAddr_rw_bitmask = 0, 230409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_LLAddr_shift = 4, 231409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .SYNCI_Step = 32, 232409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CCRes = 2, 233409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli /* No DSP implemented. */ 234409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Status_rw_bitmask = 0x1278FF1F, 235409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .SEGBITS = 32, 236409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .PABITS = 32, 237409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .insn_flags = CPU_MIPS32R2 | ASE_MIPS16, 238409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .mmu_type = MMU_TYPE_R4000, 239409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli }, 240409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli { 241409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .name = "24Kf", 242409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_PRid = 0x00019300, 243409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | 244409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (MMU_TYPE_R4000 << CP0C0_MT), 245409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | 246409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | 247409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), 248409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Config2 = MIPS_CONFIG2, 249409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt), 250409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_LLAddr_rw_bitmask = 0, 251409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_LLAddr_shift = 4, 252409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .SYNCI_Step = 32, 253409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CCRes = 2, 254409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli /* No DSP implemented. */ 255409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Status_rw_bitmask = 0x3678FF1F, 256409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | 257409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID), 258409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .SEGBITS = 32, 259409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .PABITS = 32, 260409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .insn_flags = CPU_MIPS32R2 | ASE_MIPS16, 261409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .mmu_type = MMU_TYPE_R4000, 262409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli }, 263409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli { 264409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .name = "34Kf", 265409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_PRid = 0x00019500, 266409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | 267409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (MMU_TYPE_R4000 << CP0C0_MT), 268409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | 269409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | 270409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), 271409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Config2 = MIPS_CONFIG2, 272409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt) | (1 << CP0C3_MT), 273409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_LLAddr_rw_bitmask = 0, 274409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_LLAddr_shift = 0, 275409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .SYNCI_Step = 32, 276409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CCRes = 2, 277409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli /* No DSP implemented. */ 278409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Status_rw_bitmask = 0x3678FF1F, 279409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli /* No DSP implemented. */ 280409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) | 281409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) | 282409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) | 283409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (1 << CP0TCSt_DA) | (1 << CP0TCSt_A) | 284409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (0x3 << CP0TCSt_TKSU) | (1 << CP0TCSt_IXMT) | 285409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (0xff << CP0TCSt_TASID), 286409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | 287409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID), 288409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_SRSCtl = (0xf << CP0SRSCtl_HSS), 289409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_SRSConf0_rw_bitmask = 0x3fffffff, 290409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_SRSConf0 = (1 << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) | 291409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (0x3fe << CP0SRSC0_SRS2) | (0x3fe << CP0SRSC0_SRS1), 292409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_SRSConf1_rw_bitmask = 0x3fffffff, 293409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_SRSConf1 = (1 << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) | 294409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (0x3fe << CP0SRSC1_SRS5) | (0x3fe << CP0SRSC1_SRS4), 295409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_SRSConf2_rw_bitmask = 0x3fffffff, 296409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_SRSConf2 = (1 << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) | 297409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (0x3fe << CP0SRSC2_SRS8) | (0x3fe << CP0SRSC2_SRS7), 298409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_SRSConf3_rw_bitmask = 0x3fffffff, 299409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_SRSConf3 = (1 << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) | 300409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (0x3fe << CP0SRSC3_SRS11) | (0x3fe << CP0SRSC3_SRS10), 301409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_SRSConf4_rw_bitmask = 0x3fffffff, 302409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) | 303409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13), 304409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .SEGBITS = 32, 305409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .PABITS = 32, 306409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT, 307409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .mmu_type = MMU_TYPE_R4000, 308409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli }, 309409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#if defined(TARGET_MIPS64) 310409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli { 311409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .name = "R4000", 312409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_PRid = 0x00000400, 313409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */ 314409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0), 315409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli /* Note: Config1 is only used internally, the R4000 has only Config0. */ 316409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), 317409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_LLAddr_rw_bitmask = 0xFFFFFFFF, 318409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_LLAddr_shift = 4, 319409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .SYNCI_Step = 16, 320409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CCRes = 2, 321409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Status_rw_bitmask = 0x3678FFFF, 322409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli /* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */ 323409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV), 324409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .SEGBITS = 40, 325409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .PABITS = 36, 326409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .insn_flags = CPU_MIPS3, 327409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .mmu_type = MMU_TYPE_R4000, 328409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli }, 329409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli { 330409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .name = "VR5432", 331409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_PRid = 0x00005400, 332409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */ 333409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0), 334409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), 335409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_LLAddr_rw_bitmask = 0xFFFFFFFFL, 336409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_LLAddr_shift = 4, 337409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .SYNCI_Step = 16, 338409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CCRes = 2, 339409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Status_rw_bitmask = 0x3678FFFF, 340409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli /* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */ 341409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV), 342409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .SEGBITS = 40, 343409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .PABITS = 32, 344409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .insn_flags = CPU_VR54XX, 345409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .mmu_type = MMU_TYPE_R4000, 346409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli }, 347409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli { 348409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .name = "5Kc", 349409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_PRid = 0x00018100, 350409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) | 351409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (MMU_TYPE_R4000 << CP0C0_MT), 352409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) | 353409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) | 354409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) | 355409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), 356409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Config2 = MIPS_CONFIG2, 357409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Config3 = MIPS_CONFIG3, 358409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_LLAddr_rw_bitmask = 0, 359409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_LLAddr_shift = 4, 360409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .SYNCI_Step = 32, 361409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CCRes = 2, 362409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Status_rw_bitmask = 0x32F8FFFF, 363409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .SEGBITS = 42, 364409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .PABITS = 36, 365409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .insn_flags = CPU_MIPS64, 366409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .mmu_type = MMU_TYPE_R4000, 367409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli }, 368409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli { 369409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .name = "5Kf", 370409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_PRid = 0x00018100, 371409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) | 372409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (MMU_TYPE_R4000 << CP0C0_MT), 373409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) | 374409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) | 375409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) | 376409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), 377409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Config2 = MIPS_CONFIG2, 378409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Config3 = MIPS_CONFIG3, 379409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_LLAddr_rw_bitmask = 0, 380409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_LLAddr_shift = 4, 381409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .SYNCI_Step = 32, 382409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CCRes = 2, 383409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Status_rw_bitmask = 0x36F8FFFF, 384409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli /* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */ 385409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) | 386409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (0x81 << FCR0_PRID) | (0x0 << FCR0_REV), 387409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .SEGBITS = 42, 388409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .PABITS = 36, 389409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .insn_flags = CPU_MIPS64, 390409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .mmu_type = MMU_TYPE_R4000, 391409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli }, 392409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli { 393409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .name = "20Kc", 394409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli /* We emulate a later version of the 20Kc, earlier ones had a broken 395409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli WAIT instruction. */ 396409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_PRid = 0x000182a0, 397409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) | 398409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (MMU_TYPE_R4000 << CP0C0_MT) | (1 << CP0C0_VI), 399409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) | 400409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | 401409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | 402409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), 403409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Config2 = MIPS_CONFIG2, 404409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Config3 = MIPS_CONFIG3, 405409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_LLAddr_rw_bitmask = 0, 406409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_LLAddr_shift = 0, 407409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .SYNCI_Step = 32, 408409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CCRes = 1, 409409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Status_rw_bitmask = 0x36FBFFFF, 410409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli /* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */ 411409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) | 412409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (1 << FCR0_D) | (1 << FCR0_S) | 413409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (0x82 << FCR0_PRID) | (0x0 << FCR0_REV), 414409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .SEGBITS = 40, 415409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .PABITS = 36, 416409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .insn_flags = CPU_MIPS64 | ASE_MIPS3D, 417409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .mmu_type = MMU_TYPE_R4000, 418409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli }, 419409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli { 420409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli /* A generic CPU providing MIPS64 Release 2 features. 421409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli FIXME: Eventually this should be replaced by a real CPU model. */ 422409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .name = "MIPS64R2-generic", 423409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_PRid = 0x00010000, 424409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | 425409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (MMU_TYPE_R4000 << CP0C0_MT), 426409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) | 427409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | 428409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | 429409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), 430409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Config2 = MIPS_CONFIG2, 431409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA), 432409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_LLAddr_rw_bitmask = 0, 433409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_LLAddr_shift = 0, 434409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .SYNCI_Step = 32, 435409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CCRes = 2, 436409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP0_Status_rw_bitmask = 0x36FBFFFF, 437409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) | 438409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | 439409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), 440409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .SEGBITS = 42, 441409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli /* The architectural limit is 59, but we have hardcoded 36 bit 442409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli in some places... 443409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .PABITS = 59, */ /* the architectural limit */ 444409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .PABITS = 36, 445409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D, 446409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli .mmu_type = MMU_TYPE_R4000, 447409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli }, 448409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#endif 449409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli}; 450409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 451409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallistatic const mips_def_t *cpu_mips_find_by_name (const char *name) 452409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli{ 453409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int i; 454409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 455409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli for (i = 0; i < ARRAY_SIZE(mips_defs); i++) { 456409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli if (strcasecmp(name, mips_defs[i].name) == 0) { 457409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli return &mips_defs[i]; 458409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli } 459409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli } 460409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli return NULL; 461409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli} 462409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 463409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallivoid mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) 464409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli{ 465409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int i; 466409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 467409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli for (i = 0; i < ARRAY_SIZE(mips_defs); i++) { 468409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (*cpu_fprintf)(f, "MIPS '%s'\n", 469409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli mips_defs[i].name); 470409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli } 471409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli} 472409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 473409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#ifndef CONFIG_USER_ONLY 474409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallistatic void no_mmu_init (CPUMIPSState *env, const mips_def_t *def) 475409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli{ 476409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli env->tlb->nb_tlb = 1; 477409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli env->tlb->map_address = &no_mmu_map_address; 478409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli} 479409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 480409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallistatic void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def) 481409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli{ 482409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli env->tlb->nb_tlb = 1; 483409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli env->tlb->map_address = &fixed_mmu_map_address; 484409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli} 485409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 486409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallistatic void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def) 487409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli{ 488409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63); 489409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli env->tlb->map_address = &r4k_map_address; 490409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli env->tlb->helper_tlbwi = r4k_helper_tlbwi; 491409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli env->tlb->helper_tlbwr = r4k_helper_tlbwr; 492409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli env->tlb->helper_tlbp = r4k_helper_tlbp; 493409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli env->tlb->helper_tlbr = r4k_helper_tlbr; 494409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli} 495409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 496409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallistatic void mmu_init (CPUMIPSState *env, const mips_def_t *def) 497409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli{ 498aa8236dc1b1ea300ab18716db5b8fab42aca3ca7David 'Digit' Turner env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext)); 499409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 500409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli switch (def->mmu_type) { 501409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli case MMU_TYPE_NONE: 502409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli no_mmu_init(env, def); 503409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli break; 504409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli case MMU_TYPE_R4000: 505409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli r4k_mmu_init(env, def); 506409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli break; 507409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli case MMU_TYPE_FMT: 508409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli fixed_mmu_init(env, def); 509409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli break; 510409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli case MMU_TYPE_R3000: 511409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli case MMU_TYPE_R6000: 512409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli case MMU_TYPE_R8000: 513409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli default: 514409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli cpu_abort(env, "MMU type not supported\n"); 515409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli } 516409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli} 517409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#endif /* CONFIG_USER_ONLY */ 518409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 519409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallistatic void fpu_init (CPUMIPSState *env, const mips_def_t *def) 520409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli{ 521409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli int i; 522409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 523409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli for (i = 0; i < MIPS_FPU_MAX; i++) 524409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli env->fpus[i].fcr0 = def->CP1_fcr0; 525409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 526409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli memcpy(&env->active_fpu, &env->fpus[0], sizeof(env->active_fpu)); 527409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli} 528409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 529409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapallistatic void mvp_init (CPUMIPSState *env, const mips_def_t *def) 530409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli{ 531aa8236dc1b1ea300ab18716db5b8fab42aca3ca7David 'Digit' Turner env->mvp = g_malloc0(sizeof(CPUMIPSMVPContext)); 532409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 533409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli /* MVPConf1 implemented, TLB sharable, no gating storage support, 534409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli programmable cache partitioning implemented, number of allocatable 535409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli and sharable TLB entries, MVP has allocatable TCs, 2 VPEs 536409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli implemented, 5 TCs implemented. */ 537409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli env->mvp->CP0_MVPConf0 = (1 << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) | 538409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) | 539409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli// TODO: actually do 2 VPEs. 540409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli// (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) | 541409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli// (0x04 << CP0MVPC0_PTC); 542409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) | 543409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (0x04 << CP0MVPC0_PTC); 544409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#if !defined(CONFIG_USER_ONLY) 545409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli /* Usermode has no TLB support */ 546409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli env->mvp->CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE); 547409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#endif 548409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 549409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli /* Allocatable CP1 have media extensions, allocatable CP1 have FP support, 550409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli no UDI implemented, no CP2 implemented, 1 CP1 implemented. */ 551409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli env->mvp->CP0_MVPConf1 = (1 << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) | 552409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) | 553409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli (0x1 << CP0MVPC1_PCP1); 554409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli} 555