basic_op.h revision 813eebeb773b1e4c42c2063a7fe37a94514e596a
1/* 2 ** Copyright 2003-2010, VisualOn, Inc. 3 ** 4 ** Licensed under the Apache License, Version 2.0 (the "License"); 5 ** you may not use this file except in compliance with the License. 6 ** You may obtain a copy of the License at 7 ** 8 ** http://www.apache.org/licenses/LICENSE-2.0 9 ** 10 ** Unless required by applicable law or agreed to in writing, software 11 ** distributed under the License is distributed on an "AS IS" BASIS, 12 ** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 ** See the License for the specific language governing permissions and 14 ** limitations under the License. 15 */ 16/******************************************************************************* 17 File: basicop2.h 18 19 Content: Constants , Globals and Basic arithmetic operators. 20 21*******************************************************************************/ 22 23#ifndef __BASIC_OP_H 24#define __BASIC_OP_H 25 26#include "typedef.h" 27 28#define MAX_32 (Word32)0x7fffffffL 29#define MIN_32 (Word32)0x80000000L 30 31#define MAX_16 (Word16)0x7fff 32#define MIN_16 (Word16)0x8000 33#define ABS(a) ((a) >= 0) ? (a) : (-(a)) 34 35/* Short abs, 1 */ 36#define abs_s(x) ((Word16)(((x) != MIN_16) ? (((x) >= 0) ? (x) : (-(x))) : MAX_16)) 37 38/* 16 bit var1 -> MSB, 2 */ 39#define L_deposit_h(x) (((Word32)(x)) << 16) 40 41 42/* 16 bit var1 -> LSB, 2 */ 43#define L_deposit_l(x) ((Word32)(x)) 44 45 46/* Long abs, 3 */ 47#define L_abs(x) (((x) != MIN_32) ? (((x) >= 0) ? (x) : (-(x))) : MAX_32) 48 49 50/* Short negate, 1 */ 51#define negate(var1) ((Word16)(((var1) == MIN_16) ? MAX_16 : (-(var1)))) 52 53 54/* Long negate, 2 */ 55#define L_negate(L_var1) (((L_var1) == (MIN_32)) ? (MAX_32) : (-(L_var1))) 56 57 58#define MULHIGH(A,B) (int)(((Word64)(A)*(Word64)(B)) >> 32) 59#define fixmul(a, b) (int)((((Word64)(a)*(Word64)(b)) >> 32) << 1) 60 61 62#if (SATRUATE_IS_INLINE) 63__inline Word16 saturate(Word32 L_var1); 64#else 65Word16 saturate(Word32 L_var1); 66#endif 67 68/* Short shift left, 1 */ 69#if (SHL_IS_INLINE) 70__inline Word16 shl (Word16 var1, Word16 var2); 71#else 72Word16 shl (Word16 var1, Word16 var2); 73#endif 74 75/* Short shift right, 1 */ 76#if (SHR_IS_INLINE) 77__inline Word16 shr (Word16 var1, Word16 var2); 78#else 79Word16 shr (Word16 var1, Word16 var2); 80#endif 81 82#if (L_MULT_IS_INLINE) 83__inline Word32 L_mult(Word16 var1, Word16 var2); 84#else 85Word32 L_mult(Word16 var1, Word16 var2); 86#endif 87 88/* Msu, 1 */ 89#if (L_MSU_IS_INLINE) 90__inline Word32 L_msu (Word32 L_var3, Word16 var1, Word16 var2); 91#else 92Word32 L_msu (Word32 L_var3, Word16 var1, Word16 var2); 93#endif 94 95/* Long sub, 2 */ 96#if (L_SUB_IS_INLINE) 97__inline Word32 L_sub(Word32 L_var1, Word32 L_var2); 98#else 99Word32 L_sub(Word32 L_var1, Word32 L_var2); 100#endif 101 102/* Long shift left, 2 */ 103#if (L_SHL_IS_INLINE) 104__inline Word32 L_shl (Word32 L_var1, Word16 var2); 105#else 106Word32 L_shl (Word32 L_var1, Word16 var2); 107#endif 108 109/* Long shift right, 2*/ 110#if (L_SHR_IS_INLINE) 111__inline Word32 L_shr (Word32 L_var1, Word16 var2); 112#else 113Word32 L_shr (Word32 L_var1, Word16 var2); 114#endif 115 116/* Short add, 1 */ 117#if (ADD_IS_INLINE) 118__inline Word16 add (Word16 var1, Word16 var2); 119#else 120Word16 add (Word16 var1, Word16 var2); 121#endif 122 123/* Short sub, 1 */ 124#if (SUB_IS_INLINE) 125__inline Word16 sub(Word16 var1, Word16 var2); 126#else 127Word16 sub(Word16 var1, Word16 var2); 128#endif 129 130/* Short division, 18 */ 131#if (DIV_S_IS_INLINE) 132__inline Word16 div_s (Word16 var1, Word16 var2); 133#else 134Word16 div_s (Word16 var1, Word16 var2); 135#endif 136 137/* Short mult, 1 */ 138#if (MULT_IS_INLINE) 139__inline Word16 mult (Word16 var1, Word16 var2); 140#else 141Word16 mult (Word16 var1, Word16 var2); 142#endif 143 144/* Short norm, 15 */ 145#if (NORM_S_IS_INLINE) 146__inline Word16 norm_s (Word16 var1); 147#else 148Word16 norm_s (Word16 var1); 149#endif 150 151/* Long norm, 30 */ 152#if (NORM_L_IS_INLINE) 153__inline Word16 norm_l (Word32 L_var1); 154#else 155Word16 norm_l (Word32 L_var1); 156#endif 157 158/* Round, 1 */ 159#if (ROUND_IS_INLINE) 160__inline Word16 round16(Word32 L_var1); 161#else 162Word16 round16(Word32 L_var1); 163#endif 164 165/* Mac, 1 */ 166#if (L_MAC_IS_INLINE) 167__inline Word32 L_mac (Word32 L_var3, Word16 var1, Word16 var2); 168#else 169Word32 L_mac (Word32 L_var3, Word16 var1, Word16 var2); 170#endif 171 172#if (L_ADD_IS_INLINE) 173__inline Word32 L_add (Word32 L_var1, Word32 L_var2); 174#else 175Word32 L_add (Word32 L_var1, Word32 L_var2); 176#endif 177 178/* Extract high, 1 */ 179#if (EXTRACT_H_IS_INLINE) 180__inline Word16 extract_h (Word32 L_var1); 181#else 182Word16 extract_h (Word32 L_var1); 183#endif 184 185/* Extract low, 1 */ 186#if (EXTRACT_L_IS_INLINE) 187__inline Word16 extract_l(Word32 L_var1); 188#else 189Word16 extract_l(Word32 L_var1); 190#endif 191 192/* Mult with round, 2 */ 193#if (MULT_R_IS_INLINE) 194__inline Word16 mult_r(Word16 var1, Word16 var2); 195#else 196Word16 mult_r(Word16 var1, Word16 var2); 197#endif 198 199/* Shift right with round, 2 */ 200#if (SHR_R_IS_INLINE) 201__inline Word16 shr_r (Word16 var1, Word16 var2); 202#else 203Word16 shr_r (Word16 var1, Word16 var2); 204#endif 205 206/* Mac with rounding,2 */ 207#if (MAC_R_IS_INLINE) 208__inline Word16 mac_r (Word32 L_var3, Word16 var1, Word16 var2); 209#else 210Word16 mac_r (Word32 L_var3, Word16 var1, Word16 var2); 211#endif 212 213/* Msu with rounding,2 */ 214#if (MSU_R_IS_INLINE) 215__inline Word16 msu_r (Word32 L_var3, Word16 var1, Word16 var2); 216#else 217Word16 msu_r (Word32 L_var3, Word16 var1, Word16 var2); 218#endif 219 220/* Long shift right with round, 3 */ 221#if (L_SHR_R_IS_INLINE) 222__inline Word32 L_shr_r (Word32 L_var1, Word16 var2); 223#else 224Word32 L_shr_r (Word32 L_var1, Word16 var2); 225#endif 226 227#if ARMV4_INASM 228__inline Word32 ASM_L_shr(Word32 L_var1, Word16 var2) 229{ 230 Word32 result; 231 asm ( 232 "MOV %[result], %[L_var1], ASR %[var2] \n" 233 :[result]"=r"(result) 234 :[L_var1]"r"(L_var1), [var2]"r"(var2) 235 ); 236 return result; 237} 238 239__inline Word32 ASM_L_shl(Word32 L_var1, Word16 var2) 240{ 241 Word32 result; 242 asm ( 243 "MOV %[result], %[L_var1], ASL %[var2] \n" 244 "TEQ %[L_var1], %[result], ASR %[var2]\n" 245 "EORNE %[result], %[mask], %[L_var1], ASR #31\n" 246 :[result]"=&r"(result) 247 :[L_var1]"r"(L_var1), [var2]"r"(var2), [mask]"r"(0x7fffffff) 248 ); 249 return result; 250} 251 252__inline Word32 ASM_shr(Word32 L_var1, Word16 var2) 253{ 254 Word32 result; 255 asm ( 256 "CMP %[var2], #15\n" 257 "MOVLT %[result], %[L_var1], ASR %[var2]\n" 258 "MOVGE %[result], %[L_var1], ASR #15\n" 259 :[result]"=r"(result) 260 :[L_var1]"r"(L_var1), [var2]"r"(var2) 261 ); 262 return result; 263} 264 265__inline Word32 ASM_shl(Word32 L_var1, Word16 var2) 266{ 267#if ARMV6_SAT 268 Word32 result; 269 asm ( 270 "CMP %[var2], #16\n" 271 "MOVLT %[result], %[L_var1], ASL %[var2]\n" 272 "MOVGE %[result], %[L_var1], ASL #16\n" 273 "SSAT %[result], #16, %[result]\n" 274 :[result]"=r"(result) 275 :[L_var1]"r"(L_var1), [var2]"r"(var2) 276 ); 277 return result; 278#else 279 Word32 result; 280 Word32 tmp; 281 asm ( 282 "CMP %[var2], #16\n" 283 "MOVLT %[result], %[L_var1], ASL %[var2]\n" 284 "MOVGE %[result], %[L_var1], ASL #16\n" 285 "MOV %[tmp], %[result], ASR #15\n" 286 "TEQ %[tmp], %[result], ASR #31 \n" 287 "EORNE %[result], %[mask], %[result],ASR #31" 288 :[result]"=&r"(result), [tmp]"=&r"(tmp) 289 :[L_var1]"r"(L_var1), [var2]"r"(var2), [mask]"r"(0x7fff) 290 ); 291 return result; 292#endif 293} 294#endif 295 296/*___________________________________________________________________________ 297 | | 298 | definitions for inline basic arithmetic operators | 299 |___________________________________________________________________________| 300*/ 301#if (SATRUATE_IS_INLINE) 302__inline Word16 saturate(Word32 L_var1) 303{ 304#if ARMV6_SAT 305 Word16 result; 306 asm ( 307 "SSAT %[result], #16, %[L_var1]" 308 : [result]"=r"(result) 309 : [L_var1]"r"(L_var1) 310 ); 311 return result; 312#elif ARMV5TE_SAT 313 Word16 result; 314 Word32 tmp; 315 asm volatile ( 316 "MOV %[tmp], %[L_var1],ASR#15\n" 317 "TEQ %[tmp], %[L_var1],ASR#31\n" 318 "EORNE %[result], %[mask],%[L_var1],ASR#31\n" 319 "MOVEQ %[result], %[L_var1]\n" 320 :[result]"=&r"(result), [tmp]"=&r"(tmp) 321 :[L_var1]"r"(L_var1), [mask]"r"(0x7fff) 322 ); 323 324 return result; 325#else 326 Word16 var_out; 327 328 //var_out = (L_var1 > (Word32)0X00007fffL) ? (MAX_16) : ((L_var1 < (Word32)0xffff8000L) ? (MIN_16) : ((Word16)L_var1)); 329 330 if (L_var1 > 0X00007fffL) 331 { 332 var_out = MAX_16; 333 } 334 else if (L_var1 < (Word32) 0xffff8000L) 335 { 336 var_out = MIN_16; 337 } 338 else 339 { 340 var_out = extract_l(L_var1); 341 } 342 343 return (var_out); 344#endif 345} 346#endif 347 348/* Short shift left, 1 */ 349#if (SHL_IS_INLINE) 350__inline Word16 shl (Word16 var1, Word16 var2) 351{ 352#if ARMV5TE_SHL 353 if(var2>=0) 354 { 355 return ASM_shl( var1, var2); 356 } 357 else 358 { 359 return ASM_shr( var1, -var2); 360 } 361#else 362 Word16 var_out; 363 Word32 result; 364 365 if (var2 < 0) 366 { 367 var_out = shr (var1, (Word16)-var2); 368 } 369 else 370 { 371 result = (Word32) var1 *((Word32) 1 << var2); 372 373 if ((var2 > 15 && var1 != 0) || (result != (Word32) ((Word16) result))) 374 { 375 var_out = (Word16)((var1 > 0) ? MAX_16 : MIN_16); 376 } 377 else 378 { 379 var_out = extract_l(result); 380 } 381 } 382 return (var_out); 383#endif 384} 385#endif 386 387/* Short shift right, 1 */ 388#if (SHR_IS_INLINE) 389__inline Word16 shr (Word16 var1, Word16 var2) 390{ 391#if ARMV5TE_SHR 392 if(var2>=0) 393 { 394 return ASM_shr( var1, var2); 395 } 396 else 397 { 398 return ASM_shl( var1, -var2); 399 } 400#else 401 Word16 var_out; 402 403 if (var2 < 0) 404 { 405 var_out = shl (var1, (Word16)-var2); 406 } 407 else 408 { 409 if (var2 >= 15) 410 { 411 var_out = (Word16)((var1 < 0) ? -1 : 0); 412 } 413 else 414 { 415 if (var1 < 0) 416 { 417 var_out = (Word16)(~((~var1) >> var2)); 418 } 419 else 420 { 421 var_out = (Word16)(var1 >> var2); 422 } 423 } 424 } 425 426 return (var_out); 427#endif 428} 429#endif 430 431 432#if (L_MULT_IS_INLINE) 433__inline Word32 L_mult(Word16 var1, Word16 var2) 434{ 435#if ARMV5TE_L_MULT 436 Word32 result; 437 asm ( 438 "SMULBB %[result], %[var1], %[var2] \n" 439 "QADD %[result], %[result], %[result] \n" 440 :[result]"=r"(result) 441 :[var1]"r"(var1), [var2]"r"(var2) 442 ); 443 return result; 444#else 445 Word32 L_var_out; 446 447 L_var_out = (Word32) var1 *(Word32) var2; 448 449 if (L_var_out != (Word32) 0x40000000L) 450 { 451 L_var_out <<= 1; 452 } 453 else 454 { 455 L_var_out = MAX_32; 456 } 457 return (L_var_out); 458#endif 459} 460#endif 461 462#if (L_MSU_IS_INLINE) 463__inline Word32 L_msu (Word32 L_var3, Word16 var1, Word16 var2) 464{ 465#if ARMV5TE_L_MSU 466 Word32 result; 467 asm ( 468 "SMULBB %[result], %[var1], %[var2] \n" 469 "QADD %[result], %[result], %[result] \n" 470 "QSUB %[result], %[L_var3], %[result]\n" 471 :[result]"=&r"(result) 472 :[L_var3]"r"(L_var3), [var1]"r"(var1), [var2]"r"(var2) 473 ); 474 return result; 475#else 476 Word32 L_var_out; 477 Word32 L_product; 478 479 L_product = L_mult(var1, var2); 480 L_var_out = L_sub(L_var3, L_product); 481 return (L_var_out); 482#endif 483} 484#endif 485 486#if (L_SUB_IS_INLINE) 487__inline Word32 L_sub(Word32 L_var1, Word32 L_var2) 488{ 489#if ARMV5TE_L_SUB 490 Word32 result; 491 asm ( 492 "QSUB %[result], %[L_var1], %[L_var2]\n" 493 :[result]"=r"(result) 494 :[L_var1]"r"(L_var1), [L_var2]"r"(L_var2) 495 ); 496 return result; 497#else 498 Word32 L_var_out; 499 500 L_var_out = L_var1 - L_var2; 501 502 if (((L_var1 ^ L_var2) & MIN_32) != 0) 503 { 504 if ((L_var_out ^ L_var1) & MIN_32) 505 { 506 L_var_out = (L_var1 < 0L) ? MIN_32 : MAX_32; 507 } 508 } 509 510 return (L_var_out); 511#endif 512} 513#endif 514 515#if (L_SHL_IS_INLINE) 516__inline Word32 L_shl(Word32 L_var1, Word16 var2) 517{ 518#if ARMV5TE_L_SHL 519 if(var2>=0) 520 { 521 return ASM_L_shl( L_var1, var2); 522 } 523 else 524 { 525 return ASM_L_shr( L_var1, -var2); 526 } 527#else 528 Word32 L_var_out = 0L; 529 530 if (var2 <= 0) 531 { 532 L_var1 = L_shr(L_var1, (Word16)-var2); 533 } 534 else 535 { 536 for (; var2 > 0; var2--) 537 { 538 if (L_var1 > (Word32) 0X3fffffffL) 539 { 540 return MAX_32; 541 } 542 else 543 { 544 if (L_var1 < (Word32) 0xc0000000L) 545 { 546 return MIN_32; 547 } 548 } 549 L_var1 <<= 1; 550 L_var_out = L_var1; 551 } 552 } 553 return (L_var1); 554#endif 555} 556#endif 557 558#if (L_SHR_IS_INLINE) 559__inline Word32 L_shr (Word32 L_var1, Word16 var2) 560{ 561#if ARMV5TE_L_SHR 562 if(var2>=0) 563 { 564 return ASM_L_shr( L_var1, var2); 565 } 566 else 567 { 568 return ASM_L_shl( L_var1, -var2); 569 } 570#else 571 Word32 L_var_out; 572 573 if (var2 < 0) 574 { 575 L_var_out = L_shl (L_var1, (Word16)-var2); 576 } 577 else 578 { 579 if (var2 >= 31) 580 { 581 L_var_out = (L_var1 < 0L) ? -1 : 0; 582 } 583 else 584 { 585 if (L_var1 < 0) 586 { 587 L_var_out = ~((~L_var1) >> var2); 588 } 589 else 590 { 591 L_var_out = L_var1 >> var2; 592 } 593 } 594 } 595 return (L_var_out); 596#endif 597} 598#endif 599 600/* Short add, 1 */ 601#if (ADD_IS_INLINE) 602__inline Word16 add (Word16 var1, Word16 var2) 603{ 604#if ARMV5TE_ADD 605 Word32 result; 606 Word32 tmp; 607 asm ( 608 "ADD %[result], %[var1], %[var2] \n" 609 "MOV %[tmp], %[result], ASR #15 \n" 610 "TEQ %[tmp], %[result], ASR #31 \n" 611 "EORNE %[result], %[mask], %[result], ASR #31" 612 :[result]"=&r"(result), [tmp]"=&r"(tmp) 613 :[var1]"r"(var1), [var2]"r"(var2), [mask]"r"(0x7fff) 614 ); 615 return result; 616#else 617 Word16 var_out; 618 Word32 L_sum; 619 620 L_sum = (Word32) var1 + var2; 621 var_out = saturate(L_sum); 622 623 return (var_out); 624#endif 625} 626#endif 627 628/* Short sub, 1 */ 629#if (SUB_IS_INLINE) 630__inline Word16 sub(Word16 var1, Word16 var2) 631{ 632#if ARMV5TE_SUB 633 Word32 result; 634 Word32 tmp; 635 asm ( 636 "SUB %[result], %[var1], %[var2] \n" 637 "MOV %[tmp], %[var1], ASR #15 \n" 638 "TEQ %[tmp], %[var1], ASR #31 \n" 639 "EORNE %[result], %[mask], %[result], ASR #31 \n" 640 :[result]"=&r"(result), [tmp]"=&r"(tmp) 641 :[var1]"r"(var1), [var2]"r"(var2), [mask]"r"(0x7fff) 642 ); 643 return result; 644#else 645 Word16 var_out; 646 Word32 L_diff; 647 648 L_diff = (Word32) var1 - var2; 649 var_out = saturate(L_diff); 650 651 return (var_out); 652#endif 653} 654#endif 655 656/* Short division, 18 */ 657#if (DIV_S_IS_INLINE) 658__inline Word16 div_s (Word16 var1, Word16 var2) 659{ 660 Word16 var_out = 0; 661 Word16 iteration; 662 Word32 L_num; 663 Word32 L_denom; 664 665 var_out = MAX_16; 666 if (var1!= var2)//var1!= var2 667 { 668 var_out = 0; 669 L_num = (Word32) var1; 670 671 L_denom = (Word32) var2; 672 673 //return (L_num<<15)/var2; 674 675 for (iteration = 0; iteration < 15; iteration++) 676 { 677 var_out <<= 1; 678 L_num <<= 1; 679 680 if (L_num >= L_denom) 681 { 682 L_num -= L_denom; 683 var_out++; 684 } 685 } 686 } 687 return (var_out); 688} 689#endif 690 691/* Short mult, 1 */ 692#if (MULT_IS_INLINE) 693__inline Word16 mult (Word16 var1, Word16 var2) 694{ 695#if ARMV5TE_MULT && ARMV6_SAT 696 Word32 result; 697 asm ( 698 "SMULBB %[result], %[var1], %[var2] \n" 699 "SSAT %[result], #16, %[result], ASR #15 \n" 700 :[result]"=r"(result) 701 :[var1]"r"(var1), [var2]"r"(var2) 702 ); 703 return result; 704#elif ARMV5TE_MULT 705 Word32 result, tmp; 706 asm ( 707 "SMULBB %[tmp], %[var1], %[var2] \n" 708 "MOV %[result], %[tmp], ASR #15\n" 709 "MOV %[tmp], %[result], ASR #15\n" 710 "TEQ %[tmp], %[result], ASR #31\n" 711 "EORNE %[result], %[mask], %[result], ASR #31 \n" 712 :[result]"=&r"(result), [tmp]"=&r"(tmp) 713 :[var1]"r"(var1), [var2]"r"(var2), [mask]"r"(0x7fff) 714 ); 715 return result; 716#else 717 Word16 var_out; 718 Word32 L_product; 719 720 L_product = (Word32) var1 *(Word32) var2; 721 L_product = (L_product & (Word32) 0xffff8000L) >> 15; 722 if (L_product & (Word32) 0x00010000L) 723 L_product = L_product | (Word32) 0xffff0000L; 724 var_out = saturate(L_product); 725 726 return (var_out); 727#endif 728} 729#endif 730 731 732/* Short norm, 15 */ 733#if (NORM_S_IS_INLINE) 734__inline Word16 norm_s (Word16 var1) 735{ 736#if ARMV5TE_NORM_S 737 Word16 result; 738 Word32 tmp; 739 asm ( 740 "RSBS %[tmp], %[var1], #0 \n" 741 "CLZLT %[result], %[var1]\n" 742 "CLZGT %[result], %[tmp]\n" 743 "SUBNE %[result], %[result], #17\n" 744 "MOVEQ %[result], #0\n" 745 "CMP %[var1], #-1\n" 746 "MOVEQ %[result], #15\n" 747 :[result]"=&r"(result), [tmp]"=&r"(tmp) 748 :[var1]"r"(var1) 749 ); 750 return result; 751#else 752 Word16 var_out; 753 754 if (var1 == 0) 755 { 756 var_out = 0; 757 } 758 else 759 { 760 if (var1 == -1) 761 { 762 var_out = 15; 763 } 764 else 765 { 766 if (var1 < 0) 767 { 768 var1 = (Word16)~var1; 769 } 770 for (var_out = 0; var1 < 0x4000; var_out++) 771 { 772 var1 <<= 1; 773 } 774 } 775 } 776 return (var_out); 777#endif 778} 779#endif 780 781/* Long norm, 30 */ 782#if (NORM_L_IS_INLINE) 783__inline Word16 norm_l (Word32 L_var1) 784{ 785#if ARMV5TE_NORM_L 786 Word16 result; 787 asm volatile( 788 "CMP %[L_var1], #0\n" 789 "CLZNE %[result], %[L_var1]\n" 790 "SUBNE %[result], %[result], #1\n" 791 "MOVEQ %[result], #0\n" 792 :[result]"=r"(result) 793 :[L_var1]"r"(L_var1) 794 ); 795 return result; 796#else 797 //Word16 var_out; 798 799 //if (L_var1 == 0) 800 //{ 801 // var_out = 0; 802 //} 803 //else 804 //{ 805 // if (L_var1 == (Word32) 0xffffffffL) 806 // { 807 // var_out = 31; 808 // } 809 // else 810 // { 811 // if (L_var1 < 0) 812 // { 813 // L_var1 = ~L_var1; 814 // } 815 // for (var_out = 0; L_var1 < (Word32) 0x40000000L; var_out++) 816 // { 817 // L_var1 <<= 1; 818 // } 819 // } 820 //} 821 //return (var_out); 822 Word16 a16; 823 Word16 r = 0 ; 824 825 826 if ( L_var1 < 0 ) { 827 L_var1 = ~L_var1; 828 } 829 830 if (0 == (L_var1 & 0x7fff8000)) { 831 a16 = extract_l(L_var1); 832 r += 16; 833 834 if (0 == (a16 & 0x7f80)) { 835 r += 8; 836 837 if (0 == (a16 & 0x0078)) { 838 r += 4; 839 840 if (0 == (a16 & 0x0006)) { 841 r += 2; 842 843 if (0 == (a16 & 0x0001)) { 844 r += 1; 845 } 846 } 847 else { 848 849 if (0 == (a16 & 0x0004)) { 850 r += 1; 851 } 852 } 853 } 854 else { 855 856 if (0 == (a16 & 0x0060)) { 857 r += 2; 858 859 if (0 == (a16 & 0x0010)) { 860 r += 1; 861 } 862 } 863 else { 864 865 if (0 == (a16 & 0x0040)) { 866 r += 1; 867 } 868 } 869 } 870 } 871 else { 872 873 if (0 == (a16 & 0x7800)) { 874 r += 4; 875 876 if (0 == (a16 & 0x0600)) { 877 r += 2; 878 879 if (0 == (a16 & 0x0100)) { 880 r += 1; 881 } 882 } 883 else { 884 885 if (0 == (a16 & 0x0400)) { 886 r += 1; 887 } 888 } 889 } 890 else { 891 892 if (0 == (a16 & 0x6000)) { 893 r += 2; 894 895 if (0 == (a16 & 0x1000)) { 896 r += 1; 897 } 898 } 899 else { 900 901 if (0 == (a16 & 0x4000)) { 902 r += 1; 903 } 904 } 905 } 906 } 907 } 908 else { 909 a16 = extract_h(L_var1); 910 911 if (0 == (a16 & 0x7f80)) { 912 r += 8; 913 914 if (0 == (a16 & 0x0078)) { 915 r += 4 ; 916 917 if (0 == (a16 & 0x0006)) { 918 r += 2; 919 920 if (0 == (a16 & 0x0001)) { 921 r += 1; 922 } 923 } 924 else { 925 926 if (0 == (a16 & 0x0004)) { 927 r += 1; 928 } 929 } 930 } 931 else { 932 933 if (0 == (a16 & 0x0060)) { 934 r += 2; 935 936 if (0 == (a16 & 0x0010)) { 937 r += 1; 938 } 939 } 940 else { 941 942 if (0 == (a16 & 0x0040)) { 943 r += 1; 944 } 945 } 946 } 947 } 948 else { 949 950 if (0 == (a16 & 0x7800)) { 951 r += 4; 952 953 if (0 == (a16 & 0x0600)) { 954 r += 2; 955 956 if (0 == (a16 & 0x0100)) { 957 r += 1; 958 } 959 } 960 else { 961 962 if (0 == (a16 & 0x0400)) { 963 r += 1; 964 } 965 } 966 } 967 else { 968 969 if (0 == (a16 & 0x6000)) { 970 r += 2; 971 972 if (0 == (a16 & 0x1000)) { 973 r += 1; 974 } 975 } 976 else { 977 978 if (0 == (a16 & 0x4000)) { 979 return 1; 980 } 981 } 982 } 983 } 984 } 985 986 return r ; 987#endif 988} 989#endif 990 991/* Round, 1 */ 992#if (ROUND_IS_INLINE) 993__inline Word16 round16(Word32 L_var1) 994{ 995#if ARMV5TE_ROUND 996 Word16 result; 997 asm ( 998 "QADD %[result], %[L_var1], %[bias]\n" 999 "MOV %[result], %[result], ASR #16 \n" 1000 :[result]"=r"(result) 1001 :[L_var1]"r"(L_var1), [bias]"r"(0x8000) 1002 ); 1003 return result; 1004#else 1005 Word16 var_out; 1006 Word32 L_rounded; 1007 1008 L_rounded = L_add (L_var1, (Word32) 0x00008000L); 1009 var_out = extract_h (L_rounded); 1010 return (var_out); 1011#endif 1012} 1013#endif 1014 1015/* Mac, 1 */ 1016#if (L_MAC_IS_INLINE) 1017__inline Word32 L_mac (Word32 L_var3, Word16 var1, Word16 var2) 1018{ 1019#if ARMV5TE_L_MAC 1020 Word32 result; 1021 asm ( 1022 "SMULBB %[result], %[var1], %[var2]\n" 1023 "QADD %[result], %[result], %[result]\n" 1024 "QADD %[result], %[result], %[L_var3]\n" 1025 :[result]"=&r"(result) 1026 : [L_var3]"r"(L_var3), [var1]"r"(var1), [var2]"r"(var2) 1027 ); 1028 return result; 1029#else 1030 Word32 L_var_out; 1031 Word32 L_product; 1032 1033 L_product = L_mult(var1, var2); 1034 L_var_out = L_add (L_var3, L_product); 1035 return (L_var_out); 1036#endif 1037} 1038#endif 1039 1040#if (L_ADD_IS_INLINE) 1041__inline Word32 L_add (Word32 L_var1, Word32 L_var2) 1042{ 1043#if ARMV5TE_L_ADD 1044 Word32 result; 1045 asm ( 1046 "QADD %[result], %[L_var1], %[L_var2]\n" 1047 :[result]"=r"(result) 1048 :[L_var1]"r"(L_var1), [L_var2]"r"(L_var2) 1049 ); 1050 return result; 1051#else 1052 Word32 L_var_out; 1053 1054 L_var_out = L_var1 + L_var2; 1055 if (((L_var1 ^ L_var2) & MIN_32) == 0) 1056 { 1057 if ((L_var_out ^ L_var1) & MIN_32) 1058 { 1059 L_var_out = (L_var1 < 0) ? MIN_32 : MAX_32; 1060 } 1061 } 1062 return (L_var_out); 1063#endif 1064} 1065#endif 1066 1067 1068 1069#if (MULT_R_IS_INLINE) 1070__inline Word16 mult_r (Word16 var1, Word16 var2) 1071{ 1072 Word16 var_out; 1073 Word32 L_product_arr; 1074 1075 L_product_arr = (Word32)var1 *(Word32)var2; /* product */ 1076 L_product_arr += (Word32)0x00004000L; /* round */ 1077 L_product_arr >>= 15; /* shift */ 1078 1079 var_out = saturate(L_product_arr); 1080 1081 return (var_out); 1082} 1083#endif 1084 1085#if (SHR_R_IS_INLINE) 1086__inline Word16 shr_r (Word16 var1, Word16 var2) 1087{ 1088 Word16 var_out; 1089 1090 if (var2 > 15) 1091 { 1092 var_out = 0; 1093 } 1094 else 1095 { 1096 var_out = shr(var1, var2); 1097 1098 if (var2 > 0) 1099 { 1100 if ((var1 & ((Word16) 1 << (var2 - 1))) != 0) 1101 { 1102 var_out++; 1103 } 1104 } 1105 } 1106 1107 return (var_out); 1108} 1109#endif 1110 1111#if (MAC_R_IS_INLINE) 1112__inline Word16 mac_r (Word32 L_var3, Word16 var1, Word16 var2) 1113{ 1114 Word16 var_out; 1115 1116 L_var3 = L_mac (L_var3, var1, var2); 1117 var_out = (Word16)((L_var3 + 0x8000L) >> 16); 1118 1119 return (var_out); 1120} 1121#endif 1122 1123#if (MSU_R_IS_INLINE) 1124__inline Word16 msu_r (Word32 L_var3, Word16 var1, Word16 var2) 1125{ 1126 Word16 var_out; 1127 1128 L_var3 = L_msu (L_var3, var1, var2); 1129 var_out = (Word16)((L_var3 + 0x8000L) >> 16); 1130 1131 return (var_out); 1132} 1133#endif 1134 1135#if (L_SHR_R_IS_INLINE) 1136__inline Word32 L_shr_r (Word32 L_var1, Word16 var2) 1137{ 1138 Word32 L_var_out; 1139 1140 if (var2 > 31) 1141 { 1142 L_var_out = 0; 1143 } 1144 else 1145 { 1146 L_var_out = L_shr(L_var1, var2); 1147 1148 if (var2 > 0) 1149 { 1150 if ((L_var1 & ((Word32) 1 << (var2 - 1))) != 0) 1151 { 1152 L_var_out++; 1153 } 1154 } 1155 } 1156 1157 return (L_var_out); 1158} 1159#endif 1160 1161#if (EXTRACT_H_IS_INLINE) 1162__inline Word16 extract_h (Word32 L_var1) 1163{ 1164 Word16 var_out; 1165 1166 var_out = (Word16) (L_var1 >> 16); 1167 1168 return (var_out); 1169} 1170#endif 1171 1172#if (EXTRACT_L_IS_INLINE) 1173__inline Word16 extract_l(Word32 L_var1) 1174{ 1175 return (Word16) L_var1; 1176} 1177#endif 1178 1179#endif 1180