sad_halfpel_inline.h revision f5af6314db25ff3bef9bd2eeba201bc6cc60805d 
1/* ------------------------------------------------------------------
2 * Copyright (C) 1998-2009 PacketVideo
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 *      http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either
13 * express or implied.
14 * See the License for the specific language governing permissions
15 * and limitations under the License.
16 * -------------------------------------------------------------------
17 */
18
19#ifndef _SAD_HALFPEL_INLINE_H_
20#define _SAD_HALFPEL_INLINE_H_
21
22#ifdef __cplusplus
23extern "C"
24{
25#endif
26
27/* Intentionally not using the gcc asm version, since it (if fixed so
28 * as to not crash - the current register constraints are faulty) is
29 * slightly slower than the plain C version on modern GCC versions. */
30#if !defined(__CC_ARM) /* Generic C version */
31
32    __inline int32 INTERP1_SUB_SAD(int32 sad, int32 tmp, int32 tmp2)
33    {
34        tmp = (tmp2 >> 1) - tmp;
35        if (tmp > 0) sad += tmp;
36        else sad -= tmp;
37
38        return sad;
39    }
40
41    __inline int32 INTERP2_SUB_SAD(int32 sad, int32 tmp, int32 tmp2)
42    {
43        tmp = (tmp >> 2) - tmp2;
44        if (tmp > 0) sad += tmp;
45        else sad -= tmp;
46
47        return sad;
48    }
49
50#elif defined(__CC_ARM)  /* only work with arm v5 */
51
52    __inline int32 INTERP1_SUB_SAD(int32 sad, int32 tmp, int32 tmp2)
53    {
54        __asm
55        {
56            rsbs    tmp, tmp, tmp2, asr #1 ;
57            rsbmi   tmp, tmp, #0 ;
58            add     sad, sad, tmp ;
59        }
60
61        return sad;
62    }
63
64    __inline int32 INTERP2_SUB_SAD(int32 sad, int32 tmp, int32 tmp2)
65    {
66        __asm
67        {
68            rsbs    tmp, tmp2, tmp, asr #2 ;
69            rsbmi   tmp, tmp, #0 ;
70            add     sad, sad, tmp ;
71        }
72
73        return sad;
74    }
75
76#elif defined(__GNUC__) && defined(__arm__) /* ARM GNU COMPILER  */
77
78    __inline int32 INTERP1_SUB_SAD(int32 sad, int32 tmp, int32 tmp2)
79    {
80__asm__ volatile("rsbs	%1, %1, %2, asr #1\n\trsbmi %1, %1, #0\n\tadd  %0, %0, %1": "=r"(sad), "=r"(tmp): "r"(tmp2));
81
82        return sad;
83    }
84
85    __inline int32 INTERP2_SUB_SAD(int32 sad, int32 tmp, int32 tmp2)
86    {
87__asm__ volatile("rsbs	%1, %2, %1, asr #2\n\trsbmi %1, %1, #0\n\tadd	%0, %0, %1": "=r"(sad), "=r"(tmp): "r"(tmp2));
88
89        return sad;
90    }
91
92#endif
93
94#ifdef __cplusplus
95}
96#endif
97
98#endif //_SAD_HALFPEL_INLINE_H_
99
100