armVCM4P10_DecodeCoeffsToPair_s.S revision 0c1bc742181ded4930842b46e9507372f0b1b963 
1/*
2 * (c) Copyright 2007-2008 ARM Limited. All Rights Reserved.
3 *
4 */
5
6    .eabi_attribute 24, 1
7    .eabi_attribute 25, 1
8
9    .arm
10    .fpu neon
11    .text
12
13    .global armVCM4P10_DecodeCoeffsToPair
14    .func   armVCM4P10_DecodeCoeffsToPair
15armVCM4P10_DecodeCoeffsToPair:
16    PUSH     {r4-r12,lr}
17    SUB      sp,sp,#0x40
18    LDR      r10,[r0,#0]
19    LDR      r12,[r1,#0]
20    LDR      r6, =armVCM4P10_CAVLCCoeffTokenTables
21    LDR      r4,[sp,#0x68]
22    LDRB     r9,[r10,#2]
23    LDRB     r8,[r10,#1]
24    LDRB     r11,[r10],#3
25    ADD      r12,r12,#8
26    LDR      r6,[r6,r4,LSL #2]
27    ORR      r9,r9,r8,LSL #8
28    ORR      r11,r9,r11,LSL #16
29    LSLS     r8,r11,r12
30    MOVS     r7,#0x1e
31    AND      r7,r7,r8,LSR #27
32    SUBS     r12,r12,#8
33L0x44:
34    BCC      L1
35    LDRB     r8,[r10],#1
36L1:
37    LDRH     r7,[r6,r7]
38    ADDCC    r12,r12,#8
39    ADD      r12,r12,#4
40    ORRCS    r11,r8,r11,LSL #8
41    LSRS     r8,r7,#1
42    BCS      L0x74
43    LSLS     r8,r11,r12
44    SUBS     r12,r12,#0xa
45    ADD      r7,r7,r8,LSR #29
46    BIC      r7,r7,#1
47    B        L0x44
48L0x74:
49    SUB      r12,r12,r7,LSR #13
50    BIC      r7,r8,#0xf000
51    LSRS     r5,r7,#2
52    STRB     r5,[r2,#0]
53    BEQ      L0x344
54    CMP      r7,#0x44
55    BGE      L0x33c
56    STR      r0,[sp,#0]
57    STR      r1,[sp,#4]
58    STR      r3,[sp,#8]
59    ANDS     r1,r7,#3
60    ADD      r2,sp,#0xc
61    BEQ      L0xd8
62    MOV      r0,r1
63L0xac:
64    LSLS     r7,r11,r12
65    SUBS     r12,r12,#7
66    BCC      L2
67    LDRB     r8,[r10],#1
68L2:
69    ADDCC    r12,r12,#8
70    LSR      r7,r7,#31
71    ORRCS    r11,r8,r11,LSL #8
72    SUBS     r0,r0,#1
73    MOV      r8,#1
74    SUB      r8,r8,r7,LSL #1
75    STRH     r8,[r2],#2
76    BGT      L0xac
77L0xd8:
78    SUBS     r0,r5,r1
79    BEQ      L0x1b8
80    MOV      r4,#1
81    CMP      r5,#0xa
82    MOVLE    r4,#0
83    CMP      r1,#3
84    MOVLT    r1,#4
85    MOVGE    r1,#2
86    MOVGE    r4,#0
87L0xfc:
88    LSLS     r7,r11,r12
89    CLZ      r7,r7
90    ADD      r12,r12,r7
91    SUBS     r12,r12,#7
92    BCC      L3
93    LDRB     r8,[r10],#1
94    ORR      r11,r8,r11,LSL #8
95    SUBS     r12,r12,#8
96    BCC      L3
97    LDRB     r8,[r10],#1
98L3:
99    ADDCC    r12,r12,#8
100    ORRCS    r11,r8,r11,LSL #8
101    CMP      r7,#0x10
102    BGE      L0x33c
103    MOVS     lr,r4
104    TEQEQ    r7,#0xe
105    MOVEQ    lr,#4
106    TEQ      r7,#0xf
107    MOVEQ    lr,#0xc
108    TEQEQ    r4,#0
109    ADDEQ    r7,r7,#0xf
110    TEQ      lr,#0
111    BEQ      L0x184
112    LSL      r3,r11,r12
113    ADD      r12,r12,lr
114    SUBS     r12,r12,#8
115    RSB      r9,lr,#0x20
116    BCC      L4
117    LDRB     r8,[r10],#1
118    ORR      r11,r8,r11,LSL #8
119    SUBS     r12,r12,#8
120    BCC      L4
121    LDRB     r8,[r10],#1
122L4:
123    ADDCC    r12,r12,#8
124    LSR      r3,r3,r9
125    ORRCS    r11,r8,r11,LSL #8
126    LSL      r7,r7,r4
127    ADD      r7,r3,r7
128L0x184:
129    ADD      r7,r7,r1
130    MOV      r1,#2
131    LSRS     r8,r7,#1
132    RSBCS    r8,r8,#0
133    STRH     r8,[r2],#2
134    LDR      r9, =armVCM4P10_SuffixToLevel
135    LDRSB    r8,[r9,r4]
136    TEQ      r4,#0
137    MOVEQ    r4,#1
138    CMP      r7,r8
139    ADDCS    r4,r4,#1
140    SUBS     r0,r0,#1
141    BGT      L0xfc
142L0x1b8:
143    LDR      r8,[sp,#0x6c]
144    SUB      r0,r5,#1
145    SUBS     r1,r8,r5
146    ADD      r4,sp,#0x2c
147    MOV      lr,r5
148    SUB      lr,lr,#1
149    BEQ      L0x2b0
150    TEQ      r8,#4
151    LDREQ    r6, =(armVCM4P10_CAVLCTotalZeros2x2Tables - 4)
152    LDRNE    r6, =(armVCM4P10_CAVLCTotalZeroTables - 4)
153    LDR      r6,[r6,r5,LSL #2]
154    LSLS     r8,r11,r12
155    MOVS     r7,#0x1e
156    AND      r7,r7,r8,LSR #27
157    SUBS     r12,r12,#8
158L0x1f4:
159    BCC      L5
160    LDRB     r8,[r10],#1
161L5:
162    LDRH     r7,[r6,r7]
163    ADDCC    r12,r12,#8
164    ADD      r12,r12,#4
165    ORRCS    r11,r8,r11,LSL #8
166    LSRS     r8,r7,#1
167    BCS      L0x224
168    LSLS     r8,r11,r12
169    SUBS     r12,r12,#0xa
170    ADD      r7,r7,r8,LSR #29
171    BIC      r7,r7,#1
172    B        L0x1f4
173L0x224:
174    SUB      r12,r12,r7,LSR #13
175    BIC      r7,r8,#0xf000
176    CMP      r7,#0x10
177    BGE      L0x33c
178    LDR      r3, =(armVCM4P10_CAVLCRunBeforeTables - 4)
179    ADD      r4,sp,#0x2c
180    MOVS     r1,r7
181    ADD      lr,lr,r1
182    BEQ      L0x2b0
183L0x248:
184    SUBS     r0,r0,#1
185    LDR      r6,[r3,r1,LSL #2]
186    BLT      L0x2bc
187    LSLS     r8,r11,r12
188    MOVS     r7,#0xe
189    AND      r7,r7,r8,LSR #28
190    SUBS     r12,r12,#8
191L0x264:
192    BCC      L6
193    LDRB     r8,[r10],#1
194L6:
195    LDRH     r7,[r6,r7]
196    ADDCC    r12,r12,#8
197    ADD      r12,r12,#3
198    ORRCS    r11,r8,r11,LSL #8
199    LSRS     r8,r7,#1
200    BCS      L0x294
201    LSLS     r8,r11,r12
202    SUBS     r12,r12,#9
203    ADD      r7,r7,r8,LSR #29
204    BIC      r7,r7,#1
205    B        L0x264
206L0x294:
207    SUB      r12,r12,r7,LSR #13
208    BIC      r7,r8,#0xf000
209    CMP      r7,#0xf
210    BGE      L0x33c
211    SUBS     r1,r1,r7
212    STRB     r7,[r4],#1
213    BGT      L0x248
214L0x2b0:
215    SUBS     r0,r0,#1
216    BLT      L7
217    STRB     r1,[r4],#1
218L7:
219    BGT      L0x2b0
220L0x2bc:
221    STRB     r1,[r4],#1
222    LDR      r8,[sp,#0x6c]
223    TEQ      r8,#0xf
224    ADDEQ    lr,lr,#1
225    SUB      r4,r4,r5
226    SUB      r2,r2,r5
227    SUB      r2,r2,r5
228    LDR      r3,[sp,#8]
229    LDR      r0,[r3,#0]
230    TEQ      r8,#4
231    LDREQ    r6, =armVCM4P10_ZigZag_2x2
232    LDRNE    r6, =armVCM4P10_ZigZag_4x4
233L0x2ec:
234    LDRB     r9,[r4],#1
235    LDRB     r8,[r6,lr]
236    SUB      lr,lr,#1
237    SUB      lr,lr,r9
238    LDRSH    r9,[r2],#2
239    SUBS     r5,r5,#1
240    ORREQ    r8,r8,#0x20
241    ADD      r1,r9,#0x80
242    CMP      r1,#0x100
243    ORRCS    r8,r8,#0x10
244    TEQ      r5,#0
245    STRB     r8,[r0],#1
246    STRB     r9,[r0],#1
247    LSR      r9,r9,#8
248    BCC      L8
249    STRB     r9,[r0],#1
250L8:
251    BNE      L0x2ec
252    STR      r0,[r3,#0]
253    LDR      r0,[sp,#0]
254    LDR      r1,[sp,#4]
255    B        L0x344
256L0x33c:
257    MVN      r0,#1
258    B        L0x35c
259L0x344:
260    ADD      r10,r10,r12,LSR #3
261    AND      r12,r12,#7
262    SUB      r10,r10,#4
263    STR      r12,[r1,#0]
264    STR      r10,[r0,#0]
265    MOV      r0,#0
266L0x35c:
267    ADD      sp,sp,#0x40
268    POP      {r4-r12,pc}
269    .endfunc
270
271    .end
272
273