armVCM4P10_DecodeCoeffsToPair_s.S revision 22e06318d04074d1a7c90caa173857abdcfd153e 
1/*
2 * (c) Copyright 2007-2008 ARM Limited. All Rights Reserved.
3 *
4 */
5
6    .eabi_attribute 24, 1
7    .eabi_attribute 25, 1
8
9    .arm
10    .fpu neon
11    .text
12
13    .global armVCM4P10_DecodeCoeffsToPair
14    .func   armVCM4P10_DecodeCoeffsToPair
15armVCM4P10_DecodeCoeffsToPair:
16    PUSH     {r4-r12,lr}
17    SUB      sp,sp,#0x40
18    LDR      r10,[r0,#0]
19    LDR      r12,[r1,#0]
20    LDR      r6, .LarmVCM4P10_CAVLCCoeffTokenTables
21P0: ADD      r6, pc
22    LDR      r4,[sp,#0x68]
23    LDRB     r9,[r10,#2]
24    LDRB     r8,[r10,#1]
25    LDRB     r11,[r10],#3
26    ADD      r12,r12,#8
27    LDR      r6,[r6,r4,LSL #2]
28    ORR      r9,r9,r8,LSL #8
29    ORR      r11,r9,r11,LSL #16
30    LSLS     r8,r11,r12
31    MOVS     r7,#0x1e
32    AND      r7,r7,r8,LSR #27
33    SUBS     r12,r12,#8
34L0x44:
35    BCC      L1
36    LDRB     r8,[r10],#1
37L1:
38    LDRH     r7,[r6,r7]
39    ADDCC    r12,r12,#8
40    ADD      r12,r12,#4
41    ORRCS    r11,r8,r11,LSL #8
42    LSRS     r8,r7,#1
43    BCS      L0x74
44    LSLS     r8,r11,r12
45    SUBS     r12,r12,#0xa
46    ADD      r7,r7,r8,LSR #29
47    BIC      r7,r7,#1
48    B        L0x44
49L0x74:
50    SUB      r12,r12,r7,LSR #13
51    BIC      r7,r8,#0xf000
52    LSRS     r5,r7,#2
53    STRB     r5,[r2,#0]
54    BEQ      L0x344
55    CMP      r7,#0x44
56    BGE      L0x33c
57    STR      r0,[sp,#0]
58    STR      r1,[sp,#4]
59    STR      r3,[sp,#8]
60    ANDS     r1,r7,#3
61    ADD      r2,sp,#0xc
62    BEQ      L0xd8
63    MOV      r0,r1
64L0xac:
65    LSLS     r7,r11,r12
66    SUBS     r12,r12,#7
67    BCC      L2
68    LDRB     r8,[r10],#1
69L2:
70    ADDCC    r12,r12,#8
71    LSR      r7,r7,#31
72    ORRCS    r11,r8,r11,LSL #8
73    SUBS     r0,r0,#1
74    MOV      r8,#1
75    SUB      r8,r8,r7,LSL #1
76    STRH     r8,[r2],#2
77    BGT      L0xac
78L0xd8:
79    SUBS     r0,r5,r1
80    BEQ      L0x1b8
81    MOV      r4,#1
82    CMP      r5,#0xa
83    MOVLE    r4,#0
84    CMP      r1,#3
85    MOVLT    r1,#4
86    MOVGE    r1,#2
87    MOVGE    r4,#0
88L0xfc:
89    LSLS     r7,r11,r12
90    CLZ      r7,r7
91    ADD      r12,r12,r7
92    SUBS     r12,r12,#7
93    BCC      L3
94    LDRB     r8,[r10],#1
95    ORR      r11,r8,r11,LSL #8
96    SUBS     r12,r12,#8
97    BCC      L3
98    LDRB     r8,[r10],#1
99L3:
100    ADDCC    r12,r12,#8
101    ORRCS    r11,r8,r11,LSL #8
102    CMP      r7,#0x10
103    BGE      L0x33c
104    MOVS     lr,r4
105    TEQEQ    r7,#0xe
106    MOVEQ    lr,#4
107    TEQ      r7,#0xf
108    MOVEQ    lr,#0xc
109    TEQEQ    r4,#0
110    ADDEQ    r7,r7,#0xf
111    TEQ      lr,#0
112    BEQ      L0x184
113    LSL      r3,r11,r12
114    ADD      r12,r12,lr
115    SUBS     r12,r12,#8
116    RSB      r9,lr,#0x20
117    BCC      L4
118    LDRB     r8,[r10],#1
119    ORR      r11,r8,r11,LSL #8
120    SUBS     r12,r12,#8
121    BCC      L4
122    LDRB     r8,[r10],#1
123L4:
124    ADDCC    r12,r12,#8
125    LSR      r3,r3,r9
126    ORRCS    r11,r8,r11,LSL #8
127    LSL      r7,r7,r4
128    ADD      r7,r3,r7
129L0x184:
130    ADD      r7,r7,r1
131    MOV      r1,#2
132    LSRS     r8,r7,#1
133    RSBCS    r8,r8,#0
134    STRH     r8,[r2],#2
135    LDR      r9, .LarmVCM4P10_SuffixToLevel
136P1: ADD      r9, pc
137    LDRSB    r8,[r9,r4]
138    TEQ      r4,#0
139    MOVEQ    r4,#1
140    CMP      r7,r8
141    ADDCS    r4,r4,#1
142    SUBS     r0,r0,#1
143    BGT      L0xfc
144L0x1b8:
145    LDR      r8,[sp,#0x6c]
146    SUB      r0,r5,#1
147    SUBS     r1,r8,r5
148    ADD      r4,sp,#0x2c
149    MOV      lr,r5
150    SUB      lr,lr,#1
151    BEQ      L0x2b0
152    TEQ      r8,#4
153    LDREQ    r6, .LarmVCM4P10_CAVLCTotalZeros2x2Tables
154    LDRNE    r6, .LarmVCM4P10_CAVLCTotalZeroTables
155P2: ADD      r6, pc
156    LDR      r6,[r6,r5,LSL #2]
157    LSLS     r8,r11,r12
158    MOVS     r7,#0x1e
159    AND      r7,r7,r8,LSR #27
160    SUBS     r12,r12,#8
161L0x1f4:
162    BCC      L5
163    LDRB     r8,[r10],#1
164L5:
165    LDRH     r7,[r6,r7]
166    ADDCC    r12,r12,#8
167    ADD      r12,r12,#4
168    ORRCS    r11,r8,r11,LSL #8
169    LSRS     r8,r7,#1
170    BCS      L0x224
171    LSLS     r8,r11,r12
172    SUBS     r12,r12,#0xa
173    ADD      r7,r7,r8,LSR #29
174    BIC      r7,r7,#1
175    B        L0x1f4
176L0x224:
177    SUB      r12,r12,r7,LSR #13
178    BIC      r7,r8,#0xf000
179    CMP      r7,#0x10
180    BGE      L0x33c
181    LDR      r3, .LarmVCM4P10_CAVLCRunBeforeTables
182P3: ADD      r3, pc
183    ADD      r4,sp,#0x2c
184    MOVS     r1,r7
185    ADD      lr,lr,r1
186    BEQ      L0x2b0
187L0x248:
188    SUBS     r0,r0,#1
189    LDR      r6,[r3,r1,LSL #2]
190    BLT      L0x2bc
191    LSLS     r8,r11,r12
192    MOVS     r7,#0xe
193    AND      r7,r7,r8,LSR #28
194    SUBS     r12,r12,#8
195L0x264:
196    BCC      L6
197    LDRB     r8,[r10],#1
198L6:
199    LDRH     r7,[r6,r7]
200    ADDCC    r12,r12,#8
201    ADD      r12,r12,#3
202    ORRCS    r11,r8,r11,LSL #8
203    LSRS     r8,r7,#1
204    BCS      L0x294
205    LSLS     r8,r11,r12
206    SUBS     r12,r12,#9
207    ADD      r7,r7,r8,LSR #29
208    BIC      r7,r7,#1
209    B        L0x264
210L0x294:
211    SUB      r12,r12,r7,LSR #13
212    BIC      r7,r8,#0xf000
213    CMP      r7,#0xf
214    BGE      L0x33c
215    SUBS     r1,r1,r7
216    STRB     r7,[r4],#1
217    BGT      L0x248
218L0x2b0:
219    SUBS     r0,r0,#1
220    BLT      L7
221    STRB     r1,[r4],#1
222L7:
223    BGT      L0x2b0
224L0x2bc:
225    STRB     r1,[r4],#1
226    LDR      r8,[sp,#0x6c]
227    TEQ      r8,#0xf
228    ADDEQ    lr,lr,#1
229    SUB      r4,r4,r5
230    SUB      r2,r2,r5
231    SUB      r2,r2,r5
232    LDR      r3,[sp,#8]
233    LDR      r0,[r3,#0]
234    TEQ      r8,#4
235    LDREQ    r6, .LarmVCM4P10_ZigZag_2x2
236    LDRNE    r6, .LarmVCM4P10_ZigZag_4x4
237P4: ADD      r6, pc
238L0x2ec:
239    LDRB     r9,[r4],#1
240    LDRB     r8,[r6,lr]
241    SUB      lr,lr,#1
242    SUB      lr,lr,r9
243    LDRSH    r9,[r2],#2
244    SUBS     r5,r5,#1
245    ORREQ    r8,r8,#0x20
246    ADD      r1,r9,#0x80
247    CMP      r1,#0x100
248    ORRCS    r8,r8,#0x10
249    TEQ      r5,#0
250    STRB     r8,[r0],#1
251    STRB     r9,[r0],#1
252    LSR      r9,r9,#8
253    BCC      L8
254    STRB     r9,[r0],#1
255L8:
256    BNE      L0x2ec
257    STR      r0,[r3,#0]
258    LDR      r0,[sp,#0]
259    LDR      r1,[sp,#4]
260    B        L0x344
261L0x33c:
262    MVN      r0,#1
263    B        L0x35c
264L0x344:
265    ADD      r10,r10,r12,LSR #3
266    AND      r12,r12,#7
267    SUB      r10,r10,#4
268    STR      r12,[r1,#0]
269    STR      r10,[r0,#0]
270    MOV      r0,#0
271L0x35c:
272    ADD      sp,sp,#0x40
273    POP      {r4-r12,pc}
274    .endfunc
275
276.LarmVCM4P10_CAVLCCoeffTokenTables:
277    .word   armVCM4P10_CAVLCCoeffTokenTables-(P0+8)
278.LarmVCM4P10_SuffixToLevel:
279    .word   armVCM4P10_SuffixToLevel-(P1+8)
280.LarmVCM4P10_CAVLCTotalZeros2x2Tables:
281    .word   (armVCM4P10_CAVLCTotalZeros2x2Tables - 4)-(P2+8)
282.LarmVCM4P10_CAVLCTotalZeroTables:
283    .word   (armVCM4P10_CAVLCTotalZeroTables - 4)-(P2+8)
284.LarmVCM4P10_CAVLCRunBeforeTables:
285    .word   (armVCM4P10_CAVLCRunBeforeTables - 4)-(P3+8)
286.LarmVCM4P10_ZigZag_2x2:
287    .word   armVCM4P10_ZigZag_2x2-(P4+8)
288.LarmVCM4P10_ZigZag_4x4:
289    .word   armVCM4P10_ZigZag_4x4-(P4+8)
290
291    .end
292