msmb_isp.h revision d5781d29acafa196ed9a8e6216c477ab90d01335 
1/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
10 * GNU General Public License for more details.
11 */
12#ifndef __MSMB_ISP__
13#define __MSMB_ISP__
14
15#include <linux/videodev2.h>
16
17#define MAX_PLANES_PER_STREAM 3
18#define MAX_NUM_STREAM 7
19
20#define ISP_VERSION_46        46
21#define ISP_VERSION_44        44
22#define ISP_VERSION_40        40
23#define ISP_VERSION_32        32
24#define ISP_NATIVE_BUF_BIT    (0x10000 << 0)
25#define ISP0_BIT              (0x10000 << 1)
26#define ISP1_BIT              (0x10000 << 2)
27#define ISP_META_CHANNEL_BIT  (0x10000 << 3)
28#define ISP_SCRATCH_BUF_BIT   (0x10000 << 4)
29#define ISP_STATS_STREAM_BIT  0x80000000
30
31struct msm_vfe_cfg_cmd_list;
32
33enum ISP_START_PIXEL_PATTERN {
34	ISP_BAYER_RGRGRG,
35	ISP_BAYER_GRGRGR,
36	ISP_BAYER_BGBGBG,
37	ISP_BAYER_GBGBGB,
38	ISP_YUV_YCbYCr,
39	ISP_YUV_YCrYCb,
40	ISP_YUV_CbYCrY,
41	ISP_YUV_CrYCbY,
42	ISP_PIX_PATTERN_MAX
43};
44
45enum msm_vfe_plane_fmt {
46	Y_PLANE,
47	CB_PLANE,
48	CR_PLANE,
49	CRCB_PLANE,
50	CBCR_PLANE,
51	VFE_PLANE_FMT_MAX
52};
53
54enum msm_vfe_input_src {
55	VFE_PIX_0,
56	VFE_RAW_0,
57	VFE_RAW_1,
58	VFE_RAW_2,
59	VFE_SRC_MAX,
60};
61
62enum msm_vfe_axi_stream_src {
63	PIX_ENCODER,
64	PIX_VIEWFINDER,
65	PIX_VIDEO,
66	CAMIF_RAW,
67	IDEAL_RAW,
68	RDI_INTF_0,
69	RDI_INTF_1,
70	RDI_INTF_2,
71	VFE_AXI_SRC_MAX
72};
73
74enum msm_vfe_frame_skip_pattern {
75	NO_SKIP,
76	EVERY_2FRAME,
77	EVERY_3FRAME,
78	EVERY_4FRAME,
79	EVERY_5FRAME,
80	EVERY_6FRAME,
81	EVERY_7FRAME,
82	EVERY_8FRAME,
83	EVERY_16FRAME,
84	EVERY_32FRAME,
85	SKIP_ALL,
86	MAX_SKIP,
87};
88
89enum msm_vfe_camif_input {
90	CAMIF_DISABLED,
91	CAMIF_PAD_REG_INPUT,
92	CAMIF_MIDDI_INPUT,
93	CAMIF_MIPI_INPUT,
94};
95
96struct msm_vfe_camif_cfg {
97	uint32_t lines_per_frame;
98	uint32_t pixels_per_line;
99	uint32_t first_pixel;
100	uint32_t last_pixel;
101	uint32_t first_line;
102	uint32_t last_line;
103	uint32_t epoch_line0;
104	uint32_t epoch_line1;
105	enum msm_vfe_camif_input camif_input;
106};
107
108enum msm_vfe_inputmux {
109	CAMIF,
110	TESTGEN,
111	EXTERNAL_READ,
112};
113
114enum msm_vfe_stats_composite_group {
115	STATS_COMPOSITE_GRP_NONE,
116	STATS_COMPOSITE_GRP_1,
117	STATS_COMPOSITE_GRP_2,
118	STATS_COMPOSITE_GRP_MAX,
119};
120
121struct msm_vfe_pix_cfg {
122	struct msm_vfe_camif_cfg camif_cfg;
123	enum msm_vfe_inputmux input_mux;
124	enum ISP_START_PIXEL_PATTERN pixel_pattern;
125	uint32_t input_format;
126};
127
128struct msm_vfe_rdi_cfg {
129	uint8_t cid;
130	uint8_t frame_based;
131};
132
133struct msm_vfe_input_cfg {
134	union {
135		struct msm_vfe_pix_cfg pix_cfg;
136		struct msm_vfe_rdi_cfg rdi_cfg;
137	} d;
138	enum msm_vfe_input_src input_src;
139	uint32_t input_pix_clk;
140};
141
142struct msm_vfe_axi_plane_cfg {
143	uint32_t output_width; /*Include padding*/
144	uint32_t output_height;
145	uint32_t output_stride;
146	uint32_t output_scan_lines;
147	uint32_t output_plane_format; /*Y/Cb/Cr/CbCr*/
148	uint32_t plane_addr_offset;
149	uint8_t csid_src; /*RDI 0-2*/
150	uint8_t rdi_cid;/*CID 1-16*/
151};
152
153struct msm_vfe_axi_stream_request_cmd {
154	uint32_t session_id;
155	uint32_t stream_id;
156	uint32_t vt_enable;
157	uint32_t output_format;/*Planar/RAW/Misc*/
158	enum msm_vfe_axi_stream_src stream_src; /*CAMIF/IDEAL/RDIs*/
159	struct msm_vfe_axi_plane_cfg plane_cfg[MAX_PLANES_PER_STREAM];
160
161	uint32_t burst_count;
162	uint32_t hfr_mode;
163	uint8_t frame_base;
164
165	uint32_t init_frame_drop; /*MAX 31 Frames*/
166	enum msm_vfe_frame_skip_pattern frame_skip_pattern;
167	uint8_t buf_divert; /* if TRUE no vb2 buf done. */
168	/*Return values*/
169	uint32_t axi_stream_handle;
170	uint32_t controllable_output;
171};
172
173struct msm_vfe_axi_stream_release_cmd {
174	uint32_t stream_handle;
175};
176
177enum msm_vfe_axi_stream_cmd {
178	STOP_STREAM,
179	START_STREAM,
180	STOP_IMMEDIATELY,
181};
182
183struct msm_vfe_axi_stream_cfg_cmd {
184	uint8_t num_streams;
185	uint32_t stream_handle[MAX_NUM_STREAM];
186	enum msm_vfe_axi_stream_cmd cmd;
187};
188
189enum msm_vfe_axi_stream_update_type {
190	ENABLE_STREAM_BUF_DIVERT,
191	DISABLE_STREAM_BUF_DIVERT,
192	UPDATE_STREAM_FRAMEDROP_PATTERN,
193	UPDATE_STREAM_STATS_FRAMEDROP_PATTERN,
194	UPDATE_STREAM_AXI_CONFIG,
195	UPDATE_STREAM_REQUEST_FRAMES,
196	UPDATE_STREAM_ADD_BUFQ,
197	UPDATE_STREAM_REMOVE_BUFQ,
198};
199
200enum msm_vfe_iommu_type {
201	IOMMU_ATTACH,
202	IOMMU_DETACH,
203};
204
205struct msm_vfe_axi_stream_cfg_update_info {
206	uint32_t stream_handle;
207	uint32_t output_format;
208	uint32_t user_stream_id;
209	uint8_t need_divert;
210	enum msm_vfe_frame_skip_pattern skip_pattern;
211	struct msm_vfe_axi_plane_cfg plane_cfg[MAX_PLANES_PER_STREAM];
212};
213
214struct msm_vfe_axi_stream_update_cmd {
215	uint32_t num_streams;
216	enum msm_vfe_axi_stream_update_type update_type;
217	struct msm_vfe_axi_stream_cfg_update_info update_info[MAX_NUM_STREAM];
218	uint32_t cur_frame_id;
219};
220
221struct msm_vfe_smmu_attach_cmd {
222	uint32_t security_mode;
223	uint32_t iommu_attach_mode;
224};
225
226enum msm_isp_stats_type {
227	MSM_ISP_STATS_AEC,   /* legacy based AEC */
228	MSM_ISP_STATS_AF,    /* legacy based AF */
229	MSM_ISP_STATS_AWB,   /* legacy based AWB */
230	MSM_ISP_STATS_RS,    /* legacy based RS */
231	MSM_ISP_STATS_CS,    /* legacy based CS */
232	MSM_ISP_STATS_IHIST, /* legacy based HIST */
233	MSM_ISP_STATS_SKIN,  /* legacy based SKIN */
234	MSM_ISP_STATS_BG,    /* Bayer Grids */
235	MSM_ISP_STATS_BF,    /* Bayer Focus */
236	MSM_ISP_STATS_BE,    /* Bayer Exposure*/
237	MSM_ISP_STATS_BHIST, /* Bayer Hist */
238	MSM_ISP_STATS_BF_SCALE, /* Bayer Focus scale */
239	MSM_ISP_STATS_HDR_BE, /* HDR Bayer Exposure */
240	MSM_ISP_STATS_HDR_BHIST, /* HDR Bayer Hist */
241	MSM_ISP_STATS_MAX    /* MAX */
242};
243
244struct msm_vfe_stats_stream_request_cmd {
245	uint32_t session_id;
246	uint32_t stream_id;
247	enum msm_isp_stats_type stats_type;
248	uint32_t composite_flag;
249	uint32_t framedrop_pattern;
250	uint32_t init_frame_drop; /*MAX 31 Frames*/
251	uint32_t irq_subsample_pattern;
252	uint32_t buffer_offset;
253	uint32_t stream_handle;
254};
255
256struct msm_vfe_stats_stream_release_cmd {
257	uint32_t stream_handle;
258};
259struct msm_vfe_stats_stream_cfg_cmd {
260	uint8_t num_streams;
261	uint32_t stream_handle[MSM_ISP_STATS_MAX];
262	uint8_t enable;
263};
264
265enum msm_vfe_reg_cfg_type {
266	VFE_WRITE,
267	VFE_WRITE_MB,
268	VFE_READ,
269	VFE_CFG_MASK,
270	VFE_WRITE_DMI_16BIT,
271	VFE_WRITE_DMI_32BIT,
272	VFE_WRITE_DMI_64BIT,
273	VFE_READ_DMI_16BIT,
274	VFE_READ_DMI_32BIT,
275	VFE_READ_DMI_64BIT,
276	GET_MAX_CLK_RATE,
277	GET_ISP_ID,
278};
279
280struct msm_vfe_cfg_cmd2 {
281	uint16_t num_cfg;
282	uint16_t cmd_len;
283	void __user *cfg_data;
284	void __user *cfg_cmd;
285};
286
287struct msm_vfe_cfg_cmd_list {
288	struct msm_vfe_cfg_cmd2      cfg_cmd;
289	struct msm_vfe_cfg_cmd_list *next;
290	uint32_t                     next_size;
291};
292
293struct msm_vfe_reg_rw_info {
294	uint32_t reg_offset;
295	uint32_t cmd_data_offset;
296	uint32_t len;
297};
298
299struct msm_vfe_reg_mask_info {
300	uint32_t reg_offset;
301	uint32_t mask;
302	uint32_t val;
303};
304
305struct msm_vfe_reg_dmi_info {
306	uint32_t hi_tbl_offset; /*Optional*/
307	uint32_t lo_tbl_offset; /*Required*/
308	uint32_t len;
309};
310
311struct msm_vfe_reg_cfg_cmd {
312	union {
313		struct msm_vfe_reg_rw_info rw_info;
314		struct msm_vfe_reg_mask_info mask_info;
315		struct msm_vfe_reg_dmi_info dmi_info;
316	} u;
317
318	enum msm_vfe_reg_cfg_type cmd_type;
319};
320
321enum msm_isp_buf_type {
322	ISP_PRIVATE_BUF,
323	ISP_SHARE_BUF,
324	MAX_ISP_BUF_TYPE,
325};
326
327struct msm_isp_buf_request {
328	uint32_t session_id;
329	uint32_t stream_id;
330	uint8_t num_buf;
331	uint32_t handle;
332	enum msm_isp_buf_type buf_type;
333};
334
335struct msm_isp_qbuf_plane {
336	uint32_t addr;
337	uint32_t offset;
338};
339
340struct msm_isp_qbuf_buffer {
341	struct msm_isp_qbuf_plane planes[MAX_PLANES_PER_STREAM];
342	uint32_t num_planes;
343};
344
345struct msm_isp_qbuf_info {
346	uint32_t handle;
347	int32_t buf_idx;
348	/*Only used for prepare buffer*/
349	struct msm_isp_qbuf_buffer buffer;
350	/*Only used for diverted buffer*/
351	uint32_t dirty_buf;
352};
353
354struct msm_vfe_axi_src_state {
355	enum msm_vfe_input_src input_src;
356	uint32_t src_active;
357};
358
359enum msm_isp_event_idx {
360	ISP_REG_UPDATE      = 0,
361	ISP_START_ACK       = 1,
362	ISP_STOP_ACK        = 2,
363	ISP_IRQ_VIOLATION   = 3,
364	ISP_WM_BUS_OVERFLOW = 4,
365	ISP_STATS_OVERFLOW  = 5,
366	ISP_CAMIF_ERROR     = 6,
367	ISP_EPOCH0_IRQ      = 7,
368	ISP_BUF_DONE        = 9,
369	ISP_UPDATE_AXI_DONE = 10,
370	ISP_EVENT_MAX       = 11
371};
372
373enum msm_isp_epoch_idx {
374	ISP_EPOCH_0   = 0,
375	ISP_EPOCH_1   = 1,
376	ISP_EPOCH_MAX = 2
377};
378
379#define ISP_EVENT_OFFSET          8
380#define ISP_EVENT_BASE            (V4L2_EVENT_PRIVATE_START)
381#define ISP_BUF_EVENT_BASE        (ISP_EVENT_BASE + (1 << ISP_EVENT_OFFSET))
382#define ISP_STATS_EVENT_BASE      (ISP_EVENT_BASE + (2 << ISP_EVENT_OFFSET))
383#define ISP_SOF_EVENT_BASE        (ISP_EVENT_BASE + (3 << ISP_EVENT_OFFSET))
384#define ISP_EOF_EVENT_BASE        (ISP_EVENT_BASE + (4 << ISP_EVENT_OFFSET))
385#define ISP_EVENT_REG_UPDATE      (ISP_EVENT_BASE + ISP_REG_UPDATE)
386#define ISP_EVENT_START_ACK       (ISP_EVENT_BASE + ISP_START_ACK)
387#define ISP_EVENT_STOP_ACK        (ISP_EVENT_BASE + ISP_STOP_ACK)
388#define ISP_EVENT_IRQ_VIOLATION   (ISP_EVENT_BASE + ISP_IRQ_VIOLATION)
389#define ISP_EVENT_WM_BUS_OVERFLOW (ISP_EVENT_BASE + ISP_WM_BUS_OVERFLOW)
390#define ISP_EVENT_STATS_OVERFLOW  (ISP_EVENT_BASE + ISP_STATS_OVERFLOW)
391#define ISP_EVENT_CAMIF_ERROR     (ISP_EVENT_BASE + ISP_CAMIF_ERROR)
392#define ISP_EVENT_EPOCH0_IRQ      (ISP_EVENT_BASE + ISP_EPOCH0_IRQ)
393#define ISP_EVENT_UPDATE_AXI_DONE (ISP_EVENT_BASE + ISP_UPDATE_AXI_DONE)
394#define ISP_EVENT_SOF             (ISP_SOF_EVENT_BASE)
395#define ISP_EVENT_EOF             (ISP_EOF_EVENT_BASE)
396#define ISP_EVENT_BUF_DONE        (ISP_EVENT_BASE + ISP_BUF_DONE)
397#define ISP_EVENT_BUF_DIVERT      (ISP_BUF_EVENT_BASE)
398#define ISP_EVENT_STATS_NOTIFY    (ISP_STATS_EVENT_BASE)
399#define ISP_EVENT_COMP_STATS_NOTIFY (ISP_EVENT_STATS_NOTIFY + MSM_ISP_STATS_MAX)
400/* The msm_v4l2_event_data structure should match the
401 * v4l2_event.u.data field.
402 * should not exceed 64 bytes */
403
404struct msm_isp_buf_event {
405	uint32_t session_id;
406	uint32_t stream_id;
407	uint32_t handle;
408	uint32_t output_format;
409	int8_t buf_idx;
410};
411struct msm_isp_stats_event {
412	uint32_t stats_mask;                        /* 4 bytes */
413	uint8_t stats_buf_idxs[MSM_ISP_STATS_MAX];  /* 11 bytes */
414};
415
416struct msm_isp_stream_ack {
417	uint32_t session_id;
418	uint32_t stream_id;
419	uint32_t handle;
420};
421
422struct msm_isp_epoch_event {
423	enum msm_isp_epoch_idx epoch_idx;
424};
425
426struct msm_isp_event_data {
427	/*Wall clock except for buffer divert events
428	 *which use monotonic clock
429	 */
430	struct timeval timestamp;
431	/* Monotonic timestamp since bootup */
432	struct timeval mono_timestamp;
433	enum msm_vfe_input_src input_intf;
434	uint32_t frame_id;
435	union {
436		struct msm_isp_stats_event stats;
437		struct msm_isp_buf_event buf_done;
438		struct msm_isp_epoch_event epoch;
439	} u; /* union can have max 52 bytes */
440};
441
442#define V4L2_PIX_FMT_QBGGR8  v4l2_fourcc('Q', 'B', 'G', '8')
443#define V4L2_PIX_FMT_QGBRG8  v4l2_fourcc('Q', 'G', 'B', '8')
444#define V4L2_PIX_FMT_QGRBG8  v4l2_fourcc('Q', 'G', 'R', '8')
445#define V4L2_PIX_FMT_QRGGB8  v4l2_fourcc('Q', 'R', 'G', '8')
446#define V4L2_PIX_FMT_QBGGR10 v4l2_fourcc('Q', 'B', 'G', '0')
447#define V4L2_PIX_FMT_QGBRG10 v4l2_fourcc('Q', 'G', 'B', '0')
448#define V4L2_PIX_FMT_QGRBG10 v4l2_fourcc('Q', 'G', 'R', '0')
449#define V4L2_PIX_FMT_QRGGB10 v4l2_fourcc('Q', 'R', 'G', '0')
450#define V4L2_PIX_FMT_QBGGR12 v4l2_fourcc('Q', 'B', 'G', '2')
451#define V4L2_PIX_FMT_QGBRG12 v4l2_fourcc('Q', 'G', 'B', '2')
452#define V4L2_PIX_FMT_QGRBG12 v4l2_fourcc('Q', 'G', 'R', '2')
453#define V4L2_PIX_FMT_QRGGB12 v4l2_fourcc('Q', 'R', 'G', '2')
454#define V4L2_PIX_FMT_NV14 v4l2_fourcc('N', 'V', '1', '4')
455#define V4L2_PIX_FMT_NV41 v4l2_fourcc('N', 'V', '4', '1')
456#define V4L2_PIX_FMT_META v4l2_fourcc('Q', 'M', 'E', 'T')
457
458#define VIDIOC_MSM_VFE_REG_CFG \
459	_IOWR('V', BASE_VIDIOC_PRIVATE, struct msm_vfe_cfg_cmd2)
460
461#define VIDIOC_MSM_ISP_REQUEST_BUF \
462	_IOWR('V', BASE_VIDIOC_PRIVATE+1, struct msm_isp_buf_request)
463
464#define VIDIOC_MSM_ISP_ENQUEUE_BUF \
465	_IOWR('V', BASE_VIDIOC_PRIVATE+2, struct msm_isp_qbuf_info)
466
467#define VIDIOC_MSM_ISP_RELEASE_BUF \
468	_IOWR('V', BASE_VIDIOC_PRIVATE+3, struct msm_isp_buf_request)
469
470#define VIDIOC_MSM_ISP_REQUEST_STREAM \
471	_IOWR('V', BASE_VIDIOC_PRIVATE+4, struct msm_vfe_axi_stream_request_cmd)
472
473#define VIDIOC_MSM_ISP_CFG_STREAM \
474	_IOWR('V', BASE_VIDIOC_PRIVATE+5, struct msm_vfe_axi_stream_cfg_cmd)
475
476#define VIDIOC_MSM_ISP_RELEASE_STREAM \
477	_IOWR('V', BASE_VIDIOC_PRIVATE+6, struct msm_vfe_axi_stream_release_cmd)
478
479#define VIDIOC_MSM_ISP_INPUT_CFG \
480	_IOWR('V', BASE_VIDIOC_PRIVATE+7, struct msm_vfe_input_cfg)
481
482#define VIDIOC_MSM_ISP_SET_SRC_STATE \
483	_IOWR('V', BASE_VIDIOC_PRIVATE+8, struct msm_vfe_axi_src_state)
484
485#define VIDIOC_MSM_ISP_REQUEST_STATS_STREAM \
486	_IOWR('V', BASE_VIDIOC_PRIVATE+9, \
487	struct msm_vfe_stats_stream_request_cmd)
488
489#define VIDIOC_MSM_ISP_CFG_STATS_STREAM \
490	_IOWR('V', BASE_VIDIOC_PRIVATE+10, struct msm_vfe_stats_stream_cfg_cmd)
491
492#define VIDIOC_MSM_ISP_RELEASE_STATS_STREAM \
493	_IOWR('V', BASE_VIDIOC_PRIVATE+11, \
494	struct msm_vfe_stats_stream_release_cmd)
495
496#define VIDIOC_MSM_ISP_UPDATE_STREAM \
497	_IOWR('V', BASE_VIDIOC_PRIVATE+13, struct msm_vfe_axi_stream_update_cmd)
498
499#define VIDIOC_MSM_VFE_REG_LIST_CFG \
500	_IOWR('V', BASE_VIDIOC_PRIVATE+14, struct msm_vfe_cfg_cmd_list)
501
502#define VIDIOC_MSM_ISP_SMMU_ATTACH \
503	_IOWR('V', BASE_VIDIOC_PRIVATE+15, struct msm_vfe_smmu_attach_cmd)
504
505#define VIDIOC_MSM_ISP_UPDATE_STATS_STREAM \
506	_IOWR('V', BASE_VIDIOC_PRIVATE+16, struct msm_vfe_axi_stream_update_cmd)
507
508#endif /* __MSMB_ISP__ */
509