Cross Reference: /art/compiler/optimizing/code_generator

Lines Matching refs:dst
800       GpuRegister dst = location.AsRegister<GpuRegister>();
802         __ LoadConst32(dst, GetInt32ValueOf(instruction->AsConstant()));
804         __ LoadConst64(dst, instruction->AsLongConstant()->GetValue());
1057       GpuRegister dst = locations->Out().AsRegister<GpuRegister>();
1072           __ Andi(dst, lhs, rhs_imm);
1074           __ And(dst, lhs, rhs_reg);
1077           __ Ori(dst, lhs, rhs_imm);
1079           __ Or(dst, lhs, rhs_reg);
1082           __ Xori(dst, lhs, rhs_imm);
1084           __ Xor(dst, lhs, rhs_reg);
1088             __ Addiu(dst, lhs, rhs_imm);
1090             __ Addu(dst, lhs, rhs_reg);
1093             __ Daddiu(dst, lhs, rhs_imm);
1095             __ Daddu(dst, lhs, rhs_reg);
1101             __ Addiu(dst, lhs, -rhs_imm);
1103             __ Subu(dst, lhs, rhs_reg);
1106             __ Daddiu(dst, lhs, -rhs_imm);
1108             __ Dsubu(dst, lhs, rhs_reg);
1115       FpuRegister dst = locations->Out().AsFpuRegister<FpuRegister>();
1120           __ AddS(dst, lhs, rhs);
1122           __ AddD(dst, lhs, rhs);
1125           __ SubS(dst, lhs, rhs);
1127           __ SubD(dst, lhs, rhs);
1164       GpuRegister dst = locations->Out().AsRegister<GpuRegister>();
1184             __ Sll(dst, lhs, shift_value);
1186             __ Sra(dst, lhs, shift_value);
1188             __ Srl(dst, lhs, shift_value);
1193               __ Dsll(dst, lhs, shift_value);
1195               __ Dsra(dst, lhs, shift_value);
1197               __ Dsrl(dst, lhs, shift_value);
1202               __ Dsll32(dst, lhs, shift_value);
1204               __ Dsra32(dst, lhs, shift_value);
1206               __ Dsrl32(dst, lhs, shift_value);
1213             __ Sllv(dst, lhs, rhs_reg);
1215             __ Srav(dst, lhs, rhs_reg);
1217             __ Srlv(dst, lhs, rhs_reg);
1221             __ Dsllv(dst, lhs, rhs_reg);
1223             __ Dsrav(dst, lhs, rhs_reg);
1225             __ Dsrlv(dst, lhs, rhs_reg);
1687       GpuRegister dst = locations->Out().AsRegister<GpuRegister>();
1692       __ Slt(dst, rhs, lhs);
1693       __ Subu(dst, dst, TMP);
1732   GpuRegister dst = locations->Out().AsRegister<GpuRegister>();
1751         __ Xori(dst, lhs, rhs_imm);
1757         __ Xor(dst, lhs, rhs_reg);
1760         __ Sltiu(dst, dst, 1);
1762         __ Sltu(dst, ZERO, dst);
1769         __ Slti(dst, lhs, rhs_imm);
1775         __ Slt(dst, lhs, rhs_reg);
1780         __ Xori(dst, dst, 1);
1788         __ Slti(dst, lhs, rhs_imm + 1);
1792           __ Xori(dst, dst, 1);
1799         __ Slt(dst, rhs_reg, lhs);
1803           __ Xori(dst, dst, 1);
1840       GpuRegister dst = locations->Out().AsRegister<GpuRegister>();
1844         __ DivR6(dst, lhs, rhs);
1846         __ Ddiv(dst, lhs, rhs);
1851       FpuRegister dst = locations->Out().AsFpuRegister<FpuRegister>();
1855         __ DivS(dst, lhs, rhs);
1857         __ DivD(dst, lhs, rhs);
2148     GpuRegister dst = locations->Out().AsRegister<GpuRegister>();
2149     __ LoadFromOffset(load_type, dst, obj, field_info.GetFieldOffset().Uint32Value());
2152     FpuRegister dst = locations->Out().AsFpuRegister<FpuRegister>();
2153     __ LoadFpuFromOffset(load_type, dst, obj, field_info.GetFieldOffset().Uint32Value());
2616       GpuRegister dst = locations->Out().AsRegister<GpuRegister>();
2620         __ MulR6(dst, lhs, rhs);
2622         __ Dmul(dst, lhs, rhs);
2627       FpuRegister dst = locations->Out().AsFpuRegister<FpuRegister>();
2631         __ MulS(dst, lhs, rhs);
2633         __ MulD(dst, lhs, rhs);
2669       GpuRegister dst = locations->Out().AsRegister<GpuRegister>();
2672         __ Subu(dst, ZERO, src);
2674         __ Dsubu(dst, ZERO, src);
2679       FpuRegister dst = locations->Out().AsFpuRegister<FpuRegister>();
2682         __ NegS(dst, src);
2684         __ NegD(dst, src);
2750       GpuRegister dst = locations->Out().AsRegister<GpuRegister>();
2752       __ Nor(dst, src, ZERO);
2889       GpuRegister dst = locations->Out().AsRegister<GpuRegister>();
2893         __ ModR6(dst, lhs, rhs);
2895         __ Dmod(dst, lhs, rhs);
3096     GpuRegister dst = locations->Out().AsRegister<GpuRegister>();
3101         __ Andi(dst, src, 0xFFFF);
3108         __ Seb(dst, src);
3115         __ Seh(dst, src);
3121         __ Sll(dst, src, 0);
3130       FpuRegister dst = locations->Out().AsFpuRegister<FpuRegister>();
3134         __ Cvtsw(dst, FTMP);
3136         __ Cvtdw(dst, FTMP);
3162     FpuRegister dst = locations->Out().AsFpuRegister<FpuRegister>();
3165       __ Cvtsd(dst, src);
3167       __ Cvtds(dst, src);