Cross Reference: /art/compiler/utils/arm/assembler

Lines Matching defs:rd
51 bool Arm32Assembler::ShifterOperandCanHold(Register rd ATTRIBUTE_UNUSED,
59 void Arm32Assembler::and_(Register rd, Register rn, const ShifterOperand& so,
61   EmitType01(cond, so.type(), AND, 0, rn, rd, so);
65 void Arm32Assembler::eor(Register rd, Register rn, const ShifterOperand& so,
67   EmitType01(cond, so.type(), EOR, 0, rn, rd, so);
71 void Arm32Assembler::sub(Register rd, Register rn, const ShifterOperand& so,
73   EmitType01(cond, so.type(), SUB, 0, rn, rd, so);
76 void Arm32Assembler::rsb(Register rd, Register rn, const ShifterOperand& so,
78   EmitType01(cond, so.type(), RSB, 0, rn, rd, so);
81 void Arm32Assembler::rsbs(Register rd, Register rn, const ShifterOperand& so,
83   EmitType01(cond, so.type(), RSB, 1, rn, rd, so);
87 void Arm32Assembler::add(Register rd, Register rn, const ShifterOperand& so,
89   EmitType01(cond, so.type(), ADD, 0, rn, rd, so);
93 void Arm32Assembler::adds(Register rd, Register rn, const ShifterOperand& so,
95   EmitType01(cond, so.type(), ADD, 1, rn, rd, so);
99 void Arm32Assembler::subs(Register rd, Register rn, const ShifterOperand& so,
101   EmitType01(cond, so.type(), SUB, 1, rn, rd, so);
105 void Arm32Assembler::adc(Register rd, Register rn, const ShifterOperand& so,
107   EmitType01(cond, so.type(), ADC, 0, rn, rd, so);
111 void Arm32Assembler::sbc(Register rd, Register rn, const ShifterOperand& so,
113   EmitType01(cond, so.type(), SBC, 0, rn, rd, so);
117 void Arm32Assembler::rsc(Register rd, Register rn, const ShifterOperand& so,
119   EmitType01(cond, so.type(), RSC, 0, rn, rd, so);
145 void Arm32Assembler::orr(Register rd, Register rn,
147   EmitType01(cond, so.type(), ORR, 0, rn, rd, so);
151 void Arm32Assembler::orrs(Register rd, Register rn,
153   EmitType01(cond, so.type(), ORR, 1, rn, rd, so);
157 void Arm32Assembler::mov(Register rd, const ShifterOperand& so, Condition cond) {
158   EmitType01(cond, so.type(), MOV, 0, R0, rd, so);
162 void Arm32Assembler::movs(Register rd, const ShifterOperand& so, Condition cond) {
163   EmitType01(cond, so.type(), MOV, 1, R0, rd, so);
167 void Arm32Assembler::bic(Register rd, Register rn, const ShifterOperand& so,
169   EmitType01(cond, so.type(), BIC, 0, rn, rd, so);
173 void Arm32Assembler::mvn(Register rd, const ShifterOperand& so, Condition cond) {
174   EmitType01(cond, so.type(), MVN, 0, R0, rd, so);
178 void Arm32Assembler::mvns(Register rd, const ShifterOperand& so, Condition cond) {
179   EmitType01(cond, so.type(), MVN, 1, R0, rd, so);
183 void Arm32Assembler::mul(Register rd, Register rn, Register rm, Condition cond) {
184   // Assembler registers rd, rn, rm are encoded as rn, rm, rs.
185   EmitMulOp(cond, 0, R0, rd, rn, rm);
189 void Arm32Assembler::mla(Register rd, Register rn, Register rm, Register ra,
191   // Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd.
192   EmitMulOp(cond, B21, ra, rd, rn, rm);
196 void Arm32Assembler::mls(Register rd, Register rn, Register rm, Register ra,
198   // Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd.
199   EmitMulOp(cond, B22 | B21, ra, rd, rn, rm);
205   // Assembler registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
210 void Arm32Assembler::sdiv(Register rd, Register rn, Register rm, Condition cond) {
211   CHECK_NE(rd, kNoRegister);
219       (static_cast<int32_t>(rd) << 16) |
226 void Arm32Assembler::udiv(Register rd, Register rn, Register rm, Condition cond) {
227   CHECK_NE(rd, kNoRegister);
235       (static_cast<int32_t>(rd) << 16) |
242 void Arm32Assembler::sbfx(Register rd, Register rn, uint32_t lsb, uint32_t width, Condition cond) {
243   CHECK_NE(rd, kNoRegister);
253       (static_cast<uint32_t>(rd) << 12) |
261 void Arm32Assembler::ubfx(Register rd, Register rn, uint32_t lsb, uint32_t width, Condition cond) {
262   CHECK_NE(rd, kNoRegister);
272       (static_cast<uint32_t>(rd) << 12) |
280 void Arm32Assembler::ldr(Register rd, const Address& ad, Condition cond) {
281   EmitMemOp(cond, true, false, rd, ad);
285 void Arm32Assembler::str(Register rd, const Address& ad, Condition cond) {
286   EmitMemOp(cond, false, false, rd, ad);
290 void Arm32Assembler::ldrb(Register rd, const Address& ad, Condition cond) {
291   EmitMemOp(cond, true, true, rd, ad);
295 void Arm32Assembler::strb(Register rd, const Address& ad, Condition cond) {
296   EmitMemOp(cond, false, true, rd, ad);
300 void Arm32Assembler::ldrh(Register rd, const Address& ad, Condition cond) {
301   EmitMemOpAddressMode3(cond, L | B7 | H | B4, rd, ad);
305 void Arm32Assembler::strh(Register rd, const Address& ad, Condition cond) {
306   EmitMemOpAddressMode3(cond, B7 | H | B4, rd, ad);
310 void Arm32Assembler::ldrsb(Register rd, const Address& ad, Condition cond) {
311   EmitMemOpAddressMode3(cond, L | B7 | B6 | B4, rd, ad);
315 void Arm32Assembler::ldrsh(Register rd, const Address& ad, Condition cond) {
316   EmitMemOpAddressMode3(cond, L | B7 | B6 | H | B4, rd, ad);
320 void Arm32Assembler::ldrd(Register rd, const Address& ad, Condition cond) {
321   CHECK_EQ(rd % 2, 0);
322   EmitMemOpAddressMode3(cond, B7 | B6 | B4, rd, ad);
326 void Arm32Assembler::strd(Register rd, const Address& ad, Condition cond) {
327   CHECK_EQ(rd % 2, 0);
328   EmitMemOpAddressMode3(cond, B7 | B6 | B5 | B4, rd, ad);
588                                 Register rd,
590   CHECK_NE(rd, kNoRegister);
597                      static_cast<int32_t>(rd) << kRdShift |
615                                Register rd,
617   CHECK_NE(rd, kNoRegister);
635          (static_cast<int32_t>(rd) << kRdShift) |
644         (static_cast<int32_t>(rd) << kRdShift) |
653                                            Register rd,
655   CHECK_NE(rd, kNoRegister);
661                      (static_cast<int32_t>(rd) << kRdShift) |
686                                         Register rd,
693                      static_cast<int32_t>(rd) << kRdShift |
703                                        Register rd,
710                      static_cast<int32_t>(rd) << kRdShift |
731 void Arm32Assembler::clz(Register rd, Register rm, Condition cond) {
732   CHECK_NE(rd, kNoRegister);
735   CHECK_NE(rd, PC);
739                      (static_cast<int32_t>(rd) << kRdShift) |
745 void Arm32Assembler::movw(Register rd, uint16_t imm16, Condition cond) {
749                      static_cast<int32_t>(rd) << kRdShift | (imm16 & 0xfff);
754 void Arm32Assembler::movt(Register rd, uint16_t imm16, Condition cond) {
758                      static_cast<int32_t>(rd) << kRdShift | (imm16 & 0xfff);
764                                Register rd, Register rn,
766   CHECK_NE(rd, kNoRegister);
774       (static_cast<int32_t>(rd) << kRdShift) |
816 void Arm32Assembler::strex(Register rd,
821   CHECK_NE(rd, kNoRegister);
828                      (static_cast<int32_t>(rd) << kStrExRdShift) |
834 void Arm32Assembler::strexd(Register rd, Register rt, Register rt2, Register rn, Condition cond) {
835   CHECK_NE(rd, kNoRegister);
840   CHECK_NE(rd, rt);
841   CHECK_NE(rd, rt2);
850       static_cast<uint32_t>(rd) << 12 |
1153 void Arm32Assembler::Lsl(Register rd, Register rm, uint32_t shift_imm,
1157     movs(rd, ShifterOperand(rm, LSL, shift_imm), cond);
1159     mov(rd, ShifterOperand(rm, LSL, shift_imm), cond);
1164 void Arm32Assembler::Lsr(Register rd, Register rm, uint32_t shift_imm,
1169     movs(rd, ShifterOperand(rm, LSR, shift_imm), cond);
1171     mov(rd, ShifterOperand(rm, LSR, shift_imm), cond);
1176 void Arm32Assembler::Asr(Register rd, Register rm, uint32_t shift_imm,
1181     movs(rd, ShifterOperand(rm, ASR, shift_imm), cond);
1183     mov(rd, ShifterOperand(rm, ASR, shift_imm), cond);
1188 void Arm32Assembler::Ror(Register rd, Register rm, uint32_t shift_imm,
1192     movs(rd, ShifterOperand(rm, ROR, shift_imm), cond);
1194     mov(rd, ShifterOperand(rm, ROR, shift_imm), cond);
1198 void Arm32Assembler::Rrx(Register rd, Register rm, bool setcc, Condition cond) {
1200     movs(rd, ShifterOperand(rm, ROR, 0), cond);
1202     mov(rd, ShifterOperand(rm, ROR, 0), cond);
1207 void Arm32Assembler::Lsl(Register rd, Register rm, Register rn,
1210     movs(rd, ShifterOperand(rm, LSL, rn), cond);
1212     mov(rd, ShifterOperand(rm, LSL, rn), cond);
1217 void Arm32Assembler::Lsr(Register rd, Register rm, Register rn,
1220     movs(rd, ShifterOperand(rm, LSR, rn), cond);
1222     mov(rd, ShifterOperand(rm, LSR, rn), cond);
1227 void Arm32Assembler::Asr(Register rd, Register rm, Register rn,
1230     movs(rd, ShifterOperand(rm, ASR, rn), cond);
1232     mov(rd, ShifterOperand(rm, ASR, rn), cond);
1237 void Arm32Assembler::Ror(Register rd, Register rm, Register rn,
1240     movs(rd, ShifterOperand(rm, ROR, rn), cond);
1242     mov(rd, ShifterOperand(rm, ROR, rn), cond);
1290 void Arm32Assembler::Push(Register rd, Condition cond) {
1291   str(rd, Address(SP, -kRegisterSize, Address::PreIndex), cond);
1295 void Arm32Assembler::Pop(Register rd, Condition cond) {
1296   ldr(rd, Address(SP, kRegisterSize, Address::PostIndex), cond);
1310 void Arm32Assembler::Mov(Register rd, Register rm, Condition cond) {
1311   if (rd != rm) {
1312     mov(rd, ShifterOperand(rm), cond);
1350 void Arm32Assembler::AddConstant(Register rd, int32_t value, Condition cond) {
1351   AddConstant(rd, rd, value, cond);
1355 void Arm32Assembler::AddConstant(Register rd, Register rn, int32_t value,
1358     if (rd != rn) {
1359       mov(rd, ShifterOperand(rn), cond);
1368     add(rd, rn, shifter_op, cond);
1370     sub(rd, rn, shifter_op, cond);
1375       add(rd, rn, ShifterOperand(IP), cond);
1378       sub(rd, rn, ShifterOperand(IP), cond);
1385       add(rd, rn, ShifterOperand(IP), cond);
1391 void Arm32Assembler::AddConstantSetFlags(Register rd, Register rn, int32_t value,
1395     adds(rd, rn, shifter_op, cond);
1397     subs(rd, rn, shifter_op, cond);
1402       adds(rd, rn, ShifterOperand(IP), cond);
1405       subs(rd, rn, ShifterOperand(IP), cond);
1412       adds(rd, rn, ShifterOperand(IP), cond);
1417 void Arm32Assembler::LoadImmediate(Register rd, int32_t value, Condition cond) {
1420     mov(rd, shifter_op, cond);
1422     mvn(rd, shifter_op, cond);
1424     movw(rd, Low16Bits(value), cond);
1427       movt(rd, value_high, cond);