Cross Reference: /art/compiler/utils/mips/assembler

Lines Matching defs:dest
614 void MipsAssembler::Store(FrameOffset dest, ManagedRegister msrc, size_t size) {
620     StoreToOffset(kStoreWord, src.AsCoreRegister(), SP, dest.Int32Value());
623     StoreToOffset(kStoreWord, src.AsRegisterPairLow(), SP, dest.Int32Value());
625                   SP, dest.Int32Value() + 4);
627     StoreFToOffset(src.AsFRegister(), SP, dest.Int32Value());
630     StoreDToOffset(src.AsDRegister(), SP, dest.Int32Value());
634 void MipsAssembler::StoreRef(FrameOffset dest, ManagedRegister msrc) {
637   StoreToOffset(kStoreWord, src.AsCoreRegister(), SP, dest.Int32Value());
640 void MipsAssembler::StoreRawPtr(FrameOffset dest, ManagedRegister msrc) {
643   StoreToOffset(kStoreWord, src.AsCoreRegister(), SP, dest.Int32Value());
646 void MipsAssembler::StoreImmediateToFrame(FrameOffset dest, uint32_t imm,
651   StoreToOffset(kStoreWord, scratch.AsCoreRegister(), SP, dest.Int32Value());
654 void MipsAssembler::StoreImmediateToThread32(ThreadOffset<4> dest, uint32_t imm,
659   StoreToOffset(kStoreWord, scratch.AsCoreRegister(), S1, dest.Int32Value());
676 void MipsAssembler::StoreSpanning(FrameOffset dest, ManagedRegister msrc,
680   StoreToOffset(kStoreWord, src.AsCoreRegister(), SP, dest.Int32Value());
682   StoreToOffset(kStoreWord, scratch.AsCoreRegister(), SP, dest.Int32Value() + 4);
694   MipsManagedRegister dest = mdest.AsMips();
695   CHECK(dest.IsCoreRegister());
696   LoadFromOffset(kLoadWord, dest.AsCoreRegister(), SP, src.Int32Value());
701   MipsManagedRegister dest = mdest.AsMips();
702   CHECK(dest.IsCoreRegister() && dest.IsCoreRegister());
703   LoadFromOffset(kLoadWord, dest.AsCoreRegister(),
706     Subu(dest.AsCoreRegister(), ZERO, dest.AsCoreRegister());
712   MipsManagedRegister dest = mdest.AsMips();
713   CHECK(dest.IsCoreRegister() && dest.IsCoreRegister()) << dest;
714   LoadFromOffset(kLoadWord, dest.AsCoreRegister(),
720   MipsManagedRegister dest = mdest.AsMips();
721   CHECK(dest.IsCoreRegister());
722   LoadFromOffset(kLoadWord, dest.AsCoreRegister(), S1, offs.Int32Value());
734   MipsManagedRegister dest = mdest.AsMips();
736   if (!dest.Equals(src)) {
737     if (dest.IsCoreRegister()) {
739       Move(dest.AsCoreRegister(), src.AsCoreRegister());
740     } else if (dest.IsFRegister()) {
742       MovS(dest.AsFRegister(), src.AsFRegister());
743     } else if (dest.IsDRegister()) {
745       MovD(dest.AsDRegister(), src.AsDRegister());
747       CHECK(dest.IsRegisterPair()) << dest;
750       if (src.AsRegisterPairHigh() != dest.AsRegisterPairLow()) {
751         Move(dest.AsRegisterPairLow(), src.AsRegisterPairLow());
752         Move(dest.AsRegisterPairHigh(), src.AsRegisterPairHigh());
754         Move(dest.AsRegisterPairHigh(), src.AsRegisterPairHigh());
755         Move(dest.AsRegisterPairLow(), src.AsRegisterPairLow());
761 void MipsAssembler::CopyRef(FrameOffset dest, FrameOffset src,
766   StoreToOffset(kStoreWord, scratch.AsCoreRegister(), SP, dest.Int32Value());
791 void MipsAssembler::Copy(FrameOffset dest, FrameOffset src,
798     StoreToOffset(kStoreWord, scratch.AsCoreRegister(), SP, dest.Int32Value());
801     StoreToOffset(kStoreWord, scratch.AsCoreRegister(), SP, dest.Int32Value());
803     StoreToOffset(kStoreWord, scratch.AsCoreRegister(), SP, dest.Int32Value() + 4);
807 void MipsAssembler::Copy(FrameOffset dest, ManagedRegister src_base, Offset src_offset,
812   StoreToOffset(kStoreWord, scratch, SP, dest.Int32Value());
823 void MipsAssembler::Copy(FrameOffset /*dest*/, FrameOffset /*src_base*/, Offset /*src_offset*/,
828 void MipsAssembler::Copy(ManagedRegister dest, Offset dest_offset,
834   StoreToOffset(kStoreWord, scratch, dest.AsMips().AsCoreRegister(), dest_offset.Int32Value());
837 void MipsAssembler::Copy(FrameOffset /*dest*/, Offset /*dest_offset*/, FrameOffset /*src*/, Offset /*src_offset*/,