Cross Reference: /art/compiler/utils/mips64/assembler

Lines Matching refs:scratch
1192   Mips64ManagedRegister scratch = mscratch.AsMips64();
1193   CHECK(scratch.IsGpuRegister()) << scratch;
1194   LoadConst32(scratch.AsGpuRegister(), imm);
1195   StoreToOffset(kStoreWord, scratch.AsGpuRegister(), SP, dest.Int32Value());
1200   Mips64ManagedRegister scratch = mscratch.AsMips64();
1201   CHECK(scratch.IsGpuRegister()) << scratch;
1204   LoadConst32(scratch.AsGpuRegister(), imm);
1205   StoreToOffset(kStoreDoubleword, scratch.AsGpuRegister(), S1, dest.Int32Value());
1211   Mips64ManagedRegister scratch = mscratch.AsMips64();
1212   CHECK(scratch.IsGpuRegister()) << scratch;
1213   Daddiu64(scratch.AsGpuRegister(), SP, fr_offs.Int32Value());
1214   StoreToOffset(kStoreDoubleword, scratch.AsGpuRegister(), S1, thr_offs.Int32Value());
1224   Mips64ManagedRegister scratch = mscratch.AsMips64();
1226   LoadFromOffset(kLoadDoubleword, scratch.AsGpuRegister(), SP, in_off.Int32Value());
1227   StoreToOffset(kStoreDoubleword, scratch.AsGpuRegister(), SP, dest.Int32Value() + 8);
1304   Mips64ManagedRegister scratch = mscratch.AsMips64();
1305   CHECK(scratch.IsGpuRegister()) << scratch;
1306   LoadFromOffset(kLoadWord, scratch.AsGpuRegister(), SP, src.Int32Value());
1307   StoreToOffset(kStoreWord, scratch.AsGpuRegister(), SP, dest.Int32Value());
1313   Mips64ManagedRegister scratch = mscratch.AsMips64();
1314   CHECK(scratch.IsGpuRegister()) << scratch;
1315   LoadFromOffset(kLoadDoubleword, scratch.AsGpuRegister(), S1, thr_offs.Int32Value());
1316   StoreToOffset(kStoreDoubleword, scratch.AsGpuRegister(), SP, fr_offs.Int32Value());
1322   Mips64ManagedRegister scratch = mscratch.AsMips64();
1323   CHECK(scratch.IsGpuRegister()) << scratch;
1324   LoadFromOffset(kLoadDoubleword, scratch.AsGpuRegister(),
1326   StoreToOffset(kStoreDoubleword, scratch.AsGpuRegister(),
1332   Mips64ManagedRegister scratch = mscratch.AsMips64();
1333   CHECK(scratch.IsGpuRegister()) << scratch;
1336     LoadFromOffset(kLoadWord, scratch.AsGpuRegister(), SP, src.Int32Value());
1337     StoreToOffset(kStoreDoubleword, scratch.AsGpuRegister(), SP, dest.Int32Value());
1339     LoadFromOffset(kLoadDoubleword, scratch.AsGpuRegister(), SP, src.Int32Value());
1340     StoreToOffset(kStoreDoubleword, scratch.AsGpuRegister(), SP, dest.Int32Value());
1348   GpuRegister scratch = mscratch.AsMips64().AsGpuRegister();
1351     LoadFromOffset(kLoadWord, scratch, src_base.AsMips64().AsGpuRegister(),
1353     StoreToOffset(kStoreDoubleword, scratch, SP, dest.Int32Value());
1355     LoadFromOffset(kLoadDoubleword, scratch, src_base.AsMips64().AsGpuRegister(),
1357     StoreToOffset(kStoreDoubleword, scratch, SP, dest.Int32Value());
1365   GpuRegister scratch = mscratch.AsMips64().AsGpuRegister();
1368     LoadFromOffset(kLoadWord, scratch, SP, src.Int32Value());
1369     StoreToOffset(kStoreDoubleword, scratch, dest_base.AsMips64().AsGpuRegister(),
1372     LoadFromOffset(kLoadDoubleword, scratch, SP, src.Int32Value());
1373     StoreToOffset(kStoreDoubleword, scratch, dest_base.AsMips64().AsGpuRegister(),
1388   GpuRegister scratch = mscratch.AsMips64().AsGpuRegister();
1391     LoadFromOffset(kLoadWord, scratch, src.AsMips64().AsGpuRegister(), src_offset.Int32Value());
1392     StoreToOffset(kStoreDoubleword, scratch, dest.AsMips64().AsGpuRegister(), dest_offset.Int32Value());
1394     LoadFromOffset(kLoadDoubleword, scratch, src.AsMips64().AsGpuRegister(),
1396     StoreToOffset(kStoreDoubleword, scratch, dest.AsMips64().AsGpuRegister(),
1447   Mips64ManagedRegister scratch = mscratch.AsMips64();
1448   CHECK(scratch.IsGpuRegister()) << scratch;
1451     LoadFromOffset(kLoadUnsignedWord, scratch.AsGpuRegister(), SP,
1455     // e.g. scratch = (scratch == 0) ? 0 : (SP+handle_scope_offset)
1456     Beqzc(scratch.AsGpuRegister(), &null_arg);
1457     Daddiu64(scratch.AsGpuRegister(), SP, handle_scope_offset.Int32Value());
1460     Daddiu64(scratch.AsGpuRegister(), SP, handle_scope_offset.Int32Value());
1462   StoreToOffset(kStoreDoubleword, scratch.AsGpuRegister(), SP, out_off.Int32Value());
1492   Mips64ManagedRegister scratch = mscratch.AsMips64();
1494   CHECK(scratch.IsGpuRegister()) << scratch;
1495   LoadFromOffset(kLoadDoubleword, scratch.AsGpuRegister(),
1497   Jalr(scratch.AsGpuRegister());
1502   Mips64ManagedRegister scratch = mscratch.AsMips64();
1503   CHECK(scratch.IsGpuRegister()) << scratch;
1505   LoadFromOffset(kLoadDoubleword, scratch.AsGpuRegister(),
1507   LoadFromOffset(kLoadDoubleword, scratch.AsGpuRegister(),
1508                  scratch.AsGpuRegister(), offset.Int32Value());
1509   Jalr(scratch.AsGpuRegister());
1527   Mips64ManagedRegister scratch = mscratch.AsMips64();
1528   Mips64ExceptionSlowPath* slow = new Mips64ExceptionSlowPath(scratch, stack_adjust);
1530   LoadFromOffset(kLoadDoubleword, scratch.AsGpuRegister(),
1532   Bnezc(scratch.AsGpuRegister(), slow->Entry());