Cross Reference: /art/compiler/utils/x86_64/assembler_x86

Lines Matching refs:dst
106 void X86_64Assembler::movq(CpuRegister dst, const Immediate& imm) {
110     EmitRex64(dst);
112     EmitRegisterOperand(0, dst.LowBits());
115     EmitRex64(dst);
116     EmitUint8(0xB8 + dst.LowBits());
122 void X86_64Assembler::movl(CpuRegister dst, const Immediate& imm) {
125   EmitOptionalRex32(dst);
126   EmitUint8(0xB8 + dst.LowBits());
131 void X86_64Assembler::movq(const Address& dst, const Immediate& imm) {
134   EmitRex64(dst);
136   EmitOperand(0, dst);
141 void X86_64Assembler::movq(CpuRegister dst, CpuRegister src) {
144   EmitRex64(src, dst);
146   EmitRegisterOperand(src.LowBits(), dst.LowBits());
150 void X86_64Assembler::movl(CpuRegister dst, CpuRegister src) {
152   EmitOptionalRex32(dst, src);
154   EmitRegisterOperand(dst.LowBits(), src.LowBits());
158 void X86_64Assembler::movq(CpuRegister dst, const Address& src) {
160   EmitRex64(dst, src);
162   EmitOperand(dst.LowBits(), src);
166 void X86_64Assembler::movl(CpuRegister dst, const Address& src) {
168   EmitOptionalRex32(dst, src);
170   EmitOperand(dst.LowBits(), src);
174 void X86_64Assembler::movq(const Address& dst, CpuRegister src) {
176   EmitRex64(src, dst);
178   EmitOperand(src.LowBits(), dst);
182 void X86_64Assembler::movl(const Address& dst, CpuRegister src) {
184   EmitOptionalRex32(src, dst);
186   EmitOperand(src.LowBits(), dst);
189 void X86_64Assembler::movl(const Address& dst, const Immediate& imm) {
191   EmitOptionalRex32(dst);
193   EmitOperand(0, dst);
198 void X86_64Assembler::cmov(Condition c, CpuRegister dst, CpuRegister src) {
199   cmov(c, dst, src, true);
202 void X86_64Assembler::cmov(Condition c, CpuRegister dst, CpuRegister src, bool is64bit) {
204   EmitOptionalRex(false, is64bit, dst.NeedsRex(), false, src.NeedsRex());
207   EmitRegisterOperand(dst.LowBits(), src.LowBits());
211 void X86_64Assembler::movzxb(CpuRegister dst, CpuRegister src) {
213   EmitOptionalByteRegNormalizingRex32(dst, src);
216   EmitRegisterOperand(dst.LowBits(), src.LowBits());
220 void X86_64Assembler::movzxb(CpuRegister dst, const Address& src) {
223   // EmitOptionalByteRegNormalizingRex32(dst, src);
224   EmitOptionalRex32(dst, src);
227   EmitOperand(dst.LowBits(), src);
231 void X86_64Assembler::movsxb(CpuRegister dst, CpuRegister src) {
233   EmitOptionalByteRegNormalizingRex32(dst, src);
236   EmitRegisterOperand(dst.LowBits(), src.LowBits());
240 void X86_64Assembler::movsxb(CpuRegister dst, const Address& src) {
243   // EmitOptionalByteRegNormalizingRex32(dst, src);
244   EmitOptionalRex32(dst, src);
247   EmitOperand(dst.LowBits(), src);
251 void X86_64Assembler::movb(CpuRegister /*dst*/, const Address& /*src*/) {
256 void X86_64Assembler::movb(const Address& dst, CpuRegister src) {
258   EmitOptionalByteRegNormalizingRex32(src, dst);
260   EmitOperand(src.LowBits(), dst);
264 void X86_64Assembler::movb(const Address& dst, const Immediate& imm) {
266   EmitOptionalRex32(dst);
268   EmitOperand(Register::RAX, dst);
274 void X86_64Assembler::movzxw(CpuRegister dst, CpuRegister src) {
276   EmitOptionalRex32(dst, src);
279   EmitRegisterOperand(dst.LowBits(), src.LowBits());
283 void X86_64Assembler::movzxw(CpuRegister dst, const Address& src) {
285   EmitOptionalRex32(dst, src);
288   EmitOperand(dst.LowBits(), src);
292 void X86_64Assembler::movsxw(CpuRegister dst, CpuRegister src) {
294   EmitOptionalRex32(dst, src);
297   EmitRegisterOperand(dst.LowBits(), src.LowBits());
301 void X86_64Assembler::movsxw(CpuRegister dst, const Address& src) {
303   EmitOptionalRex32(dst, src);
306   EmitOperand(dst.LowBits(), src);
310 void X86_64Assembler::movw(CpuRegister /*dst*/, const Address& /*src*/) {
315 void X86_64Assembler::movw(const Address& dst, CpuRegister src) {
318   EmitOptionalRex32(src, dst);
320   EmitOperand(src.LowBits(), dst);
324 void X86_64Assembler::movw(const Address& dst, const Immediate& imm) {
327   EmitOptionalRex32(dst);
329   EmitOperand(Register::RAX, dst);
336 void X86_64Assembler::leaq(CpuRegister dst, const Address& src) {
338   EmitRex64(dst, src);
340   EmitOperand(dst.LowBits(), src);
344 void X86_64Assembler::leal(CpuRegister dst, const Address& src) {
346   EmitOptionalRex32(dst, src);
348   EmitOperand(dst.LowBits(), src);
352 void X86_64Assembler::movaps(XmmRegister dst, XmmRegister src) {
354   EmitOptionalRex32(dst, src);
357   EmitXmmRegisterOperand(dst.LowBits(), src);
361 void X86_64Assembler::movss(XmmRegister dst, const Address& src) {
364   EmitOptionalRex32(dst, src);
367   EmitOperand(dst.LowBits(), src);
371 void X86_64Assembler::movss(const Address& dst, XmmRegister src) {
374   EmitOptionalRex32(src, dst);
377   EmitOperand(src.LowBits(), dst);
381 void X86_64Assembler::movss(XmmRegister dst, XmmRegister src) {
384   EmitOptionalRex32(src, dst);  // Movss is MR encoding instead of the usual RM.
387   EmitXmmRegisterOperand(src.LowBits(), dst);
391 void X86_64Assembler::movsxd(CpuRegister dst, CpuRegister src) {
393   EmitRex64(dst, src);
395   EmitRegisterOperand(dst.LowBits(), src.LowBits());
399 void X86_64Assembler::movsxd(CpuRegister dst, const Address& src) {
401   EmitRex64(dst, src);
403   EmitOperand(dst.LowBits(), src);
407 void X86_64Assembler::movd(XmmRegister dst, CpuRegister src) {
408   movd(dst, src, true);
411 void X86_64Assembler::movd(CpuRegister dst, XmmRegister src) {
412   movd(dst, src, true);
415 void X86_64Assembler::movd(XmmRegister dst, CpuRegister src, bool is64bit) {
418   EmitOptionalRex(false, is64bit, dst.NeedsRex(), false, src.NeedsRex());
421   EmitOperand(dst.LowBits(), Operand(src));
424 void X86_64Assembler::movd(CpuRegister dst, XmmRegister src, bool is64bit) {
427   EmitOptionalRex(false, is64bit, src.NeedsRex(), false, dst.NeedsRex());
430   EmitOperand(src.LowBits(), Operand(dst));
434 void X86_64Assembler::addss(XmmRegister dst, XmmRegister src) {
437   EmitOptionalRex32(dst, src);
440   EmitXmmRegisterOperand(dst.LowBits(), src);
444 void X86_64Assembler::addss(XmmRegister dst, const Address& src) {
447   EmitOptionalRex32(dst, src);
450   EmitOperand(dst.LowBits(), src);
454 void X86_64Assembler::subss(XmmRegister dst, XmmRegister src) {
457   EmitOptionalRex32(dst, src);
460   EmitXmmRegisterOperand(dst.LowBits(), src);
464 void X86_64Assembler::subss(XmmRegister dst, const Address& src) {
467   EmitOptionalRex32(dst, src);
470   EmitOperand(dst.LowBits(), src);
474 void X86_64Assembler::mulss(XmmRegister dst, XmmRegister src) {
477   EmitOptionalRex32(dst, src);
480   EmitXmmRegisterOperand(dst.LowBits(), src);
484 void X86_64Assembler::mulss(XmmRegister dst, const Address& src) {
487   EmitOptionalRex32(dst, src);
490   EmitOperand(dst.LowBits(), src);
494 void X86_64Assembler::divss(XmmRegister dst, XmmRegister src) {
497   EmitOptionalRex32(dst, src);
500   EmitXmmRegisterOperand(dst.LowBits(), src);
504 void X86_64Assembler::divss(XmmRegister dst, const Address& src) {
507   EmitOptionalRex32(dst, src);
510   EmitOperand(dst.LowBits(), src);
521 void X86_64Assembler::fsts(const Address& dst) {
524   EmitOperand(2, dst);
528 void X86_64Assembler::fstps(const Address& dst) {
531   EmitOperand(3, dst);
535 void X86_64Assembler::movsd(XmmRegister dst, const Address& src) {
538   EmitOptionalRex32(dst, src);
541   EmitOperand(dst.LowBits(), src);
545 void X86_64Assembler::movsd(const Address& dst, XmmRegister src) {
548   EmitOptionalRex32(src, dst);
551   EmitOperand(src.LowBits(), dst);
555 void X86_64Assembler::movsd(XmmRegister dst, XmmRegister src) {
558   EmitOptionalRex32(src, dst);  // Movsd is MR encoding instead of the usual RM.
561   EmitXmmRegisterOperand(src.LowBits(), dst);
565 void X86_64Assembler::addsd(XmmRegister dst, XmmRegister src) {
568   EmitOptionalRex32(dst, src);
571   EmitXmmRegisterOperand(dst.LowBits(), src);
575 void X86_64Assembler::addsd(XmmRegister dst, const Address& src) {
578   EmitOptionalRex32(dst, src);
581   EmitOperand(dst.LowBits(), src);
585 void X86_64Assembler::subsd(XmmRegister dst, XmmRegister src) {
588   EmitOptionalRex32(dst, src);
591   EmitXmmRegisterOperand(dst.LowBits(), src);
595 void X86_64Assembler::subsd(XmmRegister dst, const Address& src) {
598   EmitOptionalRex32(dst, src);
601   EmitOperand(dst.LowBits(), src);
605 void X86_64Assembler::mulsd(XmmRegister dst, XmmRegister src) {
608   EmitOptionalRex32(dst, src);
611   EmitXmmRegisterOperand(dst.LowBits(), src);
615 void X86_64Assembler::mulsd(XmmRegister dst, const Address& src) {
618   EmitOptionalRex32(dst, src);
621   EmitOperand(dst.LowBits(), src);
625 void X86_64Assembler::divsd(XmmRegister dst, XmmRegister src) {
628   EmitOptionalRex32(dst, src);
631   EmitXmmRegisterOperand(dst.LowBits(), src);
635 void X86_64Assembler::divsd(XmmRegister dst, const Address& src) {
638   EmitOptionalRex32(dst, src);
641   EmitOperand(dst.LowBits(), src);
645 void X86_64Assembler::cvtsi2ss(XmmRegister dst, CpuRegister src) {
646   cvtsi2ss(dst, src, false);
650 void X86_64Assembler::cvtsi2ss(XmmRegister dst, CpuRegister src, bool is64bit) {
655     EmitRex64(dst, src);
657     EmitOptionalRex32(dst, src);
661   EmitOperand(dst.LowBits(), Operand(src));
665 void X86_64Assembler::cvtsi2ss(XmmRegister dst, const Address& src, bool is64bit) {
670     EmitRex64(dst, src);
672     EmitOptionalRex32(dst, src);
676   EmitOperand(dst.LowBits(), src);
680 void X86_64Assembler::cvtsi2sd(XmmRegister dst, CpuRegister src) {
681   cvtsi2sd(dst, src, false);
685 void X86_64Assembler::cvtsi2sd(XmmRegister dst, CpuRegister src, bool is64bit) {
690     EmitRex64(dst, src);
692     EmitOptionalRex32(dst, src);
696   EmitOperand(dst.LowBits(), Operand(src));
700 void X86_64Assembler::cvtsi2sd(XmmRegister dst, const Address& src, bool is64bit) {
705     EmitRex64(dst, src);
707     EmitOptionalRex32(dst, src);
711   EmitOperand(dst.LowBits(), src);
715 void X86_64Assembler::cvtss2si(CpuRegister dst, XmmRegister src) {
718   EmitOptionalRex32(dst, src);
721   EmitXmmRegisterOperand(dst.LowBits(), src);
725 void X86_64Assembler::cvtss2sd(XmmRegister dst, XmmRegister src) {
728   EmitOptionalRex32(dst, src);
731   EmitXmmRegisterOperand(dst.LowBits(), src);
735 void X86_64Assembler::cvtss2sd(XmmRegister dst, const Address& src) {
738   EmitOptionalRex32(dst, src);
741   EmitOperand(dst.LowBits(), src);
745 void X86_64Assembler::cvtsd2si(CpuRegister dst, XmmRegister src) {
748   EmitOptionalRex32(dst, src);
751   EmitXmmRegisterOperand(dst.LowBits(), src);
755 void X86_64Assembler::cvttss2si(CpuRegister dst, XmmRegister src) {
756   cvttss2si(dst, src, false);
760 void X86_64Assembler::cvttss2si(CpuRegister dst, XmmRegister src, bool is64bit) {
765     EmitRex64(dst, src);
767     EmitOptionalRex32(dst, src);
771   EmitXmmRegisterOperand(dst.LowBits(), src);
775 void X86_64Assembler::cvttsd2si(CpuRegister dst, XmmRegister src) {
776   cvttsd2si(dst, src, false);
780 void X86_64Assembler::cvttsd2si(CpuRegister dst, XmmRegister src, bool is64bit) {
785     EmitRex64(dst, src);
787     EmitOptionalRex32(dst, src);
791   EmitXmmRegisterOperand(dst.LowBits(), src);
795 void X86_64Assembler::cvtsd2ss(XmmRegister dst, XmmRegister src) {
798   EmitOptionalRex32(dst, src);
801   EmitXmmRegisterOperand(dst.LowBits(), src);
805 void X86_64Assembler::cvtsd2ss(XmmRegister dst, const Address& src) {
808   EmitOptionalRex32(dst, src);
811   EmitOperand(dst.LowBits(), src);
815 void X86_64Assembler::cvtdq2pd(XmmRegister dst, XmmRegister src) {
818   EmitOptionalRex32(dst, src);
821   EmitXmmRegisterOperand(dst.LowBits(), src);
901 void X86_64Assembler::roundsd(XmmRegister dst, XmmRegister src, const Immediate& imm) {
904   EmitOptionalRex32(dst, src);
908   EmitXmmRegisterOperand(dst.LowBits(), src);
913 void X86_64Assembler::roundss(XmmRegister dst, XmmRegister src, const Immediate& imm) {
916   EmitOptionalRex32(dst, src);
920   EmitXmmRegisterOperand(dst.LowBits(), src);
925 void X86_64Assembler::sqrtsd(XmmRegister dst, XmmRegister src) {
928   EmitOptionalRex32(dst, src);
931   EmitXmmRegisterOperand(dst.LowBits(), src);
935 void X86_64Assembler::sqrtss(XmmRegister dst, XmmRegister src) {
938   EmitOptionalRex32(dst, src);
941   EmitXmmRegisterOperand(dst.LowBits(), src);
945 void X86_64Assembler::xorpd(XmmRegister dst, const Address& src) {
948   EmitOptionalRex32(dst, src);
951   EmitOperand(dst.LowBits(), src);
955 void X86_64Assembler::xorpd(XmmRegister dst, XmmRegister src) {
958   EmitOptionalRex32(dst, src);
961   EmitXmmRegisterOperand(dst.LowBits(), src);
965 void X86_64Assembler::xorps(XmmRegister dst, const Address& src) {
967   EmitOptionalRex32(dst, src);
970   EmitOperand(dst.LowBits(), src);
974 void X86_64Assembler::xorps(XmmRegister dst, XmmRegister src) {
976   EmitOptionalRex32(dst, src);
979   EmitXmmRegisterOperand(dst.LowBits(), src);
983 void X86_64Assembler::andpd(XmmRegister dst, const Address& src) {
986   EmitOptionalRex32(dst, src);
989   EmitOperand(dst.LowBits(), src);
992 void X86_64Assembler::andpd(XmmRegister dst, XmmRegister src) {
995   EmitOptionalRex32(dst, src);
998   EmitXmmRegisterOperand(dst.LowBits(), src);
1001 void X86_64Assembler::andps(XmmRegister dst, XmmRegister src) {
1003   EmitOptionalRex32(dst, src);
1006   EmitXmmRegisterOperand(dst.LowBits(), src);
1009 void X86_64Assembler::orpd(XmmRegister dst, XmmRegister src) {
1012   EmitOptionalRex32(dst, src);
1015   EmitXmmRegisterOperand(dst.LowBits(), src);
1018 void X86_64Assembler::orps(XmmRegister dst, XmmRegister src) {
1020   EmitOptionalRex32(dst, src);
1023   EmitXmmRegisterOperand(dst.LowBits(), src);
1033 void X86_64Assembler::fstl(const Address& dst) {
1036   EmitOperand(2, dst);
1040 void X86_64Assembler::fstpl(const Address& dst) {
1043   EmitOperand(3, dst);
1055 void X86_64Assembler::fnstcw(const Address& dst) {
1058   EmitOperand(7, dst);
1069 void X86_64Assembler::fistpl(const Address& dst) {
1072   EmitOperand(7, dst);
1076 void X86_64Assembler::fistps(const Address& dst) {
1079   EmitOperand(3, dst);
1146 void X86_64Assembler::xchgl(CpuRegister dst, CpuRegister src) {
1152   const bool dst_rax = dst.AsRegister() == RAX;
1154     EmitOptionalRex32(src_rax ? dst : src);
1155     EmitUint8(0x90 + (src_rax ? dst.LowBits() : src.LowBits()));
1160   EmitOptionalRex32(src, dst);
1162   EmitRegisterOperand(src.LowBits(), dst.LowBits());
1166 void X86_64Assembler::xchgq(CpuRegister dst, CpuRegister src) {
1172   const bool dst_rax = dst.AsRegister() == RAX;
1178       EmitRex64(src_rax ? dst : src);
1179       EmitUint8(0x90 + (src_rax ? dst.LowBits() : src.LowBits()));
1185   EmitRex64(src, dst);
1187   EmitRegisterOperand(src.LowBits(), dst.LowBits());
1277 void X86_64Assembler::addl(CpuRegister dst, CpuRegister src) {
1279   EmitOptionalRex32(dst, src);
1281   EmitRegisterOperand(dst.LowBits(), src.LowBits());
1351 void X86_64Assembler::andl(CpuRegister dst, CpuRegister src) {
1353   EmitOptionalRex32(dst, src);
1355   EmitOperand(dst.LowBits(), Operand(src));
1367 void X86_64Assembler::andl(CpuRegister dst, const Immediate& imm) {
1369   EmitOptionalRex32(dst);
1370   EmitComplex(4, Operand(dst), imm);
1382 void X86_64Assembler::andq(CpuRegister dst, CpuRegister src) {
1384   EmitRex64(dst, src);
1386   EmitOperand(dst.LowBits(), Operand(src));
1390 void X86_64Assembler::andq(CpuRegister dst, const Address& src) {
1392   EmitRex64(dst, src);
1394   EmitOperand(dst.LowBits(), src);
1398 void X86_64Assembler::orl(CpuRegister dst, CpuRegister src) {
1400   EmitOptionalRex32(dst, src);
1402   EmitOperand(dst.LowBits(), Operand(src));
1414 void X86_64Assembler::orl(CpuRegister dst, const Immediate& imm) {
1416   EmitOptionalRex32(dst);
1417   EmitComplex(1, Operand(dst), imm);
1421 void X86_64Assembler::orq(CpuRegister dst, const Immediate& imm) {
1424   EmitRex64(dst);
1425   EmitComplex(1, Operand(dst), imm);
1429 void X86_64Assembler::orq(CpuRegister dst, CpuRegister src) {
1431   EmitRex64(dst, src);
1433   EmitOperand(dst.LowBits(), Operand(src));
1437 void X86_64Assembler::orq(CpuRegister dst, const Address& src) {
1439   EmitRex64(dst, src);
1441   EmitOperand(dst.LowBits(), src);
1445 void X86_64Assembler::xorl(CpuRegister dst, CpuRegister src) {
1447   EmitOptionalRex32(dst, src);
1449   EmitOperand(dst.LowBits(), Operand(src));
1461 void X86_64Assembler::xorl(CpuRegister dst, const Immediate& imm) {
1463   EmitOptionalRex32(dst);
1464   EmitComplex(6, Operand(dst), imm);
1468 void X86_64Assembler::xorq(CpuRegister dst, CpuRegister src) {
1470   EmitRex64(dst, src);
1472   EmitOperand(dst.LowBits(), Operand(src));
1476 void X86_64Assembler::xorq(CpuRegister dst, const Immediate& imm) {
1479   EmitRex64(dst);
1480   EmitComplex(6, Operand(dst), imm);
1483 void X86_64Assembler::xorq(CpuRegister dst, const Address& src) {
1485   EmitRex64(dst, src);
1487   EmitOperand(dst.LowBits(), src);
1519 void X86_64Assembler::rex_reg_mem(bool force, bool w, Register* dst, const Address& mem) {
1532   if (dst != nullptr && *dst >= Register::R8 && *dst < Register::kNumberOfCpuRegisters) {
1534     *dst = static_cast<Register>(*dst - 8);
1559 void X86_64Assembler::addq(CpuRegister dst, const Address& address) {
1561   EmitRex64(dst, address);
1563   EmitOperand(dst.LowBits(), address);
1567 void X86_64Assembler::addq(CpuRegister dst, CpuRegister src) {
1570   EmitRex64(src, dst);
1572   EmitRegisterOperand(src.LowBits(), dst.LowBits());
1591 void X86_64Assembler::subl(CpuRegister dst, CpuRegister src) {
1593   EmitOptionalRex32(dst, src);
1595   EmitOperand(dst.LowBits(), Operand(src));
1614 void X86_64Assembler::subq(CpuRegister dst, CpuRegister src) {
1616   EmitRex64(dst, src);
1618   EmitRegisterOperand(dst.LowBits(), src.LowBits());
1667 void X86_64Assembler::imull(CpuRegister dst, CpuRegister src) {
1669   EmitOptionalRex32(dst, src);
1672   EmitOperand(dst.LowBits(), Operand(src));
1706 void X86_64Assembler::imulq(CpuRegister dst, CpuRegister src) {
1708   EmitRex64(dst, src);
1711   EmitRegisterOperand(dst.LowBits(), src.LowBits());
1719 void X86_64Assembler::imulq(CpuRegister dst, CpuRegister reg, const Immediate& imm) {
1723   EmitRex64(dst, reg);
1730     EmitOperand(dst.LowBits(), Operand(reg));
1735     EmitOperand(dst.LowBits(), Operand(reg));
2042 void X86_64Assembler::setcc(Condition condition, CpuRegister dst) {
2045   if (dst.NeedsRex() || dst.AsRegister() > 3) {
2046     EmitOptionalRex(true, false, false, false, dst.NeedsRex());
2050   EmitUint8(0xC0 + dst.LowBits());
2053 void X86_64Assembler::bswapl(CpuRegister dst) {
2055   EmitOptionalRex(false, false, false, false, dst.NeedsRex());
2057   EmitUint8(0xC8 + dst.LowBits());
2060 void X86_64Assembler::bswapq(CpuRegister dst) {
2062   EmitOptionalRex(false, true, false, false, dst.NeedsRex());
2064   EmitUint8(0xC8 + dst.LowBits());
2076 void X86_64Assembler::LoadDoubleConstant(XmmRegister dst, double value) {
2081   movsd(dst, Address(CpuRegister(RSP), 0));
2242 void X86_64Assembler::EmitOptionalRex32(CpuRegister dst, CpuRegister src) {
2243   EmitOptionalRex(false, false, dst.NeedsRex(), false, src.NeedsRex());
2246 void X86_64Assembler::EmitOptionalRex32(XmmRegister dst, XmmRegister src) {
2247   EmitOptionalRex(false, false, dst.NeedsRex(), false, src.NeedsRex());
2250 void X86_64Assembler::EmitOptionalRex32(CpuRegister dst, XmmRegister src) {
2251   EmitOptionalRex(false, false, dst.NeedsRex(), false, src.NeedsRex());
2254 void X86_64Assembler::EmitOptionalRex32(XmmRegister dst, CpuRegister src) {
2255   EmitOptionalRex(false, false, dst.NeedsRex(), false, src.NeedsRex());
2265 void X86_64Assembler::EmitOptionalRex32(CpuRegister dst, const Operand& operand) {
2267   if (dst.NeedsRex()) {
2275 void X86_64Assembler::EmitOptionalRex32(XmmRegister dst, const Operand& operand) {
2277   if (dst.NeedsRex()) {
2299 void X86_64Assembler::EmitRex64(CpuRegister dst, CpuRegister src) {
2300   EmitOptionalRex(false, true, dst.NeedsRex(), false, src.NeedsRex());
2303 void X86_64Assembler::EmitRex64(XmmRegister dst, CpuRegister src) {
2304   EmitOptionalRex(false, true, dst.NeedsRex(), false, src.NeedsRex());
2307 void X86_64Assembler::EmitRex64(CpuRegister dst, XmmRegister src) {
2308   EmitOptionalRex(false, true, dst.NeedsRex(), false, src.NeedsRex());
2311 void X86_64Assembler::EmitRex64(CpuRegister dst, const Operand& operand) {
2313   if (dst.NeedsRex()) {
2319 void X86_64Assembler::EmitRex64(XmmRegister dst, const Operand& operand) {
2321   if (dst.NeedsRex()) {
2327 void X86_64Assembler::EmitOptionalByteRegNormalizingRex32(CpuRegister dst, CpuRegister src) {
2330   EmitOptionalRex(force, false, dst.NeedsRex(), false, src.NeedsRex());
2333 void X86_64Assembler::EmitOptionalByteRegNormalizingRex32(CpuRegister dst, const Operand& operand) {
2335   // For dst, SPL, BPL, SIL, DIL need the rex prefix.
2336   bool force = dst.AsRegister() > 3;
2340   if (dst.NeedsRex()) {
2530 void X86_64Assembler::StoreSpanning(FrameOffset /*dst*/, ManagedRegister /*src*/,
2709 void X86_64Assembler::Copy(FrameOffset /*dst*/, ManagedRegister /*src_base*/, Offset /*src_offset*/,