Cross Reference: /external/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp

Lines Matching defs:Op0IsKill
424   bool Op0IsKill = hasTrivialKill(I->getOperand(0));
445                                       Op0IsKill, Imm, VT.getSimpleVT());
457                                      ISDOpcode, Op0, Op0IsKill, CF);
472                                    ISDOpcode, Op0, Op0IsKill, Op1, Op1IsKill);
1282   bool Op0IsKill = hasTrivialKill(I->getOperand(0));
1299     ResultReg = fastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0, Op0IsKill);
1613                               bool /*Op0IsKill*/) {
1618                                bool /*Op0IsKill*/, unsigned /*Op1*/,
1633                                bool /*Op0IsKill*/, uint64_t /*Imm*/) {
1638                                bool /*Op0IsKill*/,
1644                                 bool /*Op0IsKill*/, unsigned /*Op1*/,
1654                                 bool Op0IsKill, uint64_t Imm, MVT ImmType) {
1672   unsigned ResultReg = fastEmit_ri(VT, VT, Opcode, Op0, Op0IsKill, Imm);
1685   return fastEmit_rr(VT, VT, Opcode, Op0, Op0IsKill, MaterialReg,
1721                                   bool Op0IsKill) {
1729         .addReg(Op0, getKillRegState(Op0IsKill));
1732         .addReg(Op0, getKillRegState(Op0IsKill));
1742                                    bool Op0IsKill, unsigned Op1,
1752         .addReg(Op0, getKillRegState(Op0IsKill))
1756         .addReg(Op0, getKillRegState(Op0IsKill))
1766                                     bool Op0IsKill, unsigned Op1,
1778         .addReg(Op0, getKillRegState(Op0IsKill))
1783         .addReg(Op0, getKillRegState(Op0IsKill))
1794                                    bool Op0IsKill, uint64_t Imm) {
1802         .addReg(Op0, getKillRegState(Op0IsKill))
1806         .addReg(Op0, getKillRegState(Op0IsKill))
1816                                     bool Op0IsKill, uint64_t Imm1,
1825         .addReg(Op0, getKillRegState(Op0IsKill))
1830         .addReg(Op0, getKillRegState(Op0IsKill))
1841                                    bool Op0IsKill, const ConstantFP *FPImm) {
1849         .addReg(Op0, getKillRegState(Op0IsKill))
1853         .addReg(Op0, getKillRegState(Op0IsKill))
1863                                     bool Op0IsKill, unsigned Op1,
1873         .addReg(Op0, getKillRegState(Op0IsKill))
1878         .addReg(Op0, getKillRegState(Op0IsKill))
1889                                      unsigned Op0, bool Op0IsKill, unsigned Op1,
1900         .addReg(Op0, getKillRegState(Op0IsKill))
1906         .addReg(Op0, getKillRegState(Op0IsKill))
1952                                               bool Op0IsKill, uint32_t Idx) {
1959           ResultReg).addReg(Op0, getKillRegState(Op0IsKill), Idx);
1965 unsigned FastISel::fastEmitZExtFromI1(MVT VT, unsigned Op0, bool Op0IsKill) {
1966   return fastEmit_ri(VT, VT, ISD::AND, Op0, Op0IsKill, 1);