Cross Reference: /external/llvm/lib/Target/AArch64/AArch64FastISel.cpp

Lines Matching defs:DestVT
188   unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
189   unsigned emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt);
2743   MVT DestVT;
2744   if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector())
2758       Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWDr : AArch64::FCVTZSUXDr;
2760       Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWDr : AArch64::FCVTZUUXDr;
2763       Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWSr : AArch64::FCVTZSUXSr;
2765       Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWSr : AArch64::FCVTZUUXSr;
2768       DestVT == MVT::i32 ? &AArch64::GPR32RegClass : &AArch64::GPR64RegClass);
2776   MVT DestVT;
2777   if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector())
2779   assert ((DestVT == MVT::f32 || DestVT == MVT::f64) &&
2801       Opc = (DestVT == MVT::f32) ? AArch64::SCVTFUXSri : AArch64::SCVTFUXDri;
2803       Opc = (DestVT == MVT::f32) ? AArch64::UCVTFUXSri : AArch64::UCVTFUXDri;
2806       Opc = (DestVT == MVT::f32) ? AArch64::SCVTFUWSri : AArch64::SCVTFUWDri;
2808       Opc = (DestVT == MVT::f32) ? AArch64::UCVTFUWSri : AArch64::UCVTFUWDri;
2811   unsigned ResultReg = fastEmitInst_r(Opc, TLI.getRegClassFor(DestVT), SrcReg,
2957       MVT DestVT = VA.getLocVT();
2959       ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false);
2967       MVT DestVT = VA.getLocVT();
2969       ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true);
3720     MVT DestVT = VA.getValVT();
3722     if (RVVT != DestVT) {
3730       SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt);
3763   MVT DestVT = DestEVT.getSimpleVT();
3768   if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8 &&
3769       DestVT != MVT::i1)
3785     switch (DestVT.SimpleTy) {
3816 unsigned AArch64FastISel::emiti1Ext(unsigned SrcReg, MVT DestVT, bool IsZExt) {
3817   assert((DestVT == MVT::i8 || DestVT == MVT::i16 || DestVT == MVT::i32 ||
3818           DestVT == MVT::i64) &&
3821   if (DestVT == MVT::i8 || DestVT == MVT::i16)
3822     DestVT = MVT::i32;
3827     if (DestVT == MVT::i64) {
3840     if (DestVT == MVT::i64) {
4225 unsigned AArch64FastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
4227   assert(DestVT != MVT::i1 && "ZeroExt/SignExt an i1?");
4230   // DestVT are odd things, so test to make sure that they are both types we can
4231   // handle (i1/i8/i16/i32 for SrcVT and i8/i16/i32/i64 for DestVT), otherwise
4233   if (((DestVT != MVT::i8) && (DestVT != MVT::i16) &&
4234        (DestVT != MVT::i32) && (DestVT != MVT::i64)) ||
4246     return emiti1Ext(SrcReg, DestVT, IsZExt);
4248     if (DestVT == MVT::i64)
4255     if (DestVT == MVT::i64)
4262     assert(DestVT == MVT::i64 && "IntExt i32 to i32?!?");
4269   if (DestVT == MVT::i8 || DestVT == MVT::i16)
4270     DestVT = MVT::i32;
4271   else if (DestVT == MVT::i64) {
4282       (DestVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
4446   MVT DestVT = DestEVT.getSimpleVT();
4447   if (DestVT != MVT::i64 && DestVT != MVT::i32)
4451   bool Is64bit = (DestVT == MVT::i64);
4474       (DestVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;