Lines Matching defs:RetVT
153 bool optimizeIntExtLoad(const Instruction *I, MVT RetVT, MVT SrcVT);
158 unsigned emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS,
161 unsigned emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg,
164 unsigned emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg,
167 unsigned emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg,
172 unsigned emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg,
181 bool emitICmp(MVT RetVT, const Value *LHS, const Value *RHS, bool IsZExt);
182 bool emitICmp_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm);
183 bool emitFCmp(MVT RetVT, const Value *LHS, const Value *RHS);
190 unsigned emitAdd(MVT RetVT, const Value *LHS, const Value *RHS,
194 unsigned emitSub(MVT RetVT, const Value *LHS, const Value *RHS,
197 unsigned emitSubs_rr(MVT RetVT, unsigned LHSReg, bool LHSIsKill,
199 unsigned emitSubs_rs(MVT RetVT, unsigned LHSReg, bool LHSIsKill,
203 unsigned emitLogicalOp(unsigned ISDOpc, MVT RetVT, const Value *LHS,
205 unsigned emitLogicalOp_ri(unsigned ISDOpc, MVT RetVT, unsigned LHSReg,
207 unsigned emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT, unsigned LHSReg,
210 unsigned emitAnd_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm);
211 unsigned emitMul_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
213 unsigned emitSMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
215 unsigned emitUMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
217 unsigned emitLSL_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
219 unsigned emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
221 unsigned emitLSR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
223 unsigned emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
225 unsigned emitASR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
227 unsigned emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
239 bool finishCall(CallLoweringInfo &CLI, MVT RetVT, unsigned NumBytes);
1084 unsigned AArch64FastISel::emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS,
1089 switch (RetVT.SimpleTy) {
1107 MVT SrcVT = RetVT;
1108 RetVT.SimpleTy = std::max(RetVT.SimpleTy, MVT::i32);
1134 LHSReg = emitIntExt(SrcVT, LHSReg, RetVT, IsZExt);
1140 ResultReg = emitAddSub_ri(!UseAdd, RetVT, LHSReg, LHSIsKill, -Imm,
1143 ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, LHSIsKill, Imm, SetFlags,
1147 ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, LHSIsKill, 0, SetFlags,
1163 return emitAddSub_rx(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg,
1171 return emitAddSub_rx(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg, RHSIsKill,
1191 return emitAddSub_rs(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg, RHSIsKill,
1212 return emitAddSub_rs(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg,
1225 RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt);
1227 return emitAddSub_rr(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg, RHSIsKill,
1231 unsigned AArch64FastISel::emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg,
1237 if (RetVT != MVT::i32 && RetVT != MVT::i64)
1246 bool Is64Bit = RetVT == MVT::i64;
1265 unsigned AArch64FastISel::emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg,
1270 if (RetVT != MVT::i32 && RetVT != MVT::i64)
1288 bool Is64Bit = RetVT == MVT::i64;
1310 unsigned AArch64FastISel::emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg,
1318 if (RetVT != MVT::i32 && RetVT != MVT::i64)
1327 bool Is64Bit = RetVT == MVT::i64;
1347 unsigned AArch64FastISel::emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg,
1355 if (RetVT != MVT::i32 && RetVT != MVT::i64)
1364 bool Is64Bit = RetVT == MVT::i64;
1409 bool AArch64FastISel::emitICmp(MVT RetVT, const Value *LHS, const Value *RHS,
1411 return emitSub(RetVT, LHS, RHS, /*SetFlags=*/true, /*WantResult=*/false,
1415 bool AArch64FastISel::emitICmp_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill,
1417 return emitAddSub_ri(/*UseAdd=*/false, RetVT, LHSReg, LHSIsKill, Imm,
1421 bool AArch64FastISel::emitFCmp(MVT RetVT, const Value *LHS, const Value *RHS) {
1422 if (RetVT != MVT::f32 && RetVT != MVT::f64)
1438 unsigned Opc = (RetVT == MVT::f64) ? AArch64::FCMPDri : AArch64::FCMPSri;
1449 unsigned Opc = (RetVT == MVT::f64) ? AArch64::FCMPDrr : AArch64::FCMPSrr;
1456 unsigned AArch64FastISel::emitAdd(MVT RetVT, const Value *LHS, const Value *RHS,
1458 return emitAddSub(/*UseAdd=*/true, RetVT, LHS, RHS, SetFlags, WantResult,
1486 unsigned AArch64FastISel::emitSub(MVT RetVT, const Value *LHS, const Value *RHS,
1488 return emitAddSub(/*UseAdd=*/false, RetVT, LHS, RHS, SetFlags, WantResult,
1492 unsigned AArch64FastISel::emitSubs_rr(MVT RetVT, unsigned LHSReg,
1495 return emitAddSub_rr(/*UseAdd=*/false, RetVT, LHSReg, LHSIsKill, RHSReg,
1499 unsigned AArch64FastISel::emitSubs_rs(MVT RetVT, unsigned LHSReg,
1504 return emitAddSub_rs(/*UseAdd=*/false, RetVT, LHSReg, LHSIsKill, RHSReg,
1509 unsigned AArch64FastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT,
1534 ResultReg = emitLogicalOp_ri(ISDOpc, RetVT, LHSReg, LHSIsKill, Imm);
1556 return emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, LHSIsKill, RHSReg,
1569 return emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, LHSIsKill, RHSReg,
1578 MVT VT = std::max(MVT::i32, RetVT.SimpleTy);
1580 if (RetVT >= MVT::i8 && RetVT <= MVT::i16) {
1581 uint64_t Mask = (RetVT == MVT::i8) ? 0xff : 0xffff;
1587 unsigned AArch64FastISel::emitLogicalOp_ri(unsigned ISDOpc, MVT RetVT,
1600 switch (RetVT.SimpleTy) {
1626 if (RetVT >= MVT::i8 && RetVT <= MVT::i16 && ISDOpc != ISD::AND) {
1627 uint64_t Mask = (RetVT == MVT::i8) ? 0xff : 0xffff;
1633 unsigned AArch64FastISel::emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT,
1646 switch (RetVT.SimpleTy) {
1664 if (RetVT >= MVT::i8 && RetVT <= MVT::i16) {
1665 uint64_t Mask = (RetVT == MVT::i8) ? 0xff : 0xffff;
1671 unsigned AArch64FastISel::emitAnd_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill,
1673 return emitLogicalOp_ri(ISD::AND, RetVT, LHSReg, LHSIsKill, Imm);
1676 unsigned AArch64FastISel::emitLoad(MVT VT, MVT RetVT, Address Addr,
1749 bool IsRet64Bit = RetVT == MVT::i64;
1798 if (WantZExt && RetVT == MVT::i64 && VT <= MVT::i32) {
1881 MVT RetVT = VT;
1885 if (isTypeSupported(ZE->getType(), RetVT))
1888 RetVT = VT;
1890 if (isTypeSupported(SE->getType(), RetVT))
1893 RetVT = VT;
1899 emitLoad(VT, RetVT, Addr, WantZExt, createMachineMemOperandFor(I));
1922 if (RetVT == MVT::i64 && VT <= MVT::i32) {
3017 bool AArch64FastISel::finishCall(CallLoweringInfo &CLI, MVT RetVT,
3027 if (RetVT != MVT::isVoid) {
3030 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC));
3084 MVT RetVT;
3086 RetVT = MVT::isVoid;
3087 else if (!isTypeLegal(CLI.RetTy, RetVT))
3172 return finishCall(CLI, RetVT, NumBytes);
3247 MVT RetVT;
3251 if (!isTypeLegal(RetTy, RetVT))
3254 if (RetVT != MVT::i32 && RetVT != MVT::i64)
3411 MVT RetVT;
3412 if (!isTypeLegal(II->getType(), RetVT))
3415 if (RetVT != MVT::f32 && RetVT != MVT::f64)
3424 bool Is64Bit = RetVT == MVT::f64;
3849 unsigned AArch64FastISel::emitMul_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
3852 switch (RetVT.SimpleTy) {
3857 RetVT = MVT::i32;
3864 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
3869 unsigned AArch64FastISel::emitSMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
3871 if (RetVT != MVT::i64)
3879 unsigned AArch64FastISel::emitUMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
3881 if (RetVT != MVT::i64)
3889 unsigned AArch64FastISel::emitLSL_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
3894 switch (RetVT.SimpleTy) {
3903 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
3915 unsigned AArch64FastISel::emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0,
3918 assert(RetVT.SimpleTy >= SrcVT.SimpleTy &&
3923 assert((RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32 ||
3924 RetVT == MVT::i64) && "Unexpected return value type.");
3926 bool Is64Bit = (RetVT == MVT::i64);
3928 unsigned DstBits = RetVT.getSizeInBits();
3935 if (RetVT == SrcVT) {
3942 return emitIntExt(SrcVT, Op0, RetVT, IsZExt);
3982 if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) {
3995 unsigned AArch64FastISel::emitLSR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
4000 switch (RetVT.SimpleTy) {
4009 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
4022 unsigned AArch64FastISel::emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0,
4025 assert(RetVT.SimpleTy >= SrcVT.SimpleTy &&
4030 assert((RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32 ||
4031 RetVT == MVT::i64) && "Unexpected return value type.");
4033 bool Is64Bit = (RetVT == MVT::i64);
4035 unsigned DstBits = RetVT.getSizeInBits();
4042 if (RetVT == SrcVT) {
4049 return emitIntExt(SrcVT, Op0, RetVT, IsZExt);
4082 return materializeInt(ConstantInt::get(*Context, APInt(RegSize, 0)), RetVT);
4087 Op0 = emitIntExt(SrcVT, Op0, RetVT, IsZExt);
4091 SrcVT = RetVT;
4103 if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) {
4116 unsigned AArch64FastISel::emitASR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
4121 switch (RetVT.SimpleTy) {
4130 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
4132 Op0Reg = emitIntExt(RetVT, Op0Reg, MVT::i32, /*IsZExt=*/false);
4143 unsigned AArch64FastISel::emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0,
4146 assert(RetVT.SimpleTy >= SrcVT.SimpleTy &&
4151 assert((RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32 ||
4152 RetVT == MVT::i64) && "Unexpected return value type.");
4154 bool Is64Bit = (RetVT == MVT::i64);
4156 unsigned DstBits = RetVT.getSizeInBits();
4163 if (RetVT == SrcVT) {
4170 return emitIntExt(SrcVT, Op0, RetVT, IsZExt);
4203 return materializeInt(ConstantInt::get(*Context, APInt(RegSize, 0)), RetVT);
4212 if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) {
4334 bool AArch64FastISel::optimizeIntExtLoad(const Instruction *I, MVT RetVT,
4363 if (RetVT != MVT::i64 || SrcVT > MVT::i32) {
4390 MVT RetVT;
4392 if (!isTypeSupported(I->getType(), RetVT))
4399 if (optimizeIntExtLoad(I, RetVT, SrcVT))
4411 if (RetVT == MVT::i64 && SrcVT != MVT::i64) {
4433 unsigned ResultReg = emitIntExt(SrcVT, SrcReg, RetVT, IsZExt);
4561 MVT RetVT;
4562 if (!isTypeSupported(I->getType(), RetVT, /*IsVectorAllowed=*/true))
4565 if (RetVT.isVector())
4571 MVT SrcVT = RetVT;
4602 ResultReg = emitLSL_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt);
4605 ResultReg = emitASR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt);
4608 ResultReg = emitLSR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt);
4632 ResultReg = emitLSL_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill);
4635 ResultReg = emitASR_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill);
4638 ResultReg = emitLSR_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill);
4650 MVT RetVT, SrcVT;
4654 if (!isTypeLegal(I->getType(), RetVT))
4658 if (RetVT == MVT::f32 && SrcVT == MVT::i32)
4660 else if (RetVT == MVT::f64 && SrcVT == MVT::i64)
4662 else if (RetVT == MVT::i32 && SrcVT == MVT::f32)
4664 else if (RetVT == MVT::i64 && SrcVT == MVT::f64)
4670 switch (RetVT.SimpleTy) {
4691 MVT RetVT;
4692 if (!isTypeLegal(I->getType(), RetVT))
4696 switch (RetVT.SimpleTy) {