Lines Matching defs:ISD
181 int ISD = TLI->InstructionOpcodeToISD(Opcode);
182 assert(ISD && "Invalid opcode");
192 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
193 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
194 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 },
195 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
196 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
197 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 },
200 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 },
201 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 },
202 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 2 },
203 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 },
204 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 },
205 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 2 },
208 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 4 },
209 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
210 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
211 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
214 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 },
215 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i16, 4 },
216 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
217 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 },
218 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 4 },
219 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
223 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f32, 1 },
224 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 },
225 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 },
226 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 },
227 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 },
228 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 },
231 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 2 },
232 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f32, 1 },
233 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f32, 1 },
234 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 2 },
235 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f32, 1 },
236 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f32, 1 },
239 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 },
240 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 2 },
241 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 2 },
242 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f32, 2 },
245 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 },
246 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f64, 2 },
247 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f64, 2 },
248 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 2 },
249 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f64, 2 },
250 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f64, 2 },
254 ConversionTbl, array_lengthof(ConversionTbl), ISD, DstTy.getSimpleVT(),
294 int ISD = TLI->InstructionOpcodeToISD(Opcode);
296 if (ISD == ISD::SDIV &&
319 switch (ISD) {
323 case ISD::ADD:
324 case ISD::MUL:
325 case ISD::XOR:
326 case ISD::OR:
327 case ISD::AND:
352 int ISD = TLI->InstructionOpcodeToISD(Opcode);
354 if (ValTy->isVectorTy() && ISD == ISD::SELECT) {
359 { ISD::SELECT, MVT::v16i1, MVT::v16i16, 16 * AmortizationCost },
360 { ISD::SELECT, MVT::v8i1, MVT::v8i32, 8 * AmortizationCost },
361 { ISD::SELECT, MVT::v16i1, MVT::v16i32, 16 * AmortizationCost },
362 { ISD::SELECT, MVT::v4i1, MVT::v4i64, 4 * AmortizationCost },
363 { ISD::SELECT, MVT::v8i1, MVT::v8i64, 8 * AmortizationCost },
364 { ISD::SELECT, MVT::v16i1, MVT::v16i64, 16 * AmortizationCost }
371 ConvertCostTableLookup(VectorSelectTbl, ISD, SelCondTy.getSimpleVT(),