Lines Matching defs:UseIdx
3200 unsigned UseIdx, unsigned UseAlign) const {
3201 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
3203 return ItinData->getOperandCycle(UseClass, UseIdx);
3240 unsigned UseIdx, unsigned UseAlign) const {
3241 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
3243 return ItinData->getOperandCycle(UseClass, UseIdx);
3270 unsigned UseIdx, unsigned UseAlign) const {
3274 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands())
3275 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
3325 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx);
3334 UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
3352 UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
3366 UseClass, UseIdx))
3369 UseClass, UseIdx)) {
3402 unsigned &UseIdx, unsigned &Dist) {
3425 UseIdx = Idx;
3616 unsigned UseIdx) const {
3645 UseIdx = NewUseIdx;
3674 if (DefMO.isImplicit() || UseMI->getOperand(UseIdx).isImplicit())
3684 *UseMCID, UseIdx, UseAlign);
3704 SDNode *UseNode, unsigned UseIdx) const {
3732 UseMCID, UseIdx, UseAlign);
4008 const MachineInstr *UseMI, unsigned UseIdx) const {
4017 int Latency = computeOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx);