Lines Matching defs:isZExt
172 bool isZExt);
174 unsigned Alignment = 0, bool isZExt = true,
183 unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
963 unsigned Alignment, bool isZExt, bool allocReg) {
975 Opc = isZExt ? ARM::t2LDRBi8 : ARM::t2LDRSBi8;
977 Opc = isZExt ? ARM::t2LDRBi12 : ARM::t2LDRSBi12;
979 if (isZExt) {
994 Opc = isZExt ? ARM::t2LDRHi8 : ARM::t2LDRSHi8;
996 Opc = isZExt ? ARM::t2LDRHi12 : ARM::t2LDRSHi12;
998 Opc = isZExt ? ARM::LDRH : ARM::LDRSH;
1366 bool isZExt) {
1387 Imm = (isZExt) ? (int)CIVal.getZExtValue() : (int)CIVal.getSExtValue();
1449 SrcReg1 = ARMEmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt);
1452 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt);
1573 /*isZExt*/!isSigned);
1958 Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/false);
1967 Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/true);
2134 if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) {
2135 SrcReg = ARMEmitIntExt(RVVT, SrcReg, DestVT, Outs[0].Flags.isZExt());
2593 bool isZExt) {
2678 bool isSingleInstr = isSingleInstrTbl[Bitness][isThumb2][hasV6Ops][isZExt];
2680 const InstructionTable *ITP = &IT[isSingleInstr][isThumb2][Bitness][isZExt];
2736 bool isZExt = isa<ZExtInst>(I);
2748 unsigned ResultReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT, isZExt);
2888 uint8_t isZExt : 1;
2919 bool isZExt;
2926 isZExt = FoldableLoadExtends[i].isZExt;
2936 if (!ARMEmitLoad(VT, ResultReg, Addr, LI->getAlignment(), isZExt, false))