Lines Matching refs:destination

700                                  InstructionOperand* destination) {
702 // Dispatch on the source and destination operand kinds. Not all
705 DCHECK(destination->IsRegister() || destination->IsStackSlot());
707 if (destination->IsRegister()) {
708 __ mov(g.ToRegister(destination), src);
710 __ str(src, g.ToMemOperand(destination));
713 DCHECK(destination->IsRegister() || destination->IsStackSlot());
715 if (destination->IsRegister()) {
716 __ ldr(g.ToRegister(destination), src);
720 __ str(temp, g.ToMemOperand(destination));
723 if (destination->IsRegister() || destination->IsStackSlot()) {
725 destination->IsRegister() ? g.ToRegister(destination) : kScratchReg;
745 if (destination->IsStackSlot()) __ str(dst, g.ToMemOperand(destination));
746 } else if (destination->IsDoubleRegister()) {
747 DwVfpRegister result = g.ToDoubleRegister(destination);
750 DCHECK(destination->IsDoubleStackSlot());
753 __ vstr(temp, g.ToMemOperand(destination));
757 if (destination->IsDoubleRegister()) {
758 DwVfpRegister dst = g.ToDoubleRegister(destination);
761 DCHECK(destination->IsDoubleStackSlot());
762 __ vstr(src, g.ToMemOperand(destination));
765 DCHECK(destination->IsDoubleRegister() || destination->IsDoubleStackSlot());
767 if (destination->IsDoubleRegister()) {
768 __ vldr(g.ToDoubleRegister(destination), src);
772 __ vstr(temp, g.ToMemOperand(destination));
781 InstructionOperand* destination) {
783 // Dispatch on the source and destination operand kinds. Not all
789 if (destination->IsRegister()) {
790 Register dst = g.ToRegister(destination);
795 DCHECK(destination->IsStackSlot());
796 MemOperand dst = g.ToMemOperand(destination);
802 DCHECK(destination->IsStackSlot());
806 MemOperand dst = g.ToMemOperand(destination);
814 if (destination->IsDoubleRegister()) {
815 DwVfpRegister dst = g.ToDoubleRegister(destination);
820 DCHECK(destination->IsDoubleStackSlot());
821 MemOperand dst = g.ToMemOperand(destination);
827 DCHECK(destination->IsDoubleStackSlot());
832 MemOperand dst0 = g.ToMemOperand(destination);
834 __ vldr(temp_1, dst0); // Save destination in temp_1.
835 __ ldr(temp_0, src0); // Then use temp_0 to copy source to destination.