/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | TargetLowering.cpp | 1218 DAGCombinerInfo &DCI, SDLoc dl) const { 1219 SelectionDAG &DAG = DCI.DAG; 1239 (DCI.isBeforeLegalizeOps() || 1298 DCI.isBeforeLegalize() && N0->hasOneUse()) { 1352 if (DCI.isBeforeLegalize() && 1445 if (DCI.isBeforeLegalizeOps() || 1481 if (!DCI.isCalledByLegalizer()) 1482 DCI.AddToWorklist(ZextOp.getNode()); 1502 if (DCI.isBeforeLegalizeOps() || 1592 if ((DCI 1216 SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, DAGCombinerInfo &DCI, SDLoc dl) const argument [all...] |
/external/llvm/lib/Target/Mips/ |
H A D | MipsSEISelLowering.cpp | 529 TargetLowering::DAGCombinerInfo &DCI, 531 if (DCI.isBeforeLegalize()) 549 TargetLowering::DAGCombinerInfo &DCI, 664 TargetLowering::DAGCombinerInfo &DCI, 784 TargetLowering::DAGCombinerInfo &DCI, 786 if (DCI.isBeforeLegalize()) 835 const TargetLowering::DAGCombinerInfo &DCI, 872 TargetLowering::DAGCombinerInfo &DCI, 895 TargetLowering::DAGCombinerInfo &DCI, 941 TargetLowering::DAGCombinerInfo &DCI, 528 performADDECombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument 548 performANDCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument 663 performORCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument 783 performSUBECombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument 834 performMULCombine(SDNode *N, SelectionDAG &DAG, const TargetLowering::DAGCombinerInfo &DCI, const MipsSETargetLowering *TL) argument 871 performSHLCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument 894 performSRACombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument 940 performSRLCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument [all...] |
H A D | MipsISelLowering.cpp | 452 TargetLowering::DAGCombinerInfo &DCI, 454 if (DCI.isBeforeLegalizeOps()) 562 TargetLowering::DAGCombinerInfo &DCI, 564 if (DCI.isBeforeLegalizeOps()) 641 TargetLowering::DAGCombinerInfo &DCI, 643 if (DCI.isBeforeLegalizeOps()) 668 TargetLowering::DAGCombinerInfo &DCI, 673 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) 708 TargetLowering::DAGCombinerInfo &DCI, 714 if (DCI 451 performDivRemCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument 561 performSELECTCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument 640 performCMovFPCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument 667 performANDCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument 707 performORCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument 761 performADDCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument [all...] |
/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 1949 //return DCI.CombineTo(N, NewSt, true); 3828 TargetLowering::DAGCombinerInfo &DCI, 3831 SelectionDAG &DAG = DCI.DAG; 3934 TargetLowering::DAGCombinerInfo &DCI, 3941 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget, 3947 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget, OptLevel); 3951 TargetLowering::DAGCombinerInfo &DCI) { 4013 Val = DCI.DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), 4019 DCI.CombineTo(N, Val, AddTo); 4108 TargetLowering::DAGCombinerInfo &DCI) { 3827 PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1, TargetLowering::DAGCombinerInfo &DCI, const NVPTXSubtarget &Subtarget, CodeGenOpt::Level OptLevel) argument 3933 PerformADDCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const NVPTXSubtarget &Subtarget, CodeGenOpt::Level OptLevel) argument 3950 PerformANDCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) argument 4107 TryMULWIDECombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) argument 4173 PerformMULCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, CodeGenOpt::Level OptLevel) argument 4187 PerformSHLCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, CodeGenOpt::Level OptLevel) argument [all...] |
/external/llvm/lib/Target/R600/ |
H A D | AMDGPUISelLowering.cpp | 1075 DAGCombinerInfo &DCI) const { 1082 SelectionDAG &DAG = DCI.DAG; 1112 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG && 1113 !DCI.isCalledByLegalizer()) 1133 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG && 1134 !DCI.isCalledByLegalizer()) 2294 static void simplifyI24(SDValue Op, TargetLowering::DAGCombinerInfo &DCI) { argument 2296 SelectionDAG &DAG = DCI.DAG; 2304 DCI.CommitTargetLoweringOpt(TLO); 2333 DAGCombinerInfo &DCI) cons 2671 getRsqrtEstimate(SDValue Operand, DAGCombinerInfo &DCI, unsigned &RefinementSteps, bool &UseOneConstNR) const argument 2689 getRecipEstimate(SDValue Operand, DAGCombinerInfo &DCI, unsigned &RefinementSteps) const argument [all...] |
/external/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 6914 TargetLowering::DAGCombinerInfo &DCI, 6916 if (DCI.isBeforeLegalizeOps()) 6965 TargetLowering::DAGCombinerInfo &DCI, 6967 if (DCI.isBeforeLegalizeOps()) 7134 TargetLowering::DAGCombinerInfo &DCI) { 7135 SelectionDAG &DAG = DCI.DAG; 7174 TargetLowering::DAGCombinerInfo &DCI) { 7176 SelectionDAG &DAG = DCI.DAG; 7220 static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, argument 7225 SelectionDAG &DAG = DCI 6913 performXorCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget) argument 6964 performMulCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget) argument 7133 tryCombineToEXTR(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) argument 7173 tryCombineToBSL(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) argument 7242 performBitcastCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument 7308 performConcatVectorsCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument 7389 tryCombineFixedPointConvert(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument 7632 performAddSubLongCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument 7681 tryCombineLongOpWithDup(unsigned IID, SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument 7792 performIntrinsicCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget) argument 7843 performExtendCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument 8001 performSTORECombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG, const AArch64Subtarget *Subtarget) argument 8069 performPostLD1Combine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, bool IsLaneOp) argument 8160 performNEONPostLDSTCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument 8476 performCONDCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG, unsigned CCIndex, unsigned CmpIndex) argument 8550 performBRCONDCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 7705 // @param DCI Context. 7710 TargetLowering::DAGCombinerInfo &DCI, 7712 SelectionDAG &DAG = DCI.DAG; 7736 TargetLowering::DAGCombinerInfo &DCI) { 7740 SDValue Result = combineSelectAndUse(N, N0, N1, DCI, AllOnes); 7745 SDValue Result = combineSelectAndUse(N, N1, N0, DCI, AllOnes); 7755 TargetLowering::DAGCombinerInfo &DCI, 7760 if (DCI.isBeforeLegalize() || !Subtarget->hasNEON() 7814 SelectionDAG &DAG = DCI.DAG; 7851 TargetLowering::DAGCombinerInfo &DCI, 7709 combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp, TargetLowering::DAGCombinerInfo &DCI, bool AllOnes = false) argument 7735 combineSelectAndUseCommutative(SDNode *N, bool AllOnes, TargetLowering::DAGCombinerInfo &DCI) argument 7754 AddCombineToVPADDL(SDNode *N, SDValue N0, SDValue N1, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument 7850 AddCombineTo64bitMLAL(SDNode *AddcNode, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument 7988 PerformADDCCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument 8000 PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument 8019 PerformADDCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument 8036 PerformSUBCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) argument 8065 PerformVMULCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument 8096 PerformMULCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument 8180 PerformANDCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument 8224 PerformORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument 8421 PerformXORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument 8442 PerformBFICombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) argument 8467 PerformVMOVRRDCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument 8543 PerformBUILD_VECTORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument 8578 PerformARMBUILD_VECTORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) argument 8670 PerformInsertEltCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) argument 8752 CombineBaseUpdate(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) argument 8956 PerformVLDCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) argument 8968 CombineVLDDUP(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) argument 9047 PerformVDUPLANECombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) argument 9077 PerformLOADCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) argument 9091 PerformSTORECombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) argument 9270 PerformVCVTCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument 9323 PerformVDIVCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 8852 DAGCombinerInfo &DCI, 8870 return DCI.DAG.getNode(PPCISD::FRSQRTE, SDLoc(Operand), VT, Operand); 8876 DAGCombinerInfo &DCI, 8892 return DCI.DAG.getNode(PPCISD::FRE, SDLoc(Operand), VT, Operand); 9126 DAGCombinerInfo &DCI) const { 9127 SelectionDAG &DAG = DCI.DAG; 9404 DAGCombinerInfo &DCI) const { 9405 SelectionDAG &DAG = DCI.DAG; 9682 DAGCombinerInfo &DCI) const { 9690 SelectionDAG &DAG = DCI 8851 getRsqrtEstimate(SDValue Operand, DAGCombinerInfo &DCI, unsigned &RefinementSteps, bool &UseOneConstNR) const argument 8875 getRecipEstimate(SDValue Operand, DAGCombinerInfo &DCI, unsigned &RefinementSteps) const argument [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 12769 DAGCombinerInfo &DCI, 12792 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op); 12800 DAGCombinerInfo &DCI, 12821 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op); 19444 TargetLowering::DAGCombinerInfo &DCI, 19513 return DCI.CombineTo(N, InsV); 19524 return DCI.CombineTo(N, InsV); 19531 return DCI.CombineTo(N, InsV); 19548 TargetLowering::DAGCombinerInfo &DCI, 19564 DCI 12768 getRsqrtEstimate(SDValue Op, DAGCombinerInfo &DCI, unsigned &RefinementSteps, bool &UseOneConstNR) const argument 12799 getRecipEstimate(SDValue Op, DAGCombinerInfo &DCI, unsigned &RefinementSteps) const argument 19443 PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget* Subtarget) argument 19546 combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask, int Depth, bool HasPSHUFB, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget *Subtarget) argument 19744 combineX86ShufflesRecursively(SDValue Op, SDValue Root, ArrayRef<int> RootMask, int Depth, bool HasPSHUFB, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget *Subtarget) argument 19906 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI) argument 20039 combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI) argument 20102 PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget *Subtarget) argument 20258 PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget *Subtarget) argument [all...] |