| /external/llvm/utils/TableGen/ |
| H A D | CallingConvEmitter.cpp | 224 MVT::SimpleValueType DestVT = getValueType(DestTy); local
225 O << IndentStr << "LocVT = " << getEnumName(DestVT) <<";\n";
226 if (MVT(DestVT).isFloatingPoint()) {
238 MVT::SimpleValueType DestVT = getValueType(DestTy); local
239 O << IndentStr << "LocVT = " << getEnumName(DestVT) << ";\n";
240 if (MVT(DestVT).isFloatingPoint()) {
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeTypes.cpp | 907 EVT DestVT) {
911 SDValue StackPtr = DAG.CreateStackTemporary(Op.getValueType(), DestVT);
916 return DAG.getLoad(DestVT, dl, Store, StackPtr, MachinePointerInfo(),
906 CreateStackStoreLoad(SDValue Op, EVT DestVT) argument
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| H A D | LegalizeVectorTypes.cpp | 239 EVT DestVT = N->getValueType(0).getVectorElementType(); local
257 return DAG.getNode(N->getOpcode(), SDLoc(N), DestVT, Op);
1105 EVT DestVT = N->getValueType(0); local
1107 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(DestVT);
1124 SrcVT.getSizeInBits() * 2 < DestVT.getSizeInBits()) {
|
| /external/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 1068 MVT DestVT = TLI->getRegisterType(NewVT); local
1069 RegisterVT = DestVT;
1070 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1071 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1437 MVT DestVT = getRegisterType(Context, NewVT); local
1438 RegisterVT = DestVT;
1445 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1446 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
|
| /external/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 120 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
121 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
124 bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
126 bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
127 bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
129 bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
855 EVT DestVT = TLI.getValueType(I->getType(), true); local
857 if (SrcVT != MVT::f32 || DestVT != MVT::f64)
878 EVT DestVT = TLI.getValueType(I->getType(), true); local
880 if (SrcVT != MVT::f64 || DestVT !
1008 MVT DestVT = VA.getLocVT(); local
1016 MVT DestVT = VA.getLocVT(); local
1269 EVT SrcVT, DestVT; local
1306 MVT DestVT = DestEVT.getSimpleVT(); local
1314 emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg) argument
1333 emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg) argument
1348 emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg) argument
1357 emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg) argument
1375 emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg, bool IsZExt) argument
1382 emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt) argument
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 159 bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
875 EVT DestVT = TLI.getValueType(I->getType(), true); local
877 if (SrcVT != MVT::f32 || DestVT != MVT::f64)
893 EVT DestVT = TLI.getValueType(I->getType(), true); local
895 if (SrcVT != MVT::f64 || DestVT != MVT::f32)
1138 EVT DestVT = TLI.getValueType(I->getType(), true); local
1142 if (DestVT != MVT::i16 && DestVT != MVT::i8)
1310 MVT DestVT = VA.getLocVT(); local
1312 (DestVT
1322 MVT DestVT = VA.getLocVT(); local
1377 MVT DestVT = VA.getValVT(); local
1626 MVT DestVT = VA.getLocVT(); local
1679 PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg, bool IsZExt) argument
1751 EVT DestVT = TLI.getValueType(I->getType(), true); local
1795 MVT DestVT = DestEVT.getSimpleVT(); local
[all...] |
| /external/llvm/lib/Target/R600/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 1115 EVT DestVT = ASC->getValueType(0); local
1119 unsigned DestSize = DestVT.getSizeInBits();
1126 DestVT,
1153 return CurDAG->getNode(ISD::BITCAST, DL, DestVT, Src).getNode();
|
| /external/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 183 unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
1753 EVT DestVT = TLI.getValueType(I->getType(), true); local
1757 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
1957 MVT DestVT = VA.getLocVT(); local
1958 Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/false);
1960 ArgVT = DestVT;
1966 MVT DestVT = VA.getLocVT(); local
1967 Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZEx
2044 MVT DestVT = RVLocs[0].getValVT(); local
2124 MVT DestVT = VA.getValVT(); local
2574 EVT SrcVT, DestVT; local
2592 ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt) argument
2747 MVT DestVT = DestEVT.getSimpleVT(); local
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 188 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
189 unsigned emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt);
2743 MVT DestVT; local
2744 if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector())
2758 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWDr : AArch64::FCVTZSUXDr;
2760 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWDr : AArch64::FCVTZUUXDr;
2763 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWSr : AArch64::FCVTZSUXSr;
2765 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWSr : AArch64::FCVTZUUXSr;
2768 DestVT
2776 MVT DestVT; local
2957 MVT DestVT = VA.getLocVT(); local
2967 MVT DestVT = VA.getLocVT(); local
3763 MVT DestVT = DestEVT.getSimpleVT(); local
3816 emiti1Ext(unsigned SrcReg, MVT DestVT, bool IsZExt) argument
4225 emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool IsZExt) argument
[all...] |
| H A D | AArch64ISelLowering.cpp | 4612 EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumSrcElts); local
4619 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec,
4634 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4640 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4645 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4648 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4652 Src.ShuffleVec = DAG.getNode(AArch64ISD::EXT, dl, DestVT, VEXTSrc1,
|
| /external/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 11593 EVT DestVT = Op.getValueType(); local
11595 if (DestVT.bitsLT(MVT::f64))
11596 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
11598 if (DestVT.bitsGT(MVT::f64))
11599 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
|