/external/llvm/bindings/ocaml/linker/ |
H A D | linker_ocaml.c | 27 CAMLprim value llvm_link_modules(LLVMModuleRef Dst, LLVMModuleRef Src) { argument 30 if (LLVMLinkModules(Dst, Src, 0, &Message))
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/external/clang/lib/Analysis/ |
H A D | CFGReachabilityAnalysis.cpp | 26 const CFGBlock *Dst) { 28 const unsigned DstBlockID = Dst->getBlockID(); 32 mapReachability(Dst); 42 void CFGReverseBlockReachabilityAnalysis::mapReachability(const CFGBlock *Dst) { argument 46 ReachableSet &DstReachability = reachable[Dst->getBlockID()]; 51 worklist.push_back(Dst); 61 // Update reachability information for this node -> Dst 63 // Don't insert Dst -> Dst unless it was a predecessor of itself 25 isReachable(const CFGBlock *Src, const CFGBlock *Dst) argument
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/external/llvm/include/llvm/Target/ |
H A D | CostTable.h | 51 TypeTy Dst; member in struct:llvm::TypeConversionCostTblEntry 60 unsigned len, int ISD, CompareTy Dst, 63 if (ISD == Tbl[i].ISD && Src == Tbl[i].Src && Dst == Tbl[i].Dst) 74 int ISD, CompareTy Dst, CompareTy Src) { member in namespace:llvm 75 return ConvertCostTableLookup(Tbl, N, ISD, Dst, Src); 59 ConvertCostTableLookup(const TypeConversionCostTblEntry<TypeTy> *Tbl, unsigned len, int ISD, CompareTy Dst, CompareTy Src) argument
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/external/mesa3d/src/gallium/drivers/r300/compiler/ |
H A D | radeon_variable.h | 46 struct rc_dst_register Dst; member in struct:rc_variable
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonSelectionDAGInfo.cpp | 30 SDValue Dst, SDValue Src, SDValue Size, unsigned Align, 29 EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument
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H A D | HexagonPeephole.cpp | 104 void ChangeOpInto(MachineOperand &Dst, MachineOperand &Src); 138 MachineOperand &Dst = MI->getOperand(0); local 140 unsigned DstReg = Dst.getReg(); 157 MachineOperand &Dst = MI->getOperand(0); local 162 unsigned DstReg = Dst.getReg(); 174 MachineOperand &Dst = MI->getOperand(0); local 179 unsigned DstReg = Dst.getReg(); 189 MachineOperand &Dst = MI->getOperand(0); local 191 unsigned DstReg = Dst.getReg(); 207 MachineOperand &Dst local 304 ChangeOpInto(MachineOperand &Dst, MachineOperand &Src) argument [all...] |
/external/llvm/include/llvm/Transforms/Utils/ |
H A D | BasicBlockUtils.h | 168 /// SplitCriticalEdge - If an edge from Src to Dst is critical, split the edge 173 SplitCriticalEdge(BasicBlock *Src, BasicBlock *Dst, argument 180 if (TI->getSuccessor(i) == Dst)
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/external/llvm/lib/ExecutionEngine/Orc/ |
H A D | CloneSubModule.cpp | 31 void CloneSubModule(llvm::Module &Dst, const Module &Src, argument 38 Dst.appendModuleInlineAsm(Src.getModuleInlineAsm()); 44 Dst, I->getType()->getElementType(), I->isConstant(), I->getLinkage(), 55 I->getLinkage(), I->getName(), &Dst); 66 I->getLinkage(), I->getName(), &Dst); 100 NamedMDNode *NewNMD = Dst.getOrInsertNamedMetadata(NMD.getName());
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64SelectionDAGInfo.cpp | 25 SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Dst, SDValue Src, 44 Entry.Node = Dst; 24 EmitTargetCodeForMemset( SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVolatile, MachinePointerInfo DstPtrInfo) const argument
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H A D | AArch64AdvSIMDScalarPass.cpp | 236 unsigned Dst = MI->getOperand(0).getReg(); local 239 Use = MRI->use_instr_nodbg_begin(Dst), 272 unsigned Dst, unsigned Src, bool IsKill) { 275 Dst) 340 unsigned Dst = MRI->createVirtualRegister(&AArch64::FPR64RegClass); local 345 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(NewOpc), Dst) 352 insertCopy(TII, MI, MI->getOperand(0).getReg(), Dst, true); 271 insertCopy(const TargetInstrInfo *TII, MachineInstr *MI, unsigned Dst, unsigned Src, bool IsKill) argument
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H A D | AArch64TargetTransformInfo.cpp | 179 unsigned AArch64TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, argument 185 EVT DstTy = TLI->getValueType(Dst); 188 return BaseT::getCastInstrCost(Opcode, Dst, Src); 259 return BaseT::getCastInstrCost(Opcode, Dst, Src);
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/external/llvm/lib/Target/R600/MCTargetDesc/ |
H A D | AMDGPUAsmBackend.cpp | 81 uint16_t *Dst = (uint16_t*)(Data + Fixup.getOffset()); local 82 *Dst = (Value - 4) / 4; 87 uint32_t *Dst = (uint32_t*)(Data + Fixup.getOffset()); local 88 *Dst = Value; 93 uint32_t *Dst = (uint32_t*)(Data + Fixup.getOffset()); local 96 *Dst = Value + 4;
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/external/llvm/lib/Target/R600/ |
H A D | SILowerI1Copies.cpp | 99 const MachineOperand &Dst = MI.getOperand(0); local 103 !TargetRegisterInfo::isVirtualRegister(Dst.getReg())) 106 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst.getReg()); 111 I1Defs.push_back(Dst.getReg()); 117 I1Defs.push_back(Dst.getReg()); 123 .addOperand(Dst) 131 .addOperand(Dst) 139 .addOperand(Dst)
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H A D | R600Packetizer.cpp | 97 unsigned Dst = BI->getOperand(DstIdx).getReg(); local 99 Result[Dst] = AMDGPU::PS; 104 Result[Dst] = AMDGPU::PV_X; 107 if (Dst == AMDGPU::OQAP) { 111 switch (TRI.getHWRegChan(Dst)) { 127 Result[Dst] = PVReg;
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/external/llvm/lib/Target/XCore/ |
H A D | XCoreSelectionDAGInfo.cpp | 27 SDValue Dst, SDValue Src, SDValue Size, unsigned Align, 40 Entry.Node = Dst; Args.push_back(Entry); 26 EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument
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/external/clang/lib/StaticAnalyzer/Core/ |
H A D | ExprEngineObjC.cpp | 24 ExplodedNodeSet &Dst) { 35 // the created nodes in 'Dst'. 36 getCheckerManager().runCheckersForPostStmt(Dst, dstIvar, Ex, *this); 41 ExplodedNodeSet &Dst) { 42 getCheckerManager().runCheckersForPreStmt(Dst, Pred, S, *this); 47 ExplodedNodeSet &Dst) { 132 getCheckerManager().runCheckersForPostStmt(Dst, Tmp, S, *this); 137 ExplodedNodeSet &Dst) { 212 // the created nodes in 'Dst'. 213 getCheckerManager().runCheckersForPostObjCMessage(Dst, dstPostvisi 22 VisitLvalObjCIvarRefExpr(const ObjCIvarRefExpr *Ex, ExplodedNode *Pred, ExplodedNodeSet &Dst) argument 39 VisitObjCAtSynchronizedStmt(const ObjCAtSynchronizedStmt *S, ExplodedNode *Pred, ExplodedNodeSet &Dst) argument 45 VisitObjCForCollectionStmt(const ObjCForCollectionStmt *S, ExplodedNode *Pred, ExplodedNodeSet &Dst) argument 135 VisitObjCMessage(const ObjCMessageExpr *ME, ExplodedNode *Pred, ExplodedNodeSet &Dst) argument [all...] |
/external/eigen/test/ |
H A D | vectorization_logic.cpp | 31 template<typename Dst, typename Src> 32 bool test_assign(const Dst&, const Src&, int traversal, int unrolling) argument 34 internal::assign_traits<Dst,Src>::debug(); 35 bool res = internal::assign_traits<Dst,Src>::Traversal==traversal 36 && internal::assign_traits<Dst,Src>::Unrolling==unrolling; 40 << " got " << demangle_traversal(internal::assign_traits<Dst,Src>::Traversal) << "\n"; 42 << " got " << demangle_unrolling(internal::assign_traits<Dst,Src>::Unrolling) << "\n"; 47 template<typename Dst, typename Src> 50 internal::assign_traits<Dst,Src>::debug(); 51 bool res = internal::assign_traits<Dst,Sr [all...] |
/external/llvm/lib/IR/ |
H A D | GCOV.cpp | 180 uint32_t Dst; local 181 if (!Buff.readInt(Dst)) 183 Edges.push_back(make_unique<GCOVEdge>(*Blocks[BlockNo], *Blocks[Dst])); 186 Blocks[Dst]->addSrcEdge(Edge); 379 if (!DstEdges[DstEdgeNo]->Dst.getNumDstEdges()) 380 DstEdges[DstEdgeNo]->Dst.Counter += N; 411 dbgs() << Edge->Dst.Number << " (" << Edge->Count << "), ";
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/external/llvm/lib/Support/ |
H A D | ConvertUTFWrapper.cpp | 115 UTF8 *Dst = reinterpret_cast<UTF8 *>(&Out[0]); local 116 UTF8 *DstEnd = Dst + Out.size(); 119 ConvertUTF16toUTF8(&Src, SrcEnd, &Dst, DstEnd, strictConversion); 127 Out.resize(reinterpret_cast<char *>(Dst) - &Out[0]); 153 UTF16 *Dst = &DstUTF16[0]; local 154 UTF16 *DstEnd = Dst + DstUTF16.size(); 157 ConvertUTF8toUTF16(&Src, SrcEnd, &Dst, DstEnd, strictConversion); 165 DstUTF16.resize(Dst - &DstUTF16[0]);
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/external/llvm/lib/Target/ARM/ |
H A D | ARMSelectionDAGInfo.cpp | 30 SDValue Dst, SDValue Src, 82 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst, 134 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst, 150 SDValue Chain, SDValue Dst, 167 Entry.Node = Dst; 28 EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument 149 EmitTargetCodeForMemset(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVolatile, MachinePointerInfo DstPtrInfo) const argument
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H A D | ARMTargetTransformInfo.cpp | 50 unsigned ARMTTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) { argument 71 EVT DstTy = TLI->getValueType(Dst); 74 return BaseT::getCastInstrCost(Opcode, Dst, Src); 245 return BaseT::getCastInstrCost(Opcode, Dst, Src);
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/external/llvm/lib/Target/ARM/InstPrinter/ |
H A D | ARMInstPrinter.cpp | 115 const MCOperand &Dst = MI->getOperand(0); local 125 printRegName(O, Dst.getReg()); 138 const MCOperand &Dst = MI->getOperand(0); local 147 printRegName(O, Dst.getReg());
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/external/clang/include/clang/StaticAnalyzer/Core/PathSensitive/ |
H A D | ExprEngine.h | 113 /// of the function are added into the Dst set, which represent the exit 118 ExplodedNodeSet &Dst) { 119 return Engine.ExecuteWorkListWithInitialState(L, Steps, InitState, Dst); 206 ExplodedNode *Pred, ExplodedNodeSet &Dst); 208 ExplodedNode *Pred, ExplodedNodeSet &Dst); 210 ExplodedNode *Pred, ExplodedNodeSet &Dst); 212 ExplodedNode *Pred, ExplodedNodeSet &Dst); 214 ExplodedNode *Pred, ExplodedNodeSet &Dst); 226 ExplodedNodeSet &Dst, 235 ExplodedNode *Pred, ExplodedNodeSet &Dst, 116 ExecuteWorkListWithInitialState(const LocationContext *L, unsigned Steps, ProgramStateRef InitState, ExplodedNodeSet &Dst) argument [all...] |
/external/llvm/lib/CodeGen/ |
H A D | MachineRegisterInfo.cpp | 230 /// Move NumOps operands from Src to Dst, updating use-def lists as needed. 232 /// The Dst range is assumed to be uninitialized memory. (Or it may contain 236 /// The Src and Dst ranges may overlap. 237 void MachineRegisterInfo::moveOperands(MachineOperand *Dst, argument 240 assert(Src != Dst && NumOps && "Noop moveOperands"); 242 // Copy backwards if Dst is within the Src range. 244 if (Dst >= Src && Dst < Src + NumOps) { 246 Dst += NumOps - 1; 252 new (Dst) MachineOperan [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCTargetTransformInfo.cpp | 261 unsigned PPCTTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) { argument 264 return BaseT::getCastInstrCost(Opcode, Dst, Src);
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