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Searched defs:Op2 (Results 1 - 6 of 6) sorted by relevance

/system/core/libpixelflinger/codeflinger/
H A D	ARMAssemblerInterface.cpp	`79 int Rd, int Rn, uint32_t Op2) 81 dataProcessing(opADD, cc, s, Rd, Rn, Op2); 84 int Rd, int Rn, uint32_t Op2) 86 dataProcessing(opSUB, cc, s, Rd, Rn, Op2); 78 ADDR_ADD(int cc, int s, int Rd, int Rn, uint32_t Op2) argument 83 ADDR_SUB(int cc, int s, int Rd, int Rn, uint32_t Op2) argument`
H A D	ARMAssembler.cpp	`217 int s, int Rd, int Rn, uint32_t Op2) 219 *mPC++ = (cc<<28) \| (opcode<<21) \| (s<<20) \| (Rn<<16) \| (Rd<<12) \| Op2; 216 dataProcessing(int opcode, int cc, int s, int Rd, int Rn, uint32_t Op2) argument`
H A D	ARMAssemblerProxy.cpp	`161 int Rd, int Rn, uint32_t Op2) 163 mTarget->dataProcessing(opcode, cc, s, Rd, Rn, Op2); 303 void ARMAssemblerProxy::ADDR_ADD(int cc, int s, int Rd, int Rn, uint32_t Op2){ argument 304 mTarget->ADDR_ADD(cc, s, Rd, Rn, Op2); 306 void ARMAssemblerProxy::ADDR_SUB(int cc, int s, int Rd, int Rn, uint32_t Op2){ argument 307 mTarget->ADDR_SUB(cc, s, Rd, Rn, Op2); 160 dataProcessing( int opcode, int cc, int s, int Rd, int Rn, uint32_t Op2) argument`
H A D	ARMAssemblerInterface.h	124 uint32_t Op2) = 0; 224 ADC(int cc, int s, int Rd, int Rn, uint32_t Op2) { argument 225 dataProcessing(opADC, cc, s, Rd, Rn, Op2); 228 ADD(int cc, int s, int Rd, int Rn, uint32_t Op2) { argument 229 dataProcessing(opADD, cc, s, Rd, Rn, Op2); 232 AND(int cc, int s, int Rd, int Rn, uint32_t Op2) { argument 233 dataProcessing(opAND, cc, s, Rd, Rn, Op2); 236 BIC(int cc, int s, int Rd, int Rn, uint32_t Op2) { argument 237 dataProcessing(opBIC, cc, s, Rd, Rn, Op2); 240 EOR(int cc, int s, int Rd, int Rn, uint32_t Op2) { argument 244 MOV(int cc, int s, int Rd, uint32_t Op2) argument 248 MVN(int cc, int s, int Rd, uint32_t Op2) argument 252 ORR(int cc, int s, int Rd, int Rn, uint32_t Op2) argument 256 RSB(int cc, int s, int Rd, int Rn, uint32_t Op2) argument 260 RSC(int cc, int s, int Rd, int Rn, uint32_t Op2) argument 264 SBC(int cc, int s, int Rd, int Rn, uint32_t Op2) argument 268 SUB(int cc, int s, int Rd, int Rn, uint32_t Op2) argument 272 TEQ(int cc, int Rn, uint32_t Op2) argument 276 TST(int cc, int Rn, uint32_t Op2) argument 280 CMP(int cc, int Rn, uint32_t Op2) argument 284 CMN(int cc, int Rn, uint32_t Op2) argument [all...]
H A D	Arm64Assembler.cpp	341 int s, int Rd, int Rn, uint32_t Op2) 356 if(Op2 == OPERAND_REG_IMM && mAddrMode.reg_imm_shift > 31) 364 if(Op2 == OPERAND_IMM) 369 Op2 = mTmpReg2; 378 if(Op2 == OPERAND_REG_IMM) 384 else if(Op2 < OPERAND_REG) 388 Rm = Op2; 409 int s, int Rd, int Rn, uint32_t Op2) 420 dataProcessingCommon(opcode, s, Wd, Rn, Op2); 424 dataProcessingCommon(opSUB, 1, mTmpReg3, Rn, Op2); 340 dataProcessingCommon(int opcode, int s, int Rd, int Rn, uint32_t Op2) argument 408 dataProcessing(int opcode, int cc, int s, int Rd, int Rn, uint32_t Op2) argument 463 ADDR_ADD(int cc, int s, int Rd, int Rn, uint32_t Op2) argument 498 ADDR_SUB(int cc, int s, int Rd, int Rn, uint32_t Op2) argument [all...]
H A D	MIPSAssembler.cpp	418 int s, int Rd, int Rn, uint32_t Op2) 434 if (dataProcAdrModes(Op2, src) == SRC_REG) { 443 if (dataProcAdrModes(Op2, src, true) == SRC_REG) { 452 if (dataProcAdrModes(Op2, src, true) == SRC_REG) { 460 if (dataProcAdrModes(Op2, src) == SRC_REG) { 468 if (dataProcAdrModes(Op2, src) == SRC_REG) { 476 if (dataProcAdrModes(Op2, src) == SRC_IMM) { 486 if (dataProcAdrModes(Op2, src) == SRC_IMM) { 495 if (Op2 < AMODE_REG) { // op2 is reg # in this case 496 mMips->MOVE(Rd, Op2); 417 dataProcessing(int opcode, int cc, int s, int Rd, int Rn, uint32_t Op2) argument [all...]

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