/external/llvm/lib/Target/XCore/ |
H A D | XCoreMachineFunctionInfo.cpp | 38 const TargetRegisterClass *RC = &XCore::GRRegsRegClass; local 42 LRSpillSlot = MFI->CreateFixedObject(RC->getSize(), 0, true); 44 LRSpillSlot = MFI->CreateStackObject(RC->getSize(), RC->getAlignment(), true); 54 const TargetRegisterClass *RC = &XCore::GRRegsRegClass; local 56 FPSpillSlot = MFI->CreateStackObject(RC->getSize(), RC->getAlignment(), true); 65 const TargetRegisterClass *RC = &XCore::GRRegsRegClass; local 67 EHSpillSlot[0] = MFI->CreateStackObject(RC->getSize(), RC [all...] |
/external/llvm/lib/CodeGen/ |
H A D | LiveStackAnalysis.cpp | 60 LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) { argument 68 S2RCMap.insert(std::make_pair(Slot, RC)); 72 S2RCMap[Slot] = TRI->getCommonSubClass(OldRC, RC); 84 const TargetRegisterClass *RC = getIntervalRegClass(Slot); local 85 if (RC) 86 OS << " [" << TRI->getRegClassName(RC) << "]\n";
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H A D | AggressiveAntiDepBreaker.h | 43 const TargetRegisterClass *RC; member in struct:llvm::AggressiveAntiDepState::__anon10390
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H A D | RegisterClassInfo.cpp | 76 /// compute - Compute the preferred allocation order for RC with reserved 79 void RegisterClassInfo::compute(const TargetRegisterClass *RC) const { 80 assert(RC && "no register class given"); 81 RCInfo &RCI = RegClass[RC->getID()]; 84 unsigned NumRegs = RC->getNumRegs(); 97 ArrayRef<MCPhysReg> RawOrder = RC->getRawAllocationOrder(*MF); 133 // Check if RC is a proper sub-class. 135 TRI->getLargestLegalSuperClass(RC, *MF)) 136 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs) 143 dbgs() << "AllocationOrder(" << TRI->getRegClassName(RC) << ") 157 const TargetRegisterClass *RC = nullptr; local [all...] |
H A D | CriticalAntiDepBreaker.cpp | 380 const TargetRegisterClass *RC, 383 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(RC); 614 const TargetRegisterClass *RC = AntiDepReg != 0 ? Classes[AntiDepReg] local 616 assert((AntiDepReg == 0 || RC != nullptr) && 618 if (RC == reinterpret_cast<TargetRegisterClass *>(-1)) 632 RC, ForbidRegs)) { 376 findSuitableFreeRegister(RegRefIter RegRefBegin, RegRefIter RegRefEnd, unsigned AntiDepReg, unsigned LastNewReg, const TargetRegisterClass *RC, SmallVectorImpl<unsigned> &Forbid) argument
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H A D | ExecutionDepsFix.cpp | 136 const TargetRegisterClass *const RC; 162 : MachineFunctionPass(ID), RC(rc), NumRegs(RC->getNumRegs()) {} 525 DEBUG(dbgs() << TRI->getName(RC->getRegister(rx)) << ":\t" << CurInstr 728 assert(NumRegs == RC->getNumRegs() && "Bad regclass"); 731 << TRI->getRegClassName(RC) << " **********\n"); 736 for (TargetRegisterClass::const_iterator I = RC->begin(), E = RC->end(); 746 // Given a PhysReg, AliasMap[PhysReg] returns a list of indices into RC and 749 for (unsigned i = 0, e = RC 804 createExecutionDependencyFixPass(const TargetRegisterClass *RC) argument [all...] |
/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXRegisterInfo.cpp | 29 std::string getNVPTXRegClassName(TargetRegisterClass const *RC) { argument 30 if (RC == &NVPTX::Float32RegsRegClass) { 33 if (RC == &NVPTX::Float64RegsRegClass) { 35 } else if (RC == &NVPTX::Int64RegsRegClass) { 37 } else if (RC == &NVPTX::Int32RegsRegClass) { 39 } else if (RC == &NVPTX::Int16RegsRegClass) { 41 } else if (RC == &NVPTX::Int1RegsRegClass) { 43 } else if (RC == &NVPTX::SpecialRegsRegClass) { 51 std::string getNVPTXRegClassStr(TargetRegisterClass const *RC) { argument 52 if (RC [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | Thumb1InstrInfo.cpp | 73 const TargetRegisterClass *RC, 75 assert((RC == &ARM::tGPRRegClass || 79 if (RC == &ARM::tGPRRegClass || 101 const TargetRegisterClass *RC, 103 assert((RC == &ARM::tGPRRegClass || 107 if (RC == &ARM::tGPRRegClass || 71 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 99 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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H A D | ThumbRegisterInfo.cpp | 44 ThumbRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC, argument 47 return ARMBaseRegisterInfo::getLargestLegalSuperClass(RC, MF); 49 if (ARM::tGPRRegClass.hasSubClassEq(RC)) 51 return ARMBaseRegisterInfo::getLargestLegalSuperClass(RC, MF); 447 MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC, 452 return ARMBaseRegisterInfo::saveScavengerRegister(MBB, I, UseMI, RC, Reg);
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/external/llvm/lib/Target/BPF/ |
H A D | BPFInstrInfo.cpp | 48 const TargetRegisterClass *RC, 54 if (RC == &BPF::GPRRegClass) 66 const TargetRegisterClass *RC, 72 if (RC == &BPF::GPRRegClass) 45 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool IsKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 63 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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/external/llvm/lib/Target/Mips/ |
H A D | MipsMachineFunction.cpp | 77 const TargetRegisterClass *RC = local 87 return GlobalBaseReg = MF.getRegInfo().createVirtualRegister(RC); 98 const TargetRegisterClass *RC = &Mips::CPU16RegsRegClass; local 99 return Mips16SPAliasReg = MF.getRegInfo().createVirtualRegister(RC); 104 const TargetRegisterClass *RC = local 109 EhDataRegFI[I] = MF.getFrameInfo()->CreateStackObject(RC->getSize(), 110 RC->getAlignment(), false); 137 int MipsFunctionInfo::getMoveF64ViaSpillFI(const TargetRegisterClass *RC) { argument 140 RC->getSize(), RC [all...] |
H A D | Mips16RegisterInfo.cpp | 64 const TargetRegisterClass *RC, 60 saveScavengerRegister(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC, unsigned Reg) const argument
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H A D | MipsRegisterInfo.cpp | 58 MipsRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, argument 60 switch (RC->getID()) {
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H A D | MipsSERegisterInfo.cpp | 171 const TargetRegisterClass *RC = local 174 unsigned Reg = RegInfo.createVirtualRegister(RC);
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCVSXCopy.cpp | 57 bool IsRegInClass(unsigned Reg, const TargetRegisterClass *RC, argument 60 return RC->hasSubClassEq(MRI.getRegClass(Reg)); 61 } else if (RC->contains(Reg)) {
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/external/llvm/lib/Target/R600/ |
H A D | SILowerI1Copies.cpp | 90 const TargetRegisterClass *RC = MRI.getRegClass(Reg); local 91 if (RC == &AMDGPU::VReg_1RegClass)
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H A D | SIFixSGPRCopies.cpp | 140 const TargetRegisterClass *RC local 145 RC = TRI->getSubRegClass(RC, SubReg); 150 RC = TRI->getCommonSubClass(RC, inferRegClassFromUses(TRI, MRI, 157 return RC; 166 const TargetRegisterClass *RC = TRI->getPhysRegClass(Reg); local 167 return TRI->getSubRegClass(RC, SubReg); 230 const TargetRegisterClass *RC local 233 MRI.constrainRegClass(Op.getReg(), RC); 236 const TargetRegisterClass *RC = inferRegClassFromUses(TRI, MRI, Reg, local [all...] |
/external/llvm/unittests/Support/ |
H A D | ProgramTest.cpp | 111 int RC = ExecuteAndWait(MyExe, ArgV, &EnvP[0], Redirects, local 115 EXPECT_EQ(0, RC);
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/external/llvm/utils/TableGen/ |
H A D | FastISelEmitter.cpp | 37 const CodeGenRegisterClass *RC; member in struct:__anon11362::InstructionMemo 257 const CodeGenRegisterClass *RC = nullptr; 261 RC = &Target.getRegisterClass(OpLeafRec); 263 RC = Target.getRegBank().getRegClassForRegister(OpLeafRec); 265 RC = OrigDstRC; 270 if (!RC) 276 if (DstRC != RC && !DstRC->hasSubClass(RC)) 279 DstRC = RC; 669 OS << "&" << InstNS << Memo.RC [all...] |
/external/skia/experimental/PdfViewer/pdfparser/native/pdfapi/ |
H A D | SkPdfAppearanceCharacteristicsDictionary_autogen.cpp | 59 SkString SkPdfAppearanceCharacteristicsDictionary::RC(SkPdfNativeDoc* doc) { function in class:SkPdfAppearanceCharacteristicsDictionary 60 SkPdfNativeObject* ret = get("RC", ""); 68 return get("RC", "") != NULL;
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/external/llvm/include/llvm/CodeGen/ |
H A D | RegisterClassInfo.h | 66 // Compute all information about RC. 67 void compute(const TargetRegisterClass *RC) const; 69 // Return an up-to-date RCInfo for RC. 70 const RCInfo &get(const TargetRegisterClass *RC) const { 71 const RCInfo &RCI = RegClass[RC->getID()]; 73 compute(RC); 85 /// registers in RC in the current function. 86 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const { 87 return get(RC).NumRegs; 90 /// getOrder - Returns the preferred allocation order for RC 119 getMinCost(const TargetRegisterClass *RC) argument 127 getLastCostChange(const TargetRegisterClass *RC) argument [all...] |
/external/llvm/lib/Target/MSP430/ |
H A D | MSP430InstrInfo.cpp | 40 const TargetRegisterClass *RC, 53 if (RC == &MSP430::GR16RegClass) 57 else if (RC == &MSP430::GR8RegClass) 68 const TargetRegisterClass *RC, 81 if (RC == &MSP430::GR16RegClass) 84 else if (RC == &MSP430::GR8RegClass) 37 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 65 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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/external/llvm/lib/Target/R600/MCTargetDesc/ |
H A D | SIMCCodeEmitter.cpp | 205 const MCRegisterClass &RC = MRI.getRegClass(RCID); local 209 if (getLitEncoding(Op, RC.getSize()) != 255) 277 const MCRegisterClass &RC = MRI.getRegClass(RCID); local 279 uint32_t Enc = getLitEncoding(MO, RC.getSize());
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/external/clang/lib/AST/ |
H A D | RawCommentList.cpp | 213 void RawCommentList::addComment(const RawComment &RC, argument 215 if (RC.isInvalid()) 221 RC.getLocStart())) { 228 if (RC.isOrdinary()) 234 Comments.push_back(new (Allocator) RawComment(RC)); 239 const RawComment &C2 = RC; 249 RC.isParseAllComments()); 251 Comments.push_back(new (Allocator) RawComment(RC));
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/external/clang/test/Layout/ |
H A D | ms-x86-pack-and-align.cpp | 450 struct RC { struct 456 RC c; 488 // CHECK-NEXT: 0 | struct RC 496 // CHECK-NEXT: 1 | struct RC c 531 // CHECK-X64-NEXT: 0 | struct RC 539 // CHECK-X64-NEXT: 1 | struct RC c 826 sizeof(RC)+
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