Searched defs:array_mode (Results 1 - 6 of 6) sorted by relevance

/external/mesa3d/src/gallium/drivers/radeonsi/
H A Dr600_texture.c78 unsigned array_mode)
95 switch (array_mode) {
149 unsigned array_mode,
467 unsigned array_mode,
496 r = r600_setup_surface(screen, rtex, array_mode, pitch_in_bytes_override);
526 unsigned array_mode = 0; local
533 array_mode = V_009910_ARRAY_2D_TILED_THIN1;
538 r = r600_init_surface(&surface, templ, array_mode);
546 return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
592 unsigned array_mode local
76 r600_init_surface(struct radeon_surface *surface, const struct pipe_resource *ptex, unsigned array_mode) argument
147 r600_setup_surface(struct pipe_screen *screen, struct r600_resource_texture *rtex, unsigned array_mode, unsigned pitch_in_bytes_override) argument
465 r600_texture_create_object(struct pipe_screen *screen, const struct pipe_resource *base, unsigned array_mode, unsigned pitch_in_bytes_override, unsigned max_buffer_size, struct pb_buffer *buf, boolean alloc_bo, struct radeon_surface *surface) argument
[all...]
/external/mesa3d/src/gallium/drivers/r600/
H A Dr600_resource.h49 unsigned array_mode[PIPE_MAX_TEXTURE_LEVELS]; member in struct:r600_texture
66 #define R600_TEX_IS_TILED(tex, level) ((tex)->array_mode[level] != V_038000_ARRAY_LINEAR_GENERAL && (tex)->array_mode[level] != V_038000_ARRAY_LINEAR_ALIGNED)
H A Devergreen_compute_internal.c505 unsigned char swizzle[4], array_mode = 0, tile_type = 0; local
527 array_mode = tmp->array_mode[0];
542 S_030004_ARRAY_MODE(array_mode)));
H A Dr600_texture.c71 unsigned array_mode,
105 switch (array_mode) {
188 rtex->array_mode[i] = V_038000_ARRAY_LINEAR_ALIGNED;
191 rtex->array_mode[i] = V_038000_ARRAY_1D_TILED_THIN1;
194 rtex->array_mode[i] = V_038000_ARRAY_2D_TILED_THIN1;
198 rtex->array_mode[i] = 0;
453 unsigned array_mode = 0; local
458 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
462 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
464 array_mode
68 r600_init_surface(struct r600_screen *rscreen, struct radeon_surface *surface, const struct pipe_resource *ptex, unsigned array_mode, bool is_transfer, bool is_flushed_depth) argument
525 unsigned array_mode = 0; local
[all...]
H A Devergreen_state.c991 unsigned char swizzle[4], array_mode = 0, tile_type = 0; local
1038 array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
1041 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1044 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1048 array_mode = V_028C70_ARRAY_LINEAR_GENERAL;
1084 S_030004_ARRAY_MODE(array_mode));
1440 unsigned level, pitch, slice, format, array_mode; local
1456 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1462 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1476 surf->db_depth_info = S_028040_ARRAY_MODE(array_mode) |
[all...]
H A Dr600_state.c1017 unsigned char swizzle[4], array_mode = 0, tile_type = 0; local
1071 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
1074 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
1077 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
1081 array_mode = V_038000_ARRAY_LINEAR_GENERAL;
1087 S_038000_TILE_MODE(array_mode) |
1480 unsigned level, pitch, slice, format, offset, array_mode; local
1491 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
1497 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
1504 surf->db_depth_info = S_028010_ARRAY_MODE(array_mode) | S_028010_FORMA
[all...]

Completed in 99 milliseconds